645 lines · c
1/* SPDX-License-Identifier: GPL-2.0-only */2/*******************************************************************************3 STMMAC Common Header File4 5 Copyright (C) 2007-2009 STMicroelectronics Ltd6 7 8 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>9*******************************************************************************/10 11#ifndef __COMMON_H__12#define __COMMON_H__13 14#include <linux/etherdevice.h>15#include <linux/netdevice.h>16#include <linux/stmmac.h>17#include <linux/phy.h>18#include <linux/pcs/pcs-xpcs.h>19#include <linux/module.h>20#if IS_ENABLED(CONFIG_VLAN_8021Q)21#define STMMAC_VLAN_TAG_USED22#include <linux/if_vlan.h>23#endif24 25#include "descs.h"26#include "hwif.h"27#include "mmc.h"28 29/* Synopsys Core versions */30#define DWMAC_CORE_3_40 0x3431#define DWMAC_CORE_3_50 0x3532#define DWMAC_CORE_3_70 0x3733#define DWMAC_CORE_4_00 0x4034#define DWMAC_CORE_4_10 0x4135#define DWMAC_CORE_5_00 0x5036#define DWMAC_CORE_5_10 0x5137#define DWMAC_CORE_5_20 0x5238#define DWXGMAC_CORE_2_10 0x2139#define DWXGMAC_CORE_2_20 0x2240#define DWXLGMAC_CORE_2_00 0x2041 42/* Device ID */43#define DWXGMAC_ID 0x7644#define DWXLGMAC_ID 0x2745 46#define STMMAC_CHAN0 0 /* Always supported and default for all chips */47 48/* TX and RX Descriptor Length, these need to be power of two.49 * TX descriptor length less than 64 may cause transmit queue timed out error.50 * RX descriptor length less than 64 may cause inconsistent Rx chain error.51 */52#define DMA_MIN_TX_SIZE 6453#define DMA_MAX_TX_SIZE 102454#define DMA_DEFAULT_TX_SIZE 51255#define DMA_MIN_RX_SIZE 6456#define DMA_MAX_RX_SIZE 102457#define DMA_DEFAULT_RX_SIZE 51258#define STMMAC_GET_ENTRY(x, size) ((x + 1) & (size - 1))59 60#undef FRAME_FILTER_DEBUG61/* #define FRAME_FILTER_DEBUG */62 63struct stmmac_q_tx_stats {64 u64_stats_t tx_bytes;65 u64_stats_t tx_set_ic_bit;66 u64_stats_t tx_tso_frames;67 u64_stats_t tx_tso_nfrags;68};69 70struct stmmac_napi_tx_stats {71 u64_stats_t tx_packets;72 u64_stats_t tx_pkt_n;73 u64_stats_t poll;74 u64_stats_t tx_clean;75 u64_stats_t tx_set_ic_bit;76};77 78struct stmmac_txq_stats {79 /* Updates protected by tx queue lock. */80 struct u64_stats_sync q_syncp;81 struct stmmac_q_tx_stats q;82 83 /* Updates protected by NAPI poll logic. */84 struct u64_stats_sync napi_syncp;85 struct stmmac_napi_tx_stats napi;86} ____cacheline_aligned_in_smp;87 88struct stmmac_napi_rx_stats {89 u64_stats_t rx_bytes;90 u64_stats_t rx_packets;91 u64_stats_t rx_pkt_n;92 u64_stats_t poll;93};94 95struct stmmac_rxq_stats {96 /* Updates protected by NAPI poll logic. */97 struct u64_stats_sync napi_syncp;98 struct stmmac_napi_rx_stats napi;99} ____cacheline_aligned_in_smp;100 101/* Updates on each CPU protected by not allowing nested irqs. */102struct stmmac_pcpu_stats {103 struct u64_stats_sync syncp;104 u64_stats_t rx_normal_irq_n[MTL_MAX_TX_QUEUES];105 u64_stats_t tx_normal_irq_n[MTL_MAX_RX_QUEUES];106};107 108/* Extra statistic and debug information exposed by ethtool */109struct stmmac_extra_stats {110 /* Transmit errors */111 unsigned long tx_underflow ____cacheline_aligned;112 unsigned long tx_carrier;113 unsigned long tx_losscarrier;114 unsigned long vlan_tag;115 unsigned long tx_deferred;116 unsigned long tx_vlan;117 unsigned long tx_jabber;118 unsigned long tx_frame_flushed;119 unsigned long tx_payload_error;120 unsigned long tx_ip_header_error;121 unsigned long tx_collision;122 /* Receive errors */123 unsigned long rx_desc;124 unsigned long sa_filter_fail;125 unsigned long overflow_error;126 unsigned long ipc_csum_error;127 unsigned long rx_collision;128 unsigned long rx_crc_errors;129 unsigned long dribbling_bit;130 unsigned long rx_length;131 unsigned long rx_mii;132 unsigned long rx_multicast;133 unsigned long rx_gmac_overflow;134 unsigned long rx_watchdog;135 unsigned long da_rx_filter_fail;136 unsigned long sa_rx_filter_fail;137 unsigned long rx_missed_cntr;138 unsigned long rx_overflow_cntr;139 unsigned long rx_vlan;140 unsigned long rx_split_hdr_pkt_n;141 /* Tx/Rx IRQ error info */142 unsigned long tx_undeflow_irq;143 unsigned long tx_process_stopped_irq;144 unsigned long tx_jabber_irq;145 unsigned long rx_overflow_irq;146 unsigned long rx_buf_unav_irq;147 unsigned long rx_process_stopped_irq;148 unsigned long rx_watchdog_irq;149 unsigned long tx_early_irq;150 unsigned long fatal_bus_error_irq;151 /* Tx/Rx IRQ Events */152 unsigned long rx_early_irq;153 unsigned long threshold;154 unsigned long irq_receive_pmt_irq_n;155 /* MMC info */156 unsigned long mmc_tx_irq_n;157 unsigned long mmc_rx_irq_n;158 unsigned long mmc_rx_csum_offload_irq_n;159 /* EEE */160 unsigned long irq_tx_path_in_lpi_mode_n;161 unsigned long irq_tx_path_exit_lpi_mode_n;162 unsigned long irq_rx_path_in_lpi_mode_n;163 unsigned long irq_rx_path_exit_lpi_mode_n;164 unsigned long phy_eee_wakeup_error_n;165 /* Extended RDES status */166 unsigned long ip_hdr_err;167 unsigned long ip_payload_err;168 unsigned long ip_csum_bypassed;169 unsigned long ipv4_pkt_rcvd;170 unsigned long ipv6_pkt_rcvd;171 unsigned long no_ptp_rx_msg_type_ext;172 unsigned long ptp_rx_msg_type_sync;173 unsigned long ptp_rx_msg_type_follow_up;174 unsigned long ptp_rx_msg_type_delay_req;175 unsigned long ptp_rx_msg_type_delay_resp;176 unsigned long ptp_rx_msg_type_pdelay_req;177 unsigned long ptp_rx_msg_type_pdelay_resp;178 unsigned long ptp_rx_msg_type_pdelay_follow_up;179 unsigned long ptp_rx_msg_type_announce;180 unsigned long ptp_rx_msg_type_management;181 unsigned long ptp_rx_msg_pkt_reserved_type;182 unsigned long ptp_frame_type;183 unsigned long ptp_ver;184 unsigned long timestamp_dropped;185 unsigned long av_pkt_rcvd;186 unsigned long av_tagged_pkt_rcvd;187 unsigned long vlan_tag_priority_val;188 unsigned long l3_filter_match;189 unsigned long l4_filter_match;190 unsigned long l3_l4_filter_no_match;191 /* PCS */192 unsigned long irq_pcs_ane_n;193 unsigned long irq_pcs_link_n;194 unsigned long irq_rgmii_n;195 unsigned long pcs_link;196 unsigned long pcs_duplex;197 unsigned long pcs_speed;198 /* debug register */199 unsigned long mtl_tx_status_fifo_full;200 unsigned long mtl_tx_fifo_not_empty;201 unsigned long mmtl_fifo_ctrl;202 unsigned long mtl_tx_fifo_read_ctrl_write;203 unsigned long mtl_tx_fifo_read_ctrl_wait;204 unsigned long mtl_tx_fifo_read_ctrl_read;205 unsigned long mtl_tx_fifo_read_ctrl_idle;206 unsigned long mac_tx_in_pause;207 unsigned long mac_tx_frame_ctrl_xfer;208 unsigned long mac_tx_frame_ctrl_idle;209 unsigned long mac_tx_frame_ctrl_wait;210 unsigned long mac_tx_frame_ctrl_pause;211 unsigned long mac_gmii_tx_proto_engine;212 unsigned long mtl_rx_fifo_fill_level_full;213 unsigned long mtl_rx_fifo_fill_above_thresh;214 unsigned long mtl_rx_fifo_fill_below_thresh;215 unsigned long mtl_rx_fifo_fill_level_empty;216 unsigned long mtl_rx_fifo_read_ctrl_flush;217 unsigned long mtl_rx_fifo_read_ctrl_read_data;218 unsigned long mtl_rx_fifo_read_ctrl_status;219 unsigned long mtl_rx_fifo_read_ctrl_idle;220 unsigned long mtl_rx_fifo_ctrl_active;221 unsigned long mac_rx_frame_ctrl_fifo;222 unsigned long mac_gmii_rx_proto_engine;223 /* EST */224 unsigned long mtl_est_cgce;225 unsigned long mtl_est_hlbs;226 unsigned long mtl_est_hlbf;227 unsigned long mtl_est_btre;228 unsigned long mtl_est_btrlm;229 unsigned long max_sdu_txq_drop[MTL_MAX_TX_QUEUES];230 unsigned long mtl_est_txq_hlbf[MTL_MAX_TX_QUEUES];231 /* per queue statistics */232 struct stmmac_txq_stats txq_stats[MTL_MAX_TX_QUEUES];233 struct stmmac_rxq_stats rxq_stats[MTL_MAX_RX_QUEUES];234 struct stmmac_pcpu_stats __percpu *pcpu_stats;235 unsigned long rx_dropped;236 unsigned long rx_errors;237 unsigned long tx_dropped;238 unsigned long tx_errors;239};240 241/* Safety Feature statistics exposed by ethtool */242struct stmmac_safety_stats {243 unsigned long mac_errors[32];244 unsigned long mtl_errors[32];245 unsigned long dma_errors[32];246 unsigned long dma_dpp_errors[32];247};248 249/* Number of fields in Safety Stats */250#define STMMAC_SAFETY_FEAT_SIZE \251 (sizeof(struct stmmac_safety_stats) / sizeof(unsigned long))252 253/* CSR Frequency Access Defines*/254#define CSR_F_35M 35000000255#define CSR_F_60M 60000000256#define CSR_F_100M 100000000257#define CSR_F_150M 150000000258#define CSR_F_250M 250000000259#define CSR_F_300M 300000000260 261#define MAC_CSR_H_FRQ_MASK 0x20262 263#define HASH_TABLE_SIZE 64264#define PAUSE_TIME 0xffff265 266/* Flow Control defines */267#define FLOW_OFF 0268#define FLOW_RX 1269#define FLOW_TX 2270#define FLOW_AUTO (FLOW_TX | FLOW_RX)271 272/* PCS defines */273#define STMMAC_PCS_RGMII (1 << 0)274#define STMMAC_PCS_SGMII (1 << 1)275 276#define SF_DMA_MODE 1 /* DMA STORE-AND-FORWARD Operation Mode */277 278/* DMA HW feature register fields */279#define DMA_HW_FEAT_MIISEL 0x00000001 /* 10/100 Mbps Support */280#define DMA_HW_FEAT_GMIISEL 0x00000002 /* 1000 Mbps Support */281#define DMA_HW_FEAT_HDSEL 0x00000004 /* Half-Duplex Support */282#define DMA_HW_FEAT_EXTHASHEN 0x00000008 /* Expanded DA Hash Filter */283#define DMA_HW_FEAT_HASHSEL 0x00000010 /* HASH Filter */284#define DMA_HW_FEAT_ADDMAC 0x00000020 /* Multiple MAC Addr Reg */285#define DMA_HW_FEAT_PCSSEL 0x00000040 /* PCS registers */286#define DMA_HW_FEAT_L3L4FLTREN 0x00000080 /* Layer 3 & Layer 4 Feature */287#define DMA_HW_FEAT_SMASEL 0x00000100 /* SMA(MDIO) Interface */288#define DMA_HW_FEAT_RWKSEL 0x00000200 /* PMT Remote Wakeup */289#define DMA_HW_FEAT_MGKSEL 0x00000400 /* PMT Magic Packet */290#define DMA_HW_FEAT_MMCSEL 0x00000800 /* RMON Module */291#define DMA_HW_FEAT_TSVER1SEL 0x00001000 /* Only IEEE 1588-2002 */292#define DMA_HW_FEAT_TSVER2SEL 0x00002000 /* IEEE 1588-2008 PTPv2 */293#define DMA_HW_FEAT_EEESEL 0x00004000 /* Energy Efficient Ethernet */294#define DMA_HW_FEAT_AVSEL 0x00008000 /* AV Feature */295#define DMA_HW_FEAT_TXCOESEL 0x00010000 /* Checksum Offload in Tx */296#define DMA_HW_FEAT_RXTYP1COE 0x00020000 /* IP COE (Type 1) in Rx */297#define DMA_HW_FEAT_RXTYP2COE 0x00040000 /* IP COE (Type 2) in Rx */298#define DMA_HW_FEAT_RXFIFOSIZE 0x00080000 /* Rx FIFO > 2048 Bytes */299#define DMA_HW_FEAT_RXCHCNT 0x00300000 /* No. additional Rx Channels */300#define DMA_HW_FEAT_TXCHCNT 0x00c00000 /* No. additional Tx Channels */301#define DMA_HW_FEAT_ENHDESSEL 0x01000000 /* Alternate Descriptor */302/* Timestamping with Internal System Time */303#define DMA_HW_FEAT_INTTSEN 0x02000000304#define DMA_HW_FEAT_FLEXIPPSEN 0x04000000 /* Flexible PPS Output */305#define DMA_HW_FEAT_SAVLANINS 0x08000000 /* Source Addr or VLAN */306#define DMA_HW_FEAT_ACTPHYIF 0x70000000 /* Active/selected PHY iface */307#define DEFAULT_DMA_PBL 8308 309/* MSI defines */310#define STMMAC_MSI_VEC_MAX 32311 312/* PCS status and mask defines */313#define PCS_ANE_IRQ BIT(2) /* PCS Auto-Negotiation */314#define PCS_LINK_IRQ BIT(1) /* PCS Link */315#define PCS_RGSMIIIS_IRQ BIT(0) /* RGMII or SMII Interrupt */316 317/* Max/Min RI Watchdog Timer count value */318#define MAX_DMA_RIWT 0xff319#define MIN_DMA_RIWT 0x10320#define DEF_DMA_RIWT 0xa0321/* Tx coalesce parameters */322#define STMMAC_COAL_TX_TIMER 5000323#define STMMAC_MAX_COAL_TX_TICK 100000324#define STMMAC_TX_MAX_FRAMES 256325#define STMMAC_TX_FRAMES 25326#define STMMAC_RX_FRAMES 0327 328/* Packets types */329enum packets_types {330 PACKET_AVCPQ = 0x1, /* AV Untagged Control packets */331 PACKET_PTPQ = 0x2, /* PTP Packets */332 PACKET_DCBCPQ = 0x3, /* DCB Control Packets */333 PACKET_UPQ = 0x4, /* Untagged Packets */334 PACKET_MCBCQ = 0x5, /* Multicast & Broadcast Packets */335};336 337/* Rx IPC status */338enum rx_frame_status {339 good_frame = 0x0,340 discard_frame = 0x1,341 csum_none = 0x2,342 llc_snap = 0x4,343 dma_own = 0x8,344 rx_not_ls = 0x10,345};346 347/* Tx status */348enum tx_frame_status {349 tx_done = 0x0,350 tx_not_ls = 0x1,351 tx_err = 0x2,352 tx_dma_own = 0x4,353 tx_err_bump_tc = 0x8,354};355 356enum dma_irq_status {357 tx_hard_error = 0x1,358 tx_hard_error_bump_tc = 0x2,359 handle_rx = 0x4,360 handle_tx = 0x8,361};362 363enum dma_irq_dir {364 DMA_DIR_RX = 0x1,365 DMA_DIR_TX = 0x2,366 DMA_DIR_RXTX = 0x3,367};368 369enum request_irq_err {370 REQ_IRQ_ERR_ALL,371 REQ_IRQ_ERR_TX,372 REQ_IRQ_ERR_RX,373 REQ_IRQ_ERR_SFTY,374 REQ_IRQ_ERR_SFTY_UE,375 REQ_IRQ_ERR_SFTY_CE,376 REQ_IRQ_ERR_LPI,377 REQ_IRQ_ERR_WOL,378 REQ_IRQ_ERR_MAC,379 REQ_IRQ_ERR_NO,380};381 382/* EEE and LPI defines */383#define CORE_IRQ_TX_PATH_IN_LPI_MODE (1 << 0)384#define CORE_IRQ_TX_PATH_EXIT_LPI_MODE (1 << 1)385#define CORE_IRQ_RX_PATH_IN_LPI_MODE (1 << 2)386#define CORE_IRQ_RX_PATH_EXIT_LPI_MODE (1 << 3)387 388/* FPE defines */389#define FPE_EVENT_UNKNOWN 0390#define FPE_EVENT_TRSP BIT(0)391#define FPE_EVENT_TVER BIT(1)392#define FPE_EVENT_RRSP BIT(2)393#define FPE_EVENT_RVER BIT(3)394 395#define CORE_IRQ_MTL_RX_OVERFLOW BIT(8)396 397/* Physical Coding Sublayer */398struct rgmii_adv {399 unsigned int pause;400 unsigned int duplex;401 unsigned int lp_pause;402 unsigned int lp_duplex;403};404 405#define STMMAC_PCS_PAUSE 1406#define STMMAC_PCS_ASYM_PAUSE 2407 408/* DMA HW capabilities */409struct dma_features {410 unsigned int mbps_10_100;411 unsigned int mbps_1000;412 unsigned int half_duplex;413 unsigned int hash_filter;414 unsigned int multi_addr;415 unsigned int pcs;416 unsigned int sma_mdio;417 unsigned int pmt_remote_wake_up;418 unsigned int pmt_magic_frame;419 unsigned int rmon;420 /* IEEE 1588-2002 */421 unsigned int time_stamp;422 /* IEEE 1588-2008 */423 unsigned int atime_stamp;424 /* 802.3az - Energy-Efficient Ethernet (EEE) */425 unsigned int eee;426 unsigned int av;427 unsigned int hash_tb_sz;428 unsigned int tsoen;429 /* TX and RX csum */430 unsigned int tx_coe;431 unsigned int rx_coe;432 unsigned int rx_coe_type1;433 unsigned int rx_coe_type2;434 unsigned int rxfifo_over_2048;435 /* TX and RX number of channels */436 unsigned int number_rx_channel;437 unsigned int number_tx_channel;438 /* TX and RX number of queues */439 unsigned int number_rx_queues;440 unsigned int number_tx_queues;441 /* PPS output */442 unsigned int pps_out_num;443 /* Number of Traffic Classes */444 unsigned int numtc;445 /* DCB Feature Enable */446 unsigned int dcben;447 /* IEEE 1588 High Word Register Enable */448 unsigned int advthword;449 /* PTP Offload Enable */450 unsigned int ptoen;451 /* One-Step Timestamping Enable */452 unsigned int osten;453 /* Priority-Based Flow Control Enable */454 unsigned int pfcen;455 /* Alternate (enhanced) DESC mode */456 unsigned int enh_desc;457 /* TX and RX FIFO sizes */458 unsigned int tx_fifo_size;459 unsigned int rx_fifo_size;460 /* Automotive Safety Package */461 unsigned int asp;462 /* RX Parser */463 unsigned int frpsel;464 unsigned int frpbs;465 unsigned int frpes;466 unsigned int addr64;467 unsigned int host_dma_width;468 unsigned int rssen;469 unsigned int vlhash;470 unsigned int sphen;471 unsigned int vlins;472 unsigned int dvlan;473 unsigned int l3l4fnum;474 unsigned int arpoffsel;475 /* One Step for PTP over UDP/IP Feature Enable */476 unsigned int pou_ost_en;477 /* Tx Timestamp FIFO Depth */478 unsigned int ttsfd;479 /* Queue/Channel-Based VLAN tag insertion on Tx */480 unsigned int cbtisel;481 /* Supported Parallel Instruction Processor Engines */482 unsigned int frppipe_num;483 /* Number of Extended VLAN Tag Filters */484 unsigned int nrvf_num;485 /* TSN Features */486 unsigned int estwid;487 unsigned int estdep;488 unsigned int estsel;489 unsigned int fpesel;490 unsigned int tbssel;491 /* Number of DMA channels enabled for TBS */492 unsigned int tbs_ch_num;493 /* Per-Stream Filtering Enable */494 unsigned int sgfsel;495 /* Numbers of Auxiliary Snapshot Inputs */496 unsigned int aux_snapshot_n;497 /* Timestamp System Time Source */498 unsigned int tssrc;499 /* Enhanced DMA Enable */500 unsigned int edma;501 /* Different Descriptor Cache Enable */502 unsigned int ediffc;503 /* VxLAN/NVGRE Enable */504 unsigned int vxn;505 /* Debug Memory Interface Enable */506 unsigned int dbgmem;507 /* Number of Policing Counters */508 unsigned int pcsel;509};510 511/* RX Buffer size must be multiple of 4/8/16 bytes */512#define BUF_SIZE_16KiB 16368513#define BUF_SIZE_8KiB 8188514#define BUF_SIZE_4KiB 4096515#define BUF_SIZE_2KiB 2048516 517/* Power Down and WOL */518#define PMT_NOT_SUPPORTED 0519#define PMT_SUPPORTED 1520 521/* Common MAC defines */522#define MAC_CTRL_REG 0x00000000 /* MAC Control */523#define MAC_ENABLE_TX 0x00000008 /* Transmitter Enable */524#define MAC_ENABLE_RX 0x00000004 /* Receiver Enable */525 526/* Default LPI timers */527#define STMMAC_DEFAULT_LIT_LS 0x3E8528#define STMMAC_DEFAULT_TWT_LS 0x1E529#define STMMAC_ET_MAX 0xFFFFF530 531#define STMMAC_CHAIN_MODE 0x1532#define STMMAC_RING_MODE 0x2533 534#define JUMBO_LEN 9000535 536/* Receive Side Scaling */537#define STMMAC_RSS_HASH_KEY_SIZE 40538#define STMMAC_RSS_MAX_TABLE_SIZE 256539 540/* VLAN */541#define STMMAC_VLAN_NONE 0x0542#define STMMAC_VLAN_REMOVE 0x1543#define STMMAC_VLAN_INSERT 0x2544#define STMMAC_VLAN_REPLACE 0x3545 546extern const struct stmmac_desc_ops enh_desc_ops;547extern const struct stmmac_desc_ops ndesc_ops;548 549struct mac_device_info;550 551extern const struct stmmac_hwtimestamp stmmac_ptp;552extern const struct stmmac_mode_ops dwmac4_ring_mode_ops;553 554struct mac_link {555 u32 caps;556 u32 speed_mask;557 u32 speed10;558 u32 speed100;559 u32 speed1000;560 u32 speed2500;561 u32 duplex;562 struct {563 u32 speed2500;564 u32 speed5000;565 u32 speed10000;566 } xgmii;567 struct {568 u32 speed25000;569 u32 speed40000;570 u32 speed50000;571 u32 speed100000;572 } xlgmii;573};574 575struct mii_regs {576 unsigned int addr; /* MII Address */577 unsigned int data; /* MII Data */578 unsigned int addr_shift; /* MII address shift */579 unsigned int reg_shift; /* MII reg shift */580 unsigned int addr_mask; /* MII address mask */581 unsigned int reg_mask; /* MII reg mask */582 unsigned int clk_csr_shift;583 unsigned int clk_csr_mask;584};585 586struct mac_device_info {587 const struct stmmac_ops *mac;588 const struct stmmac_desc_ops *desc;589 const struct stmmac_dma_ops *dma;590 const struct stmmac_mode_ops *mode;591 const struct stmmac_hwtimestamp *ptp;592 const struct stmmac_tc_ops *tc;593 const struct stmmac_mmc_ops *mmc;594 const struct stmmac_est_ops *est;595 struct dw_xpcs *xpcs;596 struct phylink_pcs *phylink_pcs;597 struct mii_regs mii; /* MII register Addresses */598 struct mac_link link;599 void __iomem *pcsr; /* vpointer to device CSRs */600 unsigned int multicast_filter_bins;601 unsigned int unicast_filter_entries;602 unsigned int mcast_bits_log2;603 unsigned int rx_csum;604 unsigned int pcs;605 unsigned int pmt;606 unsigned int ps;607 unsigned int xlgmac;608 unsigned int num_vlan;609 u32 vlan_filter[32];610 bool vlan_fail_q_en;611 u8 vlan_fail_q;612 bool hw_vlan_en;613};614 615struct stmmac_rx_routing {616 u32 reg_mask;617 u32 reg_shift;618};619 620int dwmac100_setup(struct stmmac_priv *priv);621int dwmac1000_setup(struct stmmac_priv *priv);622int dwmac4_setup(struct stmmac_priv *priv);623int dwxgmac2_setup(struct stmmac_priv *priv);624int dwxlgmac2_setup(struct stmmac_priv *priv);625 626void stmmac_set_mac_addr(void __iomem *ioaddr, const u8 addr[6],627 unsigned int high, unsigned int low);628void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,629 unsigned int high, unsigned int low);630void stmmac_set_mac(void __iomem *ioaddr, bool enable);631 632void stmmac_dwmac4_set_mac_addr(void __iomem *ioaddr, const u8 addr[6],633 unsigned int high, unsigned int low);634void stmmac_dwmac4_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,635 unsigned int high, unsigned int low);636void stmmac_dwmac4_set_mac(void __iomem *ioaddr, bool enable);637 638void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr);639 640extern const struct stmmac_mode_ops ring_mode_ops;641extern const struct stmmac_mode_ops chain_mode_ops;642extern const struct stmmac_desc_ops dwmac4_desc_ops;643 644#endif /* __COMMON_H__ */645