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1// SPDX-License-Identifier: GPL-2.0-only2/*3 * dwmac-stm32.c - DWMAC Specific Glue layer for STM32 MCU4 *5 * Copyright (C) STMicroelectronics SA 20176 * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.7 */8 9#include <linux/clk.h>10#include <linux/kernel.h>11#include <linux/mfd/syscon.h>12#include <linux/module.h>13#include <linux/of.h>14#include <linux/of_net.h>15#include <linux/phy.h>16#include <linux/platform_device.h>17#include <linux/pm_wakeirq.h>18#include <linux/regmap.h>19#include <linux/slab.h>20#include <linux/stmmac.h>21 22#include "stmmac_platform.h"23 24#define SYSCFG_MCU_ETH_MASK BIT(23)25#define SYSCFG_MP1_ETH_MASK GENMASK(23, 16)26#define SYSCFG_PMCCLRR_OFFSET 0x4027 28#define SYSCFG_PMCR_ETH_CLK_SEL BIT(16)29#define SYSCFG_PMCR_ETH_REF_CLK_SEL BIT(17)30 31/* CLOCK feed to PHY*/32#define ETH_CK_F_25M 2500000033#define ETH_CK_F_50M 5000000034#define ETH_CK_F_125M 12500000035 36/* Ethernet PHY interface selection in register SYSCFG Configuration37 *------------------------------------------38 * src |BIT(23)| BIT(22)| BIT(21)|BIT(20)|39 *------------------------------------------40 * MII | 0 | 0 | 0 | 1 |41 *------------------------------------------42 * GMII | 0 | 0 | 0 | 0 |43 *------------------------------------------44 * RGMII | 0 | 0 | 1 | n/a |45 *------------------------------------------46 * RMII | 1 | 0 | 0 | n/a |47 *------------------------------------------48 */49#define SYSCFG_PMCR_ETH_SEL_MII BIT(20)50#define SYSCFG_PMCR_ETH_SEL_RGMII BIT(21)51#define SYSCFG_PMCR_ETH_SEL_RMII BIT(23)52#define SYSCFG_PMCR_ETH_SEL_GMII 053#define SYSCFG_MCU_ETH_SEL_MII 054#define SYSCFG_MCU_ETH_SEL_RMII 155 56/* STM32MP2 register definitions */57#define SYSCFG_MP2_ETH_MASK GENMASK(31, 0)58 59#define SYSCFG_ETHCR_ETH_PTP_CLK_SEL BIT(2)60#define SYSCFG_ETHCR_ETH_CLK_SEL BIT(1)61#define SYSCFG_ETHCR_ETH_REF_CLK_SEL BIT(0)62 63#define SYSCFG_ETHCR_ETH_SEL_MII 064#define SYSCFG_ETHCR_ETH_SEL_RGMII BIT(4)65#define SYSCFG_ETHCR_ETH_SEL_RMII BIT(6)66 67/* STM32MPx register definitions68 *69 * Below table summarizes the clock requirement and clock sources for70 * supported phy interface modes.71 * __________________________________________________________________________72 *|PHY_MODE | Normal | PHY wo crystal| PHY wo crystal |No 125MHz from PHY|73 *| | | 25MHz | 50MHz | |74 * ---------------------------------------------------------------------------75 *| MII | - | eth-ck | n/a | n/a |76 *| | | st,ext-phyclk | | |77 * ---------------------------------------------------------------------------78 *| GMII | - | eth-ck | n/a | n/a |79 *| | | st,ext-phyclk | | |80 * ---------------------------------------------------------------------------81 *| RGMII | - | eth-ck | n/a | eth-ck |82 *| | | st,ext-phyclk | | st,eth-clk-sel or|83 *| | | | | st,ext-phyclk |84 * ---------------------------------------------------------------------------85 *| RMII | - | eth-ck | eth-ck | n/a |86 *| | | st,ext-phyclk | st,eth-ref-clk-sel | |87 *| | | | or st,ext-phyclk | |88 * ---------------------------------------------------------------------------89 *90 */91 92struct stm32_dwmac {93 struct clk *clk_tx;94 struct clk *clk_rx;95 struct clk *clk_eth_ck;96 struct clk *clk_ethstp;97 struct clk *syscfg_clk;98 int ext_phyclk;99 int enable_eth_ck;100 int eth_clk_sel_reg;101 int eth_ref_clk_sel_reg;102 int irq_pwr_wakeup;103 u32 mode_reg; /* MAC glue-logic mode register */104 u32 mode_mask;105 struct regmap *regmap;106 u32 speed;107 const struct stm32_ops *ops;108 struct device *dev;109};110 111struct stm32_ops {112 int (*set_mode)(struct plat_stmmacenet_data *plat_dat);113 int (*suspend)(struct stm32_dwmac *dwmac);114 void (*resume)(struct stm32_dwmac *dwmac);115 int (*parse_data)(struct stm32_dwmac *dwmac,116 struct device *dev);117 bool clk_rx_enable_in_suspend;118 bool is_mp13, is_mp2;119 u32 syscfg_clr_off;120};121 122static int stm32_dwmac_clk_enable(struct stm32_dwmac *dwmac, bool resume)123{124 int ret;125 126 ret = clk_prepare_enable(dwmac->clk_tx);127 if (ret)128 goto err_clk_tx;129 130 if (!dwmac->ops->clk_rx_enable_in_suspend || !resume) {131 ret = clk_prepare_enable(dwmac->clk_rx);132 if (ret)133 goto err_clk_rx;134 }135 136 ret = clk_prepare_enable(dwmac->syscfg_clk);137 if (ret)138 goto err_syscfg_clk;139 140 if (dwmac->enable_eth_ck) {141 ret = clk_prepare_enable(dwmac->clk_eth_ck);142 if (ret)143 goto err_clk_eth_ck;144 }145 146 return ret;147 148err_clk_eth_ck:149 clk_disable_unprepare(dwmac->syscfg_clk);150err_syscfg_clk:151 if (!dwmac->ops->clk_rx_enable_in_suspend || !resume)152 clk_disable_unprepare(dwmac->clk_rx);153err_clk_rx:154 clk_disable_unprepare(dwmac->clk_tx);155err_clk_tx:156 return ret;157}158 159static int stm32_dwmac_init(struct plat_stmmacenet_data *plat_dat, bool resume)160{161 struct stm32_dwmac *dwmac = plat_dat->bsp_priv;162 int ret;163 164 if (dwmac->ops->set_mode) {165 ret = dwmac->ops->set_mode(plat_dat);166 if (ret)167 return ret;168 }169 170 return stm32_dwmac_clk_enable(dwmac, resume);171}172 173static int stm32mp1_select_ethck_external(struct plat_stmmacenet_data *plat_dat)174{175 struct stm32_dwmac *dwmac = plat_dat->bsp_priv;176 177 switch (plat_dat->mac_interface) {178 case PHY_INTERFACE_MODE_MII:179 dwmac->enable_eth_ck = dwmac->ext_phyclk;180 return 0;181 case PHY_INTERFACE_MODE_GMII:182 dwmac->enable_eth_ck = dwmac->eth_clk_sel_reg ||183 dwmac->ext_phyclk;184 return 0;185 case PHY_INTERFACE_MODE_RMII:186 dwmac->enable_eth_ck = dwmac->eth_ref_clk_sel_reg ||187 dwmac->ext_phyclk;188 return 0;189 case PHY_INTERFACE_MODE_RGMII:190 case PHY_INTERFACE_MODE_RGMII_ID:191 case PHY_INTERFACE_MODE_RGMII_RXID:192 case PHY_INTERFACE_MODE_RGMII_TXID:193 dwmac->enable_eth_ck = dwmac->eth_clk_sel_reg ||194 dwmac->ext_phyclk;195 return 0;196 default:197 dwmac->enable_eth_ck = false;198 dev_err(dwmac->dev, "Mode %s not supported",199 phy_modes(plat_dat->mac_interface));200 return -EINVAL;201 }202}203 204static int stm32mp1_validate_ethck_rate(struct plat_stmmacenet_data *plat_dat)205{206 struct stm32_dwmac *dwmac = plat_dat->bsp_priv;207 const u32 clk_rate = clk_get_rate(dwmac->clk_eth_ck);208 209 if (!dwmac->enable_eth_ck)210 return 0;211 212 switch (plat_dat->mac_interface) {213 case PHY_INTERFACE_MODE_MII:214 case PHY_INTERFACE_MODE_GMII:215 if (clk_rate == ETH_CK_F_25M)216 return 0;217 break;218 case PHY_INTERFACE_MODE_RMII:219 if (clk_rate == ETH_CK_F_25M || clk_rate == ETH_CK_F_50M)220 return 0;221 break;222 case PHY_INTERFACE_MODE_RGMII:223 case PHY_INTERFACE_MODE_RGMII_ID:224 case PHY_INTERFACE_MODE_RGMII_RXID:225 case PHY_INTERFACE_MODE_RGMII_TXID:226 if (clk_rate == ETH_CK_F_25M || clk_rate == ETH_CK_F_125M)227 return 0;228 break;229 default:230 break;231 }232 233 dev_err(dwmac->dev, "Mode %s does not match eth-ck frequency %d Hz",234 phy_modes(plat_dat->mac_interface), clk_rate);235 return -EINVAL;236}237 238static int stm32mp1_configure_pmcr(struct plat_stmmacenet_data *plat_dat)239{240 struct stm32_dwmac *dwmac = plat_dat->bsp_priv;241 u32 reg = dwmac->mode_reg;242 int val = 0;243 244 switch (plat_dat->mac_interface) {245 case PHY_INTERFACE_MODE_MII:246 /*247 * STM32MP15xx supports both MII and GMII, STM32MP13xx MII only.248 * SYSCFG_PMCSETR ETH_SELMII is present only on STM32MP15xx and249 * acts as a selector between 0:GMII and 1:MII. As STM32MP13xx250 * supports only MII, ETH_SELMII is not present.251 */252 if (!dwmac->ops->is_mp13) /* Select MII mode on STM32MP15xx */253 val |= SYSCFG_PMCR_ETH_SEL_MII;254 break;255 case PHY_INTERFACE_MODE_GMII:256 val = SYSCFG_PMCR_ETH_SEL_GMII;257 if (dwmac->enable_eth_ck)258 val |= SYSCFG_PMCR_ETH_CLK_SEL;259 break;260 case PHY_INTERFACE_MODE_RMII:261 val = SYSCFG_PMCR_ETH_SEL_RMII;262 if (dwmac->enable_eth_ck)263 val |= SYSCFG_PMCR_ETH_REF_CLK_SEL;264 break;265 case PHY_INTERFACE_MODE_RGMII:266 case PHY_INTERFACE_MODE_RGMII_ID:267 case PHY_INTERFACE_MODE_RGMII_RXID:268 case PHY_INTERFACE_MODE_RGMII_TXID:269 val = SYSCFG_PMCR_ETH_SEL_RGMII;270 if (dwmac->enable_eth_ck)271 val |= SYSCFG_PMCR_ETH_CLK_SEL;272 break;273 default:274 dev_err(dwmac->dev, "Mode %s not supported",275 phy_modes(plat_dat->mac_interface));276 /* Do not manage others interfaces */277 return -EINVAL;278 }279 280 dev_dbg(dwmac->dev, "Mode %s", phy_modes(plat_dat->mac_interface));281 282 /* Shift value at correct ethernet MAC offset in SYSCFG_PMCSETR */283 val <<= ffs(dwmac->mode_mask) - ffs(SYSCFG_MP1_ETH_MASK);284 285 /* Need to update PMCCLRR (clear register) */286 regmap_write(dwmac->regmap, dwmac->ops->syscfg_clr_off,287 dwmac->mode_mask);288 289 /* Update PMCSETR (set register) */290 return regmap_update_bits(dwmac->regmap, reg,291 dwmac->mode_mask, val);292}293 294static int stm32mp2_configure_syscfg(struct plat_stmmacenet_data *plat_dat)295{296 struct stm32_dwmac *dwmac = plat_dat->bsp_priv;297 u32 reg = dwmac->mode_reg;298 int val = 0;299 300 switch (plat_dat->mac_interface) {301 case PHY_INTERFACE_MODE_MII:302 /* ETH_REF_CLK_SEL bit in SYSCFG register is not applicable in MII mode */303 break;304 case PHY_INTERFACE_MODE_RMII:305 val = SYSCFG_ETHCR_ETH_SEL_RMII;306 if (dwmac->enable_eth_ck) {307 /* Internal clock ETH_CLK of 50MHz from RCC is used */308 val |= SYSCFG_ETHCR_ETH_REF_CLK_SEL;309 }310 break;311 case PHY_INTERFACE_MODE_RGMII:312 case PHY_INTERFACE_MODE_RGMII_ID:313 case PHY_INTERFACE_MODE_RGMII_RXID:314 case PHY_INTERFACE_MODE_RGMII_TXID:315 val = SYSCFG_ETHCR_ETH_SEL_RGMII;316 fallthrough;317 case PHY_INTERFACE_MODE_GMII:318 if (dwmac->enable_eth_ck) {319 /* Internal clock ETH_CLK of 125MHz from RCC is used */320 val |= SYSCFG_ETHCR_ETH_CLK_SEL;321 }322 break;323 default:324 dev_err(dwmac->dev, "Mode %s not supported",325 phy_modes(plat_dat->mac_interface));326 /* Do not manage others interfaces */327 return -EINVAL;328 }329 330 dev_dbg(dwmac->dev, "Mode %s", phy_modes(plat_dat->mac_interface));331 332 /* Select PTP (IEEE1588) clock selection from RCC (ck_ker_ethxptp) */333 val |= SYSCFG_ETHCR_ETH_PTP_CLK_SEL;334 335 /* Update ETHCR (set register) */336 return regmap_update_bits(dwmac->regmap, reg,337 SYSCFG_MP2_ETH_MASK, val);338}339 340static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat)341{342 struct stm32_dwmac *dwmac = plat_dat->bsp_priv;343 int ret;344 345 ret = stm32mp1_select_ethck_external(plat_dat);346 if (ret)347 return ret;348 349 ret = stm32mp1_validate_ethck_rate(plat_dat);350 if (ret)351 return ret;352 353 if (!dwmac->ops->is_mp2)354 return stm32mp1_configure_pmcr(plat_dat);355 else356 return stm32mp2_configure_syscfg(plat_dat);357}358 359static int stm32mcu_set_mode(struct plat_stmmacenet_data *plat_dat)360{361 struct stm32_dwmac *dwmac = plat_dat->bsp_priv;362 u32 reg = dwmac->mode_reg;363 int val;364 365 switch (plat_dat->mac_interface) {366 case PHY_INTERFACE_MODE_MII:367 val = SYSCFG_MCU_ETH_SEL_MII;368 break;369 case PHY_INTERFACE_MODE_RMII:370 val = SYSCFG_MCU_ETH_SEL_RMII;371 break;372 default:373 dev_err(dwmac->dev, "Mode %s not supported",374 phy_modes(plat_dat->mac_interface));375 /* Do not manage others interfaces */376 return -EINVAL;377 }378 379 dev_dbg(dwmac->dev, "Mode %s", phy_modes(plat_dat->mac_interface));380 381 return regmap_update_bits(dwmac->regmap, reg,382 SYSCFG_MCU_ETH_MASK, val << 23);383}384 385static void stm32_dwmac_clk_disable(struct stm32_dwmac *dwmac, bool suspend)386{387 clk_disable_unprepare(dwmac->clk_tx);388 if (!dwmac->ops->clk_rx_enable_in_suspend || !suspend)389 clk_disable_unprepare(dwmac->clk_rx);390 391 clk_disable_unprepare(dwmac->syscfg_clk);392 if (dwmac->enable_eth_ck)393 clk_disable_unprepare(dwmac->clk_eth_ck);394}395 396static int stm32_dwmac_parse_data(struct stm32_dwmac *dwmac,397 struct device *dev)398{399 struct device_node *np = dev->of_node;400 int err;401 402 /* Get TX/RX clocks */403 dwmac->clk_tx = devm_clk_get(dev, "mac-clk-tx");404 if (IS_ERR(dwmac->clk_tx)) {405 dev_err(dev, "No ETH Tx clock provided...\n");406 return PTR_ERR(dwmac->clk_tx);407 }408 409 dwmac->clk_rx = devm_clk_get(dev, "mac-clk-rx");410 if (IS_ERR(dwmac->clk_rx)) {411 dev_err(dev, "No ETH Rx clock provided...\n");412 return PTR_ERR(dwmac->clk_rx);413 }414 415 if (dwmac->ops->parse_data) {416 err = dwmac->ops->parse_data(dwmac, dev);417 if (err)418 return err;419 }420 421 /* Get mode register */422 dwmac->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscon");423 if (IS_ERR(dwmac->regmap))424 return PTR_ERR(dwmac->regmap);425 426 err = of_property_read_u32_index(np, "st,syscon", 1, &dwmac->mode_reg);427 if (err) {428 dev_err(dev, "Can't get sysconfig mode offset (%d)\n", err);429 return err;430 }431 432 if (dwmac->ops->is_mp2)433 return 0;434 435 dwmac->mode_mask = SYSCFG_MP1_ETH_MASK;436 err = of_property_read_u32_index(np, "st,syscon", 2, &dwmac->mode_mask);437 if (err) {438 if (dwmac->ops->is_mp13) {439 dev_err(dev, "Sysconfig register mask must be set (%d)\n", err);440 } else {441 dev_dbg(dev, "Warning sysconfig register mask not set\n");442 err = 0;443 }444 }445 446 return err;447}448 449static int stm32mp1_parse_data(struct stm32_dwmac *dwmac,450 struct device *dev)451{452 struct platform_device *pdev = to_platform_device(dev);453 struct device_node *np = dev->of_node;454 int err = 0;455 456 /* Ethernet PHY have no crystal */457 dwmac->ext_phyclk = of_property_read_bool(np, "st,ext-phyclk");458 459 /* Gigabit Ethernet 125MHz clock selection. */460 dwmac->eth_clk_sel_reg = of_property_read_bool(np, "st,eth-clk-sel");461 462 /* Ethernet 50MHz RMII clock selection */463 dwmac->eth_ref_clk_sel_reg =464 of_property_read_bool(np, "st,eth-ref-clk-sel");465 466 /* Get ETH_CLK clocks */467 dwmac->clk_eth_ck = devm_clk_get(dev, "eth-ck");468 if (IS_ERR(dwmac->clk_eth_ck)) {469 dev_info(dev, "No phy clock provided...\n");470 dwmac->clk_eth_ck = NULL;471 }472 473 /* Clock used for low power mode */474 dwmac->clk_ethstp = devm_clk_get(dev, "ethstp");475 if (IS_ERR(dwmac->clk_ethstp)) {476 dev_err(dev,477 "No ETH peripheral clock provided for CStop mode ...\n");478 return PTR_ERR(dwmac->clk_ethstp);479 }480 481 /* Optional Clock for sysconfig */482 dwmac->syscfg_clk = devm_clk_get(dev, "syscfg-clk");483 if (IS_ERR(dwmac->syscfg_clk))484 dwmac->syscfg_clk = NULL;485 486 /* Get IRQ information early to have an ability to ask for deferred487 * probe if needed before we went too far with resource allocation.488 */489 dwmac->irq_pwr_wakeup = platform_get_irq_byname_optional(pdev,490 "stm32_pwr_wakeup");491 if (dwmac->irq_pwr_wakeup == -EPROBE_DEFER)492 return -EPROBE_DEFER;493 494 if (!dwmac->clk_eth_ck && dwmac->irq_pwr_wakeup >= 0) {495 err = device_init_wakeup(&pdev->dev, true);496 if (err) {497 dev_err(&pdev->dev, "Failed to init wake up irq\n");498 return err;499 }500 err = dev_pm_set_dedicated_wake_irq(&pdev->dev,501 dwmac->irq_pwr_wakeup);502 if (err) {503 dev_err(&pdev->dev, "Failed to set wake up irq\n");504 device_init_wakeup(&pdev->dev, false);505 }506 device_set_wakeup_enable(&pdev->dev, false);507 }508 return err;509}510 511static int stm32_dwmac_probe(struct platform_device *pdev)512{513 struct plat_stmmacenet_data *plat_dat;514 struct stmmac_resources stmmac_res;515 struct stm32_dwmac *dwmac;516 const struct stm32_ops *data;517 int ret;518 519 ret = stmmac_get_platform_resources(pdev, &stmmac_res);520 if (ret)521 return ret;522 523 plat_dat = devm_stmmac_probe_config_dt(pdev, stmmac_res.mac);524 if (IS_ERR(plat_dat))525 return PTR_ERR(plat_dat);526 527 dwmac = devm_kzalloc(&pdev->dev, sizeof(*dwmac), GFP_KERNEL);528 if (!dwmac)529 return -ENOMEM;530 531 data = of_device_get_match_data(&pdev->dev);532 if (!data) {533 dev_err(&pdev->dev, "no of match data provided\n");534 return -EINVAL;535 }536 537 dwmac->ops = data;538 dwmac->dev = &pdev->dev;539 540 ret = stm32_dwmac_parse_data(dwmac, &pdev->dev);541 if (ret) {542 dev_err(&pdev->dev, "Unable to parse OF data\n");543 return ret;544 }545 546 plat_dat->bsp_priv = dwmac;547 548 ret = stm32_dwmac_init(plat_dat, false);549 if (ret)550 return ret;551 552 ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);553 if (ret)554 goto err_clk_disable;555 556 return 0;557 558err_clk_disable:559 stm32_dwmac_clk_disable(dwmac, false);560 561 return ret;562}563 564static void stm32_dwmac_remove(struct platform_device *pdev)565{566 struct net_device *ndev = platform_get_drvdata(pdev);567 struct stmmac_priv *priv = netdev_priv(ndev);568 struct stm32_dwmac *dwmac = priv->plat->bsp_priv;569 570 stmmac_dvr_remove(&pdev->dev);571 572 stm32_dwmac_clk_disable(dwmac, false);573 574 if (dwmac->irq_pwr_wakeup >= 0) {575 dev_pm_clear_wake_irq(&pdev->dev);576 device_init_wakeup(&pdev->dev, false);577 }578}579 580static int stm32mp1_suspend(struct stm32_dwmac *dwmac)581{582 return clk_prepare_enable(dwmac->clk_ethstp);583}584 585static void stm32mp1_resume(struct stm32_dwmac *dwmac)586{587 clk_disable_unprepare(dwmac->clk_ethstp);588}589 590#ifdef CONFIG_PM_SLEEP591static int stm32_dwmac_suspend(struct device *dev)592{593 struct net_device *ndev = dev_get_drvdata(dev);594 struct stmmac_priv *priv = netdev_priv(ndev);595 struct stm32_dwmac *dwmac = priv->plat->bsp_priv;596 597 int ret;598 599 ret = stmmac_suspend(dev);600 if (ret)601 return ret;602 603 stm32_dwmac_clk_disable(dwmac, true);604 605 if (dwmac->ops->suspend)606 ret = dwmac->ops->suspend(dwmac);607 608 return ret;609}610 611static int stm32_dwmac_resume(struct device *dev)612{613 struct net_device *ndev = dev_get_drvdata(dev);614 struct stmmac_priv *priv = netdev_priv(ndev);615 struct stm32_dwmac *dwmac = priv->plat->bsp_priv;616 int ret;617 618 if (dwmac->ops->resume)619 dwmac->ops->resume(dwmac);620 621 ret = stm32_dwmac_init(priv->plat, true);622 if (ret)623 return ret;624 625 ret = stmmac_resume(dev);626 627 return ret;628}629#endif /* CONFIG_PM_SLEEP */630 631static SIMPLE_DEV_PM_OPS(stm32_dwmac_pm_ops,632 stm32_dwmac_suspend, stm32_dwmac_resume);633 634static struct stm32_ops stm32mcu_dwmac_data = {635 .set_mode = stm32mcu_set_mode636};637 638static struct stm32_ops stm32mp1_dwmac_data = {639 .set_mode = stm32mp1_set_mode,640 .suspend = stm32mp1_suspend,641 .resume = stm32mp1_resume,642 .parse_data = stm32mp1_parse_data,643 .syscfg_clr_off = 0x44,644 .is_mp13 = false,645 .clk_rx_enable_in_suspend = true646};647 648static struct stm32_ops stm32mp13_dwmac_data = {649 .set_mode = stm32mp1_set_mode,650 .suspend = stm32mp1_suspend,651 .resume = stm32mp1_resume,652 .parse_data = stm32mp1_parse_data,653 .syscfg_clr_off = 0x08,654 .is_mp13 = true,655 .clk_rx_enable_in_suspend = true656};657 658static struct stm32_ops stm32mp25_dwmac_data = {659 .set_mode = stm32mp1_set_mode,660 .suspend = stm32mp1_suspend,661 .resume = stm32mp1_resume,662 .parse_data = stm32mp1_parse_data,663 .is_mp2 = true,664 .clk_rx_enable_in_suspend = true665};666 667static const struct of_device_id stm32_dwmac_match[] = {668 { .compatible = "st,stm32-dwmac", .data = &stm32mcu_dwmac_data},669 { .compatible = "st,stm32mp1-dwmac", .data = &stm32mp1_dwmac_data},670 { .compatible = "st,stm32mp13-dwmac", .data = &stm32mp13_dwmac_data},671 { .compatible = "st,stm32mp25-dwmac", .data = &stm32mp25_dwmac_data},672 { }673};674MODULE_DEVICE_TABLE(of, stm32_dwmac_match);675 676static struct platform_driver stm32_dwmac_driver = {677 .probe = stm32_dwmac_probe,678 .remove_new = stm32_dwmac_remove,679 .driver = {680 .name = "stm32-dwmac",681 .pm = &stm32_dwmac_pm_ops,682 .of_match_table = stm32_dwmac_match,683 },684};685module_platform_driver(stm32_dwmac_driver);686 687MODULE_AUTHOR("Alexandre Torgue <alexandre.torgue@gmail.com>");688MODULE_AUTHOR("Christophe Roullier <christophe.roullier@st.com>");689MODULE_DESCRIPTION("STMicroelectronics STM32 DWMAC Specific Glue layer");690MODULE_LICENSE("GPL v2");691