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1// SPDX-License-Identifier: GPL-2.0-only2/*3 * This contains the functions to handle the descriptors for DesignWare databook4 * 4.xx.5 *6 * Copyright (C) 2015 STMicroelectronics Ltd7 *8 * Author: Alexandre Torgue <alexandre.torgue@st.com>9 */10 11#include <linux/stmmac.h>12#include "common.h"13#include "dwmac4.h"14#include "dwmac4_descs.h"15 16static int dwmac4_wrback_get_tx_status(struct stmmac_extra_stats *x,17 struct dma_desc *p,18 void __iomem *ioaddr)19{20 unsigned int tdes3;21 int ret = tx_done;22 23 tdes3 = le32_to_cpu(p->des3);24 25 /* Get tx owner first */26 if (unlikely(tdes3 & TDES3_OWN))27 return tx_dma_own;28 29 /* Verify tx error by looking at the last segment. */30 if (likely(!(tdes3 & TDES3_LAST_DESCRIPTOR)))31 return tx_not_ls;32 33 if (unlikely(tdes3 & TDES3_ERROR_SUMMARY)) {34 ret = tx_err;35 36 if (unlikely(tdes3 & TDES3_JABBER_TIMEOUT))37 x->tx_jabber++;38 if (unlikely(tdes3 & TDES3_PACKET_FLUSHED))39 x->tx_frame_flushed++;40 if (unlikely(tdes3 & TDES3_LOSS_CARRIER)) {41 x->tx_losscarrier++;42 }43 if (unlikely(tdes3 & TDES3_NO_CARRIER)) {44 x->tx_carrier++;45 }46 if (unlikely((tdes3 & TDES3_LATE_COLLISION) ||47 (tdes3 & TDES3_EXCESSIVE_COLLISION)))48 x->tx_collision +=49 (tdes3 & TDES3_COLLISION_COUNT_MASK)50 >> TDES3_COLLISION_COUNT_SHIFT;51 52 if (unlikely(tdes3 & TDES3_EXCESSIVE_DEFERRAL))53 x->tx_deferred++;54 55 if (unlikely(tdes3 & TDES3_UNDERFLOW_ERROR)) {56 x->tx_underflow++;57 ret |= tx_err_bump_tc;58 }59 60 if (unlikely(tdes3 & TDES3_IP_HDR_ERROR))61 x->tx_ip_header_error++;62 63 if (unlikely(tdes3 & TDES3_PAYLOAD_ERROR))64 x->tx_payload_error++;65 }66 67 if (unlikely(tdes3 & TDES3_DEFERRED))68 x->tx_deferred++;69 70 return ret;71}72 73static int dwmac4_wrback_get_rx_status(struct stmmac_extra_stats *x,74 struct dma_desc *p)75{76 unsigned int rdes1 = le32_to_cpu(p->des1);77 unsigned int rdes2 = le32_to_cpu(p->des2);78 unsigned int rdes3 = le32_to_cpu(p->des3);79 int message_type;80 int ret = good_frame;81 82 if (unlikely(rdes3 & RDES3_OWN))83 return dma_own;84 85 if (unlikely(rdes3 & RDES3_CONTEXT_DESCRIPTOR))86 return discard_frame;87 if (likely(!(rdes3 & RDES3_LAST_DESCRIPTOR)))88 return rx_not_ls;89 90 if (unlikely(rdes3 & RDES3_ERROR_SUMMARY)) {91 if (unlikely(rdes3 & RDES3_GIANT_PACKET))92 x->rx_length++;93 if (unlikely(rdes3 & RDES3_OVERFLOW_ERROR))94 x->rx_gmac_overflow++;95 96 if (unlikely(rdes3 & RDES3_RECEIVE_WATCHDOG))97 x->rx_watchdog++;98 99 if (unlikely(rdes3 & RDES3_RECEIVE_ERROR))100 x->rx_mii++;101 102 if (unlikely(rdes3 & RDES3_CRC_ERROR))103 x->rx_crc_errors++;104 105 if (unlikely(rdes3 & RDES3_DRIBBLE_ERROR))106 x->dribbling_bit++;107 108 ret = discard_frame;109 }110 111 message_type = (rdes1 & ERDES4_MSG_TYPE_MASK) >> 8;112 113 if (rdes1 & RDES1_IP_HDR_ERROR)114 x->ip_hdr_err++;115 if (rdes1 & RDES1_IP_CSUM_BYPASSED)116 x->ip_csum_bypassed++;117 if (rdes1 & RDES1_IPV4_HEADER)118 x->ipv4_pkt_rcvd++;119 if (rdes1 & RDES1_IPV6_HEADER)120 x->ipv6_pkt_rcvd++;121 122 if (message_type == RDES_EXT_NO_PTP)123 x->no_ptp_rx_msg_type_ext++;124 else if (message_type == RDES_EXT_SYNC)125 x->ptp_rx_msg_type_sync++;126 else if (message_type == RDES_EXT_FOLLOW_UP)127 x->ptp_rx_msg_type_follow_up++;128 else if (message_type == RDES_EXT_DELAY_REQ)129 x->ptp_rx_msg_type_delay_req++;130 else if (message_type == RDES_EXT_DELAY_RESP)131 x->ptp_rx_msg_type_delay_resp++;132 else if (message_type == RDES_EXT_PDELAY_REQ)133 x->ptp_rx_msg_type_pdelay_req++;134 else if (message_type == RDES_EXT_PDELAY_RESP)135 x->ptp_rx_msg_type_pdelay_resp++;136 else if (message_type == RDES_EXT_PDELAY_FOLLOW_UP)137 x->ptp_rx_msg_type_pdelay_follow_up++;138 else if (message_type == RDES_PTP_ANNOUNCE)139 x->ptp_rx_msg_type_announce++;140 else if (message_type == RDES_PTP_MANAGEMENT)141 x->ptp_rx_msg_type_management++;142 else if (message_type == RDES_PTP_PKT_RESERVED_TYPE)143 x->ptp_rx_msg_pkt_reserved_type++;144 145 if (rdes1 & RDES1_PTP_PACKET_TYPE)146 x->ptp_frame_type++;147 if (rdes1 & RDES1_PTP_VER)148 x->ptp_ver++;149 if (rdes1 & RDES1_TIMESTAMP_DROPPED)150 x->timestamp_dropped++;151 152 if (unlikely(rdes2 & RDES2_SA_FILTER_FAIL)) {153 x->sa_rx_filter_fail++;154 ret = discard_frame;155 }156 if (unlikely(rdes2 & RDES2_DA_FILTER_FAIL)) {157 x->da_rx_filter_fail++;158 ret = discard_frame;159 }160 161 if (rdes2 & RDES2_L3_FILTER_MATCH)162 x->l3_filter_match++;163 if (rdes2 & RDES2_L4_FILTER_MATCH)164 x->l4_filter_match++;165 if ((rdes2 & RDES2_L3_L4_FILT_NB_MATCH_MASK)166 >> RDES2_L3_L4_FILT_NB_MATCH_SHIFT)167 x->l3_l4_filter_no_match++;168 169 return ret;170}171 172static int dwmac4_rd_get_tx_len(struct dma_desc *p)173{174 return (le32_to_cpu(p->des2) & TDES2_BUFFER1_SIZE_MASK);175}176 177static int dwmac4_get_tx_owner(struct dma_desc *p)178{179 return (le32_to_cpu(p->des3) & TDES3_OWN) >> TDES3_OWN_SHIFT;180}181 182static void dwmac4_set_tx_owner(struct dma_desc *p)183{184 p->des3 |= cpu_to_le32(TDES3_OWN);185}186 187static void dwmac4_set_rx_owner(struct dma_desc *p, int disable_rx_ic)188{189 u32 flags = (RDES3_OWN | RDES3_BUFFER1_VALID_ADDR);190 191 if (!disable_rx_ic)192 flags |= RDES3_INT_ON_COMPLETION_EN;193 194 p->des3 |= cpu_to_le32(flags);195}196 197static int dwmac4_get_tx_ls(struct dma_desc *p)198{199 return (le32_to_cpu(p->des3) & TDES3_LAST_DESCRIPTOR)200 >> TDES3_LAST_DESCRIPTOR_SHIFT;201}202 203static u16 dwmac4_wrback_get_rx_vlan_tci(struct dma_desc *p)204{205 return (le32_to_cpu(p->des0) & RDES0_VLAN_TAG_MASK);206}207 208static bool dwmac4_wrback_get_rx_vlan_valid(struct dma_desc *p)209{210 return ((le32_to_cpu(p->des3) & RDES3_LAST_DESCRIPTOR) &&211 (le32_to_cpu(p->des3) & RDES3_RDES0_VALID));212}213 214static int dwmac4_wrback_get_rx_frame_len(struct dma_desc *p, int rx_coe)215{216 return (le32_to_cpu(p->des3) & RDES3_PACKET_SIZE_MASK);217}218 219static void dwmac4_rd_enable_tx_timestamp(struct dma_desc *p)220{221 p->des2 |= cpu_to_le32(TDES2_TIMESTAMP_ENABLE);222}223 224static int dwmac4_wrback_get_tx_timestamp_status(struct dma_desc *p)225{226 /* Context type from W/B descriptor must be zero */227 if (le32_to_cpu(p->des3) & TDES3_CONTEXT_TYPE)228 return 0;229 230 /* Tx Timestamp Status is 1 so des0 and des1'll have valid values */231 if (le32_to_cpu(p->des3) & TDES3_TIMESTAMP_STATUS)232 return 1;233 234 return 0;235}236 237static inline void dwmac4_get_timestamp(void *desc, u32 ats, u64 *ts)238{239 struct dma_desc *p = (struct dma_desc *)desc;240 u64 ns;241 242 ns = le32_to_cpu(p->des0);243 /* convert high/sec time stamp value to nanosecond */244 ns += le32_to_cpu(p->des1) * 1000000000ULL;245 246 *ts = ns;247}248 249static int dwmac4_rx_check_timestamp(void *desc)250{251 struct dma_desc *p = (struct dma_desc *)desc;252 unsigned int rdes0 = le32_to_cpu(p->des0);253 unsigned int rdes1 = le32_to_cpu(p->des1);254 unsigned int rdes3 = le32_to_cpu(p->des3);255 u32 own, ctxt;256 int ret = 1;257 258 own = rdes3 & RDES3_OWN;259 ctxt = ((rdes3 & RDES3_CONTEXT_DESCRIPTOR)260 >> RDES3_CONTEXT_DESCRIPTOR_SHIFT);261 262 if (likely(!own && ctxt)) {263 if ((rdes0 == 0xffffffff) && (rdes1 == 0xffffffff))264 /* Corrupted value */265 ret = -EINVAL;266 else267 /* A valid Timestamp is ready to be read */268 ret = 0;269 }270 271 /* Timestamp not ready */272 return ret;273}274 275static int dwmac4_wrback_get_rx_timestamp_status(void *desc, void *next_desc,276 u32 ats)277{278 struct dma_desc *p = (struct dma_desc *)desc;279 int ret = -EINVAL;280 281 /* Get the status from normal w/b descriptor */282 if (likely(le32_to_cpu(p->des3) & RDES3_RDES1_VALID)) {283 if (likely(le32_to_cpu(p->des1) & RDES1_TIMESTAMP_AVAILABLE)) {284 int i = 0;285 286 /* Check if timestamp is OK from context descriptor */287 do {288 ret = dwmac4_rx_check_timestamp(next_desc);289 if (ret < 0)290 goto exit;291 i++;292 293 } while ((ret == 1) && (i < 10));294 295 if (i == 10)296 ret = -EBUSY;297 }298 }299exit:300 if (likely(ret == 0))301 return 1;302 303 return 0;304}305 306static void dwmac4_rd_init_rx_desc(struct dma_desc *p, int disable_rx_ic,307 int mode, int end, int bfsize)308{309 dwmac4_set_rx_owner(p, disable_rx_ic);310}311 312static void dwmac4_rd_init_tx_desc(struct dma_desc *p, int mode, int end)313{314 p->des0 = 0;315 p->des1 = 0;316 p->des2 = 0;317 p->des3 = 0;318}319 320static void dwmac4_rd_prepare_tx_desc(struct dma_desc *p, int is_fs, int len,321 bool csum_flag, int mode, bool tx_own,322 bool ls, unsigned int tot_pkt_len)323{324 unsigned int tdes3 = le32_to_cpu(p->des3);325 326 p->des2 |= cpu_to_le32(len & TDES2_BUFFER1_SIZE_MASK);327 328 tdes3 |= tot_pkt_len & TDES3_PACKET_SIZE_MASK;329 if (is_fs)330 tdes3 |= TDES3_FIRST_DESCRIPTOR;331 else332 tdes3 &= ~TDES3_FIRST_DESCRIPTOR;333 334 if (likely(csum_flag))335 tdes3 |= (TX_CIC_FULL << TDES3_CHECKSUM_INSERTION_SHIFT);336 else337 tdes3 &= ~(TX_CIC_FULL << TDES3_CHECKSUM_INSERTION_SHIFT);338 339 if (ls)340 tdes3 |= TDES3_LAST_DESCRIPTOR;341 else342 tdes3 &= ~TDES3_LAST_DESCRIPTOR;343 344 /* Finally set the OWN bit. Later the DMA will start! */345 if (tx_own)346 tdes3 |= TDES3_OWN;347 348 if (is_fs && tx_own)349 /* When the own bit, for the first frame, has to be set, all350 * descriptors for the same frame has to be set before, to351 * avoid race condition.352 */353 dma_wmb();354 355 p->des3 = cpu_to_le32(tdes3);356}357 358static void dwmac4_rd_prepare_tso_tx_desc(struct dma_desc *p, int is_fs,359 int len1, int len2, bool tx_own,360 bool ls, unsigned int tcphdrlen,361 unsigned int tcppayloadlen)362{363 unsigned int tdes3 = le32_to_cpu(p->des3);364 365 if (len1)366 p->des2 |= cpu_to_le32((len1 & TDES2_BUFFER1_SIZE_MASK));367 368 if (len2)369 p->des2 |= cpu_to_le32((len2 << TDES2_BUFFER2_SIZE_MASK_SHIFT)370 & TDES2_BUFFER2_SIZE_MASK);371 372 if (is_fs) {373 tdes3 |= TDES3_FIRST_DESCRIPTOR |374 TDES3_TCP_SEGMENTATION_ENABLE |375 ((tcphdrlen << TDES3_HDR_LEN_SHIFT) &376 TDES3_SLOT_NUMBER_MASK) |377 ((tcppayloadlen & TDES3_TCP_PKT_PAYLOAD_MASK));378 } else {379 tdes3 &= ~TDES3_FIRST_DESCRIPTOR;380 }381 382 if (ls)383 tdes3 |= TDES3_LAST_DESCRIPTOR;384 else385 tdes3 &= ~TDES3_LAST_DESCRIPTOR;386 387 /* Finally set the OWN bit. Later the DMA will start! */388 if (tx_own)389 tdes3 |= TDES3_OWN;390 391 if (is_fs && tx_own)392 /* When the own bit, for the first frame, has to be set, all393 * descriptors for the same frame has to be set before, to394 * avoid race condition.395 */396 dma_wmb();397 398 p->des3 = cpu_to_le32(tdes3);399}400 401static void dwmac4_release_tx_desc(struct dma_desc *p, int mode)402{403 p->des0 = 0;404 p->des1 = 0;405 p->des2 = 0;406 p->des3 = 0;407}408 409static void dwmac4_rd_set_tx_ic(struct dma_desc *p)410{411 p->des2 |= cpu_to_le32(TDES2_INTERRUPT_ON_COMPLETION);412}413 414static void dwmac4_display_ring(void *head, unsigned int size, bool rx,415 dma_addr_t dma_rx_phy, unsigned int desc_size)416{417 dma_addr_t dma_addr;418 int i;419 420 pr_info("%s descriptor ring:\n", rx ? "RX" : "TX");421 422 if (desc_size == sizeof(struct dma_desc)) {423 struct dma_desc *p = (struct dma_desc *)head;424 425 for (i = 0; i < size; i++) {426 dma_addr = dma_rx_phy + i * sizeof(*p);427 pr_info("%03d [%pad]: 0x%x 0x%x 0x%x 0x%x\n",428 i, &dma_addr,429 le32_to_cpu(p->des0), le32_to_cpu(p->des1),430 le32_to_cpu(p->des2), le32_to_cpu(p->des3));431 p++;432 }433 } else if (desc_size == sizeof(struct dma_extended_desc)) {434 struct dma_extended_desc *extp = (struct dma_extended_desc *)head;435 436 for (i = 0; i < size; i++) {437 dma_addr = dma_rx_phy + i * sizeof(*extp);438 pr_info("%03d [%pad]: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",439 i, &dma_addr,440 le32_to_cpu(extp->basic.des0), le32_to_cpu(extp->basic.des1),441 le32_to_cpu(extp->basic.des2), le32_to_cpu(extp->basic.des3),442 le32_to_cpu(extp->des4), le32_to_cpu(extp->des5),443 le32_to_cpu(extp->des6), le32_to_cpu(extp->des7));444 extp++;445 }446 } else if (desc_size == sizeof(struct dma_edesc)) {447 struct dma_edesc *ep = (struct dma_edesc *)head;448 449 for (i = 0; i < size; i++) {450 dma_addr = dma_rx_phy + i * sizeof(*ep);451 pr_info("%03d [%pad]: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",452 i, &dma_addr,453 le32_to_cpu(ep->des4), le32_to_cpu(ep->des5),454 le32_to_cpu(ep->des6), le32_to_cpu(ep->des7),455 le32_to_cpu(ep->basic.des0), le32_to_cpu(ep->basic.des1),456 le32_to_cpu(ep->basic.des2), le32_to_cpu(ep->basic.des3));457 ep++;458 }459 } else {460 pr_err("unsupported descriptor!");461 }462}463 464static void dwmac4_set_mss_ctxt(struct dma_desc *p, unsigned int mss)465{466 p->des0 = 0;467 p->des1 = 0;468 p->des2 = cpu_to_le32(mss);469 p->des3 = cpu_to_le32(TDES3_CONTEXT_TYPE | TDES3_CTXT_TCMSSV);470}471 472static void dwmac4_set_addr(struct dma_desc *p, dma_addr_t addr)473{474 p->des0 = cpu_to_le32(lower_32_bits(addr));475 p->des1 = cpu_to_le32(upper_32_bits(addr));476}477 478static void dwmac4_clear(struct dma_desc *p)479{480 p->des0 = 0;481 p->des1 = 0;482 p->des2 = 0;483 p->des3 = 0;484}485 486static void dwmac4_set_sarc(struct dma_desc *p, u32 sarc_type)487{488 sarc_type <<= TDES3_SA_INSERT_CTRL_SHIFT;489 490 p->des3 |= cpu_to_le32(sarc_type & TDES3_SA_INSERT_CTRL_MASK);491}492 493static int set_16kib_bfsize(int mtu)494{495 int ret = 0;496 497 if (unlikely(mtu >= BUF_SIZE_8KiB))498 ret = BUF_SIZE_16KiB;499 return ret;500}501 502static void dwmac4_set_vlan_tag(struct dma_desc *p, u16 tag, u16 inner_tag,503 u32 inner_type)504{505 p->des0 = 0;506 p->des1 = 0;507 p->des2 = 0;508 p->des3 = 0;509 510 /* Inner VLAN */511 if (inner_type) {512 u32 des = inner_tag << TDES2_IVT_SHIFT;513 514 des &= TDES2_IVT_MASK;515 p->des2 = cpu_to_le32(des);516 517 des = inner_type << TDES3_IVTIR_SHIFT;518 des &= TDES3_IVTIR_MASK;519 p->des3 = cpu_to_le32(des | TDES3_IVLTV);520 }521 522 /* Outer VLAN */523 p->des3 |= cpu_to_le32(tag & TDES3_VLAN_TAG);524 p->des3 |= cpu_to_le32(TDES3_VLTV);525 526 p->des3 |= cpu_to_le32(TDES3_CONTEXT_TYPE);527}528 529static void dwmac4_set_vlan(struct dma_desc *p, u32 type)530{531 type <<= TDES2_VLAN_TAG_SHIFT;532 p->des2 |= cpu_to_le32(type & TDES2_VLAN_TAG_MASK);533}534 535static void dwmac4_get_rx_header_len(struct dma_desc *p, unsigned int *len)536{537 *len = le32_to_cpu(p->des2) & RDES2_HL;538}539 540static void dwmac4_set_sec_addr(struct dma_desc *p, dma_addr_t addr, bool buf2_valid)541{542 p->des2 = cpu_to_le32(lower_32_bits(addr));543 p->des3 = cpu_to_le32(upper_32_bits(addr));544 545 if (buf2_valid)546 p->des3 |= cpu_to_le32(RDES3_BUFFER2_VALID_ADDR);547 else548 p->des3 &= cpu_to_le32(~RDES3_BUFFER2_VALID_ADDR);549}550 551static void dwmac4_set_tbs(struct dma_edesc *p, u32 sec, u32 nsec)552{553 p->des4 = cpu_to_le32((sec & TDES4_LT) | TDES4_LTV);554 p->des5 = cpu_to_le32(nsec & TDES5_LT);555 p->des6 = 0;556 p->des7 = 0;557}558 559const struct stmmac_desc_ops dwmac4_desc_ops = {560 .tx_status = dwmac4_wrback_get_tx_status,561 .rx_status = dwmac4_wrback_get_rx_status,562 .get_tx_len = dwmac4_rd_get_tx_len,563 .get_tx_owner = dwmac4_get_tx_owner,564 .set_tx_owner = dwmac4_set_tx_owner,565 .set_rx_owner = dwmac4_set_rx_owner,566 .get_tx_ls = dwmac4_get_tx_ls,567 .get_rx_vlan_tci = dwmac4_wrback_get_rx_vlan_tci,568 .get_rx_vlan_valid = dwmac4_wrback_get_rx_vlan_valid,569 .get_rx_frame_len = dwmac4_wrback_get_rx_frame_len,570 .enable_tx_timestamp = dwmac4_rd_enable_tx_timestamp,571 .get_tx_timestamp_status = dwmac4_wrback_get_tx_timestamp_status,572 .get_rx_timestamp_status = dwmac4_wrback_get_rx_timestamp_status,573 .get_timestamp = dwmac4_get_timestamp,574 .set_tx_ic = dwmac4_rd_set_tx_ic,575 .prepare_tx_desc = dwmac4_rd_prepare_tx_desc,576 .prepare_tso_tx_desc = dwmac4_rd_prepare_tso_tx_desc,577 .release_tx_desc = dwmac4_release_tx_desc,578 .init_rx_desc = dwmac4_rd_init_rx_desc,579 .init_tx_desc = dwmac4_rd_init_tx_desc,580 .display_ring = dwmac4_display_ring,581 .set_mss = dwmac4_set_mss_ctxt,582 .set_addr = dwmac4_set_addr,583 .clear = dwmac4_clear,584 .set_sarc = dwmac4_set_sarc,585 .set_vlan_tag = dwmac4_set_vlan_tag,586 .set_vlan = dwmac4_set_vlan,587 .get_rx_header_len = dwmac4_get_rx_header_len,588 .set_sec_addr = dwmac4_set_sec_addr,589 .set_tbs = dwmac4_set_tbs,590};591 592const struct stmmac_mode_ops dwmac4_ring_mode_ops = {593 .set_16kib_bfsize = set_16kib_bfsize,594};595