625 lines · c
1// SPDX-License-Identifier: GPL-2.0-only2/*3 * This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.4 * DWC Ether MAC version 4.xx has been used for developing this code.5 *6 * This contains the functions to handle the dma.7 *8 * Copyright (C) 2015 STMicroelectronics Ltd9 *10 * Author: Alexandre Torgue <alexandre.torgue@st.com>11 */12 13#include <linux/io.h>14#include "dwmac4.h"15#include "dwmac4_dma.h"16#include "stmmac.h"17 18static void dwmac4_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi)19{20 u32 value = readl(ioaddr + DMA_SYS_BUS_MODE);21 int i;22 23 pr_info("dwmac4: Master AXI performs %s burst length\n",24 (value & DMA_SYS_BUS_FB) ? "fixed" : "any");25 26 if (axi->axi_lpi_en)27 value |= DMA_AXI_EN_LPI;28 if (axi->axi_xit_frm)29 value |= DMA_AXI_LPI_XIT_FRM;30 31 value &= ~DMA_AXI_WR_OSR_LMT;32 value |= (axi->axi_wr_osr_lmt & DMA_AXI_OSR_MAX) <<33 DMA_AXI_WR_OSR_LMT_SHIFT;34 35 value &= ~DMA_AXI_RD_OSR_LMT;36 value |= (axi->axi_rd_osr_lmt & DMA_AXI_OSR_MAX) <<37 DMA_AXI_RD_OSR_LMT_SHIFT;38 39 /* Depending on the UNDEF bit the Master AXI will perform any burst40 * length according to the BLEN programmed (by default all BLEN are41 * set).42 */43 for (i = 0; i < AXI_BLEN; i++) {44 switch (axi->axi_blen[i]) {45 case 256:46 value |= DMA_AXI_BLEN256;47 break;48 case 128:49 value |= DMA_AXI_BLEN128;50 break;51 case 64:52 value |= DMA_AXI_BLEN64;53 break;54 case 32:55 value |= DMA_AXI_BLEN32;56 break;57 case 16:58 value |= DMA_AXI_BLEN16;59 break;60 case 8:61 value |= DMA_AXI_BLEN8;62 break;63 case 4:64 value |= DMA_AXI_BLEN4;65 break;66 }67 }68 69 writel(value, ioaddr + DMA_SYS_BUS_MODE);70}71 72static void dwmac4_dma_init_rx_chan(struct stmmac_priv *priv,73 void __iomem *ioaddr,74 struct stmmac_dma_cfg *dma_cfg,75 dma_addr_t dma_rx_phy, u32 chan)76{77 const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;78 u32 value;79 u32 rxpbl = dma_cfg->rxpbl ?: dma_cfg->pbl;80 81 value = readl(ioaddr + DMA_CHAN_RX_CONTROL(dwmac4_addrs, chan));82 value = value | (rxpbl << DMA_BUS_MODE_RPBL_SHIFT);83 writel(value, ioaddr + DMA_CHAN_RX_CONTROL(dwmac4_addrs, chan));84 85 if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) && likely(dma_cfg->eame))86 writel(upper_32_bits(dma_rx_phy),87 ioaddr + DMA_CHAN_RX_BASE_ADDR_HI(dwmac4_addrs, chan));88 89 writel(lower_32_bits(dma_rx_phy),90 ioaddr + DMA_CHAN_RX_BASE_ADDR(dwmac4_addrs, chan));91}92 93static void dwmac4_dma_init_tx_chan(struct stmmac_priv *priv,94 void __iomem *ioaddr,95 struct stmmac_dma_cfg *dma_cfg,96 dma_addr_t dma_tx_phy, u32 chan)97{98 const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;99 u32 value;100 u32 txpbl = dma_cfg->txpbl ?: dma_cfg->pbl;101 102 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, chan));103 value = value | (txpbl << DMA_BUS_MODE_PBL_SHIFT);104 105 /* Enable OSP to get best performance */106 value |= DMA_CONTROL_OSP;107 108 writel(value, ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, chan));109 110 if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) && likely(dma_cfg->eame))111 writel(upper_32_bits(dma_tx_phy),112 ioaddr + DMA_CHAN_TX_BASE_ADDR_HI(dwmac4_addrs, chan));113 114 writel(lower_32_bits(dma_tx_phy),115 ioaddr + DMA_CHAN_TX_BASE_ADDR(dwmac4_addrs, chan));116}117 118static void dwmac4_dma_init_channel(struct stmmac_priv *priv,119 void __iomem *ioaddr,120 struct stmmac_dma_cfg *dma_cfg, u32 chan)121{122 const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;123 u32 value;124 125 /* common channel control register config */126 value = readl(ioaddr + DMA_CHAN_CONTROL(dwmac4_addrs, chan));127 if (dma_cfg->pblx8)128 value = value | DMA_BUS_MODE_PBL;129 writel(value, ioaddr + DMA_CHAN_CONTROL(dwmac4_addrs, chan));130 131 /* Mask interrupts by writing to CSR7 */132 writel(DMA_CHAN_INTR_DEFAULT_MASK,133 ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));134}135 136static void dwmac410_dma_init_channel(struct stmmac_priv *priv,137 void __iomem *ioaddr,138 struct stmmac_dma_cfg *dma_cfg, u32 chan)139{140 const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;141 u32 value;142 143 /* common channel control register config */144 value = readl(ioaddr + DMA_CHAN_CONTROL(dwmac4_addrs, chan));145 if (dma_cfg->pblx8)146 value = value | DMA_BUS_MODE_PBL;147 148 writel(value, ioaddr + DMA_CHAN_CONTROL(dwmac4_addrs, chan));149 150 /* Mask interrupts by writing to CSR7 */151 writel(DMA_CHAN_INTR_DEFAULT_MASK_4_10,152 ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));153}154 155static void dwmac4_dma_init(void __iomem *ioaddr,156 struct stmmac_dma_cfg *dma_cfg)157{158 u32 value = readl(ioaddr + DMA_SYS_BUS_MODE);159 160 /* Set the Fixed burst mode */161 if (dma_cfg->fixed_burst)162 value |= DMA_SYS_BUS_FB;163 164 /* Mixed Burst has no effect when fb is set */165 if (dma_cfg->mixed_burst)166 value |= DMA_SYS_BUS_MB;167 168 if (dma_cfg->aal)169 value |= DMA_SYS_BUS_AAL;170 171 if (dma_cfg->eame)172 value |= DMA_SYS_BUS_EAME;173 174 writel(value, ioaddr + DMA_SYS_BUS_MODE);175 176 value = readl(ioaddr + DMA_BUS_MODE);177 178 if (dma_cfg->multi_msi_en) {179 value &= ~DMA_BUS_MODE_INTM_MASK;180 value |= (DMA_BUS_MODE_INTM_MODE1 << DMA_BUS_MODE_INTM_SHIFT);181 }182 183 if (dma_cfg->dche)184 value |= DMA_BUS_MODE_DCHE;185 186 writel(value, ioaddr + DMA_BUS_MODE);187 188}189 190static void _dwmac4_dump_dma_regs(struct stmmac_priv *priv,191 void __iomem *ioaddr, u32 channel,192 u32 *reg_space)193{194 const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;195 const struct dwmac4_addrs *default_addrs = NULL;196 197 /* Purposely save the registers in the "normal" layout, regardless of198 * platform modifications, to keep reg_space size constant199 */200 reg_space[DMA_CHAN_CONTROL(default_addrs, channel) / 4] =201 readl(ioaddr + DMA_CHAN_CONTROL(dwmac4_addrs, channel));202 reg_space[DMA_CHAN_TX_CONTROL(default_addrs, channel) / 4] =203 readl(ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, channel));204 reg_space[DMA_CHAN_RX_CONTROL(default_addrs, channel) / 4] =205 readl(ioaddr + DMA_CHAN_RX_CONTROL(dwmac4_addrs, channel));206 reg_space[DMA_CHAN_TX_BASE_ADDR_HI(default_addrs, channel) / 4] =207 readl(ioaddr + DMA_CHAN_TX_BASE_ADDR_HI(dwmac4_addrs, channel));208 reg_space[DMA_CHAN_TX_BASE_ADDR(default_addrs, channel) / 4] =209 readl(ioaddr + DMA_CHAN_TX_BASE_ADDR(dwmac4_addrs, channel));210 reg_space[DMA_CHAN_RX_BASE_ADDR_HI(default_addrs, channel) / 4] =211 readl(ioaddr + DMA_CHAN_RX_BASE_ADDR_HI(dwmac4_addrs, channel));212 reg_space[DMA_CHAN_RX_BASE_ADDR(default_addrs, channel) / 4] =213 readl(ioaddr + DMA_CHAN_RX_BASE_ADDR(dwmac4_addrs, channel));214 reg_space[DMA_CHAN_TX_END_ADDR(default_addrs, channel) / 4] =215 readl(ioaddr + DMA_CHAN_TX_END_ADDR(dwmac4_addrs, channel));216 reg_space[DMA_CHAN_RX_END_ADDR(default_addrs, channel) / 4] =217 readl(ioaddr + DMA_CHAN_RX_END_ADDR(dwmac4_addrs, channel));218 reg_space[DMA_CHAN_TX_RING_LEN(default_addrs, channel) / 4] =219 readl(ioaddr + DMA_CHAN_TX_RING_LEN(dwmac4_addrs, channel));220 reg_space[DMA_CHAN_RX_RING_LEN(default_addrs, channel) / 4] =221 readl(ioaddr + DMA_CHAN_RX_RING_LEN(dwmac4_addrs, channel));222 reg_space[DMA_CHAN_INTR_ENA(default_addrs, channel) / 4] =223 readl(ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, channel));224 reg_space[DMA_CHAN_RX_WATCHDOG(default_addrs, channel) / 4] =225 readl(ioaddr + DMA_CHAN_RX_WATCHDOG(dwmac4_addrs, channel));226 reg_space[DMA_CHAN_SLOT_CTRL_STATUS(default_addrs, channel) / 4] =227 readl(ioaddr + DMA_CHAN_SLOT_CTRL_STATUS(dwmac4_addrs, channel));228 reg_space[DMA_CHAN_CUR_TX_DESC(default_addrs, channel) / 4] =229 readl(ioaddr + DMA_CHAN_CUR_TX_DESC(dwmac4_addrs, channel));230 reg_space[DMA_CHAN_CUR_RX_DESC(default_addrs, channel) / 4] =231 readl(ioaddr + DMA_CHAN_CUR_RX_DESC(dwmac4_addrs, channel));232 reg_space[DMA_CHAN_CUR_TX_BUF_ADDR_HI(default_addrs, channel) / 4] =233 readl(ioaddr + DMA_CHAN_CUR_TX_BUF_ADDR_HI(dwmac4_addrs, channel));234 reg_space[DMA_CHAN_CUR_TX_BUF_ADDR(default_addrs, channel) / 4] =235 readl(ioaddr + DMA_CHAN_CUR_TX_BUF_ADDR(dwmac4_addrs, channel));236 reg_space[DMA_CHAN_CUR_RX_BUF_ADDR_HI(default_addrs, channel) / 4] =237 readl(ioaddr + DMA_CHAN_CUR_RX_BUF_ADDR_HI(dwmac4_addrs, channel));238 reg_space[DMA_CHAN_CUR_RX_BUF_ADDR(default_addrs, channel) / 4] =239 readl(ioaddr + DMA_CHAN_CUR_RX_BUF_ADDR(dwmac4_addrs, channel));240 reg_space[DMA_CHAN_STATUS(default_addrs, channel) / 4] =241 readl(ioaddr + DMA_CHAN_STATUS(dwmac4_addrs, channel));242}243 244static void dwmac4_dump_dma_regs(struct stmmac_priv *priv, void __iomem *ioaddr,245 u32 *reg_space)246{247 int i;248 249 for (i = 0; i < DMA_CHANNEL_NB_MAX; i++)250 _dwmac4_dump_dma_regs(priv, ioaddr, i, reg_space);251}252 253static void dwmac4_rx_watchdog(struct stmmac_priv *priv, void __iomem *ioaddr,254 u32 riwt, u32 queue)255{256 const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;257 258 writel(riwt, ioaddr + DMA_CHAN_RX_WATCHDOG(dwmac4_addrs, queue));259}260 261static void dwmac4_dma_rx_chan_op_mode(struct stmmac_priv *priv,262 void __iomem *ioaddr, int mode,263 u32 channel, int fifosz, u8 qmode)264{265 const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;266 unsigned int rqs = fifosz / 256 - 1;267 u32 mtl_rx_op;268 269 mtl_rx_op = readl(ioaddr + MTL_CHAN_RX_OP_MODE(dwmac4_addrs, channel));270 271 if (mode == SF_DMA_MODE) {272 pr_debug("GMAC: enable RX store and forward mode\n");273 mtl_rx_op |= MTL_OP_MODE_RSF;274 } else {275 pr_debug("GMAC: disable RX SF mode (threshold %d)\n", mode);276 mtl_rx_op &= ~MTL_OP_MODE_RSF;277 mtl_rx_op &= MTL_OP_MODE_RTC_MASK;278 if (mode <= 32)279 mtl_rx_op |= MTL_OP_MODE_RTC_32;280 else if (mode <= 64)281 mtl_rx_op |= MTL_OP_MODE_RTC_64;282 else if (mode <= 96)283 mtl_rx_op |= MTL_OP_MODE_RTC_96;284 else285 mtl_rx_op |= MTL_OP_MODE_RTC_128;286 }287 288 mtl_rx_op &= ~MTL_OP_MODE_RQS_MASK;289 mtl_rx_op |= rqs << MTL_OP_MODE_RQS_SHIFT;290 291 /* Enable flow control only if each channel gets 4 KiB or more FIFO and292 * only if channel is not an AVB channel.293 */294 if ((fifosz >= 4096) && (qmode != MTL_QUEUE_AVB)) {295 unsigned int rfd, rfa;296 297 mtl_rx_op |= MTL_OP_MODE_EHFC;298 299 /* Set Threshold for Activating Flow Control to min 2 frames,300 * i.e. 1500 * 2 = 3000 bytes.301 *302 * Set Threshold for Deactivating Flow Control to min 1 frame,303 * i.e. 1500 bytes.304 */305 switch (fifosz) {306 case 4096:307 /* This violates the above formula because of FIFO size308 * limit therefore overflow may occur in spite of this.309 */310 rfd = 0x03; /* Full-2.5K */311 rfa = 0x01; /* Full-1.5K */312 break;313 314 default:315 rfd = 0x07; /* Full-4.5K */316 rfa = 0x04; /* Full-3K */317 break;318 }319 320 mtl_rx_op &= ~MTL_OP_MODE_RFD_MASK;321 mtl_rx_op |= rfd << MTL_OP_MODE_RFD_SHIFT;322 323 mtl_rx_op &= ~MTL_OP_MODE_RFA_MASK;324 mtl_rx_op |= rfa << MTL_OP_MODE_RFA_SHIFT;325 }326 327 writel(mtl_rx_op, ioaddr + MTL_CHAN_RX_OP_MODE(dwmac4_addrs, channel));328}329 330static void dwmac4_dma_tx_chan_op_mode(struct stmmac_priv *priv,331 void __iomem *ioaddr, int mode,332 u32 channel, int fifosz, u8 qmode)333{334 const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;335 u32 mtl_tx_op = readl(ioaddr + MTL_CHAN_TX_OP_MODE(dwmac4_addrs,336 channel));337 unsigned int tqs = fifosz / 256 - 1;338 339 if (mode == SF_DMA_MODE) {340 pr_debug("GMAC: enable TX store and forward mode\n");341 /* Transmit COE type 2 cannot be done in cut-through mode. */342 mtl_tx_op |= MTL_OP_MODE_TSF;343 } else {344 pr_debug("GMAC: disabling TX SF (threshold %d)\n", mode);345 mtl_tx_op &= ~MTL_OP_MODE_TSF;346 mtl_tx_op &= MTL_OP_MODE_TTC_MASK;347 /* Set the transmit threshold */348 if (mode <= 32)349 mtl_tx_op |= MTL_OP_MODE_TTC_32;350 else if (mode <= 64)351 mtl_tx_op |= MTL_OP_MODE_TTC_64;352 else if (mode <= 96)353 mtl_tx_op |= MTL_OP_MODE_TTC_96;354 else if (mode <= 128)355 mtl_tx_op |= MTL_OP_MODE_TTC_128;356 else if (mode <= 192)357 mtl_tx_op |= MTL_OP_MODE_TTC_192;358 else if (mode <= 256)359 mtl_tx_op |= MTL_OP_MODE_TTC_256;360 else if (mode <= 384)361 mtl_tx_op |= MTL_OP_MODE_TTC_384;362 else363 mtl_tx_op |= MTL_OP_MODE_TTC_512;364 }365 /* For an IP with DWC_EQOS_NUM_TXQ == 1, the fields TXQEN and TQS are RO366 * with reset values: TXQEN on, TQS == DWC_EQOS_TXFIFO_SIZE.367 * For an IP with DWC_EQOS_NUM_TXQ > 1, the fields TXQEN and TQS are R/W368 * with reset values: TXQEN off, TQS 256 bytes.369 *370 * TXQEN must be written for multi-channel operation and TQS must371 * reflect the available fifo size per queue (total fifo size / number372 * of enabled queues).373 */374 mtl_tx_op &= ~MTL_OP_MODE_TXQEN_MASK;375 if (qmode != MTL_QUEUE_AVB)376 mtl_tx_op |= MTL_OP_MODE_TXQEN;377 else378 mtl_tx_op |= MTL_OP_MODE_TXQEN_AV;379 mtl_tx_op &= ~MTL_OP_MODE_TQS_MASK;380 mtl_tx_op |= tqs << MTL_OP_MODE_TQS_SHIFT;381 382 writel(mtl_tx_op, ioaddr + MTL_CHAN_TX_OP_MODE(dwmac4_addrs, channel));383}384 385static int dwmac4_get_hw_feature(void __iomem *ioaddr,386 struct dma_features *dma_cap)387{388 u32 hw_cap = readl(ioaddr + GMAC_HW_FEATURE0);389 390 /* MAC HW feature0 */391 dma_cap->mbps_10_100 = (hw_cap & GMAC_HW_FEAT_MIISEL);392 dma_cap->mbps_1000 = (hw_cap & GMAC_HW_FEAT_GMIISEL) >> 1;393 dma_cap->half_duplex = (hw_cap & GMAC_HW_FEAT_HDSEL) >> 2;394 dma_cap->vlhash = (hw_cap & GMAC_HW_FEAT_VLHASH) >> 4;395 dma_cap->multi_addr = (hw_cap & GMAC_HW_FEAT_ADDMAC) >> 18;396 dma_cap->pcs = (hw_cap & GMAC_HW_FEAT_PCSSEL) >> 3;397 dma_cap->sma_mdio = (hw_cap & GMAC_HW_FEAT_SMASEL) >> 5;398 dma_cap->pmt_remote_wake_up = (hw_cap & GMAC_HW_FEAT_RWKSEL) >> 6;399 dma_cap->pmt_magic_frame = (hw_cap & GMAC_HW_FEAT_MGKSEL) >> 7;400 /* MMC */401 dma_cap->rmon = (hw_cap & GMAC_HW_FEAT_MMCSEL) >> 8;402 /* IEEE 1588-2008 */403 dma_cap->atime_stamp = (hw_cap & GMAC_HW_FEAT_TSSEL) >> 12;404 /* 802.3az - Energy-Efficient Ethernet (EEE) */405 dma_cap->eee = (hw_cap & GMAC_HW_FEAT_EEESEL) >> 13;406 /* TX and RX csum */407 dma_cap->tx_coe = (hw_cap & GMAC_HW_FEAT_TXCOSEL) >> 14;408 dma_cap->rx_coe = (hw_cap & GMAC_HW_FEAT_RXCOESEL) >> 16;409 dma_cap->vlins = (hw_cap & GMAC_HW_FEAT_SAVLANINS) >> 27;410 dma_cap->arpoffsel = (hw_cap & GMAC_HW_FEAT_ARPOFFSEL) >> 9;411 412 /* MAC HW feature1 */413 hw_cap = readl(ioaddr + GMAC_HW_FEATURE1);414 dma_cap->l3l4fnum = (hw_cap & GMAC_HW_FEAT_L3L4FNUM) >> 27;415 dma_cap->hash_tb_sz = (hw_cap & GMAC_HW_HASH_TB_SZ) >> 24;416 dma_cap->av = (hw_cap & GMAC_HW_FEAT_AVSEL) >> 20;417 dma_cap->tsoen = (hw_cap & GMAC_HW_TSOEN) >> 18;418 dma_cap->sphen = (hw_cap & GMAC_HW_FEAT_SPHEN) >> 17;419 420 dma_cap->addr64 = (hw_cap & GMAC_HW_ADDR64) >> 14;421 switch (dma_cap->addr64) {422 case 0:423 dma_cap->addr64 = 32;424 break;425 case 1:426 dma_cap->addr64 = 40;427 break;428 case 2:429 dma_cap->addr64 = 48;430 break;431 default:432 dma_cap->addr64 = 32;433 break;434 }435 436 /* RX and TX FIFO sizes are encoded as log2(n / 128). Undo that by437 * shifting and store the sizes in bytes.438 */439 dma_cap->tx_fifo_size = 128 << ((hw_cap & GMAC_HW_TXFIFOSIZE) >> 6);440 dma_cap->rx_fifo_size = 128 << ((hw_cap & GMAC_HW_RXFIFOSIZE) >> 0);441 /* MAC HW feature2 */442 hw_cap = readl(ioaddr + GMAC_HW_FEATURE2);443 /* TX and RX number of channels */444 dma_cap->number_rx_channel =445 ((hw_cap & GMAC_HW_FEAT_RXCHCNT) >> 12) + 1;446 dma_cap->number_tx_channel =447 ((hw_cap & GMAC_HW_FEAT_TXCHCNT) >> 18) + 1;448 /* TX and RX number of queues */449 dma_cap->number_rx_queues =450 ((hw_cap & GMAC_HW_FEAT_RXQCNT) >> 0) + 1;451 dma_cap->number_tx_queues =452 ((hw_cap & GMAC_HW_FEAT_TXQCNT) >> 6) + 1;453 /* PPS output */454 dma_cap->pps_out_num = (hw_cap & GMAC_HW_FEAT_PPSOUTNUM) >> 24;455 456 /* IEEE 1588-2002 */457 dma_cap->time_stamp = 0;458 /* Number of Auxiliary Snapshot Inputs */459 dma_cap->aux_snapshot_n = (hw_cap & GMAC_HW_FEAT_AUXSNAPNUM) >> 28;460 461 /* MAC HW feature3 */462 hw_cap = readl(ioaddr + GMAC_HW_FEATURE3);463 464 /* 5.10 Features */465 dma_cap->asp = (hw_cap & GMAC_HW_FEAT_ASP) >> 28;466 dma_cap->tbssel = (hw_cap & GMAC_HW_FEAT_TBSSEL) >> 27;467 dma_cap->fpesel = (hw_cap & GMAC_HW_FEAT_FPESEL) >> 26;468 dma_cap->estwid = (hw_cap & GMAC_HW_FEAT_ESTWID) >> 20;469 dma_cap->estdep = (hw_cap & GMAC_HW_FEAT_ESTDEP) >> 17;470 dma_cap->estsel = (hw_cap & GMAC_HW_FEAT_ESTSEL) >> 16;471 dma_cap->frpes = (hw_cap & GMAC_HW_FEAT_FRPES) >> 13;472 dma_cap->frpbs = (hw_cap & GMAC_HW_FEAT_FRPBS) >> 11;473 dma_cap->frpsel = (hw_cap & GMAC_HW_FEAT_FRPSEL) >> 10;474 dma_cap->dvlan = (hw_cap & GMAC_HW_FEAT_DVLAN) >> 5;475 476 return 0;477}478 479/* Enable/disable TSO feature and set MSS */480static void dwmac4_enable_tso(struct stmmac_priv *priv, void __iomem *ioaddr,481 bool en, u32 chan)482{483 const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;484 u32 value;485 486 if (en) {487 /* enable TSO */488 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, chan));489 writel(value | DMA_CONTROL_TSE,490 ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, chan));491 } else {492 /* enable TSO */493 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, chan));494 writel(value & ~DMA_CONTROL_TSE,495 ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, chan));496 }497}498 499static void dwmac4_qmode(struct stmmac_priv *priv, void __iomem *ioaddr,500 u32 channel, u8 qmode)501{502 const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;503 u32 mtl_tx_op = readl(ioaddr + MTL_CHAN_TX_OP_MODE(dwmac4_addrs,504 channel));505 506 mtl_tx_op &= ~MTL_OP_MODE_TXQEN_MASK;507 if (qmode != MTL_QUEUE_AVB)508 mtl_tx_op |= MTL_OP_MODE_TXQEN;509 else510 mtl_tx_op |= MTL_OP_MODE_TXQEN_AV;511 512 writel(mtl_tx_op, ioaddr + MTL_CHAN_TX_OP_MODE(dwmac4_addrs, channel));513}514 515static void dwmac4_set_bfsize(struct stmmac_priv *priv, void __iomem *ioaddr,516 int bfsize, u32 chan)517{518 const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;519 u32 value = readl(ioaddr + DMA_CHAN_RX_CONTROL(dwmac4_addrs, chan));520 521 value &= ~DMA_RBSZ_MASK;522 value |= (bfsize << DMA_RBSZ_SHIFT) & DMA_RBSZ_MASK;523 524 writel(value, ioaddr + DMA_CHAN_RX_CONTROL(dwmac4_addrs, chan));525}526 527static void dwmac4_enable_sph(struct stmmac_priv *priv, void __iomem *ioaddr,528 bool en, u32 chan)529{530 const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;531 u32 value = readl(ioaddr + GMAC_EXT_CONFIG);532 533 value &= ~GMAC_CONFIG_HDSMS;534 value |= GMAC_CONFIG_HDSMS_256; /* Segment max 256 bytes */535 writel(value, ioaddr + GMAC_EXT_CONFIG);536 537 value = readl(ioaddr + DMA_CHAN_CONTROL(dwmac4_addrs, chan));538 if (en)539 value |= DMA_CONTROL_SPH;540 else541 value &= ~DMA_CONTROL_SPH;542 writel(value, ioaddr + DMA_CHAN_CONTROL(dwmac4_addrs, chan));543}544 545static int dwmac4_enable_tbs(struct stmmac_priv *priv, void __iomem *ioaddr,546 bool en, u32 chan)547{548 const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;549 u32 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, chan));550 551 if (en)552 value |= DMA_CONTROL_EDSE;553 else554 value &= ~DMA_CONTROL_EDSE;555 556 writel(value, ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, chan));557 558 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs,559 chan)) & DMA_CONTROL_EDSE;560 if (en && !value)561 return -EIO;562 563 writel(DMA_TBS_DEF_FTOS, ioaddr + DMA_TBS_CTRL);564 return 0;565}566 567const struct stmmac_dma_ops dwmac4_dma_ops = {568 .reset = dwmac4_dma_reset,569 .init = dwmac4_dma_init,570 .init_chan = dwmac4_dma_init_channel,571 .init_rx_chan = dwmac4_dma_init_rx_chan,572 .init_tx_chan = dwmac4_dma_init_tx_chan,573 .axi = dwmac4_dma_axi,574 .dump_regs = dwmac4_dump_dma_regs,575 .dma_rx_mode = dwmac4_dma_rx_chan_op_mode,576 .dma_tx_mode = dwmac4_dma_tx_chan_op_mode,577 .enable_dma_irq = dwmac4_enable_dma_irq,578 .disable_dma_irq = dwmac4_disable_dma_irq,579 .start_tx = dwmac4_dma_start_tx,580 .stop_tx = dwmac4_dma_stop_tx,581 .start_rx = dwmac4_dma_start_rx,582 .stop_rx = dwmac4_dma_stop_rx,583 .dma_interrupt = dwmac4_dma_interrupt,584 .get_hw_feature = dwmac4_get_hw_feature,585 .rx_watchdog = dwmac4_rx_watchdog,586 .set_rx_ring_len = dwmac4_set_rx_ring_len,587 .set_tx_ring_len = dwmac4_set_tx_ring_len,588 .set_rx_tail_ptr = dwmac4_set_rx_tail_ptr,589 .set_tx_tail_ptr = dwmac4_set_tx_tail_ptr,590 .enable_tso = dwmac4_enable_tso,591 .qmode = dwmac4_qmode,592 .set_bfsize = dwmac4_set_bfsize,593 .enable_sph = dwmac4_enable_sph,594};595 596const struct stmmac_dma_ops dwmac410_dma_ops = {597 .reset = dwmac4_dma_reset,598 .init = dwmac4_dma_init,599 .init_chan = dwmac410_dma_init_channel,600 .init_rx_chan = dwmac4_dma_init_rx_chan,601 .init_tx_chan = dwmac4_dma_init_tx_chan,602 .axi = dwmac4_dma_axi,603 .dump_regs = dwmac4_dump_dma_regs,604 .dma_rx_mode = dwmac4_dma_rx_chan_op_mode,605 .dma_tx_mode = dwmac4_dma_tx_chan_op_mode,606 .enable_dma_irq = dwmac410_enable_dma_irq,607 .disable_dma_irq = dwmac4_disable_dma_irq,608 .start_tx = dwmac4_dma_start_tx,609 .stop_tx = dwmac4_dma_stop_tx,610 .start_rx = dwmac4_dma_start_rx,611 .stop_rx = dwmac4_dma_stop_rx,612 .dma_interrupt = dwmac4_dma_interrupt,613 .get_hw_feature = dwmac4_get_hw_feature,614 .rx_watchdog = dwmac4_rx_watchdog,615 .set_rx_ring_len = dwmac4_set_rx_ring_len,616 .set_tx_ring_len = dwmac4_set_tx_ring_len,617 .set_rx_tail_ptr = dwmac4_set_rx_tail_ptr,618 .set_tx_tail_ptr = dwmac4_set_tx_tail_ptr,619 .enable_tso = dwmac4_enable_tso,620 .qmode = dwmac4_qmode,621 .set_bfsize = dwmac4_set_bfsize,622 .enable_sph = dwmac4_enable_sph,623 .enable_tbs = dwmac4_enable_tbs,624};625