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1/* SPDX-License-Identifier: GPL-2.0-only */2/*******************************************************************************3 DWMAC DMA Header file.4 5 Copyright (C) 2007-2009 STMicroelectronics Ltd6 7 8 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>9*******************************************************************************/10 11#ifndef __DWMAC_DMA_H__12#define __DWMAC_DMA_H__13 14/* DMA CRS Control and Status Register Mapping */15#define DMA_BUS_MODE 0x00001000 /* Bus Mode */16#define DMA_XMT_POLL_DEMAND 0x00001004 /* Transmit Poll Demand */17#define DMA_RCV_POLL_DEMAND 0x00001008 /* Received Poll Demand */18#define DMA_RCV_BASE_ADDR 0x0000100c /* Receive List Base */19#define DMA_TX_BASE_ADDR 0x00001010 /* Transmit List Base */20#define DMA_STATUS 0x00001014 /* Status Register */21#define DMA_CONTROL 0x00001018 /* Ctrl (Operational Mode) */22#define DMA_INTR_ENA 0x0000101c /* Interrupt Enable */23#define DMA_MISSED_FRAME_CTR 0x00001020 /* Missed Frame Counter */24 25/* Following DMA defines are channels oriented */26#define DMA_CHAN_BASE_OFFSET 0x10027 28static inline u32 dma_chan_base_addr(u32 base, u32 chan)29{30 return base + chan * DMA_CHAN_BASE_OFFSET;31}32 33#define DMA_CHAN_BUS_MODE(chan) dma_chan_base_addr(DMA_BUS_MODE, chan)34#define DMA_CHAN_XMT_POLL_DEMAND(chan) \35 dma_chan_base_addr(DMA_XMT_POLL_DEMAND, chan)36#define DMA_CHAN_RCV_POLL_DEMAND(chan) \37 dma_chan_base_addr(DMA_RCV_POLL_DEMAND, chan)38#define DMA_CHAN_RCV_BASE_ADDR(chan) \39 dma_chan_base_addr(DMA_RCV_BASE_ADDR, chan)40#define DMA_CHAN_TX_BASE_ADDR(chan) \41 dma_chan_base_addr(DMA_TX_BASE_ADDR, chan)42#define DMA_CHAN_STATUS(chan) dma_chan_base_addr(DMA_STATUS, chan)43#define DMA_CHAN_CONTROL(chan) dma_chan_base_addr(DMA_CONTROL, chan)44#define DMA_CHAN_INTR_ENA(chan) dma_chan_base_addr(DMA_INTR_ENA, chan)45#define DMA_CHAN_MISSED_FRAME_CTR(chan) \46 dma_chan_base_addr(DMA_MISSED_FRAME_CTR, chan)47#define DMA_CHAN_RX_WATCHDOG(chan) \48 dma_chan_base_addr(DMA_RX_WATCHDOG, chan)49 50/* SW Reset */51#define DMA_BUS_MODE_SFT_RESET 0x00000001 /* Software Reset */52 53/* Rx watchdog register */54#define DMA_RX_WATCHDOG 0x0000102455 56/* AXI Master Bus Mode */57#define DMA_AXI_BUS_MODE 0x0000102858 59#define DMA_AXI_EN_LPI BIT(31)60#define DMA_AXI_LPI_XIT_FRM BIT(30)61#define DMA_AXI_WR_OSR_LMT GENMASK(23, 20)62#define DMA_AXI_WR_OSR_LMT_SHIFT 2063#define DMA_AXI_WR_OSR_LMT_MASK 0xf64#define DMA_AXI_RD_OSR_LMT GENMASK(19, 16)65#define DMA_AXI_RD_OSR_LMT_SHIFT 1666#define DMA_AXI_RD_OSR_LMT_MASK 0xf67 68#define DMA_AXI_OSR_MAX 0xf69#define DMA_AXI_MAX_OSR_LIMIT ((DMA_AXI_OSR_MAX << DMA_AXI_WR_OSR_LMT_SHIFT) | \70 (DMA_AXI_OSR_MAX << DMA_AXI_RD_OSR_LMT_SHIFT))71#define DMA_AXI_1KBBE BIT(13)72#define DMA_AXI_AAL BIT(12)73#define DMA_AXI_BLEN256 BIT(7)74#define DMA_AXI_BLEN128 BIT(6)75#define DMA_AXI_BLEN64 BIT(5)76#define DMA_AXI_BLEN32 BIT(4)77#define DMA_AXI_BLEN16 BIT(3)78#define DMA_AXI_BLEN8 BIT(2)79#define DMA_AXI_BLEN4 BIT(1)80#define DMA_BURST_LEN_DEFAULT (DMA_AXI_BLEN256 | DMA_AXI_BLEN128 | \81 DMA_AXI_BLEN64 | DMA_AXI_BLEN32 | \82 DMA_AXI_BLEN16 | DMA_AXI_BLEN8 | \83 DMA_AXI_BLEN4)84 85#define DMA_AXI_UNDEF BIT(0)86 87#define DMA_AXI_BURST_LEN_MASK 0x000000FE88 89#define DMA_CUR_TX_BUF_ADDR 0x00001050 /* Current Host Tx Buffer */90#define DMA_CUR_RX_BUF_ADDR 0x00001054 /* Current Host Rx Buffer */91#define DMA_HW_FEATURE 0x00001058 /* HW Feature Register */92 93/* DMA Control register defines */94#define DMA_CONTROL_ST 0x00002000 /* Start/Stop Transmission */95#define DMA_CONTROL_SR 0x00000002 /* Start/Stop Receive */96 97/* DMA Normal interrupt */98#define DMA_INTR_ENA_NIE 0x00010000 /* Normal Summary */99#define DMA_INTR_ENA_TIE 0x00000001 /* Transmit Interrupt */100#define DMA_INTR_ENA_TUE 0x00000004 /* Transmit Buffer Unavailable */101#define DMA_INTR_ENA_RIE 0x00000040 /* Receive Interrupt */102#define DMA_INTR_ENA_ERE 0x00004000 /* Early Receive */103 104#define DMA_INTR_NORMAL (DMA_INTR_ENA_NIE | DMA_INTR_ENA_RIE | \105 DMA_INTR_ENA_TIE)106 107/* DMA Abnormal interrupt */108#define DMA_INTR_ENA_AIE 0x00008000 /* Abnormal Summary */109#define DMA_INTR_ENA_FBE 0x00002000 /* Fatal Bus Error */110#define DMA_INTR_ENA_ETE 0x00000400 /* Early Transmit */111#define DMA_INTR_ENA_RWE 0x00000200 /* Receive Watchdog */112#define DMA_INTR_ENA_RSE 0x00000100 /* Receive Stopped */113#define DMA_INTR_ENA_RUE 0x00000080 /* Receive Buffer Unavailable */114#define DMA_INTR_ENA_UNE 0x00000020 /* Tx Underflow */115#define DMA_INTR_ENA_OVE 0x00000010 /* Receive Overflow */116#define DMA_INTR_ENA_TJE 0x00000008 /* Transmit Jabber */117#define DMA_INTR_ENA_TSE 0x00000002 /* Transmit Stopped */118 119#define DMA_INTR_ABNORMAL (DMA_INTR_ENA_AIE | DMA_INTR_ENA_FBE | \120 DMA_INTR_ENA_UNE)121 122/* DMA default interrupt mask */123#define DMA_INTR_DEFAULT_MASK (DMA_INTR_NORMAL | DMA_INTR_ABNORMAL)124#define DMA_INTR_DEFAULT_RX (DMA_INTR_ENA_RIE)125#define DMA_INTR_DEFAULT_TX (DMA_INTR_ENA_TIE)126 127/* DMA Status register defines */128#define DMA_STATUS_GLPII 0x40000000 /* GMAC LPI interrupt */129#define DMA_STATUS_GPI 0x10000000 /* PMT interrupt */130#define DMA_STATUS_GMI 0x08000000 /* MMC interrupt */131#define DMA_STATUS_GLI 0x04000000 /* GMAC Line interface int */132#define DMA_STATUS_EB_MASK 0x00380000 /* Error Bits Mask */133#define DMA_STATUS_EB_TX_ABORT 0x00080000 /* Error Bits - TX Abort */134#define DMA_STATUS_EB_RX_ABORT 0x00100000 /* Error Bits - RX Abort */135#define DMA_STATUS_TS_MASK 0x00700000 /* Transmit Process State */136#define DMA_STATUS_TS_SHIFT 20137#define DMA_STATUS_RS_MASK 0x000e0000 /* Receive Process State */138#define DMA_STATUS_RS_SHIFT 17139#define DMA_STATUS_NIS 0x00010000 /* Normal Interrupt Summary */140#define DMA_STATUS_AIS 0x00008000 /* Abnormal Interrupt Summary */141#define DMA_STATUS_ERI 0x00004000 /* Early Receive Interrupt */142#define DMA_STATUS_FBI 0x00002000 /* Fatal Bus Error Interrupt */143#define DMA_STATUS_ETI 0x00000400 /* Early Transmit Interrupt */144#define DMA_STATUS_RWT 0x00000200 /* Receive Watchdog Timeout */145#define DMA_STATUS_RPS 0x00000100 /* Receive Process Stopped */146#define DMA_STATUS_RU 0x00000080 /* Receive Buffer Unavailable */147#define DMA_STATUS_RI 0x00000040 /* Receive Interrupt */148#define DMA_STATUS_UNF 0x00000020 /* Transmit Underflow */149#define DMA_STATUS_OVF 0x00000010 /* Receive Overflow */150#define DMA_STATUS_TJT 0x00000008 /* Transmit Jabber Timeout */151#define DMA_STATUS_TU 0x00000004 /* Transmit Buffer Unavailable */152#define DMA_STATUS_TPS 0x00000002 /* Transmit Process Stopped */153#define DMA_STATUS_TI 0x00000001 /* Transmit Interrupt */154#define DMA_CONTROL_FTF 0x00100000 /* Flush transmit FIFO */155 156#define DMA_STATUS_MSK_COMMON (DMA_STATUS_NIS | \157 DMA_STATUS_AIS | \158 DMA_STATUS_FBI)159 160#define DMA_STATUS_MSK_RX (DMA_STATUS_ERI | \161 DMA_STATUS_RWT | \162 DMA_STATUS_RPS | \163 DMA_STATUS_RU | \164 DMA_STATUS_RI | \165 DMA_STATUS_OVF | \166 DMA_STATUS_MSK_COMMON)167 168#define DMA_STATUS_MSK_TX (DMA_STATUS_ETI | \169 DMA_STATUS_UNF | \170 DMA_STATUS_TJT | \171 DMA_STATUS_TU | \172 DMA_STATUS_TPS | \173 DMA_STATUS_TI | \174 DMA_STATUS_MSK_COMMON)175 176#define NUM_DWMAC100_DMA_REGS 9177#define NUM_DWMAC1000_DMA_REGS 23178#define NUM_DWMAC4_DMA_REGS 27179 180void dwmac_enable_dma_transmission(void __iomem *ioaddr, u32 chan);181void dwmac_enable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr,182 u32 chan, bool rx, bool tx);183void dwmac_disable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr,184 u32 chan, bool rx, bool tx);185void dwmac_dma_start_tx(struct stmmac_priv *priv, void __iomem *ioaddr,186 u32 chan);187void dwmac_dma_stop_tx(struct stmmac_priv *priv, void __iomem *ioaddr,188 u32 chan);189void dwmac_dma_start_rx(struct stmmac_priv *priv, void __iomem *ioaddr,190 u32 chan);191void dwmac_dma_stop_rx(struct stmmac_priv *priv, void __iomem *ioaddr,192 u32 chan);193int dwmac_dma_interrupt(struct stmmac_priv *priv, void __iomem *ioaddr,194 struct stmmac_extra_stats *x, u32 chan, u32 dir);195int dwmac_dma_reset(void __iomem *ioaddr);196 197#endif /* __DWMAC_DMA_H__ */198