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1// SPDX-License-Identifier: GPL-2.0-only2/*******************************************************************************3 This contains the functions to handle the enhanced descriptors.4 5 Copyright (C) 2007-2014 STMicroelectronics Ltd6 7 8 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>9*******************************************************************************/10 11#include <linux/stmmac.h>12#include "common.h"13#include "descs_com.h"14 15static int enh_desc_get_tx_status(struct stmmac_extra_stats *x,16 struct dma_desc *p, void __iomem *ioaddr)17{18 unsigned int tdes0 = le32_to_cpu(p->des0);19 int ret = tx_done;20 21 /* Get tx owner first */22 if (unlikely(tdes0 & ETDES0_OWN))23 return tx_dma_own;24 25 /* Verify tx error by looking at the last segment. */26 if (likely(!(tdes0 & ETDES0_LAST_SEGMENT)))27 return tx_not_ls;28 29 if (unlikely(tdes0 & ETDES0_ERROR_SUMMARY)) {30 if (unlikely(tdes0 & ETDES0_JABBER_TIMEOUT))31 x->tx_jabber++;32 33 if (unlikely(tdes0 & ETDES0_FRAME_FLUSHED)) {34 x->tx_frame_flushed++;35 dwmac_dma_flush_tx_fifo(ioaddr);36 }37 38 if (unlikely(tdes0 & ETDES0_LOSS_CARRIER)) {39 x->tx_losscarrier++;40 }41 if (unlikely(tdes0 & ETDES0_NO_CARRIER)) {42 x->tx_carrier++;43 }44 if (unlikely((tdes0 & ETDES0_LATE_COLLISION) ||45 (tdes0 & ETDES0_EXCESSIVE_COLLISIONS)))46 x->tx_collision +=47 (tdes0 & ETDES0_COLLISION_COUNT_MASK) >> 3;48 49 if (unlikely(tdes0 & ETDES0_EXCESSIVE_DEFERRAL))50 x->tx_deferred++;51 52 if (unlikely(tdes0 & ETDES0_UNDERFLOW_ERROR)) {53 dwmac_dma_flush_tx_fifo(ioaddr);54 x->tx_underflow++;55 }56 57 if (unlikely(tdes0 & ETDES0_IP_HEADER_ERROR))58 x->tx_ip_header_error++;59 60 if (unlikely(tdes0 & ETDES0_PAYLOAD_ERROR)) {61 x->tx_payload_error++;62 dwmac_dma_flush_tx_fifo(ioaddr);63 }64 65 ret = tx_err;66 }67 68 if (unlikely(tdes0 & ETDES0_DEFERRED))69 x->tx_deferred++;70 71#ifdef STMMAC_VLAN_TAG_USED72 if (tdes0 & ETDES0_VLAN_FRAME)73 x->tx_vlan++;74#endif75 76 return ret;77}78 79static int enh_desc_get_tx_len(struct dma_desc *p)80{81 return (le32_to_cpu(p->des1) & ETDES1_BUFFER1_SIZE_MASK);82}83 84static int enh_desc_coe_rdes0(int ipc_err, int type, int payload_err)85{86 int ret = good_frame;87 u32 status = (type << 2 | ipc_err << 1 | payload_err) & 0x7;88 89 /* bits 5 7 0 | Frame status90 * ----------------------------------------------------------91 * 0 0 0 | IEEE 802.3 Type frame (length < 1536 octects)92 * 1 0 0 | IPv4/6 No CSUM errorS.93 * 1 0 1 | IPv4/6 CSUM PAYLOAD error94 * 1 1 0 | IPv4/6 CSUM IP HR error95 * 1 1 1 | IPv4/6 IP PAYLOAD AND HEADER errorS96 * 0 0 1 | IPv4/6 unsupported IP PAYLOAD97 * 0 1 1 | COE bypassed.. no IPv4/6 frame98 * 0 1 0 | Reserved.99 */100 if (status == 0x0)101 ret = llc_snap;102 else if (status == 0x4)103 ret = good_frame;104 else if (status == 0x5)105 ret = csum_none;106 else if (status == 0x6)107 ret = csum_none;108 else if (status == 0x7)109 ret = csum_none;110 else if (status == 0x1)111 ret = discard_frame;112 else if (status == 0x3)113 ret = discard_frame;114 return ret;115}116 117static void enh_desc_get_ext_status(struct stmmac_extra_stats *x,118 struct dma_extended_desc *p)119{120 unsigned int rdes0 = le32_to_cpu(p->basic.des0);121 unsigned int rdes4 = le32_to_cpu(p->des4);122 123 if (unlikely(rdes0 & ERDES0_RX_MAC_ADDR)) {124 int message_type = (rdes4 & ERDES4_MSG_TYPE_MASK) >> 8;125 126 if (rdes4 & ERDES4_IP_HDR_ERR)127 x->ip_hdr_err++;128 if (rdes4 & ERDES4_IP_PAYLOAD_ERR)129 x->ip_payload_err++;130 if (rdes4 & ERDES4_IP_CSUM_BYPASSED)131 x->ip_csum_bypassed++;132 if (rdes4 & ERDES4_IPV4_PKT_RCVD)133 x->ipv4_pkt_rcvd++;134 if (rdes4 & ERDES4_IPV6_PKT_RCVD)135 x->ipv6_pkt_rcvd++;136 137 if (message_type == RDES_EXT_NO_PTP)138 x->no_ptp_rx_msg_type_ext++;139 else if (message_type == RDES_EXT_SYNC)140 x->ptp_rx_msg_type_sync++;141 else if (message_type == RDES_EXT_FOLLOW_UP)142 x->ptp_rx_msg_type_follow_up++;143 else if (message_type == RDES_EXT_DELAY_REQ)144 x->ptp_rx_msg_type_delay_req++;145 else if (message_type == RDES_EXT_DELAY_RESP)146 x->ptp_rx_msg_type_delay_resp++;147 else if (message_type == RDES_EXT_PDELAY_REQ)148 x->ptp_rx_msg_type_pdelay_req++;149 else if (message_type == RDES_EXT_PDELAY_RESP)150 x->ptp_rx_msg_type_pdelay_resp++;151 else if (message_type == RDES_EXT_PDELAY_FOLLOW_UP)152 x->ptp_rx_msg_type_pdelay_follow_up++;153 else if (message_type == RDES_PTP_ANNOUNCE)154 x->ptp_rx_msg_type_announce++;155 else if (message_type == RDES_PTP_MANAGEMENT)156 x->ptp_rx_msg_type_management++;157 else if (message_type == RDES_PTP_PKT_RESERVED_TYPE)158 x->ptp_rx_msg_pkt_reserved_type++;159 160 if (rdes4 & ERDES4_PTP_FRAME_TYPE)161 x->ptp_frame_type++;162 if (rdes4 & ERDES4_PTP_VER)163 x->ptp_ver++;164 if (rdes4 & ERDES4_TIMESTAMP_DROPPED)165 x->timestamp_dropped++;166 if (rdes4 & ERDES4_AV_PKT_RCVD)167 x->av_pkt_rcvd++;168 if (rdes4 & ERDES4_AV_TAGGED_PKT_RCVD)169 x->av_tagged_pkt_rcvd++;170 if ((rdes4 & ERDES4_VLAN_TAG_PRI_VAL_MASK) >> 18)171 x->vlan_tag_priority_val++;172 if (rdes4 & ERDES4_L3_FILTER_MATCH)173 x->l3_filter_match++;174 if (rdes4 & ERDES4_L4_FILTER_MATCH)175 x->l4_filter_match++;176 if ((rdes4 & ERDES4_L3_L4_FILT_NO_MATCH_MASK) >> 26)177 x->l3_l4_filter_no_match++;178 }179}180 181static int enh_desc_get_rx_status(struct stmmac_extra_stats *x,182 struct dma_desc *p)183{184 unsigned int rdes0 = le32_to_cpu(p->des0);185 int ret = good_frame;186 187 if (unlikely(rdes0 & RDES0_OWN))188 return dma_own;189 190 if (unlikely(!(rdes0 & RDES0_LAST_DESCRIPTOR))) {191 x->rx_length++;192 return discard_frame;193 }194 195 if (unlikely(rdes0 & RDES0_ERROR_SUMMARY)) {196 if (unlikely(rdes0 & RDES0_DESCRIPTOR_ERROR)) {197 x->rx_desc++;198 x->rx_length++;199 }200 if (unlikely(rdes0 & RDES0_OVERFLOW_ERROR))201 x->rx_gmac_overflow++;202 203 if (unlikely(rdes0 & RDES0_IPC_CSUM_ERROR))204 pr_err("\tIPC Csum Error/Giant frame\n");205 206 if (unlikely(rdes0 & RDES0_COLLISION))207 x->rx_collision++;208 if (unlikely(rdes0 & RDES0_RECEIVE_WATCHDOG))209 x->rx_watchdog++;210 211 if (unlikely(rdes0 & RDES0_MII_ERROR)) /* GMII */212 x->rx_mii++;213 214 if (unlikely(rdes0 & RDES0_CRC_ERROR)) {215 x->rx_crc_errors++;216 }217 ret = discard_frame;218 }219 220 /* After a payload csum error, the ES bit is set.221 * It doesn't match with the information reported into the databook.222 * At any rate, we need to understand if the CSUM hw computation is ok223 * and report this info to the upper layers. */224 if (likely(ret == good_frame))225 ret = enh_desc_coe_rdes0(!!(rdes0 & RDES0_IPC_CSUM_ERROR),226 !!(rdes0 & RDES0_FRAME_TYPE),227 !!(rdes0 & ERDES0_RX_MAC_ADDR));228 229 if (unlikely(rdes0 & RDES0_DRIBBLING))230 x->dribbling_bit++;231 232 if (unlikely(rdes0 & RDES0_SA_FILTER_FAIL)) {233 x->sa_rx_filter_fail++;234 ret = discard_frame;235 }236 if (unlikely(rdes0 & RDES0_DA_FILTER_FAIL)) {237 x->da_rx_filter_fail++;238 ret = discard_frame;239 }240 if (unlikely(rdes0 & RDES0_LENGTH_ERROR)) {241 x->rx_length++;242 ret = discard_frame;243 }244#ifdef STMMAC_VLAN_TAG_USED245 if (rdes0 & RDES0_VLAN_TAG)246 x->rx_vlan++;247#endif248 249 return ret;250}251 252static void enh_desc_init_rx_desc(struct dma_desc *p, int disable_rx_ic,253 int mode, int end, int bfsize)254{255 int bfsize1;256 257 p->des0 |= cpu_to_le32(RDES0_OWN);258 259 bfsize1 = min(bfsize, BUF_SIZE_8KiB);260 p->des1 |= cpu_to_le32(bfsize1 & ERDES1_BUFFER1_SIZE_MASK);261 262 if (mode == STMMAC_CHAIN_MODE)263 ehn_desc_rx_set_on_chain(p);264 else265 ehn_desc_rx_set_on_ring(p, end, bfsize);266 267 if (disable_rx_ic)268 p->des1 |= cpu_to_le32(ERDES1_DISABLE_IC);269}270 271static void enh_desc_init_tx_desc(struct dma_desc *p, int mode, int end)272{273 p->des0 &= cpu_to_le32(~ETDES0_OWN);274 if (mode == STMMAC_CHAIN_MODE)275 enh_desc_end_tx_desc_on_chain(p);276 else277 enh_desc_end_tx_desc_on_ring(p, end);278}279 280static int enh_desc_get_tx_owner(struct dma_desc *p)281{282 return (le32_to_cpu(p->des0) & ETDES0_OWN) >> 31;283}284 285static void enh_desc_set_tx_owner(struct dma_desc *p)286{287 p->des0 |= cpu_to_le32(ETDES0_OWN);288}289 290static void enh_desc_set_rx_owner(struct dma_desc *p, int disable_rx_ic)291{292 p->des0 |= cpu_to_le32(RDES0_OWN);293}294 295static int enh_desc_get_tx_ls(struct dma_desc *p)296{297 return (le32_to_cpu(p->des0) & ETDES0_LAST_SEGMENT) >> 29;298}299 300static void enh_desc_release_tx_desc(struct dma_desc *p, int mode)301{302 int ter = (le32_to_cpu(p->des0) & ETDES0_END_RING) >> 21;303 304 memset(p, 0, offsetof(struct dma_desc, des2));305 if (mode == STMMAC_CHAIN_MODE)306 enh_desc_end_tx_desc_on_chain(p);307 else308 enh_desc_end_tx_desc_on_ring(p, ter);309}310 311static void enh_desc_prepare_tx_desc(struct dma_desc *p, int is_fs, int len,312 bool csum_flag, int mode, bool tx_own,313 bool ls, unsigned int tot_pkt_len)314{315 unsigned int tdes0 = le32_to_cpu(p->des0);316 317 if (mode == STMMAC_CHAIN_MODE)318 enh_set_tx_desc_len_on_chain(p, len);319 else320 enh_set_tx_desc_len_on_ring(p, len);321 322 if (is_fs)323 tdes0 |= ETDES0_FIRST_SEGMENT;324 else325 tdes0 &= ~ETDES0_FIRST_SEGMENT;326 327 if (likely(csum_flag))328 tdes0 |= (TX_CIC_FULL << ETDES0_CHECKSUM_INSERTION_SHIFT);329 else330 tdes0 &= ~(TX_CIC_FULL << ETDES0_CHECKSUM_INSERTION_SHIFT);331 332 if (ls)333 tdes0 |= ETDES0_LAST_SEGMENT;334 335 /* Finally set the OWN bit. Later the DMA will start! */336 if (tx_own)337 tdes0 |= ETDES0_OWN;338 339 if (is_fs && tx_own)340 /* When the own bit, for the first frame, has to be set, all341 * descriptors for the same frame has to be set before, to342 * avoid race condition.343 */344 dma_wmb();345 346 p->des0 = cpu_to_le32(tdes0);347}348 349static void enh_desc_set_tx_ic(struct dma_desc *p)350{351 p->des0 |= cpu_to_le32(ETDES0_INTERRUPT);352}353 354static int enh_desc_get_rx_frame_len(struct dma_desc *p, int rx_coe_type)355{356 unsigned int csum = 0;357 /* The type-1 checksum offload engines append the checksum at358 * the end of frame and the two bytes of checksum are added in359 * the length.360 * Adjust for that in the framelen for type-1 checksum offload361 * engines.362 */363 if (rx_coe_type == STMMAC_RX_COE_TYPE1)364 csum = 2;365 366 return (((le32_to_cpu(p->des0) & RDES0_FRAME_LEN_MASK)367 >> RDES0_FRAME_LEN_SHIFT) - csum);368}369 370static void enh_desc_enable_tx_timestamp(struct dma_desc *p)371{372 p->des0 |= cpu_to_le32(ETDES0_TIME_STAMP_ENABLE);373}374 375static int enh_desc_get_tx_timestamp_status(struct dma_desc *p)376{377 return (le32_to_cpu(p->des0) & ETDES0_TIME_STAMP_STATUS) >> 17;378}379 380static void enh_desc_get_timestamp(void *desc, u32 ats, u64 *ts)381{382 u64 ns;383 384 if (ats) {385 struct dma_extended_desc *p = (struct dma_extended_desc *)desc;386 ns = le32_to_cpu(p->des6);387 /* convert high/sec time stamp value to nanosecond */388 ns += le32_to_cpu(p->des7) * 1000000000ULL;389 } else {390 struct dma_desc *p = (struct dma_desc *)desc;391 ns = le32_to_cpu(p->des2);392 ns += le32_to_cpu(p->des3) * 1000000000ULL;393 }394 395 *ts = ns;396}397 398static int enh_desc_get_rx_timestamp_status(void *desc, void *next_desc,399 u32 ats)400{401 if (ats) {402 struct dma_extended_desc *p = (struct dma_extended_desc *)desc;403 return (le32_to_cpu(p->basic.des0) & RDES0_IPC_CSUM_ERROR) >> 7;404 } else {405 struct dma_desc *p = (struct dma_desc *)desc;406 if ((le32_to_cpu(p->des2) == 0xffffffff) &&407 (le32_to_cpu(p->des3) == 0xffffffff))408 /* timestamp is corrupted, hence don't store it */409 return 0;410 else411 return 1;412 }413}414 415static void enh_desc_display_ring(void *head, unsigned int size, bool rx,416 dma_addr_t dma_rx_phy, unsigned int desc_size)417{418 struct dma_extended_desc *ep = (struct dma_extended_desc *)head;419 dma_addr_t dma_addr;420 int i;421 422 pr_info("Extended %s descriptor ring:\n", rx ? "RX" : "TX");423 424 for (i = 0; i < size; i++) {425 u64 x;426 dma_addr = dma_rx_phy + i * sizeof(*ep);427 428 x = *(u64 *)ep;429 pr_info("%03d [%pad]: 0x%x 0x%x 0x%x 0x%x\n",430 i, &dma_addr,431 (unsigned int)x, (unsigned int)(x >> 32),432 ep->basic.des2, ep->basic.des3);433 ep++;434 }435 pr_info("\n");436}437 438static void enh_desc_set_addr(struct dma_desc *p, dma_addr_t addr)439{440 p->des2 = cpu_to_le32(addr);441}442 443static void enh_desc_clear(struct dma_desc *p)444{445 p->des2 = 0;446}447 448const struct stmmac_desc_ops enh_desc_ops = {449 .tx_status = enh_desc_get_tx_status,450 .rx_status = enh_desc_get_rx_status,451 .get_tx_len = enh_desc_get_tx_len,452 .init_rx_desc = enh_desc_init_rx_desc,453 .init_tx_desc = enh_desc_init_tx_desc,454 .get_tx_owner = enh_desc_get_tx_owner,455 .release_tx_desc = enh_desc_release_tx_desc,456 .prepare_tx_desc = enh_desc_prepare_tx_desc,457 .set_tx_ic = enh_desc_set_tx_ic,458 .get_tx_ls = enh_desc_get_tx_ls,459 .set_tx_owner = enh_desc_set_tx_owner,460 .set_rx_owner = enh_desc_set_rx_owner,461 .get_rx_frame_len = enh_desc_get_rx_frame_len,462 .rx_extended_status = enh_desc_get_ext_status,463 .enable_tx_timestamp = enh_desc_enable_tx_timestamp,464 .get_tx_timestamp_status = enh_desc_get_tx_timestamp_status,465 .get_timestamp = enh_desc_get_timestamp,466 .get_rx_timestamp_status = enh_desc_get_rx_timestamp_status,467 .display_ring = enh_desc_display_ring,468 .set_addr = enh_desc_set_addr,469 .clear = enh_desc_clear,470};471