607 lines · c
1// SPDX-License-Identifier: GPL-2.0-only2/*******************************************************************************3 DWMAC Management Counters4 5 Copyright (C) 2011 STMicroelectronics Ltd6 7 8 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>9*******************************************************************************/10 11#include <linux/kernel.h>12#include <linux/io.h>13#include "hwif.h"14#include "mmc.h"15 16/* MAC Management Counters register offset */17 18#define MMC_CNTRL 0x00 /* MMC Control */19#define MMC_RX_INTR 0x04 /* MMC RX Interrupt */20#define MMC_TX_INTR 0x08 /* MMC TX Interrupt */21#define MMC_RX_INTR_MASK 0x0c /* MMC Interrupt Mask */22#define MMC_TX_INTR_MASK 0x10 /* MMC Interrupt Mask */23#define MMC_DEFAULT_MASK 0xffffffff24 25/* MMC TX counter registers */26 27/* Note:28 * _GB register stands for good and bad frames29 * _G is for good only.30 */31#define MMC_TX_OCTETCOUNT_GB 0x1432#define MMC_TX_FRAMECOUNT_GB 0x1833#define MMC_TX_BROADCASTFRAME_G 0x1c34#define MMC_TX_MULTICASTFRAME_G 0x2035#define MMC_TX_64_OCTETS_GB 0x2436#define MMC_TX_65_TO_127_OCTETS_GB 0x2837#define MMC_TX_128_TO_255_OCTETS_GB 0x2c38#define MMC_TX_256_TO_511_OCTETS_GB 0x3039#define MMC_TX_512_TO_1023_OCTETS_GB 0x3440#define MMC_TX_1024_TO_MAX_OCTETS_GB 0x3841#define MMC_TX_UNICAST_GB 0x3c42#define MMC_TX_MULTICAST_GB 0x4043#define MMC_TX_BROADCAST_GB 0x4444#define MMC_TX_UNDERFLOW_ERROR 0x4845#define MMC_TX_SINGLECOL_G 0x4c46#define MMC_TX_MULTICOL_G 0x5047#define MMC_TX_DEFERRED 0x5448#define MMC_TX_LATECOL 0x5849#define MMC_TX_EXESSCOL 0x5c50#define MMC_TX_CARRIER_ERROR 0x6051#define MMC_TX_OCTETCOUNT_G 0x6452#define MMC_TX_FRAMECOUNT_G 0x6853#define MMC_TX_EXCESSDEF 0x6c54#define MMC_TX_PAUSE_FRAME 0x7055#define MMC_TX_VLAN_FRAME_G 0x7456#define MMC_TX_OVERSIZE_G 0x7857 58/* MMC RX counter registers */59#define MMC_RX_FRAMECOUNT_GB 0x8060#define MMC_RX_OCTETCOUNT_GB 0x8461#define MMC_RX_OCTETCOUNT_G 0x8862#define MMC_RX_BROADCASTFRAME_G 0x8c63#define MMC_RX_MULTICASTFRAME_G 0x9064#define MMC_RX_CRC_ERROR 0x9465#define MMC_RX_ALIGN_ERROR 0x9866#define MMC_RX_RUN_ERROR 0x9C67#define MMC_RX_JABBER_ERROR 0xA068#define MMC_RX_UNDERSIZE_G 0xA469#define MMC_RX_OVERSIZE_G 0xA870#define MMC_RX_64_OCTETS_GB 0xAC71#define MMC_RX_65_TO_127_OCTETS_GB 0xb072#define MMC_RX_128_TO_255_OCTETS_GB 0xb473#define MMC_RX_256_TO_511_OCTETS_GB 0xb874#define MMC_RX_512_TO_1023_OCTETS_GB 0xbc75#define MMC_RX_1024_TO_MAX_OCTETS_GB 0xc076#define MMC_RX_UNICAST_G 0xc477#define MMC_RX_LENGTH_ERROR 0xc878#define MMC_RX_AUTOFRANGETYPE 0xcc79#define MMC_RX_PAUSE_FRAMES 0xd080#define MMC_RX_FIFO_OVERFLOW 0xd481#define MMC_RX_VLAN_FRAMES_GB 0xd882#define MMC_RX_WATCHDOG_ERROR 0xdc83#define MMC_RX_ERROR 0xe084 85#define MMC_TX_LPI_USEC 0xec86#define MMC_TX_LPI_TRAN 0xf087#define MMC_RX_LPI_USEC 0xf488#define MMC_RX_LPI_TRAN 0xf889 90/* IPC*/91#define MMC_RX_IPC_INTR_MASK 0x10092#define MMC_RX_IPC_INTR 0x10893/* IPv4*/94#define MMC_RX_IPV4_GD 0x11095#define MMC_RX_IPV4_HDERR 0x11496#define MMC_RX_IPV4_NOPAY 0x11897#define MMC_RX_IPV4_FRAG 0x11C98#define MMC_RX_IPV4_UDSBL 0x12099 100#define MMC_RX_IPV4_GD_OCTETS 0x150101#define MMC_RX_IPV4_HDERR_OCTETS 0x154102#define MMC_RX_IPV4_NOPAY_OCTETS 0x158103#define MMC_RX_IPV4_FRAG_OCTETS 0x15c104#define MMC_RX_IPV4_UDSBL_OCTETS 0x160105 106/* IPV6*/107#define MMC_RX_IPV6_GD_OCTETS 0x164108#define MMC_RX_IPV6_HDERR_OCTETS 0x168109#define MMC_RX_IPV6_NOPAY_OCTETS 0x16c110 111#define MMC_RX_IPV6_GD 0x124112#define MMC_RX_IPV6_HDERR 0x128113#define MMC_RX_IPV6_NOPAY 0x12c114 115/* Protocols*/116#define MMC_RX_UDP_GD 0x130117#define MMC_RX_UDP_ERR 0x134118#define MMC_RX_TCP_GD 0x138119#define MMC_RX_TCP_ERR 0x13c120#define MMC_RX_ICMP_GD 0x140121#define MMC_RX_ICMP_ERR 0x144122 123#define MMC_RX_UDP_GD_OCTETS 0x170124#define MMC_RX_UDP_ERR_OCTETS 0x174125#define MMC_RX_TCP_GD_OCTETS 0x178126#define MMC_RX_TCP_ERR_OCTETS 0x17c127#define MMC_RX_ICMP_GD_OCTETS 0x180128#define MMC_RX_ICMP_ERR_OCTETS 0x184129 130#define MMC_TX_FPE_FRAG 0x1a8131#define MMC_TX_HOLD_REQ 0x1ac132#define MMC_RX_PKT_ASSEMBLY_ERR 0x1c8133#define MMC_RX_PKT_SMD_ERR 0x1cc134#define MMC_RX_PKT_ASSEMBLY_OK 0x1d0135#define MMC_RX_FPE_FRAG 0x1d4136 137/* XGMAC MMC Registers */138#define MMC_XGMAC_TX_OCTET_GB 0x14139#define MMC_XGMAC_TX_PKT_GB 0x1c140#define MMC_XGMAC_TX_BROAD_PKT_G 0x24141#define MMC_XGMAC_TX_MULTI_PKT_G 0x2c142#define MMC_XGMAC_TX_64OCT_GB 0x34143#define MMC_XGMAC_TX_65OCT_GB 0x3c144#define MMC_XGMAC_TX_128OCT_GB 0x44145#define MMC_XGMAC_TX_256OCT_GB 0x4c146#define MMC_XGMAC_TX_512OCT_GB 0x54147#define MMC_XGMAC_TX_1024OCT_GB 0x5c148#define MMC_XGMAC_TX_UNI_PKT_GB 0x64149#define MMC_XGMAC_TX_MULTI_PKT_GB 0x6c150#define MMC_XGMAC_TX_BROAD_PKT_GB 0x74151#define MMC_XGMAC_TX_UNDER 0x7c152#define MMC_XGMAC_TX_OCTET_G 0x84153#define MMC_XGMAC_TX_PKT_G 0x8c154#define MMC_XGMAC_TX_PAUSE 0x94155#define MMC_XGMAC_TX_VLAN_PKT_G 0x9c156#define MMC_XGMAC_TX_LPI_USEC 0xa4157#define MMC_XGMAC_TX_LPI_TRAN 0xa8158 159#define MMC_XGMAC_RX_PKT_GB 0x100160#define MMC_XGMAC_RX_OCTET_GB 0x108161#define MMC_XGMAC_RX_OCTET_G 0x110162#define MMC_XGMAC_RX_BROAD_PKT_G 0x118163#define MMC_XGMAC_RX_MULTI_PKT_G 0x120164#define MMC_XGMAC_RX_CRC_ERR 0x128165#define MMC_XGMAC_RX_RUNT_ERR 0x130166#define MMC_XGMAC_RX_JABBER_ERR 0x134167#define MMC_XGMAC_RX_UNDER 0x138168#define MMC_XGMAC_RX_OVER 0x13c169#define MMC_XGMAC_RX_64OCT_GB 0x140170#define MMC_XGMAC_RX_65OCT_GB 0x148171#define MMC_XGMAC_RX_128OCT_GB 0x150172#define MMC_XGMAC_RX_256OCT_GB 0x158173#define MMC_XGMAC_RX_512OCT_GB 0x160174#define MMC_XGMAC_RX_1024OCT_GB 0x168175#define MMC_XGMAC_RX_UNI_PKT_G 0x170176#define MMC_XGMAC_RX_LENGTH_ERR 0x178177#define MMC_XGMAC_RX_RANGE 0x180178#define MMC_XGMAC_RX_PAUSE 0x188179#define MMC_XGMAC_RX_FIFOOVER_PKT 0x190180#define MMC_XGMAC_RX_VLAN_PKT_GB 0x198181#define MMC_XGMAC_RX_WATCHDOG_ERR 0x1a0182#define MMC_XGMAC_RX_LPI_USEC 0x1a4183#define MMC_XGMAC_RX_LPI_TRAN 0x1a8184#define MMC_XGMAC_RX_DISCARD_PKT_GB 0x1ac185#define MMC_XGMAC_RX_DISCARD_OCT_GB 0x1b4186#define MMC_XGMAC_RX_ALIGN_ERR_PKT 0x1bc187 188#define MMC_XGMAC_SGF_PASS_PKT 0x1f0189#define MMC_XGMAC_SGF_FAIL_PKT 0x1f4190#define MMC_XGMAC_TX_FPE_INTR_MASK 0x204191#define MMC_XGMAC_TX_FPE_FRAG 0x208192#define MMC_XGMAC_TX_HOLD_REQ 0x20c193#define MMC_XGMAC_TX_GATE_OVERRUN 0x210194#define MMC_XGMAC_RX_FPE_INTR_MASK 0x224195#define MMC_XGMAC_RX_PKT_ASSEMBLY_ERR 0x228196#define MMC_XGMAC_RX_PKT_SMD_ERR 0x22c197#define MMC_XGMAC_RX_PKT_ASSEMBLY_OK 0x230198#define MMC_XGMAC_RX_FPE_FRAG 0x234199#define MMC_XGMAC_RX_IPC_INTR_MASK 0x25c200 201#define MMC_XGMAC_RX_IPV4_GD 0x264202#define MMC_XGMAC_RX_IPV4_HDERR 0x26c203#define MMC_XGMAC_RX_IPV4_NOPAY 0x274204#define MMC_XGMAC_RX_IPV4_FRAG 0x27c205#define MMC_XGMAC_RX_IPV4_UDSBL 0x284206 207#define MMC_XGMAC_RX_IPV6_GD 0x28c208#define MMC_XGMAC_RX_IPV6_HDERR 0x294209#define MMC_XGMAC_RX_IPV6_NOPAY 0x29c210 211#define MMC_XGMAC_RX_UDP_GD 0x2a4212#define MMC_XGMAC_RX_UDP_ERR 0x2ac213#define MMC_XGMAC_RX_TCP_GD 0x2b4214#define MMC_XGMAC_RX_TCP_ERR 0x2bc215#define MMC_XGMAC_RX_ICMP_GD 0x2c4216#define MMC_XGMAC_RX_ICMP_ERR 0x2cc217 218#define MMC_XGMAC_RX_IPV4_GD_OCTETS 0x2d4219#define MMC_XGMAC_RX_IPV4_HDERR_OCTETS 0x2dc220#define MMC_XGMAC_RX_IPV4_NOPAY_OCTETS 0x2e4221#define MMC_XGMAC_RX_IPV4_FRAG_OCTETS 0x2ec222#define MMC_XGMAC_RX_IPV4_UDSBL_OCTETS 0x2f4223 224#define MMC_XGMAC_RX_IPV6_GD_OCTETS 0x2fc225#define MMC_XGMAC_RX_IPV6_HDERR_OCTETS 0x304226#define MMC_XGMAC_RX_IPV6_NOPAY_OCTETS 0x30c227 228#define MMC_XGMAC_RX_UDP_GD_OCTETS 0x314229#define MMC_XGMAC_RX_UDP_ERR_OCTETS 0x31c230#define MMC_XGMAC_RX_TCP_GD_OCTETS 0x324231#define MMC_XGMAC_RX_TCP_ERR_OCTETS 0x32c232#define MMC_XGMAC_RX_ICMP_GD_OCTETS 0x334233#define MMC_XGMAC_RX_ICMP_ERR_OCTETS 0x33c234 235static void dwmac_mmc_ctrl(void __iomem *mmcaddr, unsigned int mode)236{237 u32 value = readl(mmcaddr + MMC_CNTRL);238 239 value |= (mode & 0x3F);240 241 writel(value, mmcaddr + MMC_CNTRL);242 243 pr_debug("stmmac: MMC ctrl register (offset 0x%x): 0x%08x\n",244 MMC_CNTRL, value);245}246 247/* To mask all interrupts.*/248static void dwmac_mmc_intr_all_mask(void __iomem *mmcaddr)249{250 writel(MMC_DEFAULT_MASK, mmcaddr + MMC_RX_INTR_MASK);251 writel(MMC_DEFAULT_MASK, mmcaddr + MMC_TX_INTR_MASK);252 writel(MMC_DEFAULT_MASK, mmcaddr + MMC_RX_IPC_INTR_MASK);253}254 255/* This reads the MAC core counters (if actaully supported).256 * by default the MMC core is programmed to reset each257 * counter after a read. So all the field of the mmc struct258 * have to be incremented.259 */260static void dwmac_mmc_read(void __iomem *mmcaddr, struct stmmac_counters *mmc)261{262 mmc->mmc_tx_octetcount_gb += readl(mmcaddr + MMC_TX_OCTETCOUNT_GB);263 mmc->mmc_tx_framecount_gb += readl(mmcaddr + MMC_TX_FRAMECOUNT_GB);264 mmc->mmc_tx_broadcastframe_g += readl(mmcaddr +265 MMC_TX_BROADCASTFRAME_G);266 mmc->mmc_tx_multicastframe_g += readl(mmcaddr +267 MMC_TX_MULTICASTFRAME_G);268 mmc->mmc_tx_64_octets_gb += readl(mmcaddr + MMC_TX_64_OCTETS_GB);269 mmc->mmc_tx_65_to_127_octets_gb +=270 readl(mmcaddr + MMC_TX_65_TO_127_OCTETS_GB);271 mmc->mmc_tx_128_to_255_octets_gb +=272 readl(mmcaddr + MMC_TX_128_TO_255_OCTETS_GB);273 mmc->mmc_tx_256_to_511_octets_gb +=274 readl(mmcaddr + MMC_TX_256_TO_511_OCTETS_GB);275 mmc->mmc_tx_512_to_1023_octets_gb +=276 readl(mmcaddr + MMC_TX_512_TO_1023_OCTETS_GB);277 mmc->mmc_tx_1024_to_max_octets_gb +=278 readl(mmcaddr + MMC_TX_1024_TO_MAX_OCTETS_GB);279 mmc->mmc_tx_unicast_gb += readl(mmcaddr + MMC_TX_UNICAST_GB);280 mmc->mmc_tx_multicast_gb += readl(mmcaddr + MMC_TX_MULTICAST_GB);281 mmc->mmc_tx_broadcast_gb += readl(mmcaddr + MMC_TX_BROADCAST_GB);282 mmc->mmc_tx_underflow_error += readl(mmcaddr + MMC_TX_UNDERFLOW_ERROR);283 mmc->mmc_tx_singlecol_g += readl(mmcaddr + MMC_TX_SINGLECOL_G);284 mmc->mmc_tx_multicol_g += readl(mmcaddr + MMC_TX_MULTICOL_G);285 mmc->mmc_tx_deferred += readl(mmcaddr + MMC_TX_DEFERRED);286 mmc->mmc_tx_latecol += readl(mmcaddr + MMC_TX_LATECOL);287 mmc->mmc_tx_exesscol += readl(mmcaddr + MMC_TX_EXESSCOL);288 mmc->mmc_tx_carrier_error += readl(mmcaddr + MMC_TX_CARRIER_ERROR);289 mmc->mmc_tx_octetcount_g += readl(mmcaddr + MMC_TX_OCTETCOUNT_G);290 mmc->mmc_tx_framecount_g += readl(mmcaddr + MMC_TX_FRAMECOUNT_G);291 mmc->mmc_tx_excessdef += readl(mmcaddr + MMC_TX_EXCESSDEF);292 mmc->mmc_tx_pause_frame += readl(mmcaddr + MMC_TX_PAUSE_FRAME);293 mmc->mmc_tx_vlan_frame_g += readl(mmcaddr + MMC_TX_VLAN_FRAME_G);294 mmc->mmc_tx_oversize_g += readl(mmcaddr + MMC_TX_OVERSIZE_G);295 mmc->mmc_tx_lpi_usec += readl(mmcaddr + MMC_TX_LPI_USEC);296 mmc->mmc_tx_lpi_tran += readl(mmcaddr + MMC_TX_LPI_TRAN);297 298 /* MMC RX counter registers */299 mmc->mmc_rx_framecount_gb += readl(mmcaddr + MMC_RX_FRAMECOUNT_GB);300 mmc->mmc_rx_octetcount_gb += readl(mmcaddr + MMC_RX_OCTETCOUNT_GB);301 mmc->mmc_rx_octetcount_g += readl(mmcaddr + MMC_RX_OCTETCOUNT_G);302 mmc->mmc_rx_broadcastframe_g += readl(mmcaddr +303 MMC_RX_BROADCASTFRAME_G);304 mmc->mmc_rx_multicastframe_g += readl(mmcaddr +305 MMC_RX_MULTICASTFRAME_G);306 mmc->mmc_rx_crc_error += readl(mmcaddr + MMC_RX_CRC_ERROR);307 mmc->mmc_rx_align_error += readl(mmcaddr + MMC_RX_ALIGN_ERROR);308 mmc->mmc_rx_run_error += readl(mmcaddr + MMC_RX_RUN_ERROR);309 mmc->mmc_rx_jabber_error += readl(mmcaddr + MMC_RX_JABBER_ERROR);310 mmc->mmc_rx_undersize_g += readl(mmcaddr + MMC_RX_UNDERSIZE_G);311 mmc->mmc_rx_oversize_g += readl(mmcaddr + MMC_RX_OVERSIZE_G);312 mmc->mmc_rx_64_octets_gb += readl(mmcaddr + MMC_RX_64_OCTETS_GB);313 mmc->mmc_rx_65_to_127_octets_gb +=314 readl(mmcaddr + MMC_RX_65_TO_127_OCTETS_GB);315 mmc->mmc_rx_128_to_255_octets_gb +=316 readl(mmcaddr + MMC_RX_128_TO_255_OCTETS_GB);317 mmc->mmc_rx_256_to_511_octets_gb +=318 readl(mmcaddr + MMC_RX_256_TO_511_OCTETS_GB);319 mmc->mmc_rx_512_to_1023_octets_gb +=320 readl(mmcaddr + MMC_RX_512_TO_1023_OCTETS_GB);321 mmc->mmc_rx_1024_to_max_octets_gb +=322 readl(mmcaddr + MMC_RX_1024_TO_MAX_OCTETS_GB);323 mmc->mmc_rx_unicast_g += readl(mmcaddr + MMC_RX_UNICAST_G);324 mmc->mmc_rx_length_error += readl(mmcaddr + MMC_RX_LENGTH_ERROR);325 mmc->mmc_rx_autofrangetype += readl(mmcaddr + MMC_RX_AUTOFRANGETYPE);326 mmc->mmc_rx_pause_frames += readl(mmcaddr + MMC_RX_PAUSE_FRAMES);327 mmc->mmc_rx_fifo_overflow += readl(mmcaddr + MMC_RX_FIFO_OVERFLOW);328 mmc->mmc_rx_vlan_frames_gb += readl(mmcaddr + MMC_RX_VLAN_FRAMES_GB);329 mmc->mmc_rx_watchdog_error += readl(mmcaddr + MMC_RX_WATCHDOG_ERROR);330 mmc->mmc_rx_error += readl(mmcaddr + MMC_RX_ERROR);331 mmc->mmc_rx_lpi_usec += readl(mmcaddr + MMC_RX_LPI_USEC);332 mmc->mmc_rx_lpi_tran += readl(mmcaddr + MMC_RX_LPI_TRAN);333 334 /* IPv4 */335 mmc->mmc_rx_ipv4_gd += readl(mmcaddr + MMC_RX_IPV4_GD);336 mmc->mmc_rx_ipv4_hderr += readl(mmcaddr + MMC_RX_IPV4_HDERR);337 mmc->mmc_rx_ipv4_nopay += readl(mmcaddr + MMC_RX_IPV4_NOPAY);338 mmc->mmc_rx_ipv4_frag += readl(mmcaddr + MMC_RX_IPV4_FRAG);339 mmc->mmc_rx_ipv4_udsbl += readl(mmcaddr + MMC_RX_IPV4_UDSBL);340 341 mmc->mmc_rx_ipv4_gd_octets += readl(mmcaddr + MMC_RX_IPV4_GD_OCTETS);342 mmc->mmc_rx_ipv4_hderr_octets +=343 readl(mmcaddr + MMC_RX_IPV4_HDERR_OCTETS);344 mmc->mmc_rx_ipv4_nopay_octets +=345 readl(mmcaddr + MMC_RX_IPV4_NOPAY_OCTETS);346 mmc->mmc_rx_ipv4_frag_octets += readl(mmcaddr +347 MMC_RX_IPV4_FRAG_OCTETS);348 mmc->mmc_rx_ipv4_udsbl_octets +=349 readl(mmcaddr + MMC_RX_IPV4_UDSBL_OCTETS);350 351 /* IPV6 */352 mmc->mmc_rx_ipv6_gd_octets += readl(mmcaddr + MMC_RX_IPV6_GD_OCTETS);353 mmc->mmc_rx_ipv6_hderr_octets +=354 readl(mmcaddr + MMC_RX_IPV6_HDERR_OCTETS);355 mmc->mmc_rx_ipv6_nopay_octets +=356 readl(mmcaddr + MMC_RX_IPV6_NOPAY_OCTETS);357 358 mmc->mmc_rx_ipv6_gd += readl(mmcaddr + MMC_RX_IPV6_GD);359 mmc->mmc_rx_ipv6_hderr += readl(mmcaddr + MMC_RX_IPV6_HDERR);360 mmc->mmc_rx_ipv6_nopay += readl(mmcaddr + MMC_RX_IPV6_NOPAY);361 362 /* Protocols */363 mmc->mmc_rx_udp_gd += readl(mmcaddr + MMC_RX_UDP_GD);364 mmc->mmc_rx_udp_err += readl(mmcaddr + MMC_RX_UDP_ERR);365 mmc->mmc_rx_tcp_gd += readl(mmcaddr + MMC_RX_TCP_GD);366 mmc->mmc_rx_tcp_err += readl(mmcaddr + MMC_RX_TCP_ERR);367 mmc->mmc_rx_icmp_gd += readl(mmcaddr + MMC_RX_ICMP_GD);368 mmc->mmc_rx_icmp_err += readl(mmcaddr + MMC_RX_ICMP_ERR);369 370 mmc->mmc_rx_udp_gd_octets += readl(mmcaddr + MMC_RX_UDP_GD_OCTETS);371 mmc->mmc_rx_udp_err_octets += readl(mmcaddr + MMC_RX_UDP_ERR_OCTETS);372 mmc->mmc_rx_tcp_gd_octets += readl(mmcaddr + MMC_RX_TCP_GD_OCTETS);373 mmc->mmc_rx_tcp_err_octets += readl(mmcaddr + MMC_RX_TCP_ERR_OCTETS);374 mmc->mmc_rx_icmp_gd_octets += readl(mmcaddr + MMC_RX_ICMP_GD_OCTETS);375 mmc->mmc_rx_icmp_err_octets += readl(mmcaddr + MMC_RX_ICMP_ERR_OCTETS);376 377 mmc->mmc_tx_fpe_fragment_cntr += readl(mmcaddr + MMC_TX_FPE_FRAG);378 mmc->mmc_tx_hold_req_cntr += readl(mmcaddr + MMC_TX_HOLD_REQ);379 mmc->mmc_rx_packet_assembly_err_cntr +=380 readl(mmcaddr + MMC_RX_PKT_ASSEMBLY_ERR);381 mmc->mmc_rx_packet_smd_err_cntr += readl(mmcaddr + MMC_RX_PKT_SMD_ERR);382 mmc->mmc_rx_packet_assembly_ok_cntr +=383 readl(mmcaddr + MMC_RX_PKT_ASSEMBLY_OK);384 mmc->mmc_rx_fpe_fragment_cntr += readl(mmcaddr + MMC_RX_FPE_FRAG);385}386 387const struct stmmac_mmc_ops dwmac_mmc_ops = {388 .ctrl = dwmac_mmc_ctrl,389 .intr_all_mask = dwmac_mmc_intr_all_mask,390 .read = dwmac_mmc_read,391};392 393static void dwxgmac_mmc_ctrl(void __iomem *mmcaddr, unsigned int mode)394{395 u32 value = readl(mmcaddr + MMC_CNTRL);396 397 value |= (mode & 0x3F);398 399 writel(value, mmcaddr + MMC_CNTRL);400}401 402static void dwxgmac_mmc_intr_all_mask(void __iomem *mmcaddr)403{404 writel(0x0, mmcaddr + MMC_RX_INTR_MASK);405 writel(0x0, mmcaddr + MMC_TX_INTR_MASK);406 writel(MMC_DEFAULT_MASK, mmcaddr + MMC_XGMAC_TX_FPE_INTR_MASK);407 writel(MMC_DEFAULT_MASK, mmcaddr + MMC_XGMAC_RX_FPE_INTR_MASK);408 writel(MMC_DEFAULT_MASK, mmcaddr + MMC_XGMAC_RX_IPC_INTR_MASK);409}410 411static void dwxgmac_read_mmc_reg(void __iomem *addr, u32 reg, u32 *dest)412{413 u64 tmp = 0;414 415 tmp += readl(addr + reg);416 tmp += ((u64 )readl(addr + reg + 0x4)) << 32;417 if (tmp > GENMASK(31, 0))418 *dest = ~0x0;419 else420 *dest = *dest + tmp;421}422 423/* This reads the MAC core counters (if actaully supported).424 * by default the MMC core is programmed to reset each425 * counter after a read. So all the field of the mmc struct426 * have to be incremented.427 */428static void dwxgmac_mmc_read(void __iomem *mmcaddr, struct stmmac_counters *mmc)429{430 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_OCTET_GB,431 &mmc->mmc_tx_octetcount_gb);432 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_PKT_GB,433 &mmc->mmc_tx_framecount_gb);434 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_BROAD_PKT_G,435 &mmc->mmc_tx_broadcastframe_g);436 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_MULTI_PKT_G,437 &mmc->mmc_tx_multicastframe_g);438 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_64OCT_GB,439 &mmc->mmc_tx_64_octets_gb);440 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_65OCT_GB,441 &mmc->mmc_tx_65_to_127_octets_gb);442 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_128OCT_GB,443 &mmc->mmc_tx_128_to_255_octets_gb);444 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_256OCT_GB,445 &mmc->mmc_tx_256_to_511_octets_gb);446 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_512OCT_GB,447 &mmc->mmc_tx_512_to_1023_octets_gb);448 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_1024OCT_GB,449 &mmc->mmc_tx_1024_to_max_octets_gb);450 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_UNI_PKT_GB,451 &mmc->mmc_tx_unicast_gb);452 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_MULTI_PKT_GB,453 &mmc->mmc_tx_multicast_gb);454 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_BROAD_PKT_GB,455 &mmc->mmc_tx_broadcast_gb);456 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_UNDER,457 &mmc->mmc_tx_underflow_error);458 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_OCTET_G,459 &mmc->mmc_tx_octetcount_g);460 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_PKT_G,461 &mmc->mmc_tx_framecount_g);462 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_PAUSE,463 &mmc->mmc_tx_pause_frame);464 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_VLAN_PKT_G,465 &mmc->mmc_tx_vlan_frame_g);466 mmc->mmc_tx_lpi_usec += readl(mmcaddr + MMC_XGMAC_TX_LPI_USEC);467 mmc->mmc_tx_lpi_tran += readl(mmcaddr + MMC_XGMAC_TX_LPI_TRAN);468 469 /* MMC RX counter registers */470 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_PKT_GB,471 &mmc->mmc_rx_framecount_gb);472 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_OCTET_GB,473 &mmc->mmc_rx_octetcount_gb);474 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_OCTET_G,475 &mmc->mmc_rx_octetcount_g);476 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_BROAD_PKT_G,477 &mmc->mmc_rx_broadcastframe_g);478 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_MULTI_PKT_G,479 &mmc->mmc_rx_multicastframe_g);480 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_CRC_ERR,481 &mmc->mmc_rx_crc_error);482 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_CRC_ERR,483 &mmc->mmc_rx_crc_error);484 mmc->mmc_rx_run_error += readl(mmcaddr + MMC_XGMAC_RX_RUNT_ERR);485 mmc->mmc_rx_jabber_error += readl(mmcaddr + MMC_XGMAC_RX_JABBER_ERR);486 mmc->mmc_rx_undersize_g += readl(mmcaddr + MMC_XGMAC_RX_UNDER);487 mmc->mmc_rx_oversize_g += readl(mmcaddr + MMC_XGMAC_RX_OVER);488 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_64OCT_GB,489 &mmc->mmc_rx_64_octets_gb);490 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_65OCT_GB,491 &mmc->mmc_rx_65_to_127_octets_gb);492 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_128OCT_GB,493 &mmc->mmc_rx_128_to_255_octets_gb);494 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_256OCT_GB,495 &mmc->mmc_rx_256_to_511_octets_gb);496 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_512OCT_GB,497 &mmc->mmc_rx_512_to_1023_octets_gb);498 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_1024OCT_GB,499 &mmc->mmc_rx_1024_to_max_octets_gb);500 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_UNI_PKT_G,501 &mmc->mmc_rx_unicast_g);502 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_LENGTH_ERR,503 &mmc->mmc_rx_length_error);504 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_RANGE,505 &mmc->mmc_rx_autofrangetype);506 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_PAUSE,507 &mmc->mmc_rx_pause_frames);508 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_FIFOOVER_PKT,509 &mmc->mmc_rx_fifo_overflow);510 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_VLAN_PKT_GB,511 &mmc->mmc_rx_vlan_frames_gb);512 mmc->mmc_rx_watchdog_error += readl(mmcaddr + MMC_XGMAC_RX_WATCHDOG_ERR);513 mmc->mmc_rx_lpi_usec += readl(mmcaddr + MMC_XGMAC_RX_LPI_USEC);514 mmc->mmc_rx_lpi_tran += readl(mmcaddr + MMC_XGMAC_RX_LPI_TRAN);515 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_DISCARD_PKT_GB,516 &mmc->mmc_rx_discard_frames_gb);517 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_DISCARD_OCT_GB,518 &mmc->mmc_rx_discard_octets_gb);519 mmc->mmc_rx_align_err_frames +=520 readl(mmcaddr + MMC_XGMAC_RX_ALIGN_ERR_PKT);521 522 mmc->mmc_sgf_pass_fragment_cntr +=523 readl(mmcaddr + MMC_XGMAC_SGF_PASS_PKT);524 mmc->mmc_sgf_fail_fragment_cntr +=525 readl(mmcaddr + MMC_XGMAC_SGF_FAIL_PKT);526 mmc->mmc_tx_fpe_fragment_cntr += readl(mmcaddr + MMC_XGMAC_TX_FPE_FRAG);527 mmc->mmc_tx_hold_req_cntr += readl(mmcaddr + MMC_XGMAC_TX_HOLD_REQ);528 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_GATE_OVERRUN,529 &mmc->mmc_tx_gate_overrun_cntr);530 mmc->mmc_rx_packet_assembly_err_cntr +=531 readl(mmcaddr + MMC_XGMAC_RX_PKT_ASSEMBLY_ERR);532 mmc->mmc_rx_packet_smd_err_cntr +=533 readl(mmcaddr + MMC_XGMAC_RX_PKT_SMD_ERR);534 mmc->mmc_rx_packet_assembly_ok_cntr +=535 readl(mmcaddr + MMC_XGMAC_RX_PKT_ASSEMBLY_OK);536 mmc->mmc_rx_fpe_fragment_cntr +=537 readl(mmcaddr + MMC_XGMAC_RX_FPE_FRAG);538 539 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_IPV4_GD,540 &mmc->mmc_rx_ipv4_gd);541 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_IPV4_HDERR,542 &mmc->mmc_rx_ipv4_hderr);543 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_IPV4_NOPAY,544 &mmc->mmc_rx_ipv4_nopay);545 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_IPV4_FRAG,546 &mmc->mmc_rx_ipv4_frag);547 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_IPV4_UDSBL,548 &mmc->mmc_rx_ipv4_udsbl);549 550 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_IPV6_GD,551 &mmc->mmc_rx_ipv6_gd);552 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_IPV6_HDERR,553 &mmc->mmc_rx_ipv6_hderr);554 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_IPV6_NOPAY,555 &mmc->mmc_rx_ipv6_nopay);556 557 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_UDP_GD,558 &mmc->mmc_rx_udp_gd);559 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_UDP_ERR,560 &mmc->mmc_rx_udp_err);561 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_TCP_GD,562 &mmc->mmc_rx_tcp_gd);563 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_TCP_ERR,564 &mmc->mmc_rx_tcp_err);565 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_ICMP_GD,566 &mmc->mmc_rx_icmp_gd);567 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_ICMP_ERR,568 &mmc->mmc_rx_icmp_err);569 570 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_IPV4_GD_OCTETS,571 &mmc->mmc_rx_ipv4_gd_octets);572 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_IPV4_HDERR_OCTETS,573 &mmc->mmc_rx_ipv4_hderr_octets);574 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_IPV4_NOPAY_OCTETS,575 &mmc->mmc_rx_ipv4_nopay_octets);576 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_IPV4_FRAG_OCTETS,577 &mmc->mmc_rx_ipv4_frag_octets);578 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_IPV4_UDSBL_OCTETS,579 &mmc->mmc_rx_ipv4_udsbl_octets);580 581 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_IPV6_GD_OCTETS,582 &mmc->mmc_rx_ipv6_gd_octets);583 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_IPV6_HDERR_OCTETS,584 &mmc->mmc_rx_ipv6_hderr_octets);585 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_IPV6_NOPAY_OCTETS,586 &mmc->mmc_rx_ipv6_nopay_octets);587 588 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_UDP_GD_OCTETS,589 &mmc->mmc_rx_udp_gd_octets);590 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_UDP_ERR_OCTETS,591 &mmc->mmc_rx_udp_err_octets);592 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_TCP_GD_OCTETS,593 &mmc->mmc_rx_tcp_gd_octets);594 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_TCP_ERR_OCTETS,595 &mmc->mmc_rx_tcp_err_octets);596 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_ICMP_GD_OCTETS,597 &mmc->mmc_rx_icmp_gd_octets);598 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_ICMP_ERR_OCTETS,599 &mmc->mmc_rx_icmp_err_octets);600}601 602const struct stmmac_mmc_ops dwxgmac_mmc_ops = {603 .ctrl = dwxgmac_mmc_ctrl,604 .intr_all_mask = dwxgmac_mmc_intr_all_mask,605 .read = dwxgmac_mmc_read,606};607