352 lines · c
1/* SPDX-License-Identifier: GPL-2.0 */2/* $Id: sunqe.h,v 1.13 2000/02/09 11:15:42 davem Exp $3 * sunqe.h: Definitions for the Sun QuadEthernet driver.4 *5 * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)6 */7 8#ifndef _SUNQE_H9#define _SUNQE_H10 11/* QEC global registers. */12#define GLOB_CTRL 0x00UL /* Control */13#define GLOB_STAT 0x04UL /* Status */14#define GLOB_PSIZE 0x08UL /* Packet Size */15#define GLOB_MSIZE 0x0cUL /* Local-memory Size */16#define GLOB_RSIZE 0x10UL /* Receive partition size */17#define GLOB_TSIZE 0x14UL /* Transmit partition size */18#define GLOB_REG_SIZE 0x18UL19 20#define GLOB_CTRL_MMODE 0x40000000 /* MACE qec mode */21#define GLOB_CTRL_BMODE 0x10000000 /* BigMAC qec mode */22#define GLOB_CTRL_EPAR 0x00000020 /* Enable parity */23#define GLOB_CTRL_ACNTRL 0x00000018 /* SBUS arbitration control */24#define GLOB_CTRL_B64 0x00000004 /* 64 byte dvma bursts */25#define GLOB_CTRL_B32 0x00000002 /* 32 byte dvma bursts */26#define GLOB_CTRL_B16 0x00000000 /* 16 byte dvma bursts */27#define GLOB_CTRL_RESET 0x00000001 /* Reset the QEC */28 29#define GLOB_STAT_TX 0x00000008 /* BigMAC Transmit IRQ */30#define GLOB_STAT_RX 0x00000004 /* BigMAC Receive IRQ */31#define GLOB_STAT_BM 0x00000002 /* BigMAC Global IRQ */32#define GLOB_STAT_ER 0x00000001 /* BigMAC Error IRQ */33 34#define GLOB_PSIZE_2048 0x00 /* 2k packet size */35#define GLOB_PSIZE_4096 0x01 /* 4k packet size */36#define GLOB_PSIZE_6144 0x10 /* 6k packet size */37#define GLOB_PSIZE_8192 0x11 /* 8k packet size */38 39/* In MACE mode, there are four qe channels. Each channel has it's own40 * status bits in the QEC status register. This macro picks out the41 * ones you want.42 */43#define GLOB_STAT_PER_QE(status, channel) (((status) >> ((channel) * 4)) & 0xf)44 45/* The following registers are for per-qe channel information/status. */46#define CREG_CTRL 0x00UL /* Control */47#define CREG_STAT 0x04UL /* Status */48#define CREG_RXDS 0x08UL /* RX descriptor ring ptr */49#define CREG_TXDS 0x0cUL /* TX descriptor ring ptr */50#define CREG_RIMASK 0x10UL /* RX Interrupt Mask */51#define CREG_TIMASK 0x14UL /* TX Interrupt Mask */52#define CREG_QMASK 0x18UL /* QEC Error Interrupt Mask */53#define CREG_MMASK 0x1cUL /* MACE Error Interrupt Mask */54#define CREG_RXWBUFPTR 0x20UL /* Local memory rx write ptr */55#define CREG_RXRBUFPTR 0x24UL /* Local memory rx read ptr */56#define CREG_TXWBUFPTR 0x28UL /* Local memory tx write ptr */57#define CREG_TXRBUFPTR 0x2cUL /* Local memory tx read ptr */58#define CREG_CCNT 0x30UL /* Collision Counter */59#define CREG_PIPG 0x34UL /* Inter-Frame Gap */60#define CREG_REG_SIZE 0x38UL61 62#define CREG_CTRL_RXOFF 0x00000004 /* Disable this qe's receiver*/63#define CREG_CTRL_RESET 0x00000002 /* Reset this qe channel */64#define CREG_CTRL_TWAKEUP 0x00000001 /* Transmitter Wakeup, 'go'. */65 66#define CREG_STAT_EDEFER 0x10000000 /* Excessive Defers */67#define CREG_STAT_CLOSS 0x08000000 /* Carrier Loss */68#define CREG_STAT_ERETRIES 0x04000000 /* More than 16 retries */69#define CREG_STAT_LCOLL 0x02000000 /* Late TX Collision */70#define CREG_STAT_FUFLOW 0x01000000 /* FIFO Underflow */71#define CREG_STAT_JERROR 0x00800000 /* Jabber Error */72#define CREG_STAT_BERROR 0x00400000 /* Babble Error */73#define CREG_STAT_TXIRQ 0x00200000 /* Transmit Interrupt */74#define CREG_STAT_CCOFLOW 0x00100000 /* TX Coll-counter Overflow */75#define CREG_STAT_TXDERROR 0x00080000 /* TX Descriptor is bogus */76#define CREG_STAT_TXLERR 0x00040000 /* Late Transmit Error */77#define CREG_STAT_TXPERR 0x00020000 /* Transmit Parity Error */78#define CREG_STAT_TXSERR 0x00010000 /* Transmit SBUS error ack */79#define CREG_STAT_RCCOFLOW 0x00001000 /* RX Coll-counter Overflow */80#define CREG_STAT_RUOFLOW 0x00000800 /* Runt Counter Overflow */81#define CREG_STAT_MCOFLOW 0x00000400 /* Missed Counter Overflow */82#define CREG_STAT_RXFOFLOW 0x00000200 /* RX FIFO Overflow */83#define CREG_STAT_RLCOLL 0x00000100 /* RX Late Collision */84#define CREG_STAT_FCOFLOW 0x00000080 /* Frame Counter Overflow */85#define CREG_STAT_CECOFLOW 0x00000040 /* CRC Error-counter Overflow*/86#define CREG_STAT_RXIRQ 0x00000020 /* Receive Interrupt */87#define CREG_STAT_RXDROP 0x00000010 /* Dropped a RX'd packet */88#define CREG_STAT_RXSMALL 0x00000008 /* Receive buffer too small */89#define CREG_STAT_RXLERR 0x00000004 /* Receive Late Error */90#define CREG_STAT_RXPERR 0x00000002 /* Receive Parity Error */91#define CREG_STAT_RXSERR 0x00000001 /* Receive SBUS Error ACK */92 93#define CREG_STAT_ERRORS (CREG_STAT_EDEFER|CREG_STAT_CLOSS|CREG_STAT_ERETRIES| \94 CREG_STAT_LCOLL|CREG_STAT_FUFLOW|CREG_STAT_JERROR| \95 CREG_STAT_BERROR|CREG_STAT_CCOFLOW|CREG_STAT_TXDERROR| \96 CREG_STAT_TXLERR|CREG_STAT_TXPERR|CREG_STAT_TXSERR| \97 CREG_STAT_RCCOFLOW|CREG_STAT_RUOFLOW|CREG_STAT_MCOFLOW| \98 CREG_STAT_RXFOFLOW|CREG_STAT_RLCOLL|CREG_STAT_FCOFLOW| \99 CREG_STAT_CECOFLOW|CREG_STAT_RXDROP|CREG_STAT_RXSMALL| \100 CREG_STAT_RXLERR|CREG_STAT_RXPERR|CREG_STAT_RXSERR)101 102#define CREG_QMASK_COFLOW 0x00100000 /* CollCntr overflow */103#define CREG_QMASK_TXDERROR 0x00080000 /* TXD error */104#define CREG_QMASK_TXLERR 0x00040000 /* TX late error */105#define CREG_QMASK_TXPERR 0x00020000 /* TX parity error */106#define CREG_QMASK_TXSERR 0x00010000 /* TX sbus error ack */107#define CREG_QMASK_RXDROP 0x00000010 /* RX drop */108#define CREG_QMASK_RXBERROR 0x00000008 /* RX buffer error */109#define CREG_QMASK_RXLEERR 0x00000004 /* RX late error */110#define CREG_QMASK_RXPERR 0x00000002 /* RX parity error */111#define CREG_QMASK_RXSERR 0x00000001 /* RX sbus error ack */112 113#define CREG_MMASK_EDEFER 0x10000000 /* Excess defer */114#define CREG_MMASK_CLOSS 0x08000000 /* Carrier loss */115#define CREG_MMASK_ERETRY 0x04000000 /* Excess retry */116#define CREG_MMASK_LCOLL 0x02000000 /* Late collision error */117#define CREG_MMASK_UFLOW 0x01000000 /* Underflow */118#define CREG_MMASK_JABBER 0x00800000 /* Jabber error */119#define CREG_MMASK_BABBLE 0x00400000 /* Babble error */120#define CREG_MMASK_OFLOW 0x00000800 /* Overflow */121#define CREG_MMASK_RXCOLL 0x00000400 /* RX Coll-Cntr overflow */122#define CREG_MMASK_RPKT 0x00000200 /* Runt pkt overflow */123#define CREG_MMASK_MPKT 0x00000100 /* Missed pkt overflow */124 125#define CREG_PIPG_TENAB 0x00000020 /* Enable Throttle */126#define CREG_PIPG_MMODE 0x00000010 /* Manual Mode */127#define CREG_PIPG_WMASK 0x0000000f /* SBUS Wait Mask */128 129/* Per-channel AMD 79C940 MACE registers. */130#define MREGS_RXFIFO 0x00UL /* Receive FIFO */131#define MREGS_TXFIFO 0x01UL /* Transmit FIFO */132#define MREGS_TXFCNTL 0x02UL /* Transmit Frame Control */133#define MREGS_TXFSTAT 0x03UL /* Transmit Frame Status */134#define MREGS_TXRCNT 0x04UL /* Transmit Retry Count */135#define MREGS_RXFCNTL 0x05UL /* Receive Frame Control */136#define MREGS_RXFSTAT 0x06UL /* Receive Frame Status */137#define MREGS_FFCNT 0x07UL /* FIFO Frame Count */138#define MREGS_IREG 0x08UL /* Interrupt Register */139#define MREGS_IMASK 0x09UL /* Interrupt Mask */140#define MREGS_POLL 0x0aUL /* POLL Register */141#define MREGS_BCONFIG 0x0bUL /* BIU Config */142#define MREGS_FCONFIG 0x0cUL /* FIFO Config */143#define MREGS_MCONFIG 0x0dUL /* MAC Config */144#define MREGS_PLSCONFIG 0x0eUL /* PLS Config */145#define MREGS_PHYCONFIG 0x0fUL /* PHY Config */146#define MREGS_CHIPID1 0x10UL /* Chip-ID, low bits */147#define MREGS_CHIPID2 0x11UL /* Chip-ID, high bits */148#define MREGS_IACONFIG 0x12UL /* Internal Address Config */149 /* 0x13UL, reserved */150#define MREGS_FILTER 0x14UL /* Logical Address Filter */151#define MREGS_ETHADDR 0x15UL /* Our Ethernet Address */152 /* 0x16UL, reserved */153 /* 0x17UL, reserved */154#define MREGS_MPCNT 0x18UL /* Missed Packet Count */155 /* 0x19UL, reserved */156#define MREGS_RPCNT 0x1aUL /* Runt Packet Count */157#define MREGS_RCCNT 0x1bUL /* RX Collision Count */158 /* 0x1cUL, reserved */159#define MREGS_UTEST 0x1dUL /* User Test */160#define MREGS_RTEST1 0x1eUL /* Reserved Test 1 */161#define MREGS_RTEST2 0x1fUL /* Reserved Test 2 */162#define MREGS_REG_SIZE 0x20UL163 164#define MREGS_TXFCNTL_DRETRY 0x80 /* Retry disable */165#define MREGS_TXFCNTL_DFCS 0x08 /* Disable TX FCS */166#define MREGS_TXFCNTL_AUTOPAD 0x01 /* TX auto pad */167 168#define MREGS_TXFSTAT_VALID 0x80 /* TX valid */169#define MREGS_TXFSTAT_UNDERFLOW 0x40 /* TX underflow */170#define MREGS_TXFSTAT_LCOLL 0x20 /* TX late collision */171#define MREGS_TXFSTAT_MRETRY 0x10 /* TX > 1 retries */172#define MREGS_TXFSTAT_ORETRY 0x08 /* TX 1 retry */173#define MREGS_TXFSTAT_PDEFER 0x04 /* TX pkt deferred */174#define MREGS_TXFSTAT_CLOSS 0x02 /* TX carrier lost */175#define MREGS_TXFSTAT_RERROR 0x01 /* TX retry error */176 177#define MREGS_TXRCNT_EDEFER 0x80 /* TX Excess defers */178#define MREGS_TXRCNT_CMASK 0x0f /* TX retry count */179 180#define MREGS_RXFCNTL_LOWLAT 0x08 /* RX low latency */181#define MREGS_RXFCNTL_AREJECT 0x04 /* RX addr match rej */182#define MREGS_RXFCNTL_AUTOSTRIP 0x01 /* RX auto strip */183 184#define MREGS_RXFSTAT_OVERFLOW 0x80 /* RX overflow */185#define MREGS_RXFSTAT_LCOLL 0x40 /* RX late collision */186#define MREGS_RXFSTAT_FERROR 0x20 /* RX framing error */187#define MREGS_RXFSTAT_FCSERROR 0x10 /* RX FCS error */188#define MREGS_RXFSTAT_RBCNT 0x0f /* RX msg byte count */189 190#define MREGS_FFCNT_RX 0xf0 /* RX FIFO frame cnt */191#define MREGS_FFCNT_TX 0x0f /* TX FIFO frame cnt */192 193#define MREGS_IREG_JABBER 0x80 /* IRQ Jabber error */194#define MREGS_IREG_BABBLE 0x40 /* IRQ Babble error */195#define MREGS_IREG_COLL 0x20 /* IRQ Collision error */196#define MREGS_IREG_RCCO 0x10 /* IRQ Collision cnt overflow */197#define MREGS_IREG_RPKTCO 0x08 /* IRQ Runt packet count overflow */198#define MREGS_IREG_MPKTCO 0x04 /* IRQ missed packet cnt overflow */199#define MREGS_IREG_RXIRQ 0x02 /* IRQ RX'd a packet */200#define MREGS_IREG_TXIRQ 0x01 /* IRQ TX'd a packet */201 202#define MREGS_IMASK_BABBLE 0x40 /* IMASK Babble errors */203#define MREGS_IMASK_COLL 0x20 /* IMASK Collision errors */204#define MREGS_IMASK_MPKTCO 0x04 /* IMASK Missed pkt cnt overflow */205#define MREGS_IMASK_RXIRQ 0x02 /* IMASK RX interrupts */206#define MREGS_IMASK_TXIRQ 0x01 /* IMASK TX interrupts */207 208#define MREGS_POLL_TXVALID 0x80 /* TX is valid */209#define MREGS_POLL_TDTR 0x40 /* TX data transfer request */210#define MREGS_POLL_RDTR 0x20 /* RX data transfer request */211 212#define MREGS_BCONFIG_BSWAP 0x40 /* Byte Swap */213#define MREGS_BCONFIG_4TS 0x00 /* 4byte transmit start point */214#define MREGS_BCONFIG_16TS 0x10 /* 16byte transmit start point */215#define MREGS_BCONFIG_64TS 0x20 /* 64byte transmit start point */216#define MREGS_BCONFIG_112TS 0x30 /* 112byte transmit start point */217#define MREGS_BCONFIG_RESET 0x01 /* SW-Reset the MACE */218 219#define MREGS_FCONFIG_TXF8 0x00 /* TX fifo 8 write cycles */220#define MREGS_FCONFIG_TXF32 0x80 /* TX fifo 32 write cycles */221#define MREGS_FCONFIG_TXF16 0x40 /* TX fifo 16 write cycles */222#define MREGS_FCONFIG_RXF64 0x20 /* RX fifo 64 write cycles */223#define MREGS_FCONFIG_RXF32 0x10 /* RX fifo 32 write cycles */224#define MREGS_FCONFIG_RXF16 0x00 /* RX fifo 16 write cycles */225#define MREGS_FCONFIG_TFWU 0x08 /* TX fifo watermark update */226#define MREGS_FCONFIG_RFWU 0x04 /* RX fifo watermark update */227#define MREGS_FCONFIG_TBENAB 0x02 /* TX burst enable */228#define MREGS_FCONFIG_RBENAB 0x01 /* RX burst enable */229 230#define MREGS_MCONFIG_PROMISC 0x80 /* Promiscuous mode enable */231#define MREGS_MCONFIG_TPDDISAB 0x40 /* TX 2part deferral enable */232#define MREGS_MCONFIG_MBAENAB 0x20 /* Modified backoff enable */233#define MREGS_MCONFIG_RPADISAB 0x08 /* RX physical addr disable */234#define MREGS_MCONFIG_RBDISAB 0x04 /* RX broadcast disable */235#define MREGS_MCONFIG_TXENAB 0x02 /* Enable transmitter */236#define MREGS_MCONFIG_RXENAB 0x01 /* Enable receiver */237 238#define MREGS_PLSCONFIG_TXMS 0x08 /* TX mode select */239#define MREGS_PLSCONFIG_GPSI 0x06 /* Use GPSI connector */240#define MREGS_PLSCONFIG_DAI 0x04 /* Use DAI connector */241#define MREGS_PLSCONFIG_TP 0x02 /* Use TwistedPair connector */242#define MREGS_PLSCONFIG_AUI 0x00 /* Use AUI connector */243#define MREGS_PLSCONFIG_IOENAB 0x01 /* PLS I/O enable */244 245#define MREGS_PHYCONFIG_LSTAT 0x80 /* Link status */246#define MREGS_PHYCONFIG_LTESTDIS 0x40 /* Disable link test logic */247#define MREGS_PHYCONFIG_RXPOLARITY 0x20 /* RX polarity */248#define MREGS_PHYCONFIG_APCDISAB 0x10 /* AutoPolarityCorrect disab */249#define MREGS_PHYCONFIG_LTENAB 0x08 /* Select low threshold */250#define MREGS_PHYCONFIG_AUTO 0x04 /* Connector port auto-sel */251#define MREGS_PHYCONFIG_RWU 0x02 /* Remote WakeUp */252#define MREGS_PHYCONFIG_AW 0x01 /* Auto Wakeup */253 254#define MREGS_IACONFIG_ACHNGE 0x80 /* Do address change */255#define MREGS_IACONFIG_PARESET 0x04 /* Physical address reset */256#define MREGS_IACONFIG_LARESET 0x02 /* Logical address reset */257 258#define MREGS_UTEST_RTRENAB 0x80 /* Enable resv test register */259#define MREGS_UTEST_RTRDISAB 0x40 /* Disab resv test register */260#define MREGS_UTEST_RPACCEPT 0x20 /* Accept runt packets */261#define MREGS_UTEST_FCOLL 0x10 /* Force collision status */262#define MREGS_UTEST_FCSENAB 0x08 /* Enable FCS on RX */263#define MREGS_UTEST_INTLOOPM 0x06 /* Intern lpback w/MENDEC */264#define MREGS_UTEST_INTLOOP 0x04 /* Intern lpback */265#define MREGS_UTEST_EXTLOOP 0x02 /* Extern lpback */266#define MREGS_UTEST_NOLOOP 0x00 /* No loopback */267 268struct qe_rxd {269 u32 rx_flags;270 u32 rx_addr;271};272 273#define RXD_OWN 0x80000000 /* Ownership. */274#define RXD_UPDATE 0x10000000 /* Being Updated? */275#define RXD_LENGTH 0x000007ff /* Packet Length. */276 277struct qe_txd {278 u32 tx_flags;279 u32 tx_addr;280};281 282#define TXD_OWN 0x80000000 /* Ownership. */283#define TXD_SOP 0x40000000 /* Start Of Packet */284#define TXD_EOP 0x20000000 /* End Of Packet */285#define TXD_UPDATE 0x10000000 /* Being Updated? */286#define TXD_LENGTH 0x000007ff /* Packet Length. */287 288#define TX_RING_MAXSIZE 256289#define RX_RING_MAXSIZE 256290 291#define TX_RING_SIZE 16292#define RX_RING_SIZE 16293 294#define NEXT_RX(num) (((num) + 1) & (RX_RING_MAXSIZE - 1))295#define NEXT_TX(num) (((num) + 1) & (TX_RING_MAXSIZE - 1))296#define PREV_RX(num) (((num) - 1) & (RX_RING_MAXSIZE - 1))297#define PREV_TX(num) (((num) - 1) & (TX_RING_MAXSIZE - 1))298 299#define TX_BUFFS_AVAIL(qp) \300 (((qp)->tx_old <= (qp)->tx_new) ? \301 (qp)->tx_old + (TX_RING_SIZE - 1) - (qp)->tx_new : \302 (qp)->tx_old - (qp)->tx_new - 1)303 304struct qe_init_block {305 struct qe_rxd qe_rxd[RX_RING_MAXSIZE];306 struct qe_txd qe_txd[TX_RING_MAXSIZE];307};308 309#define qib_offset(mem, elem) \310((__u32)((unsigned long)(&(((struct qe_init_block *)0)->mem[elem]))))311 312struct sunqe;313 314struct sunqec {315 void __iomem *gregs; /* QEC Global Registers */316 struct sunqe *qes[4]; /* Each child MACE */317 unsigned int qec_bursts; /* Support burst sizes */318 struct platform_device *op; /* QEC's OF device */319 struct sunqec *next_module; /* List of all QECs in system */320};321 322#define PKT_BUF_SZ 1664323#define RXD_PKT_SZ 1664324 325struct sunqe_buffers {326 u8 tx_buf[TX_RING_SIZE][PKT_BUF_SZ];327 u8 __pad[2];328 u8 rx_buf[RX_RING_SIZE][PKT_BUF_SZ];329};330 331#define qebuf_offset(mem, elem) \332((__u32)((unsigned long)(&(((struct sunqe_buffers *)0)->mem[elem][0]))))333 334struct sunqe {335 void __iomem *qcregs; /* QEC per-channel Registers */336 void __iomem *mregs; /* Per-channel MACE Registers */337 struct qe_init_block *qe_block; /* RX and TX descriptors */338 dma_addr_t qblock_dvma; /* RX and TX descriptors */339 spinlock_t lock; /* Protects txfull state */340 int rx_new, rx_old; /* RX ring extents */341 int tx_new, tx_old; /* TX ring extents */342 struct sunqe_buffers *buffers; /* CPU visible address. */343 dma_addr_t buffers_dvma; /* DVMA visible address. */344 struct sunqec *parent;345 u8 mconfig; /* Base MACE mconfig value */346 struct platform_device *op; /* QE's OF device struct */347 struct net_device *dev; /* QE's netdevice struct */348 int channel; /* Who am I? */349};350 351#endif /* !(_SUNQE_H) */352