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1/* SPDX-License-Identifier: GPL-2.0 */2/* Copyright Sunplus Technology Co., Ltd.3 * All rights reserved.4 */5 6#ifndef __SPL2SW_DEFINE_H__7#define __SPL2SW_DEFINE_H__8 9#define MAX_NETDEV_NUM 2 /* Maximum # of net-device */10 11/* Interrupt status */12#define MAC_INT_DAISY_MODE_CHG BIT(31) /* Daisy Mode Change */13#define MAC_INT_IP_CHKSUM_ERR BIT(23) /* IP Checksum Append Error */14#define MAC_INT_WDOG_TIMER1_EXP BIT(22) /* Watchdog Timer1 Expired */15#define MAC_INT_WDOG_TIMER0_EXP BIT(21) /* Watchdog Timer0 Expired */16#define MAC_INT_INTRUDER_ALERT BIT(20) /* Atruder Alert */17#define MAC_INT_PORT_ST_CHG BIT(19) /* Port Status Change */18#define MAC_INT_BC_STORM BIT(18) /* Broad Cast Storm */19#define MAC_INT_MUST_DROP_LAN BIT(17) /* Global Queue Exhausted */20#define MAC_INT_GLOBAL_QUE_FULL BIT(16) /* Global Queue Full */21#define MAC_INT_TX_SOC_PAUSE_ON BIT(15) /* Soc Port TX Pause On */22#define MAC_INT_RX_SOC_QUE_FULL BIT(14) /* Soc Port Out Queue Full */23#define MAC_INT_TX_LAN1_QUE_FULL BIT(9) /* Port 1 Out Queue Full */24#define MAC_INT_TX_LAN0_QUE_FULL BIT(8) /* Port 0 Out Queue Full */25#define MAC_INT_RX_L_DESCF BIT(7) /* Low Priority Descriptor Full */26#define MAC_INT_RX_H_DESCF BIT(6) /* High Priority Descriptor Full */27#define MAC_INT_RX_DONE_L BIT(5) /* RX Low Priority Done */28#define MAC_INT_RX_DONE_H BIT(4) /* RX High Priority Done */29#define MAC_INT_TX_DONE_L BIT(3) /* TX Low Priority Done */30#define MAC_INT_TX_DONE_H BIT(2) /* TX High Priority Done */31#define MAC_INT_TX_DES_ERR BIT(1) /* TX Descriptor Error */32#define MAC_INT_RX_DES_ERR BIT(0) /* Rx Descriptor Error */33 34#define MAC_INT_RX (MAC_INT_RX_DONE_H | MAC_INT_RX_DONE_L | \35 MAC_INT_RX_DES_ERR)36#define MAC_INT_TX (MAC_INT_TX_DONE_L | MAC_INT_TX_DONE_H | \37 MAC_INT_TX_DES_ERR)38#define MAC_INT_MASK_DEF (MAC_INT_DAISY_MODE_CHG | MAC_INT_IP_CHKSUM_ERR | \39 MAC_INT_WDOG_TIMER1_EXP | MAC_INT_WDOG_TIMER0_EXP | \40 MAC_INT_INTRUDER_ALERT | MAC_INT_PORT_ST_CHG | \41 MAC_INT_BC_STORM | MAC_INT_MUST_DROP_LAN | \42 MAC_INT_GLOBAL_QUE_FULL | MAC_INT_TX_SOC_PAUSE_ON | \43 MAC_INT_RX_SOC_QUE_FULL | MAC_INT_TX_LAN1_QUE_FULL | \44 MAC_INT_TX_LAN0_QUE_FULL | MAC_INT_RX_L_DESCF | \45 MAC_INT_RX_H_DESCF)46 47/* Address table search */48#define MAC_ADDR_LOOKUP_IDLE BIT(2)49#define MAC_SEARCH_NEXT_ADDR BIT(1)50#define MAC_BEGIN_SEARCH_ADDR BIT(0)51 52/* Address table status */53#define MAC_HASH_LOOKUP_ADDR GENMASK(31, 22)54#define MAC_R_PORT_MAP GENMASK(13, 12)55#define MAC_R_CPU_PORT GENMASK(11, 10)56#define MAC_R_VID GENMASK(9, 7)57#define MAC_R_AGE GENMASK(6, 4)58#define MAC_R_PROXY BIT(3)59#define MAC_R_MC_INGRESS BIT(2)60#define MAC_AT_TABLE_END BIT(1)61#define MAC_AT_DATA_READY BIT(0)62 63/* Wt mac ad0 */64#define MAC_W_PORT_MAP GENMASK(13, 12)65#define MAC_W_LAN_PORT_1 BIT(13)66#define MAC_W_LAN_PORT_0 BIT(12)67#define MAC_W_CPU_PORT GENMASK(11, 10)68#define MAC_W_CPU_PORT_1 BIT(11)69#define MAC_W_CPU_PORT_0 BIT(10)70#define MAC_W_VID GENMASK(9, 7)71#define MAC_W_AGE GENMASK(6, 4)72#define MAC_W_PROXY BIT(3)73#define MAC_W_MC_INGRESS BIT(2)74#define MAC_W_MAC_DONE BIT(1)75#define MAC_W_MAC_CMD BIT(0)76 77/* W mac 15_0 bus */78#define MAC_W_MAC_15_0 GENMASK(15, 0)79 80/* W mac 47_16 bus */81#define MAC_W_MAC_47_16 GENMASK(31, 0)82 83/* PVID config 0 */84#define MAC_P1_PVID GENMASK(6, 4)85#define MAC_P0_PVID GENMASK(2, 0)86 87/* VLAN member config 0 */88#define MAC_VLAN_MEMSET_3 GENMASK(27, 24)89#define MAC_VLAN_MEMSET_2 GENMASK(19, 16)90#define MAC_VLAN_MEMSET_1 GENMASK(11, 8)91#define MAC_VLAN_MEMSET_0 GENMASK(3, 0)92 93/* VLAN member config 1 */94#define MAC_VLAN_MEMSET_5 GENMASK(11, 8)95#define MAC_VLAN_MEMSET_4 GENMASK(3, 0)96 97/* Port ability */98#define MAC_PORT_ABILITY_LINK_ST GENMASK(25, 24)99 100/* CPU control */101#define MAC_EN_SOC1_AGING BIT(15)102#define MAC_EN_SOC0_AGING BIT(14)103#define MAC_DIS_LRN_SOC1 BIT(13)104#define MAC_DIS_LRN_SOC0 BIT(12)105#define MAC_EN_CRC_SOC1 BIT(9)106#define MAC_EN_CRC_SOC0 BIT(8)107#define MAC_DIS_SOC1_CPU BIT(7)108#define MAC_DIS_SOC0_CPU BIT(6)109#define MAC_DIS_BC2CPU_P1 BIT(5)110#define MAC_DIS_BC2CPU_P0 BIT(4)111#define MAC_DIS_MC2CPU GENMASK(3, 2)112#define MAC_DIS_MC2CPU_P1 BIT(3)113#define MAC_DIS_MC2CPU_P0 BIT(2)114#define MAC_DIS_UN2CPU GENMASK(1, 0)115 116/* Port control 0 */117#define MAC_DIS_PORT GENMASK(25, 24)118#define MAC_DIS_PORT1 BIT(25)119#define MAC_DIS_PORT0 BIT(24)120#define MAC_DIS_RMC2CPU_P1 BIT(17)121#define MAC_DIS_RMC2CPU_P0 BIT(16)122#define MAC_EN_FLOW_CTL_P1 BIT(9)123#define MAC_EN_FLOW_CTL_P0 BIT(8)124#define MAC_EN_BACK_PRESS_P1 BIT(1)125#define MAC_EN_BACK_PRESS_P0 BIT(0)126 127/* Port control 1 */128#define MAC_DIS_SA_LRN_P1 BIT(9)129#define MAC_DIS_SA_LRN_P0 BIT(8)130 131/* Port control 2 */132#define MAC_EN_AGING_P1 BIT(9)133#define MAC_EN_AGING_P0 BIT(8)134 135/* Switch Global control */136#define MAC_RMC_TB_FAULT_RULE GENMASK(26, 25)137#define MAC_LED_FLASH_TIME GENMASK(24, 23)138#define MAC_BC_STORM_PREV GENMASK(5, 4)139 140/* LED port 0 */141#define MAC_LED_ACT_HI BIT(28)142 143/* PHY control register 0 */144#define MAC_CPU_PHY_WT_DATA GENMASK(31, 16)145#define MAC_CPU_PHY_CMD GENMASK(14, 13)146#define MAC_CPU_PHY_REG_ADDR GENMASK(12, 8)147#define MAC_CPU_PHY_ADDR GENMASK(4, 0)148 149/* PHY control register 1 */150#define MAC_CPU_PHY_RD_DATA GENMASK(31, 16)151#define MAC_PHY_RD_RDY BIT(1)152#define MAC_PHY_WT_DONE BIT(0)153 154/* MAC force mode */155#define MAC_EXT_PHY1_ADDR GENMASK(28, 24)156#define MAC_EXT_PHY0_ADDR GENMASK(20, 16)157#define MAC_FORCE_RMII_LINK GENMASK(9, 8)158#define MAC_FORCE_RMII_EN_1 BIT(7)159#define MAC_FORCE_RMII_EN_0 BIT(6)160#define MAC_FORCE_RMII_FC GENMASK(5, 4)161#define MAC_FORCE_RMII_DPX GENMASK(3, 2)162#define MAC_FORCE_RMII_SPD GENMASK(1, 0)163 164/* CPU transmit trigger */165#define MAC_TRIG_L_SOC0 BIT(1)166#define MAC_TRIG_H_SOC0 BIT(0)167 168/* Config descriptor queue */169#define TX_DESC_NUM 16 /* # of descriptors in TX queue */170#define MAC_GUARD_DESC_NUM 2 /* # of descriptors of gap 0 */171#define RX_QUEUE0_DESC_NUM 16 /* # of descriptors in RX queue 0 */172#define RX_QUEUE1_DESC_NUM 16 /* # of descriptors in RX queue 1 */173#define TX_DESC_QUEUE_NUM 1 /* # of TX queue */174#define RX_DESC_QUEUE_NUM 2 /* # of RX queue */175 176#define MAC_RX_LEN_MAX 2047 /* Size of RX buffer */177 178/* Tx descriptor */179/* cmd1 */180#define TXD_OWN BIT(31)181#define TXD_ERR_CODE GENMASK(29, 26)182#define TXD_SOP BIT(25) /* start of a packet */183#define TXD_EOP BIT(24) /* end of a packet */184#define TXD_VLAN GENMASK(17, 12)185#define TXD_PKT_LEN GENMASK(10, 0) /* packet length */186/* cmd2 */187#define TXD_EOR BIT(31) /* end of ring */188#define TXD_BUF_LEN2 GENMASK(22, 12)189#define TXD_BUF_LEN1 GENMASK(10, 0)190 191/* Rx descriptor */192/* cmd1 */193#define RXD_OWN BIT(31)194#define RXD_ERR_CODE GENMASK(29, 26)195#define RXD_TCP_UDP_CHKSUM BIT(23)196#define RXD_PROXY BIT(22)197#define RXD_PROTOCOL GENMASK(21, 20)198#define RXD_VLAN_TAG BIT(19)199#define RXD_IP_CHKSUM BIT(18)200#define RXD_ROUTE_TYPE GENMASK(17, 16)201#define RXD_PKT_SP GENMASK(14, 12) /* packet source port */202#define RXD_PKT_LEN GENMASK(10, 0) /* packet length */203/* cmd2 */204#define RXD_EOR BIT(31) /* end of ring */205#define RXD_BUF_LEN2 GENMASK(22, 12)206#define RXD_BUF_LEN1 GENMASK(10, 0)207 208/* structure of descriptor */209struct spl2sw_mac_desc {210 u32 cmd1;211 u32 cmd2;212 u32 addr1;213 u32 addr2;214};215 216struct spl2sw_skb_info {217 struct sk_buff *skb;218 u32 mapping;219 u32 len;220};221 222struct spl2sw_common {223 void __iomem *l2sw_reg_base;224 225 struct platform_device *pdev;226 struct reset_control *rstc;227 struct clk *clk;228 229 void *desc_base;230 dma_addr_t desc_dma;231 s32 desc_size;232 struct spl2sw_mac_desc *rx_desc[RX_DESC_QUEUE_NUM];233 struct spl2sw_skb_info *rx_skb_info[RX_DESC_QUEUE_NUM];234 u32 rx_pos[RX_DESC_QUEUE_NUM];235 u32 rx_desc_num[RX_DESC_QUEUE_NUM];236 u32 rx_desc_buff_size;237 238 struct spl2sw_mac_desc *tx_desc;239 struct spl2sw_skb_info tx_temp_skb_info[TX_DESC_NUM];240 u32 tx_done_pos;241 u32 tx_pos;242 u32 tx_desc_full;243 244 struct net_device *ndev[MAX_NETDEV_NUM];245 struct mii_bus *mii_bus;246 247 struct napi_struct rx_napi;248 struct napi_struct tx_napi;249 250 spinlock_t tx_lock; /* spinlock for accessing tx buffer */251 spinlock_t mdio_lock; /* spinlock for mdio commands */252 spinlock_t int_mask_lock; /* spinlock for accessing int mask reg. */253 254 u8 enable;255};256 257struct spl2sw_mac {258 struct net_device *ndev;259 struct spl2sw_common *comm;260 261 u8 mac_addr[ETH_ALEN];262 phy_interface_t phy_mode;263 struct device_node *phy_node;264 265 u8 lan_port;266 u8 to_vlan;267 u8 vlan_id;268};269 270#endif271