87 lines · c
1/* SPDX-License-Identifier: GPL-2.0 */2/* Copyright Sunplus Technology Co., Ltd.3 * All rights reserved.4 */5 6#ifndef __SPL2SW_REGISTER_H__7#define __SPL2SW_REGISTER_H__8 9/* Register L2SW */10#define L2SW_SW_INT_STATUS_0 0x011#define L2SW_SW_INT_MASK_0 0x412#define L2SW_FL_CNTL_TH 0x813#define L2SW_CPU_FL_CNTL_TH 0xc14#define L2SW_PRI_FL_CNTL 0x1015#define L2SW_VLAN_PRI_TH 0x1416#define L2SW_EN_TOS_BUS 0x1817#define L2SW_TOS_MAP0 0x1c18#define L2SW_TOS_MAP1 0x2019#define L2SW_TOS_MAP2 0x2420#define L2SW_TOS_MAP3 0x2821#define L2SW_TOS_MAP4 0x2c22#define L2SW_TOS_MAP5 0x3023#define L2SW_TOS_MAP6 0x3424#define L2SW_TOS_MAP7 0x3825#define L2SW_GLOBAL_QUE_STATUS 0x3c26#define L2SW_ADDR_TBL_SRCH 0x4027#define L2SW_ADDR_TBL_ST 0x4428#define L2SW_MAC_AD_SER0 0x4829#define L2SW_MAC_AD_SER1 0x4c30#define L2SW_WT_MAC_AD0 0x5031#define L2SW_W_MAC_15_0 0x5432#define L2SW_W_MAC_47_16 0x5833#define L2SW_PVID_CONFIG0 0x5c34#define L2SW_PVID_CONFIG1 0x6035#define L2SW_VLAN_MEMSET_CONFIG0 0x6436#define L2SW_VLAN_MEMSET_CONFIG1 0x6837#define L2SW_PORT_ABILITY 0x6c38#define L2SW_PORT_ST 0x7039#define L2SW_CPU_CNTL 0x7440#define L2SW_PORT_CNTL0 0x7841#define L2SW_PORT_CNTL1 0x7c42#define L2SW_PORT_CNTL2 0x8043#define L2SW_SW_GLB_CNTL 0x8444#define L2SW_L2SW_SW_RESET 0x8845#define L2SW_LED_PORT0 0x8c46#define L2SW_LED_PORT1 0x9047#define L2SW_LED_PORT2 0x9448#define L2SW_LED_PORT3 0x9849#define L2SW_LED_PORT4 0x9c50#define L2SW_WATCH_DOG_TRIG_RST 0xa051#define L2SW_WATCH_DOG_STOP_CPU 0xa452#define L2SW_PHY_CNTL_REG0 0xa853#define L2SW_PHY_CNTL_REG1 0xac54#define L2SW_MAC_FORCE_MODE 0xb055#define L2SW_VLAN_GROUP_CONFIG0 0xb456#define L2SW_VLAN_GROUP_CONFIG1 0xb857#define L2SW_FLOW_CTRL_TH3 0xbc58#define L2SW_QUEUE_STATUS_0 0xc059#define L2SW_DEBUG_CNTL 0xc460#define L2SW_RESERVED_1 0xc861#define L2SW_MEM_TEST_INFO 0xcc62#define L2SW_SW_INT_STATUS_1 0xd063#define L2SW_SW_INT_MASK_1 0xd464#define L2SW_SW_GLOBAL_SIGNAL 0xd865 66#define L2SW_CPU_TX_TRIG 0x20867#define L2SW_TX_HBASE_ADDR_0 0x20c68#define L2SW_TX_LBASE_ADDR_0 0x21069#define L2SW_RX_HBASE_ADDR_0 0x21470#define L2SW_RX_LBASE_ADDR_0 0x21871#define L2SW_TX_HW_ADDR_0 0x21c72#define L2SW_TX_LW_ADDR_0 0x22073#define L2SW_RX_HW_ADDR_0 0x22474#define L2SW_RX_LW_ADDR_0 0x22875#define L2SW_CPU_PORT_CNTL_REG_0 0x22c76#define L2SW_TX_HBASE_ADDR_1 0x23077#define L2SW_TX_LBASE_ADDR_1 0x23478#define L2SW_RX_HBASE_ADDR_1 0x23879#define L2SW_RX_LBASE_ADDR_1 0x23c80#define L2SW_TX_HW_ADDR_1 0x24081#define L2SW_TX_LW_ADDR_1 0x24482#define L2SW_RX_HW_ADDR_1 0x24883#define L2SW_RX_LW_ADDR_1 0x24c84#define L2SW_CPU_PORT_CNTL_REG_1 0x25085 86#endif87