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1/* Synopsys DesignWare Core Enterprise Ethernet (XLGMAC) Driver2 *3 * Copyright (c) 2017 Synopsys, Inc. (www.synopsys.com)4 *5 * This program is dual-licensed; you may select either version 2 of6 * the GNU General Public License ("GPL") or BSD license ("BSD").7 *8 * This Synopsys DWC XLGMAC software driver and associated documentation9 * (hereinafter the "Software") is an unsupported proprietary work of10 * Synopsys, Inc. unless otherwise expressly agreed to in writing between11 * Synopsys and you. The Software IS NOT an item of Licensed Software or a12 * Licensed Product under any End User Software License Agreement or13 * Agreement for Licensed Products with Synopsys or any supplement thereto.14 * Synopsys is a registered trademark of Synopsys, Inc. Other names included15 * in the SOFTWARE may be the trademarks of their respective owners.16 */17 18#ifndef __DWC_XLGMAC_REG_H__19#define __DWC_XLGMAC_REG_H__20 21/* MAC register offsets */22#define MAC_TCR 0x000023#define MAC_RCR 0x000424#define MAC_PFR 0x000825#define MAC_HTR0 0x001026#define MAC_VLANTR 0x005027#define MAC_VLANHTR 0x005828#define MAC_VLANIR 0x006029#define MAC_Q0TFCR 0x007030#define MAC_RFCR 0x009031#define MAC_RQC0R 0x00a032#define MAC_RQC1R 0x00a433#define MAC_RQC2R 0x00a834#define MAC_RQC3R 0x00ac35#define MAC_ISR 0x00b036#define MAC_IER 0x00b437#define MAC_VR 0x011038#define MAC_HWF0R 0x011c39#define MAC_HWF1R 0x012040#define MAC_HWF2R 0x012441#define MAC_MACA0HR 0x030042#define MAC_MACA0LR 0x030443#define MAC_MACA1HR 0x030844#define MAC_MACA1LR 0x030c45#define MAC_RSSCR 0x0c8046#define MAC_RSSAR 0x0c8847#define MAC_RSSDR 0x0c8c48 49#define MAC_QTFCR_INC 450#define MAC_MACA_INC 451#define MAC_HTR_INC 452#define MAC_RQC2_INC 453#define MAC_RQC2_Q_PER_REG 454 55/* MAC register entry bit positions and sizes */56#define MAC_HWF0R_ADDMACADRSEL_POS 1857#define MAC_HWF0R_ADDMACADRSEL_LEN 558#define MAC_HWF0R_ARPOFFSEL_POS 959#define MAC_HWF0R_ARPOFFSEL_LEN 160#define MAC_HWF0R_EEESEL_POS 1361#define MAC_HWF0R_EEESEL_LEN 162#define MAC_HWF0R_PHYIFSEL_POS 163#define MAC_HWF0R_PHYIFSEL_LEN 264#define MAC_HWF0R_MGKSEL_POS 765#define MAC_HWF0R_MGKSEL_LEN 166#define MAC_HWF0R_MMCSEL_POS 867#define MAC_HWF0R_MMCSEL_LEN 168#define MAC_HWF0R_RWKSEL_POS 669#define MAC_HWF0R_RWKSEL_LEN 170#define MAC_HWF0R_RXCOESEL_POS 1671#define MAC_HWF0R_RXCOESEL_LEN 172#define MAC_HWF0R_SAVLANINS_POS 2773#define MAC_HWF0R_SAVLANINS_LEN 174#define MAC_HWF0R_SMASEL_POS 575#define MAC_HWF0R_SMASEL_LEN 176#define MAC_HWF0R_TSSEL_POS 1277#define MAC_HWF0R_TSSEL_LEN 178#define MAC_HWF0R_TSSTSSEL_POS 2579#define MAC_HWF0R_TSSTSSEL_LEN 280#define MAC_HWF0R_TXCOESEL_POS 1481#define MAC_HWF0R_TXCOESEL_LEN 182#define MAC_HWF0R_VLHASH_POS 483#define MAC_HWF0R_VLHASH_LEN 184#define MAC_HWF1R_ADDR64_POS 1485#define MAC_HWF1R_ADDR64_LEN 286#define MAC_HWF1R_ADVTHWORD_POS 1387#define MAC_HWF1R_ADVTHWORD_LEN 188#define MAC_HWF1R_DBGMEMA_POS 1989#define MAC_HWF1R_DBGMEMA_LEN 190#define MAC_HWF1R_DCBEN_POS 1691#define MAC_HWF1R_DCBEN_LEN 192#define MAC_HWF1R_HASHTBLSZ_POS 2493#define MAC_HWF1R_HASHTBLSZ_LEN 394#define MAC_HWF1R_L3L4FNUM_POS 2795#define MAC_HWF1R_L3L4FNUM_LEN 496#define MAC_HWF1R_NUMTC_POS 2197#define MAC_HWF1R_NUMTC_LEN 398#define MAC_HWF1R_RSSEN_POS 2099#define MAC_HWF1R_RSSEN_LEN 1100#define MAC_HWF1R_RXFIFOSIZE_POS 0101#define MAC_HWF1R_RXFIFOSIZE_LEN 5102#define MAC_HWF1R_SPHEN_POS 17103#define MAC_HWF1R_SPHEN_LEN 1104#define MAC_HWF1R_TSOEN_POS 18105#define MAC_HWF1R_TSOEN_LEN 1106#define MAC_HWF1R_TXFIFOSIZE_POS 6107#define MAC_HWF1R_TXFIFOSIZE_LEN 5108#define MAC_HWF2R_AUXSNAPNUM_POS 28109#define MAC_HWF2R_AUXSNAPNUM_LEN 3110#define MAC_HWF2R_PPSOUTNUM_POS 24111#define MAC_HWF2R_PPSOUTNUM_LEN 3112#define MAC_HWF2R_RXCHCNT_POS 12113#define MAC_HWF2R_RXCHCNT_LEN 4114#define MAC_HWF2R_RXQCNT_POS 0115#define MAC_HWF2R_RXQCNT_LEN 4116#define MAC_HWF2R_TXCHCNT_POS 18117#define MAC_HWF2R_TXCHCNT_LEN 4118#define MAC_HWF2R_TXQCNT_POS 6119#define MAC_HWF2R_TXQCNT_LEN 4120#define MAC_IER_TSIE_POS 12121#define MAC_IER_TSIE_LEN 1122#define MAC_ISR_MMCRXIS_POS 9123#define MAC_ISR_MMCRXIS_LEN 1124#define MAC_ISR_MMCTXIS_POS 10125#define MAC_ISR_MMCTXIS_LEN 1126#define MAC_ISR_PMTIS_POS 4127#define MAC_ISR_PMTIS_LEN 1128#define MAC_ISR_TSIS_POS 12129#define MAC_ISR_TSIS_LEN 1130#define MAC_MACA1HR_AE_POS 31131#define MAC_MACA1HR_AE_LEN 1132#define MAC_PFR_HMC_POS 2133#define MAC_PFR_HMC_LEN 1134#define MAC_PFR_HPF_POS 10135#define MAC_PFR_HPF_LEN 1136#define MAC_PFR_HUC_POS 1137#define MAC_PFR_HUC_LEN 1138#define MAC_PFR_PM_POS 4139#define MAC_PFR_PM_LEN 1140#define MAC_PFR_PR_POS 0141#define MAC_PFR_PR_LEN 1142#define MAC_PFR_VTFE_POS 16143#define MAC_PFR_VTFE_LEN 1144#define MAC_Q0TFCR_PT_POS 16145#define MAC_Q0TFCR_PT_LEN 16146#define MAC_Q0TFCR_TFE_POS 1147#define MAC_Q0TFCR_TFE_LEN 1148#define MAC_RCR_ACS_POS 1149#define MAC_RCR_ACS_LEN 1150#define MAC_RCR_CST_POS 2151#define MAC_RCR_CST_LEN 1152#define MAC_RCR_DCRCC_POS 3153#define MAC_RCR_DCRCC_LEN 1154#define MAC_RCR_HDSMS_POS 12155#define MAC_RCR_HDSMS_LEN 3156#define MAC_RCR_IPC_POS 9157#define MAC_RCR_IPC_LEN 1158#define MAC_RCR_JE_POS 8159#define MAC_RCR_JE_LEN 1160#define MAC_RCR_LM_POS 10161#define MAC_RCR_LM_LEN 1162#define MAC_RCR_RE_POS 0163#define MAC_RCR_RE_LEN 1164#define MAC_RFCR_PFCE_POS 8165#define MAC_RFCR_PFCE_LEN 1166#define MAC_RFCR_RFE_POS 0167#define MAC_RFCR_RFE_LEN 1168#define MAC_RFCR_UP_POS 1169#define MAC_RFCR_UP_LEN 1170#define MAC_RQC0R_RXQ0EN_POS 0171#define MAC_RQC0R_RXQ0EN_LEN 2172#define MAC_RSSAR_ADDRT_POS 2173#define MAC_RSSAR_ADDRT_LEN 1174#define MAC_RSSAR_CT_POS 1175#define MAC_RSSAR_CT_LEN 1176#define MAC_RSSAR_OB_POS 0177#define MAC_RSSAR_OB_LEN 1178#define MAC_RSSAR_RSSIA_POS 8179#define MAC_RSSAR_RSSIA_LEN 8180#define MAC_RSSCR_IP2TE_POS 1181#define MAC_RSSCR_IP2TE_LEN 1182#define MAC_RSSCR_RSSE_POS 0183#define MAC_RSSCR_RSSE_LEN 1184#define MAC_RSSCR_TCP4TE_POS 2185#define MAC_RSSCR_TCP4TE_LEN 1186#define MAC_RSSCR_UDP4TE_POS 3187#define MAC_RSSCR_UDP4TE_LEN 1188#define MAC_RSSDR_DMCH_POS 0189#define MAC_RSSDR_DMCH_LEN 4190#define MAC_TCR_SS_POS 28191#define MAC_TCR_SS_LEN 3192#define MAC_TCR_TE_POS 0193#define MAC_TCR_TE_LEN 1194#define MAC_VLANHTR_VLHT_POS 0195#define MAC_VLANHTR_VLHT_LEN 16196#define MAC_VLANIR_VLTI_POS 20197#define MAC_VLANIR_VLTI_LEN 1198#define MAC_VLANIR_CSVL_POS 19199#define MAC_VLANIR_CSVL_LEN 1200#define MAC_VLANTR_DOVLTC_POS 20201#define MAC_VLANTR_DOVLTC_LEN 1202#define MAC_VLANTR_ERSVLM_POS 19203#define MAC_VLANTR_ERSVLM_LEN 1204#define MAC_VLANTR_ESVL_POS 18205#define MAC_VLANTR_ESVL_LEN 1206#define MAC_VLANTR_ETV_POS 16207#define MAC_VLANTR_ETV_LEN 1208#define MAC_VLANTR_EVLS_POS 21209#define MAC_VLANTR_EVLS_LEN 2210#define MAC_VLANTR_EVLRXS_POS 24211#define MAC_VLANTR_EVLRXS_LEN 1212#define MAC_VLANTR_VL_POS 0213#define MAC_VLANTR_VL_LEN 16214#define MAC_VLANTR_VTHM_POS 25215#define MAC_VLANTR_VTHM_LEN 1216#define MAC_VLANTR_VTIM_POS 17217#define MAC_VLANTR_VTIM_LEN 1218#define MAC_VR_DEVID_POS 8219#define MAC_VR_DEVID_LEN 8220#define MAC_VR_SNPSVER_POS 0221#define MAC_VR_SNPSVER_LEN 8222#define MAC_VR_USERVER_POS 16223#define MAC_VR_USERVER_LEN 8224 225/* MMC register offsets */226#define MMC_CR 0x0800227#define MMC_RISR 0x0804228#define MMC_TISR 0x0808229#define MMC_RIER 0x080c230#define MMC_TIER 0x0810231#define MMC_TXOCTETCOUNT_GB_LO 0x0814232#define MMC_TXFRAMECOUNT_GB_LO 0x081c233#define MMC_TXBROADCASTFRAMES_G_LO 0x0824234#define MMC_TXMULTICASTFRAMES_G_LO 0x082c235#define MMC_TX64OCTETS_GB_LO 0x0834236#define MMC_TX65TO127OCTETS_GB_LO 0x083c237#define MMC_TX128TO255OCTETS_GB_LO 0x0844238#define MMC_TX256TO511OCTETS_GB_LO 0x084c239#define MMC_TX512TO1023OCTETS_GB_LO 0x0854240#define MMC_TX1024TOMAXOCTETS_GB_LO 0x085c241#define MMC_TXUNICASTFRAMES_GB_LO 0x0864242#define MMC_TXMULTICASTFRAMES_GB_LO 0x086c243#define MMC_TXBROADCASTFRAMES_GB_LO 0x0874244#define MMC_TXUNDERFLOWERROR_LO 0x087c245#define MMC_TXOCTETCOUNT_G_LO 0x0884246#define MMC_TXFRAMECOUNT_G_LO 0x088c247#define MMC_TXPAUSEFRAMES_LO 0x0894248#define MMC_TXVLANFRAMES_G_LO 0x089c249#define MMC_RXFRAMECOUNT_GB_LO 0x0900250#define MMC_RXOCTETCOUNT_GB_LO 0x0908251#define MMC_RXOCTETCOUNT_G_LO 0x0910252#define MMC_RXBROADCASTFRAMES_G_LO 0x0918253#define MMC_RXMULTICASTFRAMES_G_LO 0x0920254#define MMC_RXCRCERROR_LO 0x0928255#define MMC_RXRUNTERROR 0x0930256#define MMC_RXJABBERERROR 0x0934257#define MMC_RXUNDERSIZE_G 0x0938258#define MMC_RXOVERSIZE_G 0x093c259#define MMC_RX64OCTETS_GB_LO 0x0940260#define MMC_RX65TO127OCTETS_GB_LO 0x0948261#define MMC_RX128TO255OCTETS_GB_LO 0x0950262#define MMC_RX256TO511OCTETS_GB_LO 0x0958263#define MMC_RX512TO1023OCTETS_GB_LO 0x0960264#define MMC_RX1024TOMAXOCTETS_GB_LO 0x0968265#define MMC_RXUNICASTFRAMES_G_LO 0x0970266#define MMC_RXLENGTHERROR_LO 0x0978267#define MMC_RXOUTOFRANGETYPE_LO 0x0980268#define MMC_RXPAUSEFRAMES_LO 0x0988269#define MMC_RXFIFOOVERFLOW_LO 0x0990270#define MMC_RXVLANFRAMES_GB_LO 0x0998271#define MMC_RXWATCHDOGERROR 0x09a0272 273/* MMC register entry bit positions and sizes */274#define MMC_CR_CR_POS 0275#define MMC_CR_CR_LEN 1276#define MMC_CR_CSR_POS 1277#define MMC_CR_CSR_LEN 1278#define MMC_CR_ROR_POS 2279#define MMC_CR_ROR_LEN 1280#define MMC_CR_MCF_POS 3281#define MMC_CR_MCF_LEN 1282#define MMC_CR_MCT_POS 4283#define MMC_CR_MCT_LEN 2284#define MMC_RIER_ALL_INTERRUPTS_POS 0285#define MMC_RIER_ALL_INTERRUPTS_LEN 23286#define MMC_RISR_RXFRAMECOUNT_GB_POS 0287#define MMC_RISR_RXFRAMECOUNT_GB_LEN 1288#define MMC_RISR_RXOCTETCOUNT_GB_POS 1289#define MMC_RISR_RXOCTETCOUNT_GB_LEN 1290#define MMC_RISR_RXOCTETCOUNT_G_POS 2291#define MMC_RISR_RXOCTETCOUNT_G_LEN 1292#define MMC_RISR_RXBROADCASTFRAMES_G_POS 3293#define MMC_RISR_RXBROADCASTFRAMES_G_LEN 1294#define MMC_RISR_RXMULTICASTFRAMES_G_POS 4295#define MMC_RISR_RXMULTICASTFRAMES_G_LEN 1296#define MMC_RISR_RXCRCERROR_POS 5297#define MMC_RISR_RXCRCERROR_LEN 1298#define MMC_RISR_RXRUNTERROR_POS 6299#define MMC_RISR_RXRUNTERROR_LEN 1300#define MMC_RISR_RXJABBERERROR_POS 7301#define MMC_RISR_RXJABBERERROR_LEN 1302#define MMC_RISR_RXUNDERSIZE_G_POS 8303#define MMC_RISR_RXUNDERSIZE_G_LEN 1304#define MMC_RISR_RXOVERSIZE_G_POS 9305#define MMC_RISR_RXOVERSIZE_G_LEN 1306#define MMC_RISR_RX64OCTETS_GB_POS 10307#define MMC_RISR_RX64OCTETS_GB_LEN 1308#define MMC_RISR_RX65TO127OCTETS_GB_POS 11309#define MMC_RISR_RX65TO127OCTETS_GB_LEN 1310#define MMC_RISR_RX128TO255OCTETS_GB_POS 12311#define MMC_RISR_RX128TO255OCTETS_GB_LEN 1312#define MMC_RISR_RX256TO511OCTETS_GB_POS 13313#define MMC_RISR_RX256TO511OCTETS_GB_LEN 1314#define MMC_RISR_RX512TO1023OCTETS_GB_POS 14315#define MMC_RISR_RX512TO1023OCTETS_GB_LEN 1316#define MMC_RISR_RX1024TOMAXOCTETS_GB_POS 15317#define MMC_RISR_RX1024TOMAXOCTETS_GB_LEN 1318#define MMC_RISR_RXUNICASTFRAMES_G_POS 16319#define MMC_RISR_RXUNICASTFRAMES_G_LEN 1320#define MMC_RISR_RXLENGTHERROR_POS 17321#define MMC_RISR_RXLENGTHERROR_LEN 1322#define MMC_RISR_RXOUTOFRANGETYPE_POS 18323#define MMC_RISR_RXOUTOFRANGETYPE_LEN 1324#define MMC_RISR_RXPAUSEFRAMES_POS 19325#define MMC_RISR_RXPAUSEFRAMES_LEN 1326#define MMC_RISR_RXFIFOOVERFLOW_POS 20327#define MMC_RISR_RXFIFOOVERFLOW_LEN 1328#define MMC_RISR_RXVLANFRAMES_GB_POS 21329#define MMC_RISR_RXVLANFRAMES_GB_LEN 1330#define MMC_RISR_RXWATCHDOGERROR_POS 22331#define MMC_RISR_RXWATCHDOGERROR_LEN 1332#define MMC_TIER_ALL_INTERRUPTS_POS 0333#define MMC_TIER_ALL_INTERRUPTS_LEN 18334#define MMC_TISR_TXOCTETCOUNT_GB_POS 0335#define MMC_TISR_TXOCTETCOUNT_GB_LEN 1336#define MMC_TISR_TXFRAMECOUNT_GB_POS 1337#define MMC_TISR_TXFRAMECOUNT_GB_LEN 1338#define MMC_TISR_TXBROADCASTFRAMES_G_POS 2339#define MMC_TISR_TXBROADCASTFRAMES_G_LEN 1340#define MMC_TISR_TXMULTICASTFRAMES_G_POS 3341#define MMC_TISR_TXMULTICASTFRAMES_G_LEN 1342#define MMC_TISR_TX64OCTETS_GB_POS 4343#define MMC_TISR_TX64OCTETS_GB_LEN 1344#define MMC_TISR_TX65TO127OCTETS_GB_POS 5345#define MMC_TISR_TX65TO127OCTETS_GB_LEN 1346#define MMC_TISR_TX128TO255OCTETS_GB_POS 6347#define MMC_TISR_TX128TO255OCTETS_GB_LEN 1348#define MMC_TISR_TX256TO511OCTETS_GB_POS 7349#define MMC_TISR_TX256TO511OCTETS_GB_LEN 1350#define MMC_TISR_TX512TO1023OCTETS_GB_POS 8351#define MMC_TISR_TX512TO1023OCTETS_GB_LEN 1352#define MMC_TISR_TX1024TOMAXOCTETS_GB_POS 9353#define MMC_TISR_TX1024TOMAXOCTETS_GB_LEN 1354#define MMC_TISR_TXUNICASTFRAMES_GB_POS 10355#define MMC_TISR_TXUNICASTFRAMES_GB_LEN 1356#define MMC_TISR_TXMULTICASTFRAMES_GB_POS 11357#define MMC_TISR_TXMULTICASTFRAMES_GB_LEN 1358#define MMC_TISR_TXBROADCASTFRAMES_GB_POS 12359#define MMC_TISR_TXBROADCASTFRAMES_GB_LEN 1360#define MMC_TISR_TXUNDERFLOWERROR_POS 13361#define MMC_TISR_TXUNDERFLOWERROR_LEN 1362#define MMC_TISR_TXOCTETCOUNT_G_POS 14363#define MMC_TISR_TXOCTETCOUNT_G_LEN 1364#define MMC_TISR_TXFRAMECOUNT_G_POS 15365#define MMC_TISR_TXFRAMECOUNT_G_LEN 1366#define MMC_TISR_TXPAUSEFRAMES_POS 16367#define MMC_TISR_TXPAUSEFRAMES_LEN 1368#define MMC_TISR_TXVLANFRAMES_G_POS 17369#define MMC_TISR_TXVLANFRAMES_G_LEN 1370 371/* MTL register offsets */372#define MTL_OMR 0x1000373#define MTL_FDDR 0x1010374#define MTL_RQDCM0R 0x1030375 376#define MTL_RQDCM_INC 4377#define MTL_RQDCM_Q_PER_REG 4378 379/* MTL register entry bit positions and sizes */380#define MTL_OMR_ETSALG_POS 5381#define MTL_OMR_ETSALG_LEN 2382#define MTL_OMR_RAA_POS 2383#define MTL_OMR_RAA_LEN 1384 385/* MTL queue register offsets386 * Multiple queues can be active. The first queue has registers387 * that begin at 0x1100. Each subsequent queue has registers that388 * are accessed using an offset of 0x80 from the previous queue.389 */390#define MTL_Q_BASE 0x1100391#define MTL_Q_INC 0x80392 393#define MTL_Q_TQOMR 0x00394#define MTL_Q_RQOMR 0x40395#define MTL_Q_RQDR 0x48396#define MTL_Q_RQFCR 0x50397#define MTL_Q_IER 0x70398#define MTL_Q_ISR 0x74399 400/* MTL queue register entry bit positions and sizes */401#define MTL_Q_RQDR_PRXQ_POS 16402#define MTL_Q_RQDR_PRXQ_LEN 14403#define MTL_Q_RQDR_RXQSTS_POS 4404#define MTL_Q_RQDR_RXQSTS_LEN 2405#define MTL_Q_RQFCR_RFA_POS 1406#define MTL_Q_RQFCR_RFA_LEN 6407#define MTL_Q_RQFCR_RFD_POS 17408#define MTL_Q_RQFCR_RFD_LEN 6409#define MTL_Q_RQOMR_EHFC_POS 7410#define MTL_Q_RQOMR_EHFC_LEN 1411#define MTL_Q_RQOMR_RQS_POS 16412#define MTL_Q_RQOMR_RQS_LEN 9413#define MTL_Q_RQOMR_RSF_POS 5414#define MTL_Q_RQOMR_RSF_LEN 1415#define MTL_Q_RQOMR_FEP_POS 4416#define MTL_Q_RQOMR_FEP_LEN 1417#define MTL_Q_RQOMR_FUP_POS 3418#define MTL_Q_RQOMR_FUP_LEN 1419#define MTL_Q_RQOMR_RTC_POS 0420#define MTL_Q_RQOMR_RTC_LEN 2421#define MTL_Q_TQOMR_FTQ_POS 0422#define MTL_Q_TQOMR_FTQ_LEN 1423#define MTL_Q_TQOMR_Q2TCMAP_POS 8424#define MTL_Q_TQOMR_Q2TCMAP_LEN 3425#define MTL_Q_TQOMR_TQS_POS 16426#define MTL_Q_TQOMR_TQS_LEN 10427#define MTL_Q_TQOMR_TSF_POS 1428#define MTL_Q_TQOMR_TSF_LEN 1429#define MTL_Q_TQOMR_TTC_POS 4430#define MTL_Q_TQOMR_TTC_LEN 3431#define MTL_Q_TQOMR_TXQEN_POS 2432#define MTL_Q_TQOMR_TXQEN_LEN 2433 434/* MTL queue register value */435#define MTL_RSF_DISABLE 0x00436#define MTL_RSF_ENABLE 0x01437#define MTL_TSF_DISABLE 0x00438#define MTL_TSF_ENABLE 0x01439 440#define MTL_RX_THRESHOLD_64 0x00441#define MTL_RX_THRESHOLD_96 0x02442#define MTL_RX_THRESHOLD_128 0x03443#define MTL_TX_THRESHOLD_64 0x00444#define MTL_TX_THRESHOLD_96 0x02445#define MTL_TX_THRESHOLD_128 0x03446#define MTL_TX_THRESHOLD_192 0x04447#define MTL_TX_THRESHOLD_256 0x05448#define MTL_TX_THRESHOLD_384 0x06449#define MTL_TX_THRESHOLD_512 0x07450 451#define MTL_ETSALG_WRR 0x00452#define MTL_ETSALG_WFQ 0x01453#define MTL_ETSALG_DWRR 0x02454#define MTL_RAA_SP 0x00455#define MTL_RAA_WSP 0x01456 457#define MTL_Q_DISABLED 0x00458#define MTL_Q_ENABLED 0x02459 460#define MTL_RQDCM0R_Q0MDMACH 0x0461#define MTL_RQDCM0R_Q1MDMACH 0x00000100462#define MTL_RQDCM0R_Q2MDMACH 0x00020000463#define MTL_RQDCM0R_Q3MDMACH 0x03000000464#define MTL_RQDCM1R_Q4MDMACH 0x00000004465#define MTL_RQDCM1R_Q5MDMACH 0x00000500466#define MTL_RQDCM1R_Q6MDMACH 0x00060000467#define MTL_RQDCM1R_Q7MDMACH 0x07000000468#define MTL_RQDCM2R_Q8MDMACH 0x00000008469#define MTL_RQDCM2R_Q9MDMACH 0x00000900470#define MTL_RQDCM2R_Q10MDMACH 0x000A0000471#define MTL_RQDCM2R_Q11MDMACH 0x0B000000472 473/* MTL traffic class register offsets474 * Multiple traffic classes can be active. The first class has registers475 * that begin at 0x1100. Each subsequent queue has registers that476 * are accessed using an offset of 0x80 from the previous queue.477 */478#define MTL_TC_BASE MTL_Q_BASE479#define MTL_TC_INC MTL_Q_INC480 481#define MTL_TC_ETSCR 0x10482#define MTL_TC_ETSSR 0x14483#define MTL_TC_QWR 0x18484 485/* MTL traffic class register entry bit positions and sizes */486#define MTL_TC_ETSCR_TSA_POS 0487#define MTL_TC_ETSCR_TSA_LEN 2488#define MTL_TC_QWR_QW_POS 0489#define MTL_TC_QWR_QW_LEN 21490 491/* MTL traffic class register value */492#define MTL_TSA_SP 0x00493#define MTL_TSA_ETS 0x02494 495/* DMA register offsets */496#define DMA_MR 0x3000497#define DMA_SBMR 0x3004498#define DMA_ISR 0x3008499#define DMA_DSR0 0x3020500#define DMA_DSR1 0x3024501 502/* DMA register entry bit positions and sizes */503#define DMA_ISR_MACIS_POS 17504#define DMA_ISR_MACIS_LEN 1505#define DMA_ISR_MTLIS_POS 16506#define DMA_ISR_MTLIS_LEN 1507#define DMA_MR_SWR_POS 0508#define DMA_MR_SWR_LEN 1509#define DMA_SBMR_EAME_POS 11510#define DMA_SBMR_EAME_LEN 1511#define DMA_SBMR_BLEN_64_POS 5512#define DMA_SBMR_BLEN_64_LEN 1513#define DMA_SBMR_BLEN_128_POS 6514#define DMA_SBMR_BLEN_128_LEN 1515#define DMA_SBMR_BLEN_256_POS 7516#define DMA_SBMR_BLEN_256_LEN 1517#define DMA_SBMR_UNDEF_POS 0518#define DMA_SBMR_UNDEF_LEN 1519 520/* DMA register values */521#define DMA_DSR_RPS_LEN 4522#define DMA_DSR_TPS_LEN 4523#define DMA_DSR_Q_LEN (DMA_DSR_RPS_LEN + DMA_DSR_TPS_LEN)524#define DMA_DSR0_TPS_START 12525#define DMA_DSRX_FIRST_QUEUE 3526#define DMA_DSRX_INC 4527#define DMA_DSRX_QPR 4528#define DMA_DSRX_TPS_START 4529#define DMA_TPS_STOPPED 0x00530#define DMA_TPS_SUSPENDED 0x06531 532/* DMA channel register offsets533 * Multiple channels can be active. The first channel has registers534 * that begin at 0x3100. Each subsequent channel has registers that535 * are accessed using an offset of 0x80 from the previous channel.536 */537#define DMA_CH_BASE 0x3100538#define DMA_CH_INC 0x80539 540#define DMA_CH_CR 0x00541#define DMA_CH_TCR 0x04542#define DMA_CH_RCR 0x08543#define DMA_CH_TDLR_HI 0x10544#define DMA_CH_TDLR_LO 0x14545#define DMA_CH_RDLR_HI 0x18546#define DMA_CH_RDLR_LO 0x1c547#define DMA_CH_TDTR_LO 0x24548#define DMA_CH_RDTR_LO 0x2c549#define DMA_CH_TDRLR 0x30550#define DMA_CH_RDRLR 0x34551#define DMA_CH_IER 0x38552#define DMA_CH_RIWT 0x3c553#define DMA_CH_SR 0x60554 555/* DMA channel register entry bit positions and sizes */556#define DMA_CH_CR_PBLX8_POS 16557#define DMA_CH_CR_PBLX8_LEN 1558#define DMA_CH_CR_SPH_POS 24559#define DMA_CH_CR_SPH_LEN 1560#define DMA_CH_IER_AIE_POS 15561#define DMA_CH_IER_AIE_LEN 1562#define DMA_CH_IER_FBEE_POS 12563#define DMA_CH_IER_FBEE_LEN 1564#define DMA_CH_IER_NIE_POS 16565#define DMA_CH_IER_NIE_LEN 1566#define DMA_CH_IER_RBUE_POS 7567#define DMA_CH_IER_RBUE_LEN 1568#define DMA_CH_IER_RIE_POS 6569#define DMA_CH_IER_RIE_LEN 1570#define DMA_CH_IER_RSE_POS 8571#define DMA_CH_IER_RSE_LEN 1572#define DMA_CH_IER_TBUE_POS 2573#define DMA_CH_IER_TBUE_LEN 1574#define DMA_CH_IER_TIE_POS 0575#define DMA_CH_IER_TIE_LEN 1576#define DMA_CH_IER_TXSE_POS 1577#define DMA_CH_IER_TXSE_LEN 1578#define DMA_CH_RCR_PBL_POS 16579#define DMA_CH_RCR_PBL_LEN 6580#define DMA_CH_RCR_RBSZ_POS 1581#define DMA_CH_RCR_RBSZ_LEN 14582#define DMA_CH_RCR_SR_POS 0583#define DMA_CH_RCR_SR_LEN 1584#define DMA_CH_RIWT_RWT_POS 0585#define DMA_CH_RIWT_RWT_LEN 8586#define DMA_CH_SR_FBE_POS 12587#define DMA_CH_SR_FBE_LEN 1588#define DMA_CH_SR_RBU_POS 7589#define DMA_CH_SR_RBU_LEN 1590#define DMA_CH_SR_RI_POS 6591#define DMA_CH_SR_RI_LEN 1592#define DMA_CH_SR_RPS_POS 8593#define DMA_CH_SR_RPS_LEN 1594#define DMA_CH_SR_TBU_POS 2595#define DMA_CH_SR_TBU_LEN 1596#define DMA_CH_SR_TI_POS 0597#define DMA_CH_SR_TI_LEN 1598#define DMA_CH_SR_TPS_POS 1599#define DMA_CH_SR_TPS_LEN 1600#define DMA_CH_TCR_OSP_POS 4601#define DMA_CH_TCR_OSP_LEN 1602#define DMA_CH_TCR_PBL_POS 16603#define DMA_CH_TCR_PBL_LEN 6604#define DMA_CH_TCR_ST_POS 0605#define DMA_CH_TCR_ST_LEN 1606#define DMA_CH_TCR_TSE_POS 12607#define DMA_CH_TCR_TSE_LEN 1608 609/* DMA channel register values */610#define DMA_OSP_DISABLE 0x00611#define DMA_OSP_ENABLE 0x01612#define DMA_PBL_1 1613#define DMA_PBL_2 2614#define DMA_PBL_4 4615#define DMA_PBL_8 8616#define DMA_PBL_16 16617#define DMA_PBL_32 32618#define DMA_PBL_64 64619#define DMA_PBL_128 128620#define DMA_PBL_256 256621#define DMA_PBL_X8_DISABLE 0x00622#define DMA_PBL_X8_ENABLE 0x01623 624/* Descriptor/Packet entry bit positions and sizes */625#define RX_PACKET_ERRORS_CRC_POS 2626#define RX_PACKET_ERRORS_CRC_LEN 1627#define RX_PACKET_ERRORS_FRAME_POS 3628#define RX_PACKET_ERRORS_FRAME_LEN 1629#define RX_PACKET_ERRORS_LENGTH_POS 0630#define RX_PACKET_ERRORS_LENGTH_LEN 1631#define RX_PACKET_ERRORS_OVERRUN_POS 1632#define RX_PACKET_ERRORS_OVERRUN_LEN 1633 634#define RX_PACKET_ATTRIBUTES_CSUM_DONE_POS 0635#define RX_PACKET_ATTRIBUTES_CSUM_DONE_LEN 1636#define RX_PACKET_ATTRIBUTES_VLAN_CTAG_POS 1637#define RX_PACKET_ATTRIBUTES_VLAN_CTAG_LEN 1638#define RX_PACKET_ATTRIBUTES_INCOMPLETE_POS 2639#define RX_PACKET_ATTRIBUTES_INCOMPLETE_LEN 1640#define RX_PACKET_ATTRIBUTES_CONTEXT_NEXT_POS 3641#define RX_PACKET_ATTRIBUTES_CONTEXT_NEXT_LEN 1642#define RX_PACKET_ATTRIBUTES_CONTEXT_POS 4643#define RX_PACKET_ATTRIBUTES_CONTEXT_LEN 1644#define RX_PACKET_ATTRIBUTES_RX_TSTAMP_POS 5645#define RX_PACKET_ATTRIBUTES_RX_TSTAMP_LEN 1646#define RX_PACKET_ATTRIBUTES_RSS_HASH_POS 6647#define RX_PACKET_ATTRIBUTES_RSS_HASH_LEN 1648 649#define RX_NORMAL_DESC0_OVT_POS 0650#define RX_NORMAL_DESC0_OVT_LEN 16651#define RX_NORMAL_DESC2_HL_POS 0652#define RX_NORMAL_DESC2_HL_LEN 10653#define RX_NORMAL_DESC3_CDA_POS 27654#define RX_NORMAL_DESC3_CDA_LEN 1655#define RX_NORMAL_DESC3_CTXT_POS 30656#define RX_NORMAL_DESC3_CTXT_LEN 1657#define RX_NORMAL_DESC3_ES_POS 15658#define RX_NORMAL_DESC3_ES_LEN 1659#define RX_NORMAL_DESC3_ETLT_POS 16660#define RX_NORMAL_DESC3_ETLT_LEN 4661#define RX_NORMAL_DESC3_FD_POS 29662#define RX_NORMAL_DESC3_FD_LEN 1663#define RX_NORMAL_DESC3_INTE_POS 30664#define RX_NORMAL_DESC3_INTE_LEN 1665#define RX_NORMAL_DESC3_L34T_POS 20666#define RX_NORMAL_DESC3_L34T_LEN 4667#define RX_NORMAL_DESC3_LD_POS 28668#define RX_NORMAL_DESC3_LD_LEN 1669#define RX_NORMAL_DESC3_OWN_POS 31670#define RX_NORMAL_DESC3_OWN_LEN 1671#define RX_NORMAL_DESC3_PL_POS 0672#define RX_NORMAL_DESC3_PL_LEN 14673#define RX_NORMAL_DESC3_RSV_POS 26674#define RX_NORMAL_DESC3_RSV_LEN 1675 676#define RX_DESC3_L34T_IPV4_TCP 1677#define RX_DESC3_L34T_IPV4_UDP 2678#define RX_DESC3_L34T_IPV4_ICMP 3679#define RX_DESC3_L34T_IPV6_TCP 9680#define RX_DESC3_L34T_IPV6_UDP 10681#define RX_DESC3_L34T_IPV6_ICMP 11682 683#define RX_CONTEXT_DESC3_TSA_POS 4684#define RX_CONTEXT_DESC3_TSA_LEN 1685#define RX_CONTEXT_DESC3_TSD_POS 6686#define RX_CONTEXT_DESC3_TSD_LEN 1687 688#define TX_PACKET_ATTRIBUTES_CSUM_ENABLE_POS 0689#define TX_PACKET_ATTRIBUTES_CSUM_ENABLE_LEN 1690#define TX_PACKET_ATTRIBUTES_TSO_ENABLE_POS 1691#define TX_PACKET_ATTRIBUTES_TSO_ENABLE_LEN 1692#define TX_PACKET_ATTRIBUTES_VLAN_CTAG_POS 2693#define TX_PACKET_ATTRIBUTES_VLAN_CTAG_LEN 1694#define TX_PACKET_ATTRIBUTES_PTP_POS 3695#define TX_PACKET_ATTRIBUTES_PTP_LEN 1696 697#define TX_CONTEXT_DESC2_MSS_POS 0698#define TX_CONTEXT_DESC2_MSS_LEN 15699#define TX_CONTEXT_DESC3_CTXT_POS 30700#define TX_CONTEXT_DESC3_CTXT_LEN 1701#define TX_CONTEXT_DESC3_TCMSSV_POS 26702#define TX_CONTEXT_DESC3_TCMSSV_LEN 1703#define TX_CONTEXT_DESC3_VLTV_POS 16704#define TX_CONTEXT_DESC3_VLTV_LEN 1705#define TX_CONTEXT_DESC3_VT_POS 0706#define TX_CONTEXT_DESC3_VT_LEN 16707 708#define TX_NORMAL_DESC2_HL_B1L_POS 0709#define TX_NORMAL_DESC2_HL_B1L_LEN 14710#define TX_NORMAL_DESC2_IC_POS 31711#define TX_NORMAL_DESC2_IC_LEN 1712#define TX_NORMAL_DESC2_TTSE_POS 30713#define TX_NORMAL_DESC2_TTSE_LEN 1714#define TX_NORMAL_DESC2_VTIR_POS 14715#define TX_NORMAL_DESC2_VTIR_LEN 2716#define TX_NORMAL_DESC3_CIC_POS 16717#define TX_NORMAL_DESC3_CIC_LEN 2718#define TX_NORMAL_DESC3_CPC_POS 26719#define TX_NORMAL_DESC3_CPC_LEN 2720#define TX_NORMAL_DESC3_CTXT_POS 30721#define TX_NORMAL_DESC3_CTXT_LEN 1722#define TX_NORMAL_DESC3_FD_POS 29723#define TX_NORMAL_DESC3_FD_LEN 1724#define TX_NORMAL_DESC3_FL_POS 0725#define TX_NORMAL_DESC3_FL_LEN 15726#define TX_NORMAL_DESC3_LD_POS 28727#define TX_NORMAL_DESC3_LD_LEN 1728#define TX_NORMAL_DESC3_OWN_POS 31729#define TX_NORMAL_DESC3_OWN_LEN 1730#define TX_NORMAL_DESC3_TCPHDRLEN_POS 19731#define TX_NORMAL_DESC3_TCPHDRLEN_LEN 4732#define TX_NORMAL_DESC3_TCPPL_POS 0733#define TX_NORMAL_DESC3_TCPPL_LEN 18734#define TX_NORMAL_DESC3_TSE_POS 18735#define TX_NORMAL_DESC3_TSE_LEN 1736 737#define TX_NORMAL_DESC2_VLAN_INSERT 0x2738 739#define XLGMAC_MTL_REG(pdata, n, reg) \740 ((pdata)->mac_regs + MTL_Q_BASE + ((n) * MTL_Q_INC) + (reg))741 742#define XLGMAC_DMA_REG(channel, reg) ((channel)->dma_regs + (reg))743 744#endif /* __DWC_XLGMAC_REG_H__ */745