246 lines · c
1/* SPDX-License-Identifier: GPL-2.0+ */2/* Copyright (c) Tehuti Networks Ltd. */3 4#ifndef _TN40_REGS_H_5#define _TN40_REGS_H_6 7/* Register region size */8#define TN40_REGS_SIZE 0x100009 10/* Registers from 0x0000-0x00fc were remapped to 0x4000-0x40fc */11#define TN40_REG_TXD_CFG1_0 0x400012#define TN40_REG_TXD_CFG1_1 0x400413#define TN40_REG_TXD_CFG1_2 0x400814#define TN40_REG_TXD_CFG1_3 0x400C15 16#define TN40_REG_RXF_CFG1_0 0x401017#define TN40_REG_RXF_CFG1_1 0x401418#define TN40_REG_RXF_CFG1_2 0x401819#define TN40_REG_RXF_CFG1_3 0x401C20 21#define TN40_REG_RXD_CFG1_0 0x402022#define TN40_REG_RXD_CFG1_1 0x402423#define TN40_REG_RXD_CFG1_2 0x402824#define TN40_REG_RXD_CFG1_3 0x402C25 26#define TN40_REG_TXF_CFG1_0 0x403027#define TN40_REG_TXF_CFG1_1 0x403428#define TN40_REG_TXF_CFG1_2 0x403829#define TN40_REG_TXF_CFG1_3 0x403C30 31#define TN40_REG_TXD_CFG0_0 0x404032#define TN40_REG_TXD_CFG0_1 0x404433#define TN40_REG_TXD_CFG0_2 0x404834#define TN40_REG_TXD_CFG0_3 0x404C35 36#define TN40_REG_RXF_CFG0_0 0x405037#define TN40_REG_RXF_CFG0_1 0x405438#define TN40_REG_RXF_CFG0_2 0x405839#define TN40_REG_RXF_CFG0_3 0x405C40 41#define TN40_REG_RXD_CFG0_0 0x406042#define TN40_REG_RXD_CFG0_1 0x406443#define TN40_REG_RXD_CFG0_2 0x406844#define TN40_REG_RXD_CFG0_3 0x406C45 46#define TN40_REG_TXF_CFG0_0 0x407047#define TN40_REG_TXF_CFG0_1 0x407448#define TN40_REG_TXF_CFG0_2 0x407849#define TN40_REG_TXF_CFG0_3 0x407C50 51#define TN40_REG_TXD_WPTR_0 0x408052#define TN40_REG_TXD_WPTR_1 0x408453#define TN40_REG_TXD_WPTR_2 0x408854#define TN40_REG_TXD_WPTR_3 0x408C55 56#define TN40_REG_RXF_WPTR_0 0x409057#define TN40_REG_RXF_WPTR_1 0x409458#define TN40_REG_RXF_WPTR_2 0x409859#define TN40_REG_RXF_WPTR_3 0x409C60 61#define TN40_REG_RXD_WPTR_0 0x40A062#define TN40_REG_RXD_WPTR_1 0x40A463#define TN40_REG_RXD_WPTR_2 0x40A864#define TN40_REG_RXD_WPTR_3 0x40AC65 66#define TN40_REG_TXF_WPTR_0 0x40B067#define TN40_REG_TXF_WPTR_1 0x40B468#define TN40_REG_TXF_WPTR_2 0x40B869#define TN40_REG_TXF_WPTR_3 0x40BC70 71#define TN40_REG_TXD_RPTR_0 0x40C072#define TN40_REG_TXD_RPTR_1 0x40C473#define TN40_REG_TXD_RPTR_2 0x40C874#define TN40_REG_TXD_RPTR_3 0x40CC75 76#define TN40_REG_RXF_RPTR_0 0x40D077#define TN40_REG_RXF_RPTR_1 0x40D478#define TN40_REG_RXF_RPTR_2 0x40D879#define TN40_REG_RXF_RPTR_3 0x40DC80 81#define TN40_REG_RXD_RPTR_0 0x40E082#define TN40_REG_RXD_RPTR_1 0x40E483#define TN40_REG_RXD_RPTR_2 0x40E884#define TN40_REG_RXD_RPTR_3 0x40EC85 86#define TN40_REG_TXF_RPTR_0 0x40F087#define TN40_REG_TXF_RPTR_1 0x40F488#define TN40_REG_TXF_RPTR_2 0x40F889#define TN40_REG_TXF_RPTR_3 0x40FC90 91/* Hardware versioning */92#define TN40_FPGA_VER 0x503093 94/* Registers from 0x0100-0x0150 were remapped to 0x5100-0x5150 */95#define TN40_REG_ISR TN40_REG_ISR096#define TN40_REG_ISR0 0x510097 98#define TN40_REG_IMR TN40_REG_IMR099#define TN40_REG_IMR0 0x5110100 101#define TN40_REG_RDINTCM0 0x5120102#define TN40_REG_RDINTCM2 0x5128103 104#define TN40_REG_TDINTCM0 0x5130105 106#define TN40_REG_ISR_MSK0 0x5140107 108#define TN40_REG_INIT_SEMAPHORE 0x5170109#define TN40_REG_INIT_STATUS 0x5180110 111#define TN40_REG_MAC_LNK_STAT 0x0200112#define TN40_MAC_LINK_STAT 0x0004 /* Link state */113 114#define TN40_REG_BLNK_LED 0x0210115 116#define TN40_REG_GMAC_RXF_A 0x1240117 118#define TN40_REG_UNC_MAC0_A 0x1250119#define TN40_REG_UNC_MAC1_A 0x1260120#define TN40_REG_UNC_MAC2_A 0x1270121 122#define TN40_REG_VLAN_0 0x1800123 124#define TN40_REG_MAX_FRAME_A 0x12C0125 126#define TN40_REG_RX_MAC_MCST0 0x1A80127#define TN40_REG_RX_MAC_MCST1 0x1A84128#define TN40_MAC_MCST_NUM 15129#define TN40_REG_RX_MCST_HASH0 0x1A00130#define TN40_MAC_MCST_HASH_NUM 8131 132#define TN40_REG_VPC 0x2300133#define TN40_REG_VIC 0x2320134#define TN40_REG_VGLB 0x2340135 136#define TN40_REG_CLKPLL 0x5000137 138/* MDIO interface */139 140#define TN40_REG_MDIO_CMD_STAT 0x6030141#define TN40_REG_MDIO_CMD 0x6034142#define TN40_REG_MDIO_DATA 0x6038143#define TN40_REG_MDIO_ADDR 0x603C144#define TN40_GET_MDIO_BUSY(x) FIELD_GET(GENMASK(0, 0), (x))145#define TN40_GET_MDIO_RD_ERR(x) FIELD_GET(GENMASK(1, 1), (x))146 147#define TN40_REG_REVISION 0x6000148#define TN40_REG_SCRATCH 0x6004149#define TN40_REG_CTRLST 0x6008150#define TN40_REG_MAC_ADDR_0 0x600C151#define TN40_REG_MAC_ADDR_1 0x6010152#define TN40_REG_FRM_LENGTH 0x6014153#define TN40_REG_PAUSE_QUANT 0x6054154#define TN40_REG_RX_FIFO_SECTION 0x601C155#define TN40_REG_TX_FIFO_SECTION 0x6020156#define TN40_REG_RX_FULLNESS 0x6024157#define TN40_REG_TX_FULLNESS 0x6028158#define TN40_REG_HASHTABLE 0x602C159 160#define TN40_REG_RST_PORT 0x7000161#define TN40_REG_DIS_PORT 0x7010162#define TN40_REG_RST_QU 0x7020163#define TN40_REG_DIS_QU 0x7030164 165#define TN40_REG_CTRLST_TX_ENA 0x0001166#define TN40_REG_CTRLST_RX_ENA 0x0002167#define TN40_REG_CTRLST_PRM_ENA 0x0010168#define TN40_REG_CTRLST_PAD_ENA 0x0020169 170#define TN40_REG_CTRLST_BASE (TN40_REG_CTRLST_PAD_ENA | REG_CTRLST_PRM_ENA)171 172/* TXD TXF RXF RXD CONFIG 0x0000 --- 0x007c */173#define TN40_TX_RX_CFG1_BASE 0xffffffff /*0-31 */174#define TN40_TX_RX_CFG0_BASE 0xfffff000 /*31:12 */175#define TN40_TX_RX_CFG0_RSVD 0x00000ffc /*11:2 */176#define TN40_TX_RX_CFG0_SIZE 0x00000003 /*1:0 */177 178/* TXD TXF RXF RXD WRITE 0x0080 --- 0x00BC */179#define TN40_TXF_WPTR_WR_PTR 0x00007ff8 /*14:3 */180 181/* TXD TXF RXF RXD READ 0x00CO --- 0x00FC */182#define TN40_TXF_RPTR_RD_PTR 0x00007ff8 /*14:3 */183 184/* The last 4 bits are dropped size is rounded to 16 */185#define TN40_TXF_WPTR_MASK 0x7ff0186 187/* regISR 0x0100 */188/* regIMR 0x0110 */189#define TN40_IMR_INPROG 0x80000000 /*31 */190#define TN40_IR_LNKCHG1 0x10000000 /*28 */191#define TN40_IR_LNKCHG0 0x08000000 /*27 */192#define TN40_IR_GPIO 0x04000000 /*26 */193#define TN40_IR_RFRSH 0x02000000 /*25 */194#define TN40_IR_RSVD 0x01000000 /*24 */195#define TN40_IR_SWI 0x00800000 /*23 */196#define TN40_IR_RX_FREE_3 0x00400000 /*22 */197#define TN40_IR_RX_FREE_2 0x00200000 /*21 */198#define TN40_IR_RX_FREE_1 0x00100000 /*20 */199#define TN40_IR_RX_FREE_0 0x00080000 /*19 */200#define TN40_IR_TX_FREE_3 0x00040000 /*18 */201#define TN40_IR_TX_FREE_2 0x00020000 /*17 */202#define TN40_IR_TX_FREE_1 0x00010000 /*16 */203#define TN40_IR_TX_FREE_0 0x00008000 /*15 */204#define TN40_IR_RX_DESC_3 0x00004000 /*14 */205#define TN40_IR_RX_DESC_2 0x00002000 /*13 */206#define TN40_IR_RX_DESC_1 0x00001000 /*12 */207#define TN40_IR_RX_DESC_0 0x00000800 /*11 */208#define TN40_IR_PSE 0x00000400 /*10 */209#define TN40_IR_TMR3 0x00000200 /* 9 */210#define TN40_IR_TMR2 0x00000100 /* 8 */211#define TN40_IR_TMR1 0x00000080 /* 7 */212#define TN40_IR_TMR0 0x00000040 /* 6 */213#define TN40_IR_VNT 0x00000020 /* 5 */214#define TN40_IR_RxFL 0x00000010 /* 4 */215#define TN40_IR_SDPERR 0x00000008 /* 3 */216#define TN40_IR_TR 0x00000004 /* 2 */217#define TN40_IR_PCIE_LINK 0x00000002 /* 1 */218#define TN40_IR_PCIE_TOUT 0x00000001 /* 0 */219 220#define TN40_IR_EXTRA \221 (TN40_IR_RX_FREE_0 | TN40_IR_LNKCHG0 | TN40_IR_LNKCHG1 |\222 TN40_IR_PSE | TN40_IR_TMR0 | TN40_IR_PCIE_LINK | \223 TN40_IR_PCIE_TOUT)224 225#define TN40_GMAC_RX_FILTER_OSEN 0x1000 /* shared OS enable */226#define TN40_GMAC_RX_FILTER_TXFC 0x0400 /* Tx flow control */227#define TN40_GMAC_RX_FILTER_RSV0 0x0200 /* reserved */228#define TN40_GMAC_RX_FILTER_FDA 0x0100 /* filter out direct address */229#define TN40_GMAC_RX_FILTER_AOF 0x0080 /* accept over run */230#define TN40_GMAC_RX_FILTER_ACF 0x0040 /* accept control frames */231#define TN40_GMAC_RX_FILTER_ARUNT 0x0020 /* accept under run */232#define TN40_GMAC_RX_FILTER_ACRC 0x0010 /* accept crc error */233#define TN40_GMAC_RX_FILTER_AM 0x0008 /* accept multicast */234#define TN40_GMAC_RX_FILTER_AB 0x0004 /* accept broadcast */235#define TN40_GMAC_RX_FILTER_PRM 0x0001 /* [0:1] promiscuous mode */236 237#define TN40_MAX_FRAME_AB_VAL 0x3fff /* 13:0 */238 239#define TN40_CLKPLL_PLLLKD 0x0200 /* 9 */240#define TN40_CLKPLL_RSTEND 0x0100 /* 8 */241#define TN40_CLKPLL_SFTRST 0x0001 /* 0 */242 243#define TN40_CLKPLL_LKD (TN40_CLKPLL_PLLLKD | TN40_CLKPLL_RSTEND)244 245#endif246