74 lines · c
1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * Texas Instruments Ethernet Switch media-access-controller (MAC) submodule/4 * Ethernet MAC Sliver (CPGMAC_SL) APIs5 *6 * Copyright (C) 2019 Texas Instruments7 *8 */9 10#ifndef __TI_CPSW_SL_H__11#define __TI_CPSW_SL_H__12 13#include <linux/device.h>14 15enum cpsw_sl_regs {16 CPSW_SL_IDVER,17 CPSW_SL_MACCONTROL,18 CPSW_SL_MACSTATUS,19 CPSW_SL_SOFT_RESET,20 CPSW_SL_RX_MAXLEN,21 CPSW_SL_BOFFTEST,22 CPSW_SL_RX_PAUSE,23 CPSW_SL_TX_PAUSE,24 CPSW_SL_EMCONTROL,25 CPSW_SL_RX_PRI_MAP,26 CPSW_SL_TX_GAP,27};28 29enum {30 CPSW_SL_CTL_FULLDUPLEX = BIT(0), /* Full Duplex mode */31 CPSW_SL_CTL_LOOPBACK = BIT(1), /* Loop Back Mode */32 CPSW_SL_CTL_MTEST = BIT(2), /* Manufacturing Test mode */33 CPSW_SL_CTL_RX_FLOW_EN = BIT(3), /* Receive Flow Control Enable */34 CPSW_SL_CTL_TX_FLOW_EN = BIT(4), /* Transmit Flow Control Enable */35 CPSW_SL_CTL_GMII_EN = BIT(5), /* GMII Enable */36 CPSW_SL_CTL_TX_PACE = BIT(6), /* Transmit Pacing Enable */37 CPSW_SL_CTL_GIG = BIT(7), /* Gigabit Mode */38 CPSW_SL_CTL_XGIG = BIT(8), /* 10 Gigabit Mode */39 CPSW_SL_CTL_TX_SHORT_GAP_EN = BIT(10), /* Transmit Short Gap Enable */40 CPSW_SL_CTL_CMD_IDLE = BIT(11), /* Command Idle */41 CPSW_SL_CTL_CRC_TYPE = BIT(12), /* Port CRC Type */42 CPSW_SL_CTL_XGMII_EN = BIT(13), /* XGMII Enable */43 CPSW_SL_CTL_IFCTL_A = BIT(15), /* Interface Control A */44 CPSW_SL_CTL_IFCTL_B = BIT(16), /* Interface Control B */45 CPSW_SL_CTL_GIG_FORCE = BIT(17), /* Gigabit Mode Force */46 CPSW_SL_CTL_EXT_EN = BIT(18), /* External Control Enable */47 CPSW_SL_CTL_EXT_EN_RX_FLO = BIT(19), /* Ext RX Flow Control Enable */48 CPSW_SL_CTL_EXT_EN_TX_FLO = BIT(20), /* Ext TX Flow Control Enable */49 CPSW_SL_CTL_TX_SG_LIM_EN = BIT(21), /* TXt Short Gap Limit Enable */50 CPSW_SL_CTL_RX_CEF_EN = BIT(22), /* RX Copy Error Frames Enable */51 CPSW_SL_CTL_RX_CSF_EN = BIT(23), /* RX Copy Short Frames Enable */52 CPSW_SL_CTL_RX_CMF_EN = BIT(24), /* RX Copy MAC Control Frames Enable */53 CPSW_SL_CTL_EXT_EN_XGIG = BIT(25), /* Ext XGIG Control En, k3 only */54 55 CPSW_SL_CTL_FUNCS_COUNT56};57 58struct cpsw_sl;59 60struct cpsw_sl *cpsw_sl_get(const char *device_id, struct device *dev,61 void __iomem *sl_base);62 63void cpsw_sl_reset(struct cpsw_sl *sl, unsigned long tmo);64 65u32 cpsw_sl_ctl_set(struct cpsw_sl *sl, u32 ctl_funcs);66u32 cpsw_sl_ctl_clr(struct cpsw_sl *sl, u32 ctl_funcs);67void cpsw_sl_ctl_reset(struct cpsw_sl *sl);68int cpsw_sl_wait_for_idle(struct cpsw_sl *sl, unsigned long tmo);69 70u32 cpsw_sl_reg_read(struct cpsw_sl *sl, enum cpsw_sl_regs reg);71void cpsw_sl_reg_write(struct cpsw_sl *sl, enum cpsw_sl_regs reg, u32 val);72 73#endif /* __TI_CPSW_SL_H__ */74