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1/* SPDX-License-Identifier: GPL-2.0 */2/* Texas Instruments ICSSG Ethernet driver3 *4 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/5 *6 */7 8#ifndef __NET_TI_ICSSG_CONFIG_H9#define __NET_TI_ICSSG_CONFIG_H10 11struct icssg_buffer_pool_cfg {12 __le32 addr;13 __le32 len;14} __packed;15 16struct icssg_flow_cfg {17 __le16 rx_base_flow;18 __le16 mgm_base_flow;19} __packed;20 21#define PRUETH_PKT_TYPE_CMD 0x1022#define PRUETH_NAV_PS_DATA_SIZE 16 /* Protocol specific data size */23#define PRUETH_NAV_SW_DATA_SIZE 16 /* SW related data size */24#define PRUETH_MAX_TX_DESC 51225#define PRUETH_MAX_RX_DESC 51226#define PRUETH_MAX_RX_FLOWS 1 /* excluding default flow */27#define PRUETH_RX_FLOW_DATA 028 29#define PRUETH_EMAC_BUF_POOL_SIZE SZ_8K30#define PRUETH_EMAC_POOLS_PER_SLICE 2431#define PRUETH_EMAC_BUF_POOL_START 832#define PRUETH_NUM_BUF_POOLS 833#define PRUETH_EMAC_RX_CTX_BUF_SIZE SZ_16K /* per slice */34#define MSMC_RAM_SIZE \35 (2 * (PRUETH_EMAC_BUF_POOL_SIZE * PRUETH_NUM_BUF_POOLS + \36 PRUETH_EMAC_RX_CTX_BUF_SIZE * 2))37 38#define PRUETH_SW_BUF_POOL_SIZE_HOST SZ_4K39#define PRUETH_SW_NUM_BUF_POOLS_HOST 840#define PRUETH_SW_NUM_BUF_POOLS_PER_PRU 441#define MSMC_RAM_SIZE_SWITCH_MODE \42 (MSMC_RAM_SIZE + \43 (2 * PRUETH_SW_BUF_POOL_SIZE_HOST * PRUETH_SW_NUM_BUF_POOLS_HOST))44 45#define PRUETH_SWITCH_FDB_MASK ((SIZE_OF_FDB / NUMBER_OF_FDB_BUCKET_ENTRIES) - 1)46 47struct icssg_rxq_ctx {48 __le32 start[3];49 __le32 end;50} __packed;51 52/* Load time Fiwmware Configuration */53 54#define ICSSG_FW_MGMT_CMD_HEADER 0x8155#define ICSSG_FW_MGMT_FDB_CMD_TYPE 0x0356#define ICSSG_FW_MGMT_CMD_TYPE 0x0457#define ICSSG_FW_MGMT_PKT 0x8000000058 59struct icssg_r30_cmd {60 u32 cmd[4];61} __packed;62 63enum icssg_port_state_cmd {64 ICSSG_EMAC_PORT_DISABLE = 0,65 ICSSG_EMAC_PORT_BLOCK,66 ICSSG_EMAC_PORT_FORWARD,67 ICSSG_EMAC_PORT_FORWARD_WO_LEARNING,68 ICSSG_EMAC_PORT_ACCEPT_ALL,69 ICSSG_EMAC_PORT_ACCEPT_TAGGED,70 ICSSG_EMAC_PORT_ACCEPT_UNTAGGED_N_PRIO,71 ICSSG_EMAC_PORT_TAS_TRIGGER,72 ICSSG_EMAC_PORT_TAS_ENABLE,73 ICSSG_EMAC_PORT_TAS_RESET,74 ICSSG_EMAC_PORT_TAS_DISABLE,75 ICSSG_EMAC_PORT_UC_FLOODING_ENABLE,76 ICSSG_EMAC_PORT_UC_FLOODING_DISABLE,77 ICSSG_EMAC_PORT_MC_FLOODING_ENABLE,78 ICSSG_EMAC_PORT_MC_FLOODING_DISABLE,79 ICSSG_EMAC_PORT_PREMPT_TX_ENABLE,80 ICSSG_EMAC_PORT_PREMPT_TX_DISABLE,81 ICSSG_EMAC_PORT_VLAN_AWARE_ENABLE,82 ICSSG_EMAC_PORT_VLAN_AWARE_DISABLE,83 ICSSG_EMAC_HSR_RX_OFFLOAD_ENABLE,84 ICSSG_EMAC_HSR_RX_OFFLOAD_DISABLE,85 ICSSG_EMAC_PORT_MAX_COMMANDS86};87 88#define EMAC_NONE 0xffff000089#define EMAC_PRU0_P_DI 0xffff000490#define EMAC_PRU1_P_DI 0xffff004091#define EMAC_TX_P_DI 0xffff010092 93#define EMAC_PRU0_P_EN 0xfffb000094#define EMAC_PRU1_P_EN 0xffbf000095#define EMAC_TX_P_EN 0xfeff000096 97#define EMAC_P_BLOCK 0xffff004098#define EMAC_TX_P_BLOCK 0xffff020099#define EMAC_P_UNBLOCK 0xffbf0000100#define EMAC_TX_P_UNBLOCK 0xfdff0000101#define EMAC_LEAN_EN 0xfff70000102#define EMAC_LEAN_DI 0xffff0008103 104#define EMAC_ACCEPT_ALL 0xffff0001105#define EMAC_ACCEPT_TAG 0xfffe0002106#define EMAC_ACCEPT_PRIOR 0xfffc0000107 108/* Config area lies in DRAM */109#define ICSSG_CONFIG_OFFSET 0x0110 111/* Config area lies in shared RAM */112#define ICSSG_CONFIG_OFFSET_SLICE0 0113#define ICSSG_CONFIG_OFFSET_SLICE1 0x8000114 115#define ICSSG_NUM_NORMAL_PDS 64116#define ICSSG_NUM_SPECIAL_PDS 16117 118#define ICSSG_NORMAL_PD_SIZE 8119#define ICSSG_SPECIAL_PD_SIZE 20120 121#define ICSSG_FLAG_MASK 0xff00ffff122 123/* SR1.0-specific bits */124#define PRUETH_MAX_RX_FLOWS_SR1 4 /* excluding default flow */125#define PRUETH_RX_FLOW_DATA_SR1 3 /* highest priority flow */126#define PRUETH_MAX_RX_MGM_DESC_SR1 8127#define PRUETH_MAX_RX_MGM_FLOWS_SR1 2 /* excluding default flow */128#define PRUETH_RX_MGM_FLOW_RESPONSE_SR1 0129#define PRUETH_RX_MGM_FLOW_TIMESTAMP_SR1 1130 131#define PRUETH_NUM_BUF_POOLS_SR1 16132#define PRUETH_EMAC_BUF_POOL_START_SR1 8133#define PRUETH_EMAC_BUF_POOL_MIN_SIZE_SR1 128134#define PRUETH_EMAC_BUF_SIZE_SR1 1536135#define PRUETH_EMAC_NUM_BUF_SR1 4136#define PRUETH_EMAC_BUF_POOL_SIZE_SR1 (PRUETH_EMAC_NUM_BUF_SR1 * \137 PRUETH_EMAC_BUF_SIZE_SR1)138#define MSMC_RAM_SIZE_SR1 (SZ_64K + SZ_32K + SZ_2K) /* 0x1880 x 8 x 2 */139 140struct icssg_sr1_config {141 __le32 status; /* Firmware status */142 __le32 addr_lo; /* MSMC Buffer pool base address low. */143 __le32 addr_hi; /* MSMC Buffer pool base address high. Must be 0 */144 __le32 tx_buf_sz[16]; /* Array of buffer pool sizes */145 __le32 num_tx_threads; /* Number of active egress threads, 1 to 4 */146 __le32 tx_rate_lim_en; /* Bitmask: Egress rate limit en per thread */147 __le32 rx_flow_id; /* RX flow id for first rx ring */148 __le32 rx_mgr_flow_id; /* RX flow id for the first management ring */149 __le32 flags; /* TBD */150 __le32 n_burst; /* for debug */151 __le32 rtu_status; /* RTU status */152 __le32 info; /* reserved */153 __le32 reserve;154 __le32 rand_seed; /* Used for the random number generation at fw */155} __packed;156 157/* SR1.0 shutdown command to stop processing at firmware.158 * Command format: 0x8101ss00, where159 * - ss: sequence number. Currently not used by driver.160 */161#define ICSSG_SHUTDOWN_CMD_SR1 0x81010000162 163/* SR1.0 pstate speed/duplex command to set speed and duplex settings164 * in firmware.165 * Command format: 0x8102ssPN, where166 * - ss: sequence number. Currently not used by driver.167 * - P: port number (for switch mode).168 * - N: Speed/Duplex state:169 * 0x0 - 10Mbps/Half duplex;170 * 0x8 - 10Mbps/Full duplex;171 * 0x2 - 100Mbps/Half duplex;172 * 0xa - 100Mbps/Full duplex;173 * 0xc - 1Gbps/Full duplex;174 * NOTE: The above are the same value as bits [3..1](slice 0)175 * or bits [7..5](slice 1) of RGMII CFG register.176 */177#define ICSSG_PSTATE_SPEED_DUPLEX_CMD_SR1 0x81020000178 179struct icssg_setclock_desc {180 u8 request;181 u8 restore;182 u8 acknowledgment;183 u8 cmp_status;184 u32 margin;185 u32 cyclecounter0_set;186 u32 cyclecounter1_set;187 u32 iepcount_set;188 u32 rsvd1;189 u32 rsvd2;190 u32 CMP0_current;191 u32 iepcount_current;192 u32 difference;193 u32 cyclecounter0_new;194 u32 cyclecounter1_new;195 u32 CMP0_new;196} __packed;197 198#define ICSSG_CMD_POP_SLICE0 56199#define ICSSG_CMD_POP_SLICE1 60200 201#define ICSSG_CMD_PUSH_SLICE0 57202#define ICSSG_CMD_PUSH_SLICE1 61203 204#define ICSSG_RSP_POP_SLICE0 58205#define ICSSG_RSP_POP_SLICE1 62206 207#define ICSSG_RSP_PUSH_SLICE0 56208#define ICSSG_RSP_PUSH_SLICE1 60209 210#define ICSSG_TS_POP_SLICE0 59211#define ICSSG_TS_POP_SLICE1 63212 213#define ICSSG_TS_PUSH_SLICE0 40214#define ICSSG_TS_PUSH_SLICE1 41215 216struct mgmt_cmd {217 u8 param;218 u8 seqnum;219 u8 type;220 u8 header;221 u32 cmd_args[3];222};223 224struct mgmt_cmd_rsp {225 u32 reserved;226 u8 status;227 u8 seqnum;228 u8 type;229 u8 header;230 u32 cmd_args[3];231};232 233/* FDB FID_C2 flag definitions */234/* Indicates host port membership.*/235#define ICSSG_FDB_ENTRY_P0_MEMBERSHIP BIT(0)236/* Indicates that MAC ID is connected to physical port 1 */237#define ICSSG_FDB_ENTRY_P1_MEMBERSHIP BIT(1)238/* Indicates that MAC ID is connected to physical port 2 */239#define ICSSG_FDB_ENTRY_P2_MEMBERSHIP BIT(2)240/* Ageable bit is set for learned entries and cleared for static entries */241#define ICSSG_FDB_ENTRY_AGEABLE BIT(3)242/* If set for DA then packet is determined to be a special packet */243#define ICSSG_FDB_ENTRY_BLOCK BIT(4)244/* If set for DA then the SA from the packet is not learned */245#define ICSSG_FDB_ENTRY_SECURE BIT(5)246/* If set, it means packet has been seen recently with source address + FID247 * matching MAC address/FID of entry248 */249#define ICSSG_FDB_ENTRY_TOUCHED BIT(6)250/* Set if entry is valid */251#define ICSSG_FDB_ENTRY_VALID BIT(7)252 253/**254 * struct prueth_vlan_tbl - VLAN table entries struct in ICSSG SMEM255 * @fid_c1: membership and forwarding rules flag to this table. See256 * above to defines for bit definitions257 * @fid: FDB index for this VID (there is 1-1 mapping b/w VID and FID)258 */259struct prueth_vlan_tbl {260 u8 fid_c1;261 u8 fid;262} __packed;263 264/**265 * struct prueth_fdb_slot - Result of FDB slot lookup266 * @mac: MAC address267 * @fid: fid to be associated with MAC268 * @fid_c2: FID_C2 entry for this MAC269 */270struct prueth_fdb_slot {271 u8 mac[ETH_ALEN];272 u8 fid;273 u8 fid_c2;274} __packed;275 276enum icssg_ietfpe_verify_states {277 ICSSG_IETFPE_STATE_UNKNOWN = 0,278 ICSSG_IETFPE_STATE_INITIAL,279 ICSSG_IETFPE_STATE_VERIFYING,280 ICSSG_IETFPE_STATE_SUCCEEDED,281 ICSSG_IETFPE_STATE_FAILED,282 ICSSG_IETFPE_STATE_DISABLED283};284#endif /* __NET_TI_ICSSG_CONFIG_H */285