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1/* SPDX-License-Identifier: GPL-2.0-or-later */2/*3 * Network device driver for Cell Processor-Based Blade and Celleb platform4 *5 * (C) Copyright IBM Corp. 20056 * (C) Copyright 2006 TOSHIBA CORPORATION7 *8 * Authors : Utz Bacher <utz.bacher@de.ibm.com>9 * Jens Osterkamp <Jens.Osterkamp@de.ibm.com>10 */11 12#ifndef _SPIDER_NET_H13#define _SPIDER_NET_H14 15#define VERSION "2.0 B"16 17#include <linux/sungem_phy.h>18 19int spider_net_stop(struct net_device *netdev);20int spider_net_open(struct net_device *netdev);21 22extern const struct ethtool_ops spider_net_ethtool_ops;23 24extern char spider_net_driver_name[];25 26#define SPIDER_NET_MAX_FRAME 231227#define SPIDER_NET_MAX_MTU 229428#define SPIDER_NET_MIN_MTU 6429 30#define SPIDER_NET_RXBUF_ALIGN 12831 32#define SPIDER_NET_RX_DESCRIPTORS_DEFAULT 25633#define SPIDER_NET_RX_DESCRIPTORS_MIN 1634#define SPIDER_NET_RX_DESCRIPTORS_MAX 51235 36#define SPIDER_NET_TX_DESCRIPTORS_DEFAULT 25637#define SPIDER_NET_TX_DESCRIPTORS_MIN 1638#define SPIDER_NET_TX_DESCRIPTORS_MAX 51239 40#define SPIDER_NET_TX_TIMER (HZ/5)41#define SPIDER_NET_ANEG_TIMER (HZ)42#define SPIDER_NET_ANEG_TIMEOUT 543 44#define SPIDER_NET_RX_CSUM_DEFAULT 145 46#define SPIDER_NET_WATCHDOG_TIMEOUT 50*HZ47 48#define SPIDER_NET_FIRMWARE_SEQS 649#define SPIDER_NET_FIRMWARE_SEQWORDS 102450#define SPIDER_NET_FIRMWARE_LEN (SPIDER_NET_FIRMWARE_SEQS * \51 SPIDER_NET_FIRMWARE_SEQWORDS * \52 sizeof(u32))53#define SPIDER_NET_FIRMWARE_NAME "spider_fw.bin"54 55/** spider_net SMMIO registers */56#define SPIDER_NET_GHIINT0STS 0x0000000057#define SPIDER_NET_GHIINT1STS 0x0000000458#define SPIDER_NET_GHIINT2STS 0x0000000859#define SPIDER_NET_GHIINT0MSK 0x0000001060#define SPIDER_NET_GHIINT1MSK 0x0000001461#define SPIDER_NET_GHIINT2MSK 0x0000001862 63#define SPIDER_NET_GRESUMINTNUM 0x0000002064#define SPIDER_NET_GREINTNUM 0x0000002465 66#define SPIDER_NET_GFFRMNUM 0x0000002867#define SPIDER_NET_GFAFRMNUM 0x0000002c68#define SPIDER_NET_GFBFRMNUM 0x0000003069#define SPIDER_NET_GFCFRMNUM 0x0000003470#define SPIDER_NET_GFDFRMNUM 0x0000003871 72/* clear them (don't use it) */73#define SPIDER_NET_GFREECNNUM 0x0000003c74#define SPIDER_NET_GONETIMENUM 0x0000004075 76#define SPIDER_NET_GTOUTFRMNUM 0x0000004477 78#define SPIDER_NET_GTXMDSET 0x0000005079#define SPIDER_NET_GPCCTRL 0x0000005480#define SPIDER_NET_GRXMDSET 0x0000005881#define SPIDER_NET_GIPSECINIT 0x0000005c82#define SPIDER_NET_GFTRESTRT 0x0000006083#define SPIDER_NET_GRXDMAEN 0x0000006484#define SPIDER_NET_GMRWOLCTRL 0x0000006885#define SPIDER_NET_GPCWOPCMD 0x0000006c86#define SPIDER_NET_GPCROPCMD 0x0000007087#define SPIDER_NET_GTTFRMCNT 0x0000007888#define SPIDER_NET_GTESTMD 0x0000007c89 90#define SPIDER_NET_GSINIT 0x0000008091#define SPIDER_NET_GSnPRGADR 0x0000008492#define SPIDER_NET_GSnPRGDAT 0x0000008893 94#define SPIDER_NET_GMACOPEMD 0x0000010095#define SPIDER_NET_GMACLENLMT 0x0000010896#define SPIDER_NET_GMACST 0x0000011097#define SPIDER_NET_GMACINTEN 0x0000011898#define SPIDER_NET_GMACPHYCTRL 0x0000012099 100#define SPIDER_NET_GMACAPAUSE 0x00000154101#define SPIDER_NET_GMACTXPAUSE 0x00000164102 103#define SPIDER_NET_GMACMODE 0x000001b0104#define SPIDER_NET_GMACBSTLMT 0x000001b4105 106#define SPIDER_NET_GMACUNIMACU 0x000001c0107#define SPIDER_NET_GMACUNIMACL 0x000001c8108 109#define SPIDER_NET_GMRMHFILnR 0x00000400110#define SPIDER_NET_MULTICAST_HASHES 256111 112#define SPIDER_NET_GMRUAFILnR 0x00000500113#define SPIDER_NET_GMRUA0FIL15R 0x00000578114 115#define SPIDER_NET_GTTQMSK 0x00000934116 117/* RX DMA controller registers, all 0x00000a.. are for DMA controller A,118 * 0x00000b.. for DMA controller B, etc. */119#define SPIDER_NET_GDADCHA 0x00000a00120#define SPIDER_NET_GDADMACCNTR 0x00000a04121#define SPIDER_NET_GDACTDPA 0x00000a08122#define SPIDER_NET_GDACTDCNT 0x00000a0c123#define SPIDER_NET_GDACDBADDR 0x00000a20124#define SPIDER_NET_GDACDBSIZE 0x00000a24125#define SPIDER_NET_GDACNEXTDA 0x00000a28126#define SPIDER_NET_GDACCOMST 0x00000a2c127#define SPIDER_NET_GDAWBCOMST 0x00000a30128#define SPIDER_NET_GDAWBRSIZE 0x00000a34129#define SPIDER_NET_GDAWBVSIZE 0x00000a38130#define SPIDER_NET_GDAWBTRST 0x00000a3c131#define SPIDER_NET_GDAWBTRERR 0x00000a40132 133/* TX DMA controller registers */134#define SPIDER_NET_GDTDCHA 0x00000e00135#define SPIDER_NET_GDTDMACCNTR 0x00000e04136#define SPIDER_NET_GDTCDPA 0x00000e08137#define SPIDER_NET_GDTDMASEL 0x00000e14138 139#define SPIDER_NET_ECMODE 0x00000f00140/* clock and reset control register */141#define SPIDER_NET_CKRCTRL 0x00000ff0142 143/** SCONFIG registers */144#define SPIDER_NET_SCONFIG_IOACTE 0x00002810145 146/** interrupt mask registers */147#define SPIDER_NET_INT0_MASK_VALUE 0x3f7fe2c7148#define SPIDER_NET_INT1_MASK_VALUE 0x0000fff2149#define SPIDER_NET_INT2_MASK_VALUE 0x000003f1150 151/* we rely on flagged descriptor interrupts */152#define SPIDER_NET_FRAMENUM_VALUE 0x00000000153/* set this first, then the FRAMENUM_VALUE */154#define SPIDER_NET_GFXFRAMES_VALUE 0x00000000155 156#define SPIDER_NET_STOP_SEQ_VALUE 0x00000000157#define SPIDER_NET_RUN_SEQ_VALUE 0x0000007e158 159#define SPIDER_NET_PHY_CTRL_VALUE 0x00040040160/* #define SPIDER_NET_PHY_CTRL_VALUE 0x01070080*/161#define SPIDER_NET_RXMODE_VALUE 0x00000011162/* auto retransmission in case of MAC aborts */163#define SPIDER_NET_TXMODE_VALUE 0x00010000164#define SPIDER_NET_RESTART_VALUE 0x00000000165#define SPIDER_NET_WOL_VALUE 0x00001111166#if 0167#define SPIDER_NET_WOL_VALUE 0x00000000168#endif169#define SPIDER_NET_IPSECINIT_VALUE 0x6f716f71170 171/* pause frames: automatic, no upper retransmission count */172/* outside loopback mode: ETOMOD signal dont matter, not connected */173/* ETOMOD signal is brought to PHY reset. bit 2 must be 1 in Celleb */174#define SPIDER_NET_OPMODE_VALUE 0x00000067175/*#define SPIDER_NET_OPMODE_VALUE 0x001b0062*/176#define SPIDER_NET_LENLMT_VALUE 0x00000908177 178#define SPIDER_NET_MACAPAUSE_VALUE 0x00000800 /* about 1 ms */179#define SPIDER_NET_TXPAUSE_VALUE 0x00000000180 181#define SPIDER_NET_MACMODE_VALUE 0x00000001182#define SPIDER_NET_BURSTLMT_VALUE 0x00000200 /* about 16 us */183 184/* DMAC control register GDMACCNTR185 *186 * 1(0) enable r/tx dma187 * 0000000 fixed to 0188 *189 * 000000 fixed to 0190 * 0(1) en/disable descr writeback on force end191 * 0(1) force end192 *193 * 000000 fixed to 0194 * 00 burst alignment: 128 bytes195 * 11 burst alignment: 1024 bytes196 *197 * 00000 fixed to 0198 * 0 descr writeback size 32 bytes199 * 0(1) descr chain end interrupt enable200 * 0(1) descr status writeback enable */201 202/* to set RX_DMA_EN */203#define SPIDER_NET_DMA_RX_VALUE 0x80000000204#define SPIDER_NET_DMA_RX_FEND_VALUE 0x00030003205/* to set TX_DMA_EN */206#define SPIDER_NET_TX_DMA_EN 0x80000000207#define SPIDER_NET_GDTBSTA 0x00000300208#define SPIDER_NET_GDTDCEIDIS 0x00000002209#define SPIDER_NET_DMA_TX_VALUE SPIDER_NET_TX_DMA_EN | \210 SPIDER_NET_GDTDCEIDIS | \211 SPIDER_NET_GDTBSTA212 213#define SPIDER_NET_DMA_TX_FEND_VALUE 0x00030003214 215/* SPIDER_NET_UA_DESCR_VALUE is OR'ed with the unicast address */216#define SPIDER_NET_UA_DESCR_VALUE 0x00080000217#define SPIDER_NET_PROMISC_VALUE 0x00080000218#define SPIDER_NET_NONPROMISC_VALUE 0x00000000219 220#define SPIDER_NET_DMASEL_VALUE 0x00000001221 222#define SPIDER_NET_ECMODE_VALUE 0x00000000223 224#define SPIDER_NET_CKRCTRL_RUN_VALUE 0x1fff010f225#define SPIDER_NET_CKRCTRL_STOP_VALUE 0x0000010f226 227#define SPIDER_NET_SBIMSTATE_VALUE 0x00000000228#define SPIDER_NET_SBTMSTATE_VALUE 0x00000000229 230/* SPIDER_NET_GHIINT0STS bits, in reverse order so that they can be used231 * with 1 << SPIDER_NET_... */232enum spider_net_int0_status {233 SPIDER_NET_GPHYINT = 0,234 SPIDER_NET_GMAC2INT,235 SPIDER_NET_GMAC1INT,236 SPIDER_NET_GIPSINT,237 SPIDER_NET_GFIFOINT,238 SPIDER_NET_GDMACINT,239 SPIDER_NET_GSYSINT,240 SPIDER_NET_GPWOPCMPINT,241 SPIDER_NET_GPROPCMPINT,242 SPIDER_NET_GPWFFINT,243 SPIDER_NET_GRMDADRINT,244 SPIDER_NET_GRMARPINT,245 SPIDER_NET_GRMMPINT,246 SPIDER_NET_GDTDEN0INT,247 SPIDER_NET_GDDDEN0INT,248 SPIDER_NET_GDCDEN0INT,249 SPIDER_NET_GDBDEN0INT,250 SPIDER_NET_GDADEN0INT,251 SPIDER_NET_GDTFDCINT,252 SPIDER_NET_GDDFDCINT,253 SPIDER_NET_GDCFDCINT,254 SPIDER_NET_GDBFDCINT,255 SPIDER_NET_GDAFDCINT,256 SPIDER_NET_GTTEDINT,257 SPIDER_NET_GDTDCEINT,258 SPIDER_NET_GRFDNMINT,259 SPIDER_NET_GRFCNMINT,260 SPIDER_NET_GRFBNMINT,261 SPIDER_NET_GRFANMINT,262 SPIDER_NET_GRFNMINT,263 SPIDER_NET_G1TMCNTINT,264 SPIDER_NET_GFREECNTINT265};266/* GHIINT1STS bits */267enum spider_net_int1_status {268 SPIDER_NET_GTMFLLINT = 0,269 SPIDER_NET_GRMFLLINT,270 SPIDER_NET_GTMSHTINT,271 SPIDER_NET_GDTINVDINT,272 SPIDER_NET_GRFDFLLINT,273 SPIDER_NET_GDDDCEINT,274 SPIDER_NET_GDDINVDINT,275 SPIDER_NET_GRFCFLLINT,276 SPIDER_NET_GDCDCEINT,277 SPIDER_NET_GDCINVDINT,278 SPIDER_NET_GRFBFLLINT,279 SPIDER_NET_GDBDCEINT,280 SPIDER_NET_GDBINVDINT,281 SPIDER_NET_GRFAFLLINT,282 SPIDER_NET_GDADCEINT,283 SPIDER_NET_GDAINVDINT,284 SPIDER_NET_GDTRSERINT,285 SPIDER_NET_GDDRSERINT,286 SPIDER_NET_GDCRSERINT,287 SPIDER_NET_GDBRSERINT,288 SPIDER_NET_GDARSERINT,289 SPIDER_NET_GDSERINT,290 SPIDER_NET_GDTPTERINT,291 SPIDER_NET_GDDPTERINT,292 SPIDER_NET_GDCPTERINT,293 SPIDER_NET_GDBPTERINT,294 SPIDER_NET_GDAPTERINT295};296/* GHIINT2STS bits */297enum spider_net_int2_status {298 SPIDER_NET_GPROPERINT = 0,299 SPIDER_NET_GMCTCRSNGINT,300 SPIDER_NET_GMCTLCOLINT,301 SPIDER_NET_GMCTTMOTINT,302 SPIDER_NET_GMCRCAERINT,303 SPIDER_NET_GMCRCALERINT,304 SPIDER_NET_GMCRALNERINT,305 SPIDER_NET_GMCROVRINT,306 SPIDER_NET_GMCRRNTINT,307 SPIDER_NET_GMCRRXERINT,308 SPIDER_NET_GTITCSERINT,309 SPIDER_NET_GTIFMTERINT,310 SPIDER_NET_GTIPKTRVKINT,311 SPIDER_NET_GTISPINGINT,312 SPIDER_NET_GTISADNGINT,313 SPIDER_NET_GTISPDNGINT,314 SPIDER_NET_GRIFMTERINT,315 SPIDER_NET_GRIPKTRVKINT,316 SPIDER_NET_GRISPINGINT,317 SPIDER_NET_GRISADNGINT,318 SPIDER_NET_GRISPDNGINT319};320 321#define SPIDER_NET_TXINT (1 << SPIDER_NET_GDTFDCINT)322 323/* We rely on flagged descriptor interrupts */324#define SPIDER_NET_RXINT ( (1 << SPIDER_NET_GDAFDCINT) )325 326#define SPIDER_NET_LINKINT ( 1 << SPIDER_NET_GMAC2INT )327 328#define SPIDER_NET_ERRINT ( 0xffffffff & \329 (~SPIDER_NET_TXINT) & \330 (~SPIDER_NET_RXINT) & \331 (~SPIDER_NET_LINKINT) )332 333#define SPIDER_NET_GPREXEC 0x80000000334#define SPIDER_NET_GPRDAT_MASK 0x0000ffff335 336#define SPIDER_NET_DMAC_NOINTR_COMPLETE 0x00800000337#define SPIDER_NET_DMAC_TXFRMTL 0x00040000338#define SPIDER_NET_DMAC_TCP 0x00020000339#define SPIDER_NET_DMAC_UDP 0x00030000340#define SPIDER_NET_TXDCEST 0x08000000341 342#define SPIDER_NET_DESCR_RXFDIS 0x00000001343#define SPIDER_NET_DESCR_RXDCEIS 0x00000002344#define SPIDER_NET_DESCR_RXDEN0IS 0x00000004345#define SPIDER_NET_DESCR_RXINVDIS 0x00000008346#define SPIDER_NET_DESCR_RXRERRIS 0x00000010347#define SPIDER_NET_DESCR_RXFDCIMS 0x00000100348#define SPIDER_NET_DESCR_RXDCEIMS 0x00000200349#define SPIDER_NET_DESCR_RXDEN0IMS 0x00000400350#define SPIDER_NET_DESCR_RXINVDIMS 0x00000800351#define SPIDER_NET_DESCR_RXRERRMIS 0x00001000352#define SPIDER_NET_DESCR_UNUSED 0x077fe0e0353 354#define SPIDER_NET_DESCR_IND_PROC_MASK 0xF0000000355#define SPIDER_NET_DESCR_COMPLETE 0x00000000 /* used in rx and tx */356#define SPIDER_NET_DESCR_RESPONSE_ERROR 0x10000000 /* used in rx and tx */357#define SPIDER_NET_DESCR_PROTECTION_ERROR 0x20000000 /* used in rx and tx */358#define SPIDER_NET_DESCR_FRAME_END 0x40000000 /* used in rx */359#define SPIDER_NET_DESCR_FORCE_END 0x50000000 /* used in rx and tx */360#define SPIDER_NET_DESCR_CARDOWNED 0xA0000000 /* used in rx and tx */361#define SPIDER_NET_DESCR_NOT_IN_USE 0xF0000000362#define SPIDER_NET_DESCR_TXDESFLG 0x00800000363 364#define SPIDER_NET_DESCR_BAD_STATUS (SPIDER_NET_DESCR_RXDEN0IS | \365 SPIDER_NET_DESCR_RXRERRIS | \366 SPIDER_NET_DESCR_RXDEN0IMS | \367 SPIDER_NET_DESCR_RXINVDIMS | \368 SPIDER_NET_DESCR_RXRERRMIS | \369 SPIDER_NET_DESCR_UNUSED)370 371/* Descriptor, as defined by the hardware */372struct spider_net_hw_descr {373 u32 buf_addr;374 u32 buf_size;375 u32 next_descr_addr;376 u32 dmac_cmd_status;377 u32 result_size;378 u32 valid_size; /* all zeroes for tx */379 u32 data_status;380 u32 data_error; /* all zeroes for tx */381} __attribute__((aligned(32)));382 383struct spider_net_descr {384 struct spider_net_hw_descr *hwdescr;385 struct sk_buff *skb;386 u32 bus_addr;387 struct spider_net_descr *next;388 struct spider_net_descr *prev;389};390 391struct spider_net_descr_chain {392 spinlock_t lock;393 struct spider_net_descr *head;394 struct spider_net_descr *tail;395 struct spider_net_descr *ring;396 int num_desc;397 struct spider_net_hw_descr *hwring;398 dma_addr_t dma_addr;399};400 401/* descriptor data_status bits */402#define SPIDER_NET_RX_IPCHK 29403#define SPIDER_NET_RX_TCPCHK 28404#define SPIDER_NET_VLAN_PACKET 21405#define SPIDER_NET_DATA_STATUS_CKSUM_MASK ( (1 << SPIDER_NET_RX_IPCHK) | \406 (1 << SPIDER_NET_RX_TCPCHK) )407 408/* descriptor data_error bits */409#define SPIDER_NET_RX_IPCHKERR 27410#define SPIDER_NET_RX_RXTCPCHKERR 28411 412#define SPIDER_NET_DATA_ERR_CKSUM_MASK (1 << SPIDER_NET_RX_IPCHKERR)413 414/* the cases we don't pass the packet to the stack.415 * 701b8000 would be correct, but every packets gets that flag */416#define SPIDER_NET_DESTROY_RX_FLAGS 0x700b8000417 418#define SPIDER_NET_DEFAULT_MSG ( NETIF_MSG_DRV | \419 NETIF_MSG_PROBE | \420 NETIF_MSG_LINK | \421 NETIF_MSG_TIMER | \422 NETIF_MSG_IFDOWN | \423 NETIF_MSG_IFUP | \424 NETIF_MSG_RX_ERR | \425 NETIF_MSG_TX_ERR | \426 NETIF_MSG_TX_QUEUED | \427 NETIF_MSG_INTR | \428 NETIF_MSG_TX_DONE | \429 NETIF_MSG_RX_STATUS | \430 NETIF_MSG_PKTDATA | \431 NETIF_MSG_HW | \432 NETIF_MSG_WOL )433 434struct spider_net_extra_stats {435 unsigned long rx_desc_error;436 unsigned long tx_timeouts;437 unsigned long alloc_rx_skb_error;438 unsigned long rx_iommu_map_error;439 unsigned long tx_iommu_map_error;440 unsigned long rx_desc_unk_state;441};442 443struct spider_net_card {444 struct net_device *netdev;445 struct pci_dev *pdev;446 struct mii_phy phy;447 448 struct napi_struct napi;449 450 int medium;451 452 void __iomem *regs;453 454 struct spider_net_descr_chain tx_chain;455 struct spider_net_descr_chain rx_chain;456 struct spider_net_descr *low_watermark;457 458 int aneg_count;459 struct timer_list aneg_timer;460 struct timer_list tx_timer;461 struct work_struct tx_timeout_task;462 atomic_t tx_timeout_task_counter;463 wait_queue_head_t waitq;464 int num_rx_ints;465 int ignore_rx_ramfull;466 467 /* for ethtool */468 int msg_enable;469 struct spider_net_extra_stats spider_stats;470 471 /* Must be last item in struct */472 struct spider_net_descr darray[];473};474 475#endif476