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1/* SPDX-License-Identifier: GPL-2.0-or-later */2/*3 * (C) Copyright 2005 Tundra Semiconductor Corp.4 * Kong Lai, <kong.lai@tundra.com).5 *6 * See file CREDITS for list of people who contributed to this7 * project.8 */9 10/*11 * net/tsi108_eth.h - definitions for Tsi108 GIGE network controller.12 */13 14#ifndef __TSI108_ETH_H15#define __TSI108_ETH_H16 17#include <linux/types.h>18 19#define TSI_WRITE(offset, val) \20 out_be32((data->regs + (offset)), val)21 22#define TSI_READ(offset) \23 in_be32((data->regs + (offset)))24 25#define TSI_WRITE_PHY(offset, val) \26 out_be32((data->phyregs + (offset)), val)27 28#define TSI_READ_PHY(offset) \29 in_be32((data->phyregs + (offset)))30 31/*32 * TSI108 GIGE port registers33 */34 35#define TSI108_ETH_PORT_NUM 236#define TSI108_PBM_PORT 237#define TSI108_SDRAM_PORT 438 39#define TSI108_MAC_CFG1 (0x000)40#define TSI108_MAC_CFG1_SOFTRST (1 << 31)41#define TSI108_MAC_CFG1_LOOPBACK (1 << 8)42#define TSI108_MAC_CFG1_RXEN (1 << 2)43#define TSI108_MAC_CFG1_TXEN (1 << 0)44 45#define TSI108_MAC_CFG2 (0x004)46#define TSI108_MAC_CFG2_DFLT_PREAMBLE (7 << 12)47#define TSI108_MAC_CFG2_IFACE_MASK (3 << 8)48#define TSI108_MAC_CFG2_NOGIG (1 << 8)49#define TSI108_MAC_CFG2_GIG (2 << 8)50#define TSI108_MAC_CFG2_PADCRC (1 << 2)51#define TSI108_MAC_CFG2_FULLDUPLEX (1 << 0)52 53#define TSI108_MAC_MII_MGMT_CFG (0x020)54#define TSI108_MAC_MII_MGMT_CLK (7 << 0)55#define TSI108_MAC_MII_MGMT_RST (1 << 31)56 57#define TSI108_MAC_MII_CMD (0x024)58#define TSI108_MAC_MII_CMD_READ (1 << 0)59 60#define TSI108_MAC_MII_ADDR (0x028)61#define TSI108_MAC_MII_ADDR_REG 062#define TSI108_MAC_MII_ADDR_PHY 863 64#define TSI108_MAC_MII_DATAOUT (0x02c)65#define TSI108_MAC_MII_DATAIN (0x030)66 67#define TSI108_MAC_MII_IND (0x034)68#define TSI108_MAC_MII_IND_NOTVALID (1 << 2)69#define TSI108_MAC_MII_IND_SCANNING (1 << 1)70#define TSI108_MAC_MII_IND_BUSY (1 << 0)71 72#define TSI108_MAC_IFCTRL (0x038)73#define TSI108_MAC_IFCTRL_PHYMODE (1 << 24)74 75#define TSI108_MAC_ADDR1 (0x040)76#define TSI108_MAC_ADDR2 (0x044)77 78#define TSI108_STAT_RXBYTES (0x06c)79#define TSI108_STAT_RXBYTES_CARRY (1 << 24)80 81#define TSI108_STAT_RXPKTS (0x070)82#define TSI108_STAT_RXPKTS_CARRY (1 << 18)83 84#define TSI108_STAT_RXFCS (0x074)85#define TSI108_STAT_RXFCS_CARRY (1 << 12)86 87#define TSI108_STAT_RXMCAST (0x078)88#define TSI108_STAT_RXMCAST_CARRY (1 << 18)89 90#define TSI108_STAT_RXALIGN (0x08c)91#define TSI108_STAT_RXALIGN_CARRY (1 << 12)92 93#define TSI108_STAT_RXLENGTH (0x090)94#define TSI108_STAT_RXLENGTH_CARRY (1 << 12)95 96#define TSI108_STAT_RXRUNT (0x09c)97#define TSI108_STAT_RXRUNT_CARRY (1 << 12)98 99#define TSI108_STAT_RXJUMBO (0x0a0)100#define TSI108_STAT_RXJUMBO_CARRY (1 << 12)101 102#define TSI108_STAT_RXFRAG (0x0a4)103#define TSI108_STAT_RXFRAG_CARRY (1 << 12)104 105#define TSI108_STAT_RXJABBER (0x0a8)106#define TSI108_STAT_RXJABBER_CARRY (1 << 12)107 108#define TSI108_STAT_RXDROP (0x0ac)109#define TSI108_STAT_RXDROP_CARRY (1 << 12)110 111#define TSI108_STAT_TXBYTES (0x0b0)112#define TSI108_STAT_TXBYTES_CARRY (1 << 24)113 114#define TSI108_STAT_TXPKTS (0x0b4)115#define TSI108_STAT_TXPKTS_CARRY (1 << 18)116 117#define TSI108_STAT_TXEXDEF (0x0c8)118#define TSI108_STAT_TXEXDEF_CARRY (1 << 12)119 120#define TSI108_STAT_TXEXCOL (0x0d8)121#define TSI108_STAT_TXEXCOL_CARRY (1 << 12)122 123#define TSI108_STAT_TXTCOL (0x0dc)124#define TSI108_STAT_TXTCOL_CARRY (1 << 13)125 126#define TSI108_STAT_TXPAUSEDROP (0x0e4)127#define TSI108_STAT_TXPAUSEDROP_CARRY (1 << 12)128 129#define TSI108_STAT_CARRY1 (0x100)130#define TSI108_STAT_CARRY1_RXBYTES (1 << 16)131#define TSI108_STAT_CARRY1_RXPKTS (1 << 15)132#define TSI108_STAT_CARRY1_RXFCS (1 << 14)133#define TSI108_STAT_CARRY1_RXMCAST (1 << 13)134#define TSI108_STAT_CARRY1_RXALIGN (1 << 8)135#define TSI108_STAT_CARRY1_RXLENGTH (1 << 7)136#define TSI108_STAT_CARRY1_RXRUNT (1 << 4)137#define TSI108_STAT_CARRY1_RXJUMBO (1 << 3)138#define TSI108_STAT_CARRY1_RXFRAG (1 << 2)139#define TSI108_STAT_CARRY1_RXJABBER (1 << 1)140#define TSI108_STAT_CARRY1_RXDROP (1 << 0)141 142#define TSI108_STAT_CARRY2 (0x104)143#define TSI108_STAT_CARRY2_TXBYTES (1 << 13)144#define TSI108_STAT_CARRY2_TXPKTS (1 << 12)145#define TSI108_STAT_CARRY2_TXEXDEF (1 << 7)146#define TSI108_STAT_CARRY2_TXEXCOL (1 << 3)147#define TSI108_STAT_CARRY2_TXTCOL (1 << 2)148#define TSI108_STAT_CARRY2_TXPAUSE (1 << 0)149 150#define TSI108_STAT_CARRYMASK1 (0x108)151#define TSI108_STAT_CARRYMASK2 (0x10c)152 153#define TSI108_EC_PORTCTRL (0x200)154#define TSI108_EC_PORTCTRL_STATRST (1 << 31)155#define TSI108_EC_PORTCTRL_STATEN (1 << 28)156#define TSI108_EC_PORTCTRL_NOGIG (1 << 18)157#define TSI108_EC_PORTCTRL_HALFDUPLEX (1 << 16)158 159#define TSI108_EC_INTSTAT (0x204)160#define TSI108_EC_INTMASK (0x208)161 162#define TSI108_INT_ANY (1 << 31)163#define TSI108_INT_SFN (1 << 30)164#define TSI108_INT_RXIDLE (1 << 29)165#define TSI108_INT_RXABORT (1 << 28)166#define TSI108_INT_RXERROR (1 << 27)167#define TSI108_INT_RXOVERRUN (1 << 26)168#define TSI108_INT_RXTHRESH (1 << 25)169#define TSI108_INT_RXWAIT (1 << 24)170#define TSI108_INT_RXQUEUE0 (1 << 16)171#define TSI108_INT_STATCARRY (1 << 15)172#define TSI108_INT_TXIDLE (1 << 13)173#define TSI108_INT_TXABORT (1 << 12)174#define TSI108_INT_TXERROR (1 << 11)175#define TSI108_INT_TXUNDERRUN (1 << 10)176#define TSI108_INT_TXTHRESH (1 << 9)177#define TSI108_INT_TXWAIT (1 << 8)178#define TSI108_INT_TXQUEUE0 (1 << 0)179 180#define TSI108_EC_TXCFG (0x220)181#define TSI108_EC_TXCFG_RST (1 << 31)182 183#define TSI108_EC_TXCTRL (0x224)184#define TSI108_EC_TXCTRL_IDLEINT (1 << 31)185#define TSI108_EC_TXCTRL_ABORT (1 << 30)186#define TSI108_EC_TXCTRL_GO (1 << 15)187#define TSI108_EC_TXCTRL_QUEUE0 (1 << 0)188 189#define TSI108_EC_TXSTAT (0x228)190#define TSI108_EC_TXSTAT_ACTIVE (1 << 15)191#define TSI108_EC_TXSTAT_QUEUE0 (1 << 0)192 193#define TSI108_EC_TXESTAT (0x22c)194#define TSI108_EC_TXESTAT_Q0_ERR (1 << 24)195#define TSI108_EC_TXESTAT_Q0_DESCINT (1 << 16)196#define TSI108_EC_TXESTAT_Q0_EOF (1 << 8)197#define TSI108_EC_TXESTAT_Q0_EOQ (1 << 0)198 199#define TSI108_EC_TXERR (0x278)200 201#define TSI108_EC_TXQ_CFG (0x280)202#define TSI108_EC_TXQ_CFG_DESC_INT (1 << 20)203#define TSI108_EC_TXQ_CFG_EOQ_OWN_INT (1 << 19)204#define TSI108_EC_TXQ_CFG_WSWP (1 << 11)205#define TSI108_EC_TXQ_CFG_BSWP (1 << 10)206#define TSI108_EC_TXQ_CFG_SFNPORT 0207 208#define TSI108_EC_TXQ_BUFCFG (0x284)209#define TSI108_EC_TXQ_BUFCFG_BURST8 (0 << 8)210#define TSI108_EC_TXQ_BUFCFG_BURST32 (1 << 8)211#define TSI108_EC_TXQ_BUFCFG_BURST128 (2 << 8)212#define TSI108_EC_TXQ_BUFCFG_BURST256 (3 << 8)213#define TSI108_EC_TXQ_BUFCFG_WSWP (1 << 11)214#define TSI108_EC_TXQ_BUFCFG_BSWP (1 << 10)215#define TSI108_EC_TXQ_BUFCFG_SFNPORT 0216 217#define TSI108_EC_TXQ_PTRLOW (0x288)218 219#define TSI108_EC_TXQ_PTRHIGH (0x28c)220#define TSI108_EC_TXQ_PTRHIGH_VALID (1 << 31)221 222#define TSI108_EC_TXTHRESH (0x230)223#define TSI108_EC_TXTHRESH_STARTFILL 0224#define TSI108_EC_TXTHRESH_STOPFILL 16225 226#define TSI108_EC_RXCFG (0x320)227#define TSI108_EC_RXCFG_RST (1 << 31)228 229#define TSI108_EC_RXSTAT (0x328)230#define TSI108_EC_RXSTAT_ACTIVE (1 << 15)231#define TSI108_EC_RXSTAT_QUEUE0 (1 << 0)232 233#define TSI108_EC_RXESTAT (0x32c)234#define TSI108_EC_RXESTAT_Q0_ERR (1 << 24)235#define TSI108_EC_RXESTAT_Q0_DESCINT (1 << 16)236#define TSI108_EC_RXESTAT_Q0_EOF (1 << 8)237#define TSI108_EC_RXESTAT_Q0_EOQ (1 << 0)238 239#define TSI108_EC_HASHADDR (0x360)240#define TSI108_EC_HASHADDR_AUTOINC (1 << 31)241#define TSI108_EC_HASHADDR_DO1STREAD (1 << 30)242#define TSI108_EC_HASHADDR_UNICAST (0 << 4)243#define TSI108_EC_HASHADDR_MCAST (1 << 4)244 245#define TSI108_EC_HASHDATA (0x364)246 247#define TSI108_EC_RXQ_PTRLOW (0x388)248 249#define TSI108_EC_RXQ_PTRHIGH (0x38c)250#define TSI108_EC_RXQ_PTRHIGH_VALID (1 << 31)251 252/* Station Enable -- accept packets destined for us */253#define TSI108_EC_RXCFG_SE (1 << 13)254/* Unicast Frame Enable -- for packets not destined for us */255#define TSI108_EC_RXCFG_UFE (1 << 12)256/* Multicast Frame Enable */257#define TSI108_EC_RXCFG_MFE (1 << 11)258/* Broadcast Frame Enable */259#define TSI108_EC_RXCFG_BFE (1 << 10)260#define TSI108_EC_RXCFG_UC_HASH (1 << 9)261#define TSI108_EC_RXCFG_MC_HASH (1 << 8)262 263#define TSI108_EC_RXQ_CFG (0x380)264#define TSI108_EC_RXQ_CFG_DESC_INT (1 << 20)265#define TSI108_EC_RXQ_CFG_EOQ_OWN_INT (1 << 19)266#define TSI108_EC_RXQ_CFG_WSWP (1 << 11)267#define TSI108_EC_RXQ_CFG_BSWP (1 << 10)268#define TSI108_EC_RXQ_CFG_SFNPORT 0269 270#define TSI108_EC_RXQ_BUFCFG (0x384)271#define TSI108_EC_RXQ_BUFCFG_BURST8 (0 << 8)272#define TSI108_EC_RXQ_BUFCFG_BURST32 (1 << 8)273#define TSI108_EC_RXQ_BUFCFG_BURST128 (2 << 8)274#define TSI108_EC_RXQ_BUFCFG_BURST256 (3 << 8)275#define TSI108_EC_RXQ_BUFCFG_WSWP (1 << 11)276#define TSI108_EC_RXQ_BUFCFG_BSWP (1 << 10)277#define TSI108_EC_RXQ_BUFCFG_SFNPORT 0278 279#define TSI108_EC_RXCTRL (0x324)280#define TSI108_EC_RXCTRL_ABORT (1 << 30)281#define TSI108_EC_RXCTRL_GO (1 << 15)282#define TSI108_EC_RXCTRL_QUEUE0 (1 << 0)283 284#define TSI108_EC_RXERR (0x378)285 286#define TSI108_TX_EOF (1 << 0) /* End of frame; last fragment of packet */287#define TSI108_TX_SOF (1 << 1) /* Start of frame; first frag. of packet */288#define TSI108_TX_VLAN (1 << 2) /* Per-frame VLAN: enables VLAN override */289#define TSI108_TX_HUGE (1 << 3) /* Huge frame enable */290#define TSI108_TX_PAD (1 << 4) /* Pad the packet if too short */291#define TSI108_TX_CRC (1 << 5) /* Generate CRC for this packet */292#define TSI108_TX_INT (1 << 14) /* Generate an IRQ after frag. processed */293#define TSI108_TX_RETRY (0xf << 16) /* 4 bit field indicating num. of retries */294#define TSI108_TX_COL (1 << 20) /* Set if a collision occurred */295#define TSI108_TX_LCOL (1 << 24) /* Set if a late collision occurred */296#define TSI108_TX_UNDER (1 << 25) /* Set if a FIFO underrun occurred */297#define TSI108_TX_RLIM (1 << 26) /* Set if the retry limit was reached */298#define TSI108_TX_OK (1 << 30) /* Set if the frame TX was successful */299#define TSI108_TX_OWN (1 << 31) /* Set if the device owns the descriptor */300 301/* Note: the descriptor layouts assume big-endian byte order. */302typedef struct {303 u32 buf0;304 u32 buf1; /* Base address of buffer */305 u32 next0; /* Address of next descriptor, if any */306 u32 next1;307 u16 vlan; /* VLAN, if override enabled for this packet */308 u16 len; /* Length of buffer in bytes */309 u32 misc; /* See TSI108_TX_* above */310 u32 reserved0; /*reserved0 and reserved1 are added to make the desc */311 u32 reserved1; /* 32-byte aligned */312} __attribute__ ((aligned(32))) tx_desc;313 314#define TSI108_RX_EOF (1 << 0) /* End of frame; last fragment of packet */315#define TSI108_RX_SOF (1 << 1) /* Start of frame; first frag. of packet */316#define TSI108_RX_VLAN (1 << 2) /* Set on SOF if packet has a VLAN */317#define TSI108_RX_FTYPE (1 << 3) /* Length/Type field is type, not length */318#define TSI108_RX_RUNT (1 << 4)/* Packet is less than minimum size */319#define TSI108_RX_HASH (1 << 7)/* Hash table match */320#define TSI108_RX_BAD (1 << 8) /* Bad frame */321#define TSI108_RX_OVER (1 << 9) /* FIFO overrun occurred */322#define TSI108_RX_TRUNC (1 << 11) /* Packet truncated due to excess length */323#define TSI108_RX_CRC (1 << 12) /* Packet had a CRC error */324#define TSI108_RX_INT (1 << 13) /* Generate an IRQ after frag. processed */325#define TSI108_RX_OWN (1 << 15) /* Set if the device owns the descriptor */326 327#define TSI108_RX_SKB_SIZE 1536 /* The RX skb length */328 329typedef struct {330 u32 buf0; /* Base address of buffer */331 u32 buf1; /* Base address of buffer */332 u32 next0; /* Address of next descriptor, if any */333 u32 next1; /* Address of next descriptor, if any */334 u16 vlan; /* VLAN of received packet, first frag only */335 u16 len; /* Length of received fragment in bytes */336 u16 blen; /* Length of buffer in bytes */337 u16 misc; /* See TSI108_RX_* above */338 u32 reserved0; /* reserved0 and reserved1 are added to make the desc */339 u32 reserved1; /* 32-byte aligned */340} __attribute__ ((aligned(32))) rx_desc;341 342#endif /* __TSI108_ETH_H */343