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1// SPDX-License-Identifier: GPL-2.02/* Copyright (c) 2015 - 2023 Beijing WangXun Technology Co., Ltd. */3 4#include <linux/gpio/machine.h>5#include <linux/gpio/driver.h>6#include <linux/gpio/property.h>7#include <linux/clk-provider.h>8#include <linux/clkdev.h>9#include <linux/i2c.h>10#include <linux/pci.h>11#include <linux/platform_device.h>12#include <linux/regmap.h>13#include <linux/pcs/pcs-xpcs.h>14#include <linux/phylink.h>15 16#include "../libwx/wx_type.h"17#include "../libwx/wx_lib.h"18#include "../libwx/wx_hw.h"19#include "txgbe_type.h"20#include "txgbe_phy.h"21#include "txgbe_hw.h"22 23static int txgbe_swnodes_register(struct txgbe *txgbe)24{25 struct txgbe_nodes *nodes = &txgbe->nodes;26 struct pci_dev *pdev = txgbe->wx->pdev;27 struct software_node *swnodes;28 u32 id;29 30 id = pci_dev_id(pdev);31 32 snprintf(nodes->gpio_name, sizeof(nodes->gpio_name), "txgbe_gpio-%x", id);33 snprintf(nodes->i2c_name, sizeof(nodes->i2c_name), "txgbe_i2c-%x", id);34 snprintf(nodes->sfp_name, sizeof(nodes->sfp_name), "txgbe_sfp-%x", id);35 snprintf(nodes->phylink_name, sizeof(nodes->phylink_name), "txgbe_phylink-%x", id);36 37 swnodes = nodes->swnodes;38 39 /* GPIO 0: tx fault40 * GPIO 1: tx disable41 * GPIO 2: sfp module absent42 * GPIO 3: rx signal lost43 * GPIO 4: rate select, 1G(0) 10G(1)44 * GPIO 5: rate select, 1G(0) 10G(1)45 */46 nodes->gpio_props[0] = PROPERTY_ENTRY_STRING("pinctrl-names", "default");47 swnodes[SWNODE_GPIO] = NODE_PROP(nodes->gpio_name, nodes->gpio_props);48 nodes->gpio0_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_GPIO], 0, GPIO_ACTIVE_HIGH);49 nodes->gpio1_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_GPIO], 1, GPIO_ACTIVE_HIGH);50 nodes->gpio2_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_GPIO], 2, GPIO_ACTIVE_LOW);51 nodes->gpio3_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_GPIO], 3, GPIO_ACTIVE_HIGH);52 nodes->gpio4_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_GPIO], 4, GPIO_ACTIVE_HIGH);53 nodes->gpio5_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_GPIO], 5, GPIO_ACTIVE_HIGH);54 55 nodes->i2c_props[0] = PROPERTY_ENTRY_STRING("compatible", "snps,designware-i2c");56 nodes->i2c_props[1] = PROPERTY_ENTRY_BOOL("wx,i2c-snps-model");57 nodes->i2c_props[2] = PROPERTY_ENTRY_U32("clock-frequency", I2C_MAX_STANDARD_MODE_FREQ);58 swnodes[SWNODE_I2C] = NODE_PROP(nodes->i2c_name, nodes->i2c_props);59 nodes->i2c_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_I2C]);60 61 nodes->sfp_props[0] = PROPERTY_ENTRY_STRING("compatible", "sff,sfp");62 nodes->sfp_props[1] = PROPERTY_ENTRY_REF_ARRAY("i2c-bus", nodes->i2c_ref);63 nodes->sfp_props[2] = PROPERTY_ENTRY_REF_ARRAY("tx-fault-gpios", nodes->gpio0_ref);64 nodes->sfp_props[3] = PROPERTY_ENTRY_REF_ARRAY("tx-disable-gpios", nodes->gpio1_ref);65 nodes->sfp_props[4] = PROPERTY_ENTRY_REF_ARRAY("mod-def0-gpios", nodes->gpio2_ref);66 nodes->sfp_props[5] = PROPERTY_ENTRY_REF_ARRAY("los-gpios", nodes->gpio3_ref);67 nodes->sfp_props[6] = PROPERTY_ENTRY_REF_ARRAY("rate-select1-gpios", nodes->gpio4_ref);68 nodes->sfp_props[7] = PROPERTY_ENTRY_REF_ARRAY("rate-select0-gpios", nodes->gpio5_ref);69 swnodes[SWNODE_SFP] = NODE_PROP(nodes->sfp_name, nodes->sfp_props);70 nodes->sfp_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_SFP]);71 72 nodes->phylink_props[0] = PROPERTY_ENTRY_STRING("managed", "in-band-status");73 nodes->phylink_props[1] = PROPERTY_ENTRY_REF_ARRAY("sfp", nodes->sfp_ref);74 swnodes[SWNODE_PHYLINK] = NODE_PROP(nodes->phylink_name, nodes->phylink_props);75 76 nodes->group[SWNODE_GPIO] = &swnodes[SWNODE_GPIO];77 nodes->group[SWNODE_I2C] = &swnodes[SWNODE_I2C];78 nodes->group[SWNODE_SFP] = &swnodes[SWNODE_SFP];79 nodes->group[SWNODE_PHYLINK] = &swnodes[SWNODE_PHYLINK];80 81 return software_node_register_node_group(nodes->group);82}83 84static int txgbe_pcs_read(struct mii_bus *bus, int addr, int devnum, int regnum)85{86 struct wx *wx = bus->priv;87 u32 offset, val;88 89 if (addr)90 return -EOPNOTSUPP;91 92 offset = devnum << 16 | regnum;93 94 /* Set the LAN port indicator to IDA_ADDR */95 wr32(wx, TXGBE_XPCS_IDA_ADDR, offset);96 97 /* Read the data from IDA_DATA register */98 val = rd32(wx, TXGBE_XPCS_IDA_DATA);99 100 return (u16)val;101}102 103static int txgbe_pcs_write(struct mii_bus *bus, int addr, int devnum, int regnum, u16 val)104{105 struct wx *wx = bus->priv;106 u32 offset;107 108 if (addr)109 return -EOPNOTSUPP;110 111 offset = devnum << 16 | regnum;112 113 /* Set the LAN port indicator to IDA_ADDR */114 wr32(wx, TXGBE_XPCS_IDA_ADDR, offset);115 116 /* Write the data to IDA_DATA register */117 wr32(wx, TXGBE_XPCS_IDA_DATA, val);118 119 return 0;120}121 122static int txgbe_mdio_pcs_init(struct txgbe *txgbe)123{124 struct mii_bus *mii_bus;125 struct dw_xpcs *xpcs;126 struct pci_dev *pdev;127 struct wx *wx;128 int ret = 0;129 130 wx = txgbe->wx;131 pdev = wx->pdev;132 133 mii_bus = devm_mdiobus_alloc(&pdev->dev);134 if (!mii_bus)135 return -ENOMEM;136 137 mii_bus->name = "txgbe_pcs_mdio_bus";138 mii_bus->read_c45 = &txgbe_pcs_read;139 mii_bus->write_c45 = &txgbe_pcs_write;140 mii_bus->parent = &pdev->dev;141 mii_bus->phy_mask = ~0;142 mii_bus->priv = wx;143 snprintf(mii_bus->id, MII_BUS_ID_SIZE, "txgbe_pcs-%x",144 pci_dev_id(pdev));145 146 ret = devm_mdiobus_register(&pdev->dev, mii_bus);147 if (ret)148 return ret;149 150 xpcs = xpcs_create_mdiodev(mii_bus, 0, PHY_INTERFACE_MODE_10GBASER);151 if (IS_ERR(xpcs))152 return PTR_ERR(xpcs);153 154 txgbe->xpcs = xpcs;155 156 return 0;157}158 159static struct phylink_pcs *txgbe_phylink_mac_select(struct phylink_config *config,160 phy_interface_t interface)161{162 struct wx *wx = phylink_to_wx(config);163 struct txgbe *txgbe = wx->priv;164 165 if (interface == PHY_INTERFACE_MODE_10GBASER)166 return &txgbe->xpcs->pcs;167 168 return NULL;169}170 171static void txgbe_mac_config(struct phylink_config *config, unsigned int mode,172 const struct phylink_link_state *state)173{174}175 176static void txgbe_mac_link_down(struct phylink_config *config,177 unsigned int mode, phy_interface_t interface)178{179 struct wx *wx = phylink_to_wx(config);180 181 wr32m(wx, WX_MAC_TX_CFG, WX_MAC_TX_CFG_TE, 0);182}183 184static void txgbe_mac_link_up(struct phylink_config *config,185 struct phy_device *phy,186 unsigned int mode, phy_interface_t interface,187 int speed, int duplex,188 bool tx_pause, bool rx_pause)189{190 struct wx *wx = phylink_to_wx(config);191 u32 txcfg, wdg;192 193 wx_fc_enable(wx, tx_pause, rx_pause);194 195 txcfg = rd32(wx, WX_MAC_TX_CFG);196 txcfg &= ~WX_MAC_TX_CFG_SPEED_MASK;197 198 switch (speed) {199 case SPEED_10000:200 txcfg |= WX_MAC_TX_CFG_SPEED_10G;201 break;202 case SPEED_1000:203 case SPEED_100:204 case SPEED_10:205 txcfg |= WX_MAC_TX_CFG_SPEED_1G;206 break;207 default:208 break;209 }210 211 wr32(wx, WX_MAC_TX_CFG, txcfg | WX_MAC_TX_CFG_TE);212 213 /* Re configure MAC Rx */214 wr32m(wx, WX_MAC_RX_CFG, WX_MAC_RX_CFG_RE, WX_MAC_RX_CFG_RE);215 wr32(wx, WX_MAC_PKT_FLT, WX_MAC_PKT_FLT_PR);216 wdg = rd32(wx, WX_MAC_WDG_TIMEOUT);217 wr32(wx, WX_MAC_WDG_TIMEOUT, wdg);218}219 220static int txgbe_mac_prepare(struct phylink_config *config, unsigned int mode,221 phy_interface_t interface)222{223 struct wx *wx = phylink_to_wx(config);224 225 wr32m(wx, WX_MAC_TX_CFG, WX_MAC_TX_CFG_TE, 0);226 wr32m(wx, WX_MAC_RX_CFG, WX_MAC_RX_CFG_RE, 0);227 228 return txgbe_disable_sec_tx_path(wx);229}230 231static int txgbe_mac_finish(struct phylink_config *config, unsigned int mode,232 phy_interface_t interface)233{234 struct wx *wx = phylink_to_wx(config);235 236 txgbe_enable_sec_tx_path(wx);237 wr32m(wx, WX_MAC_RX_CFG, WX_MAC_RX_CFG_RE, WX_MAC_RX_CFG_RE);238 239 return 0;240}241 242static const struct phylink_mac_ops txgbe_mac_ops = {243 .mac_select_pcs = txgbe_phylink_mac_select,244 .mac_prepare = txgbe_mac_prepare,245 .mac_finish = txgbe_mac_finish,246 .mac_config = txgbe_mac_config,247 .mac_link_down = txgbe_mac_link_down,248 .mac_link_up = txgbe_mac_link_up,249};250 251static int txgbe_phylink_init(struct txgbe *txgbe)252{253 struct fwnode_handle *fwnode = NULL;254 struct phylink_config *config;255 struct wx *wx = txgbe->wx;256 phy_interface_t phy_mode;257 struct phylink *phylink;258 259 config = &wx->phylink_config;260 config->dev = &wx->netdev->dev;261 config->type = PHYLINK_NETDEV;262 config->mac_capabilities = MAC_10000FD | MAC_1000FD | MAC_100FD |263 MAC_SYM_PAUSE | MAC_ASYM_PAUSE;264 265 if (wx->media_type == sp_media_copper) {266 phy_mode = PHY_INTERFACE_MODE_XAUI;267 __set_bit(PHY_INTERFACE_MODE_XAUI, config->supported_interfaces);268 } else {269 phy_mode = PHY_INTERFACE_MODE_10GBASER;270 fwnode = software_node_fwnode(txgbe->nodes.group[SWNODE_PHYLINK]);271 __set_bit(PHY_INTERFACE_MODE_10GBASER, config->supported_interfaces);272 __set_bit(PHY_INTERFACE_MODE_1000BASEX, config->supported_interfaces);273 __set_bit(PHY_INTERFACE_MODE_SGMII, config->supported_interfaces);274 }275 276 phylink = phylink_create(config, fwnode, phy_mode, &txgbe_mac_ops);277 if (IS_ERR(phylink))278 return PTR_ERR(phylink);279 280 if (wx->phydev) {281 int ret;282 283 ret = phylink_connect_phy(phylink, wx->phydev);284 if (ret) {285 phylink_destroy(phylink);286 return ret;287 }288 }289 290 wx->phylink = phylink;291 292 return 0;293}294 295irqreturn_t txgbe_link_irq_handler(int irq, void *data)296{297 struct txgbe *txgbe = data;298 struct wx *wx = txgbe->wx;299 u32 status;300 bool up;301 302 status = rd32(wx, TXGBE_CFG_PORT_ST);303 up = !!(status & TXGBE_CFG_PORT_ST_LINK_UP);304 305 phylink_pcs_change(&txgbe->xpcs->pcs, up);306 307 return IRQ_HANDLED;308}309 310static int txgbe_gpio_get(struct gpio_chip *chip, unsigned int offset)311{312 struct wx *wx = gpiochip_get_data(chip);313 int val;314 315 val = rd32m(wx, WX_GPIO_EXT, BIT(offset));316 317 return !!(val & BIT(offset));318}319 320static int txgbe_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)321{322 struct wx *wx = gpiochip_get_data(chip);323 u32 val;324 325 val = rd32(wx, WX_GPIO_DDR);326 if (BIT(offset) & val)327 return GPIO_LINE_DIRECTION_OUT;328 329 return GPIO_LINE_DIRECTION_IN;330}331 332static int txgbe_gpio_direction_in(struct gpio_chip *chip, unsigned int offset)333{334 struct wx *wx = gpiochip_get_data(chip);335 unsigned long flags;336 337 raw_spin_lock_irqsave(&wx->gpio_lock, flags);338 wr32m(wx, WX_GPIO_DDR, BIT(offset), 0);339 raw_spin_unlock_irqrestore(&wx->gpio_lock, flags);340 341 return 0;342}343 344static int txgbe_gpio_direction_out(struct gpio_chip *chip, unsigned int offset,345 int val)346{347 struct wx *wx = gpiochip_get_data(chip);348 unsigned long flags;349 u32 set;350 351 set = val ? BIT(offset) : 0;352 353 raw_spin_lock_irqsave(&wx->gpio_lock, flags);354 wr32m(wx, WX_GPIO_DR, BIT(offset), set);355 wr32m(wx, WX_GPIO_DDR, BIT(offset), BIT(offset));356 raw_spin_unlock_irqrestore(&wx->gpio_lock, flags);357 358 return 0;359}360 361static void txgbe_gpio_irq_ack(struct irq_data *d)362{363 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);364 irq_hw_number_t hwirq = irqd_to_hwirq(d);365 struct wx *wx = gpiochip_get_data(gc);366 unsigned long flags;367 368 raw_spin_lock_irqsave(&wx->gpio_lock, flags);369 wr32(wx, WX_GPIO_EOI, BIT(hwirq));370 raw_spin_unlock_irqrestore(&wx->gpio_lock, flags);371}372 373static void txgbe_gpio_irq_mask(struct irq_data *d)374{375 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);376 irq_hw_number_t hwirq = irqd_to_hwirq(d);377 struct wx *wx = gpiochip_get_data(gc);378 unsigned long flags;379 380 gpiochip_disable_irq(gc, hwirq);381 382 raw_spin_lock_irqsave(&wx->gpio_lock, flags);383 wr32m(wx, WX_GPIO_INTMASK, BIT(hwirq), BIT(hwirq));384 raw_spin_unlock_irqrestore(&wx->gpio_lock, flags);385}386 387static void txgbe_gpio_irq_unmask(struct irq_data *d)388{389 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);390 irq_hw_number_t hwirq = irqd_to_hwirq(d);391 struct wx *wx = gpiochip_get_data(gc);392 unsigned long flags;393 394 gpiochip_enable_irq(gc, hwirq);395 396 raw_spin_lock_irqsave(&wx->gpio_lock, flags);397 wr32m(wx, WX_GPIO_INTMASK, BIT(hwirq), 0);398 raw_spin_unlock_irqrestore(&wx->gpio_lock, flags);399}400 401static void txgbe_toggle_trigger(struct gpio_chip *gc, unsigned int offset)402{403 struct wx *wx = gpiochip_get_data(gc);404 u32 pol, val;405 406 pol = rd32(wx, WX_GPIO_POLARITY);407 val = rd32(wx, WX_GPIO_EXT);408 409 if (val & BIT(offset))410 pol &= ~BIT(offset);411 else412 pol |= BIT(offset);413 414 wr32(wx, WX_GPIO_POLARITY, pol);415}416 417static int txgbe_gpio_set_type(struct irq_data *d, unsigned int type)418{419 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);420 irq_hw_number_t hwirq = irqd_to_hwirq(d);421 struct wx *wx = gpiochip_get_data(gc);422 u32 level, polarity, mask;423 unsigned long flags;424 425 mask = BIT(hwirq);426 427 if (type & IRQ_TYPE_LEVEL_MASK) {428 level = 0;429 irq_set_handler_locked(d, handle_level_irq);430 } else {431 level = mask;432 irq_set_handler_locked(d, handle_edge_irq);433 }434 435 if (type == IRQ_TYPE_EDGE_RISING || type == IRQ_TYPE_LEVEL_HIGH)436 polarity = mask;437 else438 polarity = 0;439 440 raw_spin_lock_irqsave(&wx->gpio_lock, flags);441 442 wr32m(wx, WX_GPIO_INTEN, mask, mask);443 wr32m(wx, WX_GPIO_INTTYPE_LEVEL, mask, level);444 if (type == IRQ_TYPE_EDGE_BOTH)445 txgbe_toggle_trigger(gc, hwirq);446 else447 wr32m(wx, WX_GPIO_POLARITY, mask, polarity);448 449 raw_spin_unlock_irqrestore(&wx->gpio_lock, flags);450 451 return 0;452}453 454static const struct irq_chip txgbe_gpio_irq_chip = {455 .name = "txgbe-gpio-irq",456 .irq_ack = txgbe_gpio_irq_ack,457 .irq_mask = txgbe_gpio_irq_mask,458 .irq_unmask = txgbe_gpio_irq_unmask,459 .irq_set_type = txgbe_gpio_set_type,460 .flags = IRQCHIP_IMMUTABLE,461 GPIOCHIP_IRQ_RESOURCE_HELPERS,462};463 464irqreturn_t txgbe_gpio_irq_handler(int irq, void *data)465{466 struct txgbe *txgbe = data;467 struct wx *wx = txgbe->wx;468 irq_hw_number_t hwirq;469 unsigned long gpioirq;470 struct gpio_chip *gc;471 unsigned long flags;472 473 gpioirq = rd32(wx, WX_GPIO_INTSTATUS);474 475 gc = txgbe->gpio;476 for_each_set_bit(hwirq, &gpioirq, gc->ngpio) {477 int gpio = irq_find_mapping(gc->irq.domain, hwirq);478 struct irq_data *d = irq_get_irq_data(gpio);479 u32 irq_type = irq_get_trigger_type(gpio);480 481 txgbe_gpio_irq_ack(d);482 handle_nested_irq(gpio);483 484 if ((irq_type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {485 raw_spin_lock_irqsave(&wx->gpio_lock, flags);486 txgbe_toggle_trigger(gc, hwirq);487 raw_spin_unlock_irqrestore(&wx->gpio_lock, flags);488 }489 }490 491 return IRQ_HANDLED;492}493 494void txgbe_reinit_gpio_intr(struct wx *wx)495{496 struct txgbe *txgbe = wx->priv;497 irq_hw_number_t hwirq;498 unsigned long gpioirq;499 struct gpio_chip *gc;500 unsigned long flags;501 502 /* for gpio interrupt pending before irq enable */503 gpioirq = rd32(wx, WX_GPIO_INTSTATUS);504 505 gc = txgbe->gpio;506 for_each_set_bit(hwirq, &gpioirq, gc->ngpio) {507 int gpio = irq_find_mapping(gc->irq.domain, hwirq);508 struct irq_data *d = irq_get_irq_data(gpio);509 u32 irq_type = irq_get_trigger_type(gpio);510 511 txgbe_gpio_irq_ack(d);512 513 if ((irq_type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {514 raw_spin_lock_irqsave(&wx->gpio_lock, flags);515 txgbe_toggle_trigger(gc, hwirq);516 raw_spin_unlock_irqrestore(&wx->gpio_lock, flags);517 }518 }519}520 521static int txgbe_gpio_init(struct txgbe *txgbe)522{523 struct gpio_irq_chip *girq;524 struct gpio_chip *gc;525 struct device *dev;526 struct wx *wx;527 int ret;528 529 wx = txgbe->wx;530 dev = &wx->pdev->dev;531 532 raw_spin_lock_init(&wx->gpio_lock);533 534 gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL);535 if (!gc)536 return -ENOMEM;537 538 gc->label = devm_kasprintf(dev, GFP_KERNEL, "txgbe_gpio-%x",539 pci_dev_id(wx->pdev));540 if (!gc->label)541 return -ENOMEM;542 543 gc->base = -1;544 gc->ngpio = 6;545 gc->owner = THIS_MODULE;546 gc->parent = dev;547 gc->fwnode = software_node_fwnode(txgbe->nodes.group[SWNODE_GPIO]);548 gc->get = txgbe_gpio_get;549 gc->get_direction = txgbe_gpio_get_direction;550 gc->direction_input = txgbe_gpio_direction_in;551 gc->direction_output = txgbe_gpio_direction_out;552 553 girq = &gc->irq;554 gpio_irq_chip_set_chip(girq, &txgbe_gpio_irq_chip);555 girq->default_type = IRQ_TYPE_NONE;556 girq->handler = handle_bad_irq;557 558 ret = devm_gpiochip_add_data(dev, gc, wx);559 if (ret)560 return ret;561 562 txgbe->gpio = gc;563 564 return 0;565}566 567static int txgbe_clock_register(struct txgbe *txgbe)568{569 struct pci_dev *pdev = txgbe->wx->pdev;570 struct clk_lookup *clock;571 char clk_name[32];572 struct clk *clk;573 574 snprintf(clk_name, sizeof(clk_name), "i2c_designware.%d",575 pci_dev_id(pdev));576 577 clk = clk_register_fixed_rate(NULL, clk_name, NULL, 0, 156250000);578 if (IS_ERR(clk))579 return PTR_ERR(clk);580 581 clock = clkdev_create(clk, NULL, clk_name);582 if (!clock) {583 clk_unregister(clk);584 return -ENOMEM;585 }586 587 txgbe->clk = clk;588 txgbe->clock = clock;589 590 return 0;591}592 593static int txgbe_i2c_read(void *context, unsigned int reg, unsigned int *val)594{595 struct wx *wx = context;596 597 *val = rd32(wx, reg + TXGBE_I2C_BASE);598 599 return 0;600}601 602static int txgbe_i2c_write(void *context, unsigned int reg, unsigned int val)603{604 struct wx *wx = context;605 606 wr32(wx, reg + TXGBE_I2C_BASE, val);607 608 return 0;609}610 611static const struct regmap_config i2c_regmap_config = {612 .reg_bits = 32,613 .val_bits = 32,614 .reg_read = txgbe_i2c_read,615 .reg_write = txgbe_i2c_write,616 .fast_io = true,617};618 619static int txgbe_i2c_register(struct txgbe *txgbe)620{621 struct platform_device_info info = {};622 struct platform_device *i2c_dev;623 struct regmap *i2c_regmap;624 struct pci_dev *pdev;625 struct wx *wx;626 627 wx = txgbe->wx;628 pdev = wx->pdev;629 i2c_regmap = devm_regmap_init(&pdev->dev, NULL, wx, &i2c_regmap_config);630 if (IS_ERR(i2c_regmap)) {631 wx_err(wx, "failed to init I2C regmap\n");632 return PTR_ERR(i2c_regmap);633 }634 635 info.parent = &pdev->dev;636 info.fwnode = software_node_fwnode(txgbe->nodes.group[SWNODE_I2C]);637 info.name = "i2c_designware";638 info.id = pci_dev_id(pdev);639 640 info.res = &DEFINE_RES_IRQ(pdev->irq);641 info.num_res = 1;642 i2c_dev = platform_device_register_full(&info);643 if (IS_ERR(i2c_dev))644 return PTR_ERR(i2c_dev);645 646 txgbe->i2c_dev = i2c_dev;647 648 return 0;649}650 651static int txgbe_sfp_register(struct txgbe *txgbe)652{653 struct pci_dev *pdev = txgbe->wx->pdev;654 struct platform_device_info info = {};655 struct platform_device *sfp_dev;656 657 info.parent = &pdev->dev;658 info.fwnode = software_node_fwnode(txgbe->nodes.group[SWNODE_SFP]);659 info.name = "sfp";660 info.id = pci_dev_id(pdev);661 sfp_dev = platform_device_register_full(&info);662 if (IS_ERR(sfp_dev))663 return PTR_ERR(sfp_dev);664 665 txgbe->sfp_dev = sfp_dev;666 667 return 0;668}669 670static int txgbe_ext_phy_init(struct txgbe *txgbe)671{672 struct phy_device *phydev;673 struct mii_bus *mii_bus;674 struct pci_dev *pdev;675 struct wx *wx;676 int ret = 0;677 678 wx = txgbe->wx;679 pdev = wx->pdev;680 681 mii_bus = devm_mdiobus_alloc(&pdev->dev);682 if (!mii_bus)683 return -ENOMEM;684 685 mii_bus->name = "txgbe_mii_bus";686 mii_bus->read_c45 = &wx_phy_read_reg_mdi_c45;687 mii_bus->write_c45 = &wx_phy_write_reg_mdi_c45;688 mii_bus->parent = &pdev->dev;689 mii_bus->phy_mask = GENMASK(31, 1);690 mii_bus->priv = wx;691 snprintf(mii_bus->id, MII_BUS_ID_SIZE, "txgbe-%x", pci_dev_id(pdev));692 693 ret = devm_mdiobus_register(&pdev->dev, mii_bus);694 if (ret) {695 wx_err(wx, "failed to register MDIO bus: %d\n", ret);696 return ret;697 }698 699 phydev = phy_find_first(mii_bus);700 if (!phydev) {701 wx_err(wx, "no PHY found\n");702 return -ENODEV;703 }704 705 phy_attached_info(phydev);706 707 wx->link = 0;708 wx->speed = 0;709 wx->duplex = 0;710 wx->phydev = phydev;711 712 ret = txgbe_phylink_init(txgbe);713 if (ret) {714 wx_err(wx, "failed to init phylink: %d\n", ret);715 return ret;716 }717 718 return 0;719}720 721int txgbe_init_phy(struct txgbe *txgbe)722{723 struct wx *wx = txgbe->wx;724 int ret;725 726 if (txgbe->wx->media_type == sp_media_copper)727 return txgbe_ext_phy_init(txgbe);728 729 ret = txgbe_swnodes_register(txgbe);730 if (ret) {731 wx_err(wx, "failed to register software nodes\n");732 return ret;733 }734 735 ret = txgbe_mdio_pcs_init(txgbe);736 if (ret) {737 wx_err(wx, "failed to init mdio pcs: %d\n", ret);738 goto err_unregister_swnode;739 }740 741 ret = txgbe_phylink_init(txgbe);742 if (ret) {743 wx_err(wx, "failed to init phylink\n");744 goto err_destroy_xpcs;745 }746 747 ret = txgbe_gpio_init(txgbe);748 if (ret) {749 wx_err(wx, "failed to init gpio\n");750 goto err_destroy_phylink;751 }752 753 ret = txgbe_clock_register(txgbe);754 if (ret) {755 wx_err(wx, "failed to register clock: %d\n", ret);756 goto err_destroy_phylink;757 }758 759 ret = txgbe_i2c_register(txgbe);760 if (ret) {761 wx_err(wx, "failed to init i2c interface: %d\n", ret);762 goto err_unregister_clk;763 }764 765 ret = txgbe_sfp_register(txgbe);766 if (ret) {767 wx_err(wx, "failed to register sfp\n");768 goto err_unregister_i2c;769 }770 771 return 0;772 773err_unregister_i2c:774 platform_device_unregister(txgbe->i2c_dev);775err_unregister_clk:776 clkdev_drop(txgbe->clock);777 clk_unregister(txgbe->clk);778err_destroy_phylink:779 phylink_destroy(wx->phylink);780err_destroy_xpcs:781 xpcs_destroy(txgbe->xpcs);782err_unregister_swnode:783 software_node_unregister_node_group(txgbe->nodes.group);784 785 return ret;786}787 788void txgbe_remove_phy(struct txgbe *txgbe)789{790 if (txgbe->wx->media_type == sp_media_copper) {791 phylink_disconnect_phy(txgbe->wx->phylink);792 phylink_destroy(txgbe->wx->phylink);793 return;794 }795 796 platform_device_unregister(txgbe->sfp_dev);797 platform_device_unregister(txgbe->i2c_dev);798 clkdev_drop(txgbe->clock);799 clk_unregister(txgbe->clk);800 phylink_destroy(txgbe->wx->phylink);801 xpcs_destroy(txgbe->xpcs);802 software_node_unregister_node_group(txgbe->nodes.group);803}804