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1/* SPDX-License-Identifier: GPL-2.0 */2 3#ifndef XILINX_LL_TEMAC_H4#define XILINX_LL_TEMAC_H5 6#include <linux/netdevice.h>7#include <linux/of.h>8#include <linux/platform_device.h>9#include <linux/spinlock.h>10 11#ifdef CONFIG_PPC_DCR12#include <asm/dcr.h>13#include <asm/dcr-regs.h>14#endif15 16/* packet size info */17#define XTE_HDR_SIZE 14 /* size of Ethernet header */18#define XTE_TRL_SIZE 4 /* size of Ethernet trailer (FCS) */19#define XTE_JUMBO_MTU 900020#define XTE_MAX_JUMBO_FRAME_SIZE (XTE_JUMBO_MTU + XTE_HDR_SIZE + XTE_TRL_SIZE)21 22/* Configuration options */23 24/* Accept all incoming packets.25 * This option defaults to disabled (cleared)26 */27#define XTE_OPTION_PROMISC (1 << 0)28/* Jumbo frame support for Tx & Rx.29 * This option defaults to disabled (cleared)30 */31#define XTE_OPTION_JUMBO (1 << 1)32/* VLAN Rx & Tx frame support.33 * This option defaults to disabled (cleared)34 */35#define XTE_OPTION_VLAN (1 << 2)36/* Enable recognition of flow control frames on Rx37 * This option defaults to enabled (set)38 */39#define XTE_OPTION_FLOW_CONTROL (1 << 4)40/* Strip FCS and PAD from incoming frames.41 * Note: PAD from VLAN frames is not stripped.42 * This option defaults to disabled (set)43 */44#define XTE_OPTION_FCS_STRIP (1 << 5)45/* Generate FCS field and add PAD automatically for outgoing frames.46 * This option defaults to enabled (set)47 */48#define XTE_OPTION_FCS_INSERT (1 << 6)49/* Enable Length/Type error checking for incoming frames. When this option is50 * set, the MAC will filter frames that have a mismatched type/length field51 * and if XTE_OPTION_REPORT_RXERR is set, the user is notified when these52 * types of frames are encountered. When this option is cleared, the MAC will53 * allow these types of frames to be received.54 * This option defaults to enabled (set)55 */56#define XTE_OPTION_LENTYPE_ERR (1 << 7)57/* Enable the transmitter.58 * This option defaults to enabled (set)59 */60#define XTE_OPTION_TXEN (1 << 11)61/* Enable the receiver62 * This option defaults to enabled (set)63 */64#define XTE_OPTION_RXEN (1 << 12)65 66/* Default options set when device is initialized or reset */67#define XTE_OPTION_DEFAULTS \68 (XTE_OPTION_TXEN | \69 XTE_OPTION_FLOW_CONTROL | \70 XTE_OPTION_RXEN)71 72/* XPS_LL_TEMAC SDMA registers definition */73 74#define TX_NXTDESC_PTR 0x00 /* r */75#define TX_CURBUF_ADDR 0x01 /* r */76#define TX_CURBUF_LENGTH 0x02 /* r */77#define TX_CURDESC_PTR 0x03 /* rw */78#define TX_TAILDESC_PTR 0x04 /* rw */79#define TX_CHNL_CTRL 0x05 /* rw */80/*81 * 0:7 24:31 IRQTimeout82 * 8:15 16:23 IRQCount83 * 16:20 11:15 Reserved84 * 21 10 085 * 22 9 UseIntOnEnd86 * 23 8 LdIRQCnt87 * 24 7 IRQEn88 * 25:28 3:6 Reserved89 * 29 2 IrqErrEn90 * 30 1 IrqDlyEn91 * 31 0 IrqCoalEn92 */93#define CHNL_CTRL_IRQ_IOE (1 << 9)94#define CHNL_CTRL_IRQ_EN (1 << 7)95#define CHNL_CTRL_IRQ_ERR_EN (1 << 2)96#define CHNL_CTRL_IRQ_DLY_EN (1 << 1)97#define CHNL_CTRL_IRQ_COAL_EN (1 << 0)98#define TX_IRQ_REG 0x06 /* rw */99/*100 * 0:7 24:31 DltTmrValue101 * 8:15 16:23 ClscCntrValue102 * 16:17 14:15 Reserved103 * 18:21 10:13 ClscCnt104 * 22:23 8:9 DlyCnt105 * 24:28 3::7 Reserved106 * 29 2 ErrIrq107 * 30 1 DlyIrq108 * 31 0 CoalIrq109 */110#define TX_CHNL_STS 0x07 /* r */111/*112 * 0:9 22:31 Reserved113 * 10 21 TailPErr114 * 11 20 CmpErr115 * 12 19 AddrErr116 * 13 18 NxtPErr117 * 14 17 CurPErr118 * 15 16 BsyWr119 * 16:23 8:15 Reserved120 * 24 7 Error121 * 25 6 IOE122 * 26 5 SOE123 * 27 4 Cmplt124 * 28 3 SOP125 * 29 2 EOP126 * 30 1 EngBusy127 * 31 0 Reserved128 */129 130#define RX_NXTDESC_PTR 0x08 /* r */131#define RX_CURBUF_ADDR 0x09 /* r */132#define RX_CURBUF_LENGTH 0x0a /* r */133#define RX_CURDESC_PTR 0x0b /* rw */134#define RX_TAILDESC_PTR 0x0c /* rw */135#define RX_CHNL_CTRL 0x0d /* rw */136/*137 * 0:7 24:31 IRQTimeout138 * 8:15 16:23 IRQCount139 * 16:20 11:15 Reserved140 * 21 10 0141 * 22 9 UseIntOnEnd142 * 23 8 LdIRQCnt143 * 24 7 IRQEn144 * 25:28 3:6 Reserved145 * 29 2 IrqErrEn146 * 30 1 IrqDlyEn147 * 31 0 IrqCoalEn148 */149#define RX_IRQ_REG 0x0e /* rw */150#define IRQ_COAL (1 << 0)151#define IRQ_DLY (1 << 1)152#define IRQ_ERR (1 << 2)153#define IRQ_DMAERR (1 << 7) /* this is not documented ??? */154/*155 * 0:7 24:31 DltTmrValue156 * 8:15 16:23 ClscCntrValue157 * 16:17 14:15 Reserved158 * 18:21 10:13 ClscCnt159 * 22:23 8:9 DlyCnt160 * 24:28 3::7 Reserved161 */162#define RX_CHNL_STS 0x0f /* r */163#define CHNL_STS_ENGBUSY (1 << 1)164#define CHNL_STS_EOP (1 << 2)165#define CHNL_STS_SOP (1 << 3)166#define CHNL_STS_CMPLT (1 << 4)167#define CHNL_STS_SOE (1 << 5)168#define CHNL_STS_IOE (1 << 6)169#define CHNL_STS_ERR (1 << 7)170 171#define CHNL_STS_BSYWR (1 << 16)172#define CHNL_STS_CURPERR (1 << 17)173#define CHNL_STS_NXTPERR (1 << 18)174#define CHNL_STS_ADDRERR (1 << 19)175#define CHNL_STS_CMPERR (1 << 20)176#define CHNL_STS_TAILERR (1 << 21)177/*178 * 0:9 22:31 Reserved179 * 10 21 TailPErr180 * 11 20 CmpErr181 * 12 19 AddrErr182 * 13 18 NxtPErr183 * 14 17 CurPErr184 * 15 16 BsyWr185 * 16:23 8:15 Reserved186 * 24 7 Error187 * 25 6 IOE188 * 26 5 SOE189 * 27 4 Cmplt190 * 28 3 SOP191 * 29 2 EOP192 * 30 1 EngBusy193 * 31 0 Reserved194 */195 196#define DMA_CONTROL_REG 0x10 /* rw */197#define DMA_CONTROL_RST (1 << 0)198#define DMA_TAIL_ENABLE (1 << 2)199 200/* XPS_LL_TEMAC direct registers definition */201 202#define XTE_RAF0_OFFSET 0x00203#define RAF0_RST (1 << 0)204#define RAF0_MCSTREJ (1 << 1)205#define RAF0_BCSTREJ (1 << 2)206#define XTE_TPF0_OFFSET 0x04207#define XTE_IFGP0_OFFSET 0x08208#define XTE_ISR0_OFFSET 0x0c209#define ISR0_HARDACSCMPLT (1 << 0)210#define ISR0_AUTONEG (1 << 1)211#define ISR0_RXCMPLT (1 << 2)212#define ISR0_RXREJ (1 << 3)213#define ISR0_RXFIFOOVR (1 << 4)214#define ISR0_TXCMPLT (1 << 5)215#define ISR0_RXDCMLCK (1 << 6)216 217#define XTE_IPR0_OFFSET 0x10218#define XTE_IER0_OFFSET 0x14219 220#define XTE_MSW0_OFFSET 0x20221#define XTE_LSW0_OFFSET 0x24222#define XTE_CTL0_OFFSET 0x28223#define XTE_RDY0_OFFSET 0x2c224 225#define XTE_RSE_MIIM_RR_MASK 0x0002226#define XTE_RSE_MIIM_WR_MASK 0x0004227#define XTE_RSE_CFG_RR_MASK 0x0020228#define XTE_RSE_CFG_WR_MASK 0x0040229#define XTE_RDY0_HARD_ACS_RDY_MASK (0x10000)230 231/* XPS_LL_TEMAC indirect registers offset definition */232 233#define XTE_RXC0_OFFSET 0x00000200 /* Rx configuration word 0 */234#define XTE_RXC1_OFFSET 0x00000240 /* Rx configuration word 1 */235#define XTE_RXC1_RXRST_MASK (1 << 31) /* Receiver reset */236#define XTE_RXC1_RXJMBO_MASK (1 << 30) /* Jumbo frame enable */237#define XTE_RXC1_RXFCS_MASK (1 << 29) /* FCS not stripped */238#define XTE_RXC1_RXEN_MASK (1 << 28) /* Receiver enable */239#define XTE_RXC1_RXVLAN_MASK (1 << 27) /* VLAN enable */240#define XTE_RXC1_RXHD_MASK (1 << 26) /* Half duplex */241#define XTE_RXC1_RXLT_MASK (1 << 25) /* Length/type check disable */242 243#define XTE_TXC_OFFSET 0x00000280 /* Tx configuration */244#define XTE_TXC_TXRST_MASK (1 << 31) /* Transmitter reset */245#define XTE_TXC_TXJMBO_MASK (1 << 30) /* Jumbo frame enable */246#define XTE_TXC_TXFCS_MASK (1 << 29) /* Generate FCS */247#define XTE_TXC_TXEN_MASK (1 << 28) /* Transmitter enable */248#define XTE_TXC_TXVLAN_MASK (1 << 27) /* VLAN enable */249#define XTE_TXC_TXHD_MASK (1 << 26) /* Half duplex */250 251#define XTE_FCC_OFFSET 0x000002C0 /* Flow control config */252#define XTE_FCC_RXFLO_MASK (1 << 29) /* Rx flow control enable */253#define XTE_FCC_TXFLO_MASK (1 << 30) /* Tx flow control enable */254 255#define XTE_EMCFG_OFFSET 0x00000300 /* EMAC configuration */256#define XTE_EMCFG_LINKSPD_MASK 0xC0000000 /* Link speed */257#define XTE_EMCFG_HOSTEN_MASK (1 << 26) /* Host interface enable */258#define XTE_EMCFG_LINKSPD_10 0x00000000 /* 10 Mbit LINKSPD_MASK */259#define XTE_EMCFG_LINKSPD_100 (1 << 30) /* 100 Mbit LINKSPD_MASK */260#define XTE_EMCFG_LINKSPD_1000 (1 << 31) /* 1000 Mbit LINKSPD_MASK */261 262#define XTE_GMIC_OFFSET 0x00000320 /* RGMII/SGMII config */263#define XTE_MC_OFFSET 0x00000340 /* MDIO configuration */264#define XTE_UAW0_OFFSET 0x00000380 /* Unicast address word 0 */265#define XTE_UAW1_OFFSET 0x00000384 /* Unicast address word 1 */266 267#define XTE_MAW0_OFFSET 0x00000388 /* Multicast addr word 0 */268#define XTE_MAW1_OFFSET 0x0000038C /* Multicast addr word 1 */269#define XTE_AFM_OFFSET 0x00000390 /* Promiscuous mode */270#define XTE_AFM_EPPRM_MASK (1 << 31) /* Promiscuous mode enable */271 272/* Interrupt Request status */273#define XTE_TIS_OFFSET 0x000003A0274#define TIS_FRIS (1 << 0)275#define TIS_MRIS (1 << 1)276#define TIS_MWIS (1 << 2)277#define TIS_ARIS (1 << 3)278#define TIS_AWIS (1 << 4)279#define TIS_CRIS (1 << 5)280#define TIS_CWIS (1 << 6)281 282#define XTE_TIE_OFFSET 0x000003A4 /* Interrupt enable */283 284/* MII Management Control register (MGTCR) */285#define XTE_MGTDR_OFFSET 0x000003B0 /* MII data */286#define XTE_MIIMAI_OFFSET 0x000003B4 /* MII control */287 288#define CNTLREG_WRITE_ENABLE_MASK 0x8000289#define CNTLREG_EMAC1SEL_MASK 0x0400290#define CNTLREG_ADDRESSCODE_MASK 0x03ff291 292/* CDMAC descriptor status bit definitions */293 294#define STS_CTRL_APP0_ERR (1 << 31)295#define STS_CTRL_APP0_IRQONEND (1 << 30)296/* undocumented */297#define STS_CTRL_APP0_STOPONEND (1 << 29)298#define STS_CTRL_APP0_CMPLT (1 << 28)299#define STS_CTRL_APP0_SOP (1 << 27)300#define STS_CTRL_APP0_EOP (1 << 26)301#define STS_CTRL_APP0_ENGBUSY (1 << 25)302/* undocumented */303#define STS_CTRL_APP0_ENGRST (1 << 24)304 305#define TX_CONTROL_CALC_CSUM_MASK 1306 307#define MULTICAST_CAM_TABLE_NUM 4308 309/* TEMAC Synthesis features */310#define TEMAC_FEATURE_RX_CSUM (1 << 0)311#define TEMAC_FEATURE_TX_CSUM (1 << 1)312 313/* TX/RX CURDESC_PTR points to first descriptor */314/* TX/RX TAILDESC_PTR points to last descriptor in linked list */315 316/**317 * struct cdmac_bd - LocalLink buffer descriptor format318 *319 * app0 bits:320 * 0 Error321 * 1 IrqOnEnd generate an interrupt at completion of DMA op322 * 2 reserved323 * 3 completed Current descriptor completed324 * 4 SOP TX - marks first desc/ RX marks first desct325 * 5 EOP TX marks last desc/RX marks last desc326 * 6 EngBusy DMA is processing327 * 7 reserved328 * 8:31 application specific329 */330struct cdmac_bd {331 u32 next; /* Physical address of next buffer descriptor */332 u32 phys;333 u32 len;334 u32 app0;335 u32 app1; /* TX start << 16 | insert */336 u32 app2; /* TX csum */337 u32 app3;338 u32 app4; /* skb for TX length for RX */339};340 341struct temac_local {342 struct net_device *ndev;343 struct device *dev;344 345 /* Connection to PHY device */346 struct device_node *phy_node;347 /* For non-device-tree devices */348 char phy_name[MII_BUS_ID_SIZE + 3];349 phy_interface_t phy_interface;350 351 /* MDIO bus data */352 struct mii_bus *mii_bus; /* MII bus reference */353 354 /* IO registers, dma functions and IRQs */355 void __iomem *regs;356 void __iomem *sdma_regs;357#ifdef CONFIG_PPC_DCR358 dcr_host_t sdma_dcrs;359#endif360 u32 (*temac_ior)(struct temac_local *lp, int offset);361 void (*temac_iow)(struct temac_local *lp, int offset, u32 value);362 u32 (*dma_in)(struct temac_local *lp, int reg);363 void (*dma_out)(struct temac_local *lp, int reg, u32 value);364 365 int tx_irq;366 int rx_irq;367 int emac_num;368 369 struct sk_buff **rx_skb;370 spinlock_t rx_lock;371 /* For synchronization of indirect register access. Must be372 * shared mutex between interfaces in same TEMAC block.373 */374 spinlock_t *indirect_lock;375 u32 options; /* Current options word */376 int last_link;377 unsigned int temac_features;378 379 /* Buffer descriptors */380 struct cdmac_bd *tx_bd_v;381 dma_addr_t tx_bd_p;382 u32 tx_bd_num;383 struct cdmac_bd *rx_bd_v;384 dma_addr_t rx_bd_p;385 u32 rx_bd_num;386 int tx_bd_ci;387 int tx_bd_tail;388 int rx_bd_ci;389 int rx_bd_tail;390 391 /* DMA channel control setup */392 u8 coalesce_count_tx;393 u8 coalesce_delay_tx;394 u8 coalesce_count_rx;395 u8 coalesce_delay_rx;396 397 struct delayed_work restart_work;398};399 400/* Wrappers for temac_ior()/temac_iow() function pointers above */401#define temac_ior(lp, o) ((lp)->temac_ior(lp, o))402#define temac_iow(lp, o, v) ((lp)->temac_iow(lp, o, v))403 404/* xilinx_temac.c */405int temac_indirect_busywait(struct temac_local *lp);406u32 temac_indirect_in32(struct temac_local *lp, int reg);407u32 temac_indirect_in32_locked(struct temac_local *lp, int reg);408void temac_indirect_out32(struct temac_local *lp, int reg, u32 value);409void temac_indirect_out32_locked(struct temac_local *lp, int reg, u32 value);410 411/* xilinx_temac_mdio.c */412int temac_mdio_setup(struct temac_local *lp, struct platform_device *pdev);413void temac_mdio_teardown(struct temac_local *lp);414 415#endif /* XILINX_LL_TEMAC_H */416