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1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * Definitions for Xilinx Axi Ethernet device driver.4 *5 * Copyright (c) 2009 Secret Lab Technologies, Ltd.6 * Copyright (c) 2010 - 2012 Xilinx, Inc. All rights reserved.7 */8 9#ifndef XILINX_AXIENET_H10#define XILINX_AXIENET_H11 12#include <linux/netdevice.h>13#include <linux/spinlock.h>14#include <linux/interrupt.h>15#include <linux/if_vlan.h>16#include <linux/phylink.h>17#include <linux/skbuff.h>18 19/* Packet size info */20#define XAE_HDR_SIZE 14 /* Size of Ethernet header */21#define XAE_TRL_SIZE 4 /* Size of Ethernet trailer (FCS) */22#define XAE_MTU 1500 /* Max MTU of an Ethernet frame */23#define XAE_JUMBO_MTU 9000 /* Max MTU of a jumbo Eth. frame */24 25#define XAE_MAX_FRAME_SIZE (XAE_MTU + XAE_HDR_SIZE + XAE_TRL_SIZE)26#define XAE_MAX_VLAN_FRAME_SIZE (XAE_MTU + VLAN_ETH_HLEN + XAE_TRL_SIZE)27#define XAE_MAX_JUMBO_FRAME_SIZE (XAE_JUMBO_MTU + XAE_HDR_SIZE + XAE_TRL_SIZE)28 29/* Configuration options */30 31/* Accept all incoming packets. Default: disabled (cleared) */32#define XAE_OPTION_PROMISC BIT(0)33 34/* Jumbo frame support for Tx & Rx. Default: disabled (cleared) */35#define XAE_OPTION_JUMBO BIT(1)36 37/* VLAN Rx & Tx frame support. Default: disabled (cleared) */38#define XAE_OPTION_VLAN BIT(2)39 40/* Enable recognition of flow control frames on Rx. Default: enabled (set) */41#define XAE_OPTION_FLOW_CONTROL BIT(4)42 43/* Strip FCS and PAD from incoming frames. Note: PAD from VLAN frames is not44 * stripped. Default: disabled (set)45 */46#define XAE_OPTION_FCS_STRIP BIT(5)47 48/* Generate FCS field and add PAD automatically for outgoing frames.49 * Default: enabled (set)50 */51#define XAE_OPTION_FCS_INSERT BIT(6)52 53/* Enable Length/Type error checking for incoming frames. When this option is54 * set, the MAC will filter frames that have a mismatched type/length field55 * and if XAE_OPTION_REPORT_RXERR is set, the user is notified when these56 * types of frames are encountered. When this option is cleared, the MAC will57 * allow these types of frames to be received. Default: enabled (set)58 */59#define XAE_OPTION_LENTYPE_ERR BIT(7)60 61/* Enable the transmitter. Default: enabled (set) */62#define XAE_OPTION_TXEN BIT(11)63 64/* Enable the receiver. Default: enabled (set) */65#define XAE_OPTION_RXEN BIT(12)66 67/* Default options set when device is initialized or reset */68#define XAE_OPTION_DEFAULTS \69 (XAE_OPTION_TXEN | \70 XAE_OPTION_FLOW_CONTROL | \71 XAE_OPTION_RXEN)72 73/* Axi DMA Register definitions */74 75#define XAXIDMA_TX_CR_OFFSET 0x00000000 /* Channel control */76#define XAXIDMA_TX_SR_OFFSET 0x00000004 /* Status */77#define XAXIDMA_TX_CDESC_OFFSET 0x00000008 /* Current descriptor pointer */78#define XAXIDMA_TX_TDESC_OFFSET 0x00000010 /* Tail descriptor pointer */79 80#define XAXIDMA_RX_CR_OFFSET 0x00000030 /* Channel control */81#define XAXIDMA_RX_SR_OFFSET 0x00000034 /* Status */82#define XAXIDMA_RX_CDESC_OFFSET 0x00000038 /* Current descriptor pointer */83#define XAXIDMA_RX_TDESC_OFFSET 0x00000040 /* Tail descriptor pointer */84 85#define XAXIDMA_CR_RUNSTOP_MASK 0x00000001 /* Start/stop DMA channel */86#define XAXIDMA_CR_RESET_MASK 0x00000004 /* Reset DMA engine */87 88#define XAXIDMA_SR_HALT_MASK 0x00000001 /* Indicates DMA channel halted */89 90#define XAXIDMA_BD_NDESC_OFFSET 0x00 /* Next descriptor pointer */91#define XAXIDMA_BD_BUFA_OFFSET 0x08 /* Buffer address */92#define XAXIDMA_BD_CTRL_LEN_OFFSET 0x18 /* Control/buffer length */93#define XAXIDMA_BD_STS_OFFSET 0x1C /* Status */94#define XAXIDMA_BD_USR0_OFFSET 0x20 /* User IP specific word0 */95#define XAXIDMA_BD_USR1_OFFSET 0x24 /* User IP specific word1 */96#define XAXIDMA_BD_USR2_OFFSET 0x28 /* User IP specific word2 */97#define XAXIDMA_BD_USR3_OFFSET 0x2C /* User IP specific word3 */98#define XAXIDMA_BD_USR4_OFFSET 0x30 /* User IP specific word4 */99#define XAXIDMA_BD_ID_OFFSET 0x34 /* Sw ID */100#define XAXIDMA_BD_HAS_STSCNTRL_OFFSET 0x38 /* Whether has stscntrl strm */101#define XAXIDMA_BD_HAS_DRE_OFFSET 0x3C /* Whether has DRE */102 103#define XAXIDMA_BD_HAS_DRE_SHIFT 8 /* Whether has DRE shift */104#define XAXIDMA_BD_HAS_DRE_MASK 0xF00 /* Whether has DRE mask */105#define XAXIDMA_BD_WORDLEN_MASK 0xFF /* Whether has DRE mask */106 107#define XAXIDMA_BD_CTRL_LENGTH_MASK 0x007FFFFF /* Requested len */108#define XAXIDMA_BD_CTRL_TXSOF_MASK 0x08000000 /* First tx packet */109#define XAXIDMA_BD_CTRL_TXEOF_MASK 0x04000000 /* Last tx packet */110#define XAXIDMA_BD_CTRL_ALL_MASK 0x0C000000 /* All control bits */111 112#define XAXIDMA_DELAY_MASK 0xFF000000 /* Delay timeout counter */113#define XAXIDMA_COALESCE_MASK 0x00FF0000 /* Coalesce counter */114 115#define XAXIDMA_DELAY_SHIFT 24116#define XAXIDMA_COALESCE_SHIFT 16117 118#define XAXIDMA_IRQ_IOC_MASK 0x00001000 /* Completion intr */119#define XAXIDMA_IRQ_DELAY_MASK 0x00002000 /* Delay interrupt */120#define XAXIDMA_IRQ_ERROR_MASK 0x00004000 /* Error interrupt */121#define XAXIDMA_IRQ_ALL_MASK 0x00007000 /* All interrupts */122 123/* Default TX/RX Threshold and delay timer values for SGDMA mode */124#define XAXIDMA_DFT_TX_THRESHOLD 24125#define XAXIDMA_DFT_TX_USEC 50126#define XAXIDMA_DFT_RX_THRESHOLD 1127#define XAXIDMA_DFT_RX_USEC 50128 129#define XAXIDMA_BD_CTRL_TXSOF_MASK 0x08000000 /* First tx packet */130#define XAXIDMA_BD_CTRL_TXEOF_MASK 0x04000000 /* Last tx packet */131#define XAXIDMA_BD_CTRL_ALL_MASK 0x0C000000 /* All control bits */132 133#define XAXIDMA_BD_STS_ACTUAL_LEN_MASK 0x007FFFFF /* Actual len */134#define XAXIDMA_BD_STS_COMPLETE_MASK 0x80000000 /* Completed */135#define XAXIDMA_BD_STS_DEC_ERR_MASK 0x40000000 /* Decode error */136#define XAXIDMA_BD_STS_SLV_ERR_MASK 0x20000000 /* Slave error */137#define XAXIDMA_BD_STS_INT_ERR_MASK 0x10000000 /* Internal err */138#define XAXIDMA_BD_STS_ALL_ERR_MASK 0x70000000 /* All errors */139#define XAXIDMA_BD_STS_RXSOF_MASK 0x08000000 /* First rx pkt */140#define XAXIDMA_BD_STS_RXEOF_MASK 0x04000000 /* Last rx pkt */141#define XAXIDMA_BD_STS_ALL_MASK 0xFC000000 /* All status bits */142 143#define XAXIDMA_BD_MINIMUM_ALIGNMENT 0x40144 145/* Axi Ethernet registers definition */146#define XAE_RAF_OFFSET 0x00000000 /* Reset and Address filter */147#define XAE_TPF_OFFSET 0x00000004 /* Tx Pause Frame */148#define XAE_IFGP_OFFSET 0x00000008 /* Tx Inter-frame gap adjustment*/149#define XAE_IS_OFFSET 0x0000000C /* Interrupt status */150#define XAE_IP_OFFSET 0x00000010 /* Interrupt pending */151#define XAE_IE_OFFSET 0x00000014 /* Interrupt enable */152#define XAE_TTAG_OFFSET 0x00000018 /* Tx VLAN TAG */153#define XAE_RTAG_OFFSET 0x0000001C /* Rx VLAN TAG */154#define XAE_UAWL_OFFSET 0x00000020 /* Unicast address word lower */155#define XAE_UAWU_OFFSET 0x00000024 /* Unicast address word upper */156#define XAE_TPID0_OFFSET 0x00000028 /* VLAN TPID0 register */157#define XAE_TPID1_OFFSET 0x0000002C /* VLAN TPID1 register */158#define XAE_PPST_OFFSET 0x00000030 /* PCS PMA Soft Temac Status Reg */159#define XAE_STATS_OFFSET 0x00000200 /* Statistics counters */160#define XAE_RCW0_OFFSET 0x00000400 /* Rx Configuration Word 0 */161#define XAE_RCW1_OFFSET 0x00000404 /* Rx Configuration Word 1 */162#define XAE_TC_OFFSET 0x00000408 /* Tx Configuration */163#define XAE_FCC_OFFSET 0x0000040C /* Flow Control Configuration */164#define XAE_EMMC_OFFSET 0x00000410 /* MAC speed configuration */165#define XAE_PHYC_OFFSET 0x00000414 /* RX Max Frame Configuration */166#define XAE_ID_OFFSET 0x000004F8 /* Identification register */167#define XAE_ABILITY_OFFSET 0x000004FC /* Ability Register offset */168#define XAE_MDIO_MC_OFFSET 0x00000500 /* MDIO Setup */169#define XAE_MDIO_MCR_OFFSET 0x00000504 /* MDIO Control */170#define XAE_MDIO_MWD_OFFSET 0x00000508 /* MDIO Write Data */171#define XAE_MDIO_MRD_OFFSET 0x0000050C /* MDIO Read Data */172#define XAE_UAW0_OFFSET 0x00000700 /* Unicast address word 0 */173#define XAE_UAW1_OFFSET 0x00000704 /* Unicast address word 1 */174#define XAE_FMI_OFFSET 0x00000708 /* Frame Filter Control */175#define XAE_FFE_OFFSET 0x0000070C /* Frame Filter Enable */176#define XAE_AF0_OFFSET 0x00000710 /* Address Filter 0 */177#define XAE_AF1_OFFSET 0x00000714 /* Address Filter 1 */178#define XAE_AM0_OFFSET 0x00000750 /* Frame Filter Mask Value Bytes 3-0 */179#define XAE_AM1_OFFSET 0x00000754 /* Frame Filter Mask Value Bytes 7-4 */180 181#define XAE_TX_VLAN_DATA_OFFSET 0x00004000 /* TX VLAN data table address */182#define XAE_RX_VLAN_DATA_OFFSET 0x00008000 /* RX VLAN data table address */183#define XAE_MCAST_TABLE_OFFSET 0x00020000 /* Multicast table address */184 185/* Bit Masks for Axi Ethernet RAF register */186/* Reject receive multicast destination address */187#define XAE_RAF_MCSTREJ_MASK 0x00000002188/* Reject receive broadcast destination address */189#define XAE_RAF_BCSTREJ_MASK 0x00000004190#define XAE_RAF_TXVTAGMODE_MASK 0x00000018 /* Tx VLAN TAG mode */191#define XAE_RAF_RXVTAGMODE_MASK 0x00000060 /* Rx VLAN TAG mode */192#define XAE_RAF_TXVSTRPMODE_MASK 0x00000180 /* Tx VLAN STRIP mode */193#define XAE_RAF_RXVSTRPMODE_MASK 0x00000600 /* Rx VLAN STRIP mode */194#define XAE_RAF_NEWFNCENBL_MASK 0x00000800 /* New function mode */195/* Extended Multicast Filtering mode */196#define XAE_RAF_EMULTIFLTRENBL_MASK 0x00001000197#define XAE_RAF_STATSRST_MASK 0x00002000 /* Stats. Counter Reset */198#define XAE_RAF_RXBADFRMEN_MASK 0x00004000 /* Recv Bad Frame Enable */199#define XAE_RAF_TXVTAGMODE_SHIFT 3 /* Tx Tag mode shift bits */200#define XAE_RAF_RXVTAGMODE_SHIFT 5 /* Rx Tag mode shift bits */201#define XAE_RAF_TXVSTRPMODE_SHIFT 7 /* Tx strip mode shift bits*/202#define XAE_RAF_RXVSTRPMODE_SHIFT 9 /* Rx Strip mode shift bits*/203 204/* Bit Masks for Axi Ethernet TPF and IFGP registers */205#define XAE_TPF_TPFV_MASK 0x0000FFFF /* Tx pause frame value */206/* Transmit inter-frame gap adjustment value */207#define XAE_IFGP0_IFGP_MASK 0x0000007F208 209/* Bit Masks for Axi Ethernet IS, IE and IP registers, Same masks apply210 * for all 3 registers.211 */212/* Hard register access complete */213#define XAE_INT_HARDACSCMPLT_MASK 0x00000001214/* Auto negotiation complete */215#define XAE_INT_AUTONEG_MASK 0x00000002216#define XAE_INT_RXCMPIT_MASK 0x00000004 /* Rx complete */217#define XAE_INT_RXRJECT_MASK 0x00000008 /* Rx frame rejected */218#define XAE_INT_RXFIFOOVR_MASK 0x00000010 /* Rx fifo overrun */219#define XAE_INT_TXCMPIT_MASK 0x00000020 /* Tx complete */220#define XAE_INT_RXDCMLOCK_MASK 0x00000040 /* Rx Dcm Lock */221#define XAE_INT_MGTRDY_MASK 0x00000080 /* MGT clock Lock */222#define XAE_INT_PHYRSTCMPLT_MASK 0x00000100 /* Phy Reset complete */223#define XAE_INT_ALL_MASK 0x0000003F /* All the ints */224 225/* INT bits that indicate receive errors */226#define XAE_INT_RECV_ERROR_MASK \227 (XAE_INT_RXRJECT_MASK | XAE_INT_RXFIFOOVR_MASK)228 229/* Bit masks for Axi Ethernet VLAN TPID Word 0 register */230#define XAE_TPID_0_MASK 0x0000FFFF /* TPID 0 */231#define XAE_TPID_1_MASK 0xFFFF0000 /* TPID 1 */232 233/* Bit masks for Axi Ethernet VLAN TPID Word 1 register */234#define XAE_TPID_2_MASK 0x0000FFFF /* TPID 0 */235#define XAE_TPID_3_MASK 0xFFFF0000 /* TPID 1 */236 237/* Bit masks for Axi Ethernet RCW1 register */238#define XAE_RCW1_RST_MASK 0x80000000 /* Reset */239#define XAE_RCW1_JUM_MASK 0x40000000 /* Jumbo frame enable */240/* In-Band FCS enable (FCS not stripped) */241#define XAE_RCW1_FCS_MASK 0x20000000242#define XAE_RCW1_RX_MASK 0x10000000 /* Receiver enable */243#define XAE_RCW1_VLAN_MASK 0x08000000 /* VLAN frame enable */244/* Length/type field valid check disable */245#define XAE_RCW1_LT_DIS_MASK 0x02000000246/* Control frame Length check disable */247#define XAE_RCW1_CL_DIS_MASK 0x01000000248/* Pause frame source address bits [47:32]. Bits [31:0] are249 * stored in register RCW0250 */251#define XAE_RCW1_PAUSEADDR_MASK 0x0000FFFF252 253/* Bit masks for Axi Ethernet TC register */254#define XAE_TC_RST_MASK 0x80000000 /* Reset */255#define XAE_TC_JUM_MASK 0x40000000 /* Jumbo frame enable */256/* In-Band FCS enable (FCS not generated) */257#define XAE_TC_FCS_MASK 0x20000000258#define XAE_TC_TX_MASK 0x10000000 /* Transmitter enable */259#define XAE_TC_VLAN_MASK 0x08000000 /* VLAN frame enable */260/* Inter-frame gap adjustment enable */261#define XAE_TC_IFG_MASK 0x02000000262 263/* Bit masks for Axi Ethernet FCC register */264#define XAE_FCC_FCRX_MASK 0x20000000 /* Rx flow control enable */265#define XAE_FCC_FCTX_MASK 0x40000000 /* Tx flow control enable */266 267/* Bit masks for Axi Ethernet EMMC register */268#define XAE_EMMC_LINKSPEED_MASK 0xC0000000 /* Link speed */269#define XAE_EMMC_RGMII_MASK 0x20000000 /* RGMII mode enable */270#define XAE_EMMC_SGMII_MASK 0x10000000 /* SGMII mode enable */271#define XAE_EMMC_GPCS_MASK 0x08000000 /* 1000BaseX mode enable */272#define XAE_EMMC_HOST_MASK 0x04000000 /* Host interface enable */273#define XAE_EMMC_TX16BIT 0x02000000 /* 16 bit Tx client enable */274#define XAE_EMMC_RX16BIT 0x01000000 /* 16 bit Rx client enable */275#define XAE_EMMC_LINKSPD_10 0x00000000 /* Link Speed mask for 10 Mbit */276#define XAE_EMMC_LINKSPD_100 0x40000000 /* Link Speed mask for 100 Mbit */277#define XAE_EMMC_LINKSPD_1000 0x80000000 /* Link Speed mask for 1000 Mbit */278 279/* Bit masks for Axi Ethernet PHYC register */280#define XAE_PHYC_SGMIILINKSPEED_MASK 0xC0000000 /* SGMII link speed mask*/281#define XAE_PHYC_RGMIILINKSPEED_MASK 0x0000000C /* RGMII link speed */282#define XAE_PHYC_RGMIIHD_MASK 0x00000002 /* RGMII Half-duplex */283#define XAE_PHYC_RGMIILINK_MASK 0x00000001 /* RGMII link status */284#define XAE_PHYC_RGLINKSPD_10 0x00000000 /* RGMII link 10 Mbit */285#define XAE_PHYC_RGLINKSPD_100 0x00000004 /* RGMII link 100 Mbit */286#define XAE_PHYC_RGLINKSPD_1000 0x00000008 /* RGMII link 1000 Mbit */287#define XAE_PHYC_SGLINKSPD_10 0x00000000 /* SGMII link 10 Mbit */288#define XAE_PHYC_SGLINKSPD_100 0x40000000 /* SGMII link 100 Mbit */289#define XAE_PHYC_SGLINKSPD_1000 0x80000000 /* SGMII link 1000 Mbit */290 291/* Bit masks for Axi Ethernet ability register */292#define XAE_ABILITY_PFC BIT(16)293#define XAE_ABILITY_FRAME_FILTER BIT(10)294#define XAE_ABILITY_HALF_DUPLEX BIT(9)295#define XAE_ABILITY_STATS BIT(8)296#define XAE_ABILITY_2_5G BIT(3)297#define XAE_ABILITY_1G BIT(2)298#define XAE_ABILITY_100M BIT(1)299#define XAE_ABILITY_10M BIT(0)300 301/* Bit masks for Axi Ethernet MDIO interface MC register */302#define XAE_MDIO_MC_MDIOEN_MASK 0x00000040 /* MII management enable */303#define XAE_MDIO_MC_CLOCK_DIVIDE_MAX 0x3F /* Maximum MDIO divisor */304 305/* Bit masks for Axi Ethernet MDIO interface MCR register */306#define XAE_MDIO_MCR_PHYAD_MASK 0x1F000000 /* Phy Address Mask */307#define XAE_MDIO_MCR_PHYAD_SHIFT 24 /* Phy Address Shift */308#define XAE_MDIO_MCR_REGAD_MASK 0x001F0000 /* Reg Address Mask */309#define XAE_MDIO_MCR_REGAD_SHIFT 16 /* Reg Address Shift */310#define XAE_MDIO_MCR_OP_MASK 0x0000C000 /* Operation Code Mask */311#define XAE_MDIO_MCR_OP_SHIFT 13 /* Operation Code Shift */312#define XAE_MDIO_MCR_OP_READ_MASK 0x00008000 /* Op Code Read Mask */313#define XAE_MDIO_MCR_OP_WRITE_MASK 0x00004000 /* Op Code Write Mask */314#define XAE_MDIO_MCR_INITIATE_MASK 0x00000800 /* Ready Mask */315#define XAE_MDIO_MCR_READY_MASK 0x00000080 /* Ready Mask */316 317/* Bit masks for Axi Ethernet MDIO interface MIS, MIP, MIE, MIC registers */318#define XAE_MDIO_INT_MIIM_RDY_MASK 0x00000001 /* MIIM Interrupt */319 320/* Bit masks for Axi Ethernet UAW1 register */321/* Station address bits [47:32]; Station address322 * bits [31:0] are stored in register UAW0323 */324#define XAE_UAW1_UNICASTADDR_MASK 0x0000FFFF325 326/* Bit masks for Axi Ethernet FMC register */327#define XAE_FMI_PM_MASK 0x80000000 /* Promis. mode enable */328#define XAE_FMI_IND_MASK 0x00000003 /* Index Mask */329 330#define XAE_MDIO_DIV_DFT 29 /* Default MDIO clock divisor */331 332/* Defines for different options for C_PHY_TYPE parameter in Axi Ethernet IP */333#define XAE_PHY_TYPE_MII 0334#define XAE_PHY_TYPE_GMII 1335#define XAE_PHY_TYPE_RGMII_1_3 2336#define XAE_PHY_TYPE_RGMII_2_0 3337#define XAE_PHY_TYPE_SGMII 4338#define XAE_PHY_TYPE_1000BASE_X 5339 340 /* Total number of entries in the hardware multicast table. */341#define XAE_MULTICAST_CAM_TABLE_NUM 4342 343/* Axi Ethernet Synthesis features */344#define XAE_FEATURE_PARTIAL_RX_CSUM BIT(0)345#define XAE_FEATURE_PARTIAL_TX_CSUM BIT(1)346#define XAE_FEATURE_FULL_RX_CSUM BIT(2)347#define XAE_FEATURE_FULL_TX_CSUM BIT(3)348#define XAE_FEATURE_DMA_64BIT BIT(4)349#define XAE_FEATURE_STATS BIT(5)350 351#define XAE_NO_CSUM_OFFLOAD 0352 353#define XAE_FULL_CSUM_STATUS_MASK 0x00000038354#define XAE_IP_UDP_CSUM_VALIDATED 0x00000003355#define XAE_IP_TCP_CSUM_VALIDATED 0x00000002356 357#define DELAY_OF_ONE_MILLISEC 1000358 359/* Xilinx PCS/PMA PHY register for switching 1000BaseX or SGMII */360#define XLNX_MII_STD_SELECT_REG 0x11361#define XLNX_MII_STD_SELECT_SGMII BIT(0)362 363/* enum temac_stat - TEMAC statistics counters364 *365 * Index of statistics counters within the TEMAC. This must match the366 * order/offset of hardware registers exactly.367 */368enum temac_stat {369 STAT_RX_BYTES = 0,370 STAT_TX_BYTES,371 STAT_UNDERSIZE_FRAMES,372 STAT_FRAGMENT_FRAMES,373 STAT_RX_64_BYTE_FRAMES,374 STAT_RX_65_127_BYTE_FRAMES,375 STAT_RX_128_255_BYTE_FRAMES,376 STAT_RX_256_511_BYTE_FRAMES,377 STAT_RX_512_1023_BYTE_FRAMES,378 STAT_RX_1024_MAX_BYTE_FRAMES,379 STAT_RX_OVERSIZE_FRAMES,380 STAT_TX_64_BYTE_FRAMES,381 STAT_TX_65_127_BYTE_FRAMES,382 STAT_TX_128_255_BYTE_FRAMES,383 STAT_TX_256_511_BYTE_FRAMES,384 STAT_TX_512_1023_BYTE_FRAMES,385 STAT_TX_1024_MAX_BYTE_FRAMES,386 STAT_TX_OVERSIZE_FRAMES,387 STAT_RX_GOOD_FRAMES,388 STAT_RX_FCS_ERRORS,389 STAT_RX_BROADCAST_FRAMES,390 STAT_RX_MULTICAST_FRAMES,391 STAT_RX_CONTROL_FRAMES,392 STAT_RX_LENGTH_ERRORS,393 STAT_RX_VLAN_FRAMES,394 STAT_RX_PAUSE_FRAMES,395 STAT_RX_CONTROL_OPCODE_ERRORS,396 STAT_TX_GOOD_FRAMES,397 STAT_TX_BROADCAST_FRAMES,398 STAT_TX_MULTICAST_FRAMES,399 STAT_TX_UNDERRUN_ERRORS,400 STAT_TX_CONTROL_FRAMES,401 STAT_TX_VLAN_FRAMES,402 STAT_TX_PAUSE_FRAMES,403 STAT_TX_SINGLE_COLLISION_FRAMES,404 STAT_TX_MULTIPLE_COLLISION_FRAMES,405 STAT_TX_DEFERRED_FRAMES,406 STAT_TX_LATE_COLLISIONS,407 STAT_TX_EXCESS_COLLISIONS,408 STAT_TX_EXCESS_DEFERRAL,409 STAT_RX_ALIGNMENT_ERRORS,410 STAT_TX_PFC_FRAMES,411 STAT_RX_PFC_FRAMES,412 STAT_USER_DEFINED0,413 STAT_USER_DEFINED1,414 STAT_USER_DEFINED2,415 STAT_COUNT,416};417 418/**419 * struct axidma_bd - Axi Dma buffer descriptor layout420 * @next: MM2S/S2MM Next Descriptor Pointer421 * @next_msb: MM2S/S2MM Next Descriptor Pointer (high 32 bits)422 * @phys: MM2S/S2MM Buffer Address423 * @phys_msb: MM2S/S2MM Buffer Address (high 32 bits)424 * @reserved3: Reserved and not used425 * @reserved4: Reserved and not used426 * @cntrl: MM2S/S2MM Control value427 * @status: MM2S/S2MM Status value428 * @app0: MM2S/S2MM User Application Field 0.429 * @app1: MM2S/S2MM User Application Field 1.430 * @app2: MM2S/S2MM User Application Field 2.431 * @app3: MM2S/S2MM User Application Field 3.432 * @app4: MM2S/S2MM User Application Field 4.433 * @skb: Pointer to SKB transferred using DMA434 */435struct axidma_bd {436 u32 next; /* Physical address of next buffer descriptor */437 u32 next_msb; /* high 32 bits for IP >= v7.1, reserved on older IP */438 u32 phys;439 u32 phys_msb; /* for IP >= v7.1, reserved for older IP */440 u32 reserved3;441 u32 reserved4;442 u32 cntrl;443 u32 status;444 u32 app0;445 u32 app1; /* TX start << 16 | insert */446 u32 app2; /* TX csum seed */447 u32 app3;448 u32 app4; /* Last field used by HW */449 struct sk_buff *skb;450} __aligned(XAXIDMA_BD_MINIMUM_ALIGNMENT);451 452#define XAE_NUM_MISC_CLOCKS 3453 454/**455 * struct skbuf_dma_descriptor - skb for each dma descriptor456 * @sgl: Pointer for sglist.457 * @desc: Pointer to dma descriptor.458 * @dma_address: dma address of sglist.459 * @skb: Pointer to SKB transferred using DMA460 * @sg_len: number of entries in the sglist.461 */462struct skbuf_dma_descriptor {463 struct scatterlist sgl[MAX_SKB_FRAGS + 1];464 struct dma_async_tx_descriptor *desc;465 dma_addr_t dma_address;466 struct sk_buff *skb;467 int sg_len;468};469 470/**471 * struct axienet_local - axienet private per device data472 * @ndev: Pointer for net_device to which it will be attached.473 * @dev: Pointer to device structure474 * @phylink: Pointer to phylink instance475 * @phylink_config: phylink configuration settings476 * @pcs_phy: Reference to PCS/PMA PHY if used477 * @pcs: phylink pcs structure for PCS PHY478 * @switch_x_sgmii: Whether switchable 1000BaseX/SGMII mode is enabled in the core479 * @axi_clk: AXI4-Lite bus clock480 * @misc_clks: Misc ethernet clocks (AXI4-Stream, Ref, MGT clocks)481 * @mii_bus: Pointer to MII bus structure482 * @mii_clk_div: MII bus clock divider value483 * @regs_start: Resource start for axienet device addresses484 * @regs: Base address for the axienet_local device address space485 * @dma_regs: Base address for the axidma device address space486 * @napi_rx: NAPI RX control structure487 * @rx_dma_cr: Nominal content of RX DMA control register488 * @rx_bd_v: Virtual address of the RX buffer descriptor ring489 * @rx_bd_p: Physical address(start address) of the RX buffer descr. ring490 * @rx_bd_num: Size of RX buffer descriptor ring491 * @rx_bd_ci: Stores the index of the Rx buffer descriptor in the ring being492 * accessed currently.493 * @rx_packets: RX packet count for statistics494 * @rx_bytes: RX byte count for statistics495 * @rx_stat_sync: Synchronization object for RX stats496 * @napi_tx: NAPI TX control structure497 * @tx_dma_cr: Nominal content of TX DMA control register498 * @tx_bd_v: Virtual address of the TX buffer descriptor ring499 * @tx_bd_p: Physical address(start address) of the TX buffer descr. ring500 * @tx_bd_num: Size of TX buffer descriptor ring501 * @tx_bd_ci: Stores the next Tx buffer descriptor in the ring that may be502 * complete. Only updated at runtime by TX NAPI poll.503 * @tx_bd_tail: Stores the index of the next Tx buffer descriptor in the ring504 * to be populated.505 * @tx_packets: TX packet count for statistics506 * @tx_bytes: TX byte count for statistics507 * @tx_stat_sync: Synchronization object for TX stats508 * @hw_stat_base: Base offset for statistics counters. This may be nonzero if509 * the statistics counteres were reset or wrapped around.510 * @hw_last_counter: Last-seen value of each statistic counter511 * @reset_in_progress: Set while we are performing a reset and statistics512 * counters may be invalid513 * @hw_stats_seqcount: Sequence counter for @hw_stat_base, @hw_last_counter,514 * and @reset_in_progress.515 * @stats_lock: Lock for @hw_stats_seqcount516 * @stats_work: Work for reading the hardware statistics counters often enough517 * to catch overflows.518 * @dma_err_task: Work structure to process Axi DMA errors519 * @stopping: Set when @dma_err_task shouldn't do anything because we are520 * about to stop the device.521 * @tx_irq: Axidma TX IRQ number522 * @rx_irq: Axidma RX IRQ number523 * @eth_irq: Ethernet core IRQ number524 * @phy_mode: Phy type to identify between MII/GMII/RGMII/SGMII/1000 Base-X525 * @options: AxiEthernet option word526 * @features: Stores the extended features supported by the axienet hw527 * @max_frm_size: Stores the maximum size of the frame that can be that528 * Txed/Rxed in the existing hardware. If jumbo option is529 * supported, the maximum frame size would be 9k. Else it is530 * 1522 bytes (assuming support for basic VLAN)531 * @rxmem: Stores rx memory size for jumbo frame handling.532 * @coalesce_count_rx: Store the irq coalesce on RX side.533 * @coalesce_usec_rx: IRQ coalesce delay for RX534 * @coalesce_count_tx: Store the irq coalesce on TX side.535 * @coalesce_usec_tx: IRQ coalesce delay for TX536 * @use_dmaengine: flag to check dmaengine framework usage.537 * @tx_chan: TX DMA channel.538 * @rx_chan: RX DMA channel.539 * @tx_skb_ring: Pointer to TX skb ring buffer array.540 * @rx_skb_ring: Pointer to RX skb ring buffer array.541 * @tx_ring_head: TX skb ring buffer head index.542 * @tx_ring_tail: TX skb ring buffer tail index.543 * @rx_ring_head: RX skb ring buffer head index.544 * @rx_ring_tail: RX skb ring buffer tail index.545 */546struct axienet_local {547 struct net_device *ndev;548 struct device *dev;549 550 struct phylink *phylink;551 struct phylink_config phylink_config;552 553 struct mdio_device *pcs_phy;554 struct phylink_pcs pcs;555 556 bool switch_x_sgmii;557 558 struct clk *axi_clk;559 struct clk_bulk_data misc_clks[XAE_NUM_MISC_CLOCKS];560 561 struct mii_bus *mii_bus;562 u8 mii_clk_div;563 564 resource_size_t regs_start;565 void __iomem *regs;566 void __iomem *dma_regs;567 568 struct napi_struct napi_rx;569 u32 rx_dma_cr;570 struct axidma_bd *rx_bd_v;571 dma_addr_t rx_bd_p;572 u32 rx_bd_num;573 u32 rx_bd_ci;574 u64_stats_t rx_packets;575 u64_stats_t rx_bytes;576 struct u64_stats_sync rx_stat_sync;577 578 struct napi_struct napi_tx;579 u32 tx_dma_cr;580 struct axidma_bd *tx_bd_v;581 dma_addr_t tx_bd_p;582 u32 tx_bd_num;583 u32 tx_bd_ci;584 u32 tx_bd_tail;585 u64_stats_t tx_packets;586 u64_stats_t tx_bytes;587 struct u64_stats_sync tx_stat_sync;588 589 u64 hw_stat_base[STAT_COUNT];590 u32 hw_last_counter[STAT_COUNT];591 seqcount_mutex_t hw_stats_seqcount;592 struct mutex stats_lock;593 struct delayed_work stats_work;594 bool reset_in_progress;595 596 struct work_struct dma_err_task;597 bool stopping;598 599 int tx_irq;600 int rx_irq;601 int eth_irq;602 phy_interface_t phy_mode;603 604 u32 options;605 u32 features;606 607 u32 max_frm_size;608 u32 rxmem;609 610 u32 coalesce_count_rx;611 u32 coalesce_usec_rx;612 u32 coalesce_count_tx;613 u32 coalesce_usec_tx;614 u8 use_dmaengine;615 struct dma_chan *tx_chan;616 struct dma_chan *rx_chan;617 struct skbuf_dma_descriptor **tx_skb_ring;618 struct skbuf_dma_descriptor **rx_skb_ring;619 int tx_ring_head;620 int tx_ring_tail;621 int rx_ring_head;622 int rx_ring_tail;623};624 625/**626 * struct axienet_option - Used to set axi ethernet hardware options627 * @opt: Option to be set.628 * @reg: Register offset to be written for setting the option629 * @m_or: Mask to be ORed for setting the option in the register630 */631struct axienet_option {632 u32 opt;633 u32 reg;634 u32 m_or;635};636 637/**638 * axienet_ior - Memory mapped Axi Ethernet register read639 * @lp: Pointer to axienet local structure640 * @offset: Address offset from the base address of Axi Ethernet core641 *642 * Return: The contents of the Axi Ethernet register643 *644 * This function returns the contents of the corresponding register.645 */646static inline u32 axienet_ior(struct axienet_local *lp, off_t offset)647{648 return ioread32(lp->regs + offset);649}650 651static inline u32 axinet_ior_read_mcr(struct axienet_local *lp)652{653 return axienet_ior(lp, XAE_MDIO_MCR_OFFSET);654}655 656static inline void axienet_lock_mii(struct axienet_local *lp)657{658 if (lp->mii_bus)659 mutex_lock(&lp->mii_bus->mdio_lock);660}661 662static inline void axienet_unlock_mii(struct axienet_local *lp)663{664 if (lp->mii_bus)665 mutex_unlock(&lp->mii_bus->mdio_lock);666}667 668/**669 * axienet_iow - Memory mapped Axi Ethernet register write670 * @lp: Pointer to axienet local structure671 * @offset: Address offset from the base address of Axi Ethernet core672 * @value: Value to be written into the Axi Ethernet register673 *674 * This function writes the desired value into the corresponding Axi Ethernet675 * register.676 */677static inline void axienet_iow(struct axienet_local *lp, off_t offset,678 u32 value)679{680 iowrite32(value, lp->regs + offset);681}682 683/**684 * axienet_dma_out32 - Memory mapped Axi DMA register write.685 * @lp: Pointer to axienet local structure686 * @reg: Address offset from the base address of the Axi DMA core687 * @value: Value to be written into the Axi DMA register688 *689 * This function writes the desired value into the corresponding Axi DMA690 * register.691 */692 693static inline void axienet_dma_out32(struct axienet_local *lp,694 off_t reg, u32 value)695{696 iowrite32(value, lp->dma_regs + reg);697}698 699#if defined(CONFIG_64BIT) && defined(iowrite64)700/**701 * axienet_dma_out64 - Memory mapped Axi DMA register write.702 * @lp: Pointer to axienet local structure703 * @reg: Address offset from the base address of the Axi DMA core704 * @value: Value to be written into the Axi DMA register705 *706 * This function writes the desired value into the corresponding Axi DMA707 * register.708 */709static inline void axienet_dma_out64(struct axienet_local *lp,710 off_t reg, u64 value)711{712 iowrite64(value, lp->dma_regs + reg);713}714 715static inline void axienet_dma_out_addr(struct axienet_local *lp, off_t reg,716 dma_addr_t addr)717{718 if (lp->features & XAE_FEATURE_DMA_64BIT)719 axienet_dma_out64(lp, reg, addr);720 else721 axienet_dma_out32(lp, reg, lower_32_bits(addr));722}723 724#else /* CONFIG_64BIT */725 726static inline void axienet_dma_out_addr(struct axienet_local *lp, off_t reg,727 dma_addr_t addr)728{729 axienet_dma_out32(lp, reg, lower_32_bits(addr));730}731 732#endif /* CONFIG_64BIT */733 734/* Function prototypes visible in xilinx_axienet_mdio.c for other files */735int axienet_mdio_setup(struct axienet_local *lp);736void axienet_mdio_teardown(struct axienet_local *lp);737 738#endif /* XILINX_AXI_ENET_H */739