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1// SPDX-License-Identifier: GPL-2.0-only2/*3 * Intel IXP4xx Ethernet driver for Linux4 *5 * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl>6 *7 * Ethernet port config (0x00 is not present on IXP42X):8 *9 * logical port 0x00 0x10 0x2010 * NPE 0 (NPE-A) 1 (NPE-B) 2 (NPE-C)11 * physical PortId 2 0 112 * TX queue 23 24 2513 * RX-free queue 26 27 2814 * TX-done queue is always 31, per-port RX and TX-ready queues are configurable15 *16 * Queue entries:17 * bits 0 -> 1 - NPE ID (RX and TX-done)18 * bits 0 -> 2 - priority (TX, per 802.1D)19 * bits 3 -> 4 - port ID (user-set?)20 * bits 5 -> 31 - physical descriptor address21 */22 23#include <linux/delay.h>24#include <linux/dma-mapping.h>25#include <linux/dmapool.h>26#include <linux/etherdevice.h>27#include <linux/if_vlan.h>28#include <linux/io.h>29#include <linux/kernel.h>30#include <linux/net_tstamp.h>31#include <linux/of.h>32#include <linux/of_mdio.h>33#include <linux/of_net.h>34#include <linux/phy.h>35#include <linux/platform_device.h>36#include <linux/ptp_classify.h>37#include <linux/slab.h>38#include <linux/module.h>39#include <linux/soc/ixp4xx/npe.h>40#include <linux/soc/ixp4xx/qmgr.h>41#include <linux/soc/ixp4xx/cpu.h>42#include <linux/types.h>43 44#define IXP4XX_ETH_NPEA 0x0045#define IXP4XX_ETH_NPEB 0x1046#define IXP4XX_ETH_NPEC 0x2047 48#include "ixp46x_ts.h"49 50#define DEBUG_DESC 051#define DEBUG_RX 052#define DEBUG_TX 053#define DEBUG_PKT_BYTES 054#define DEBUG_MDIO 055#define DEBUG_CLOSE 056 57#define DRV_NAME "ixp4xx_eth"58 59#define MAX_NPES 360 61#define RX_DESCS 64 /* also length of all RX queues */62#define TX_DESCS 16 /* also length of all TX queues */63#define TXDONE_QUEUE_LEN 64 /* dwords */64 65#define POOL_ALLOC_SIZE (sizeof(struct desc) * (RX_DESCS + TX_DESCS))66#define REGS_SIZE 0x100067 68/* MRU is said to be 14320 in a code dump, the SW manual says that69 * MRU/MTU is 16320 and includes VLAN and ethernet headers.70 * See "IXP400 Software Programmer's Guide" section 10.3.2, page 161.71 *72 * FIXME: we have chosen the safe default (14320) but if you can test73 * jumboframes, experiment with 16320 and see what happens!74 */75#define MAX_MRU (14320 - VLAN_ETH_HLEN)76#define RX_BUFF_SIZE ALIGN((NET_IP_ALIGN) + MAX_MRU, 4)77 78#define NAPI_WEIGHT 1679#define MDIO_INTERVAL (3 * HZ)80#define MAX_MDIO_RETRIES 100 /* microseconds, typically 30 cycles */81#define MAX_CLOSE_WAIT 1000 /* microseconds, typically 2-3 cycles */82 83#define NPE_ID(port_id) ((port_id) >> 4)84#define PHYSICAL_ID(port_id) ((NPE_ID(port_id) + 2) % 3)85#define TX_QUEUE(port_id) (NPE_ID(port_id) + 23)86#define RXFREE_QUEUE(port_id) (NPE_ID(port_id) + 26)87#define TXDONE_QUEUE 3188 89#define PTP_SLAVE_MODE 190#define PTP_MASTER_MODE 291#define PORT2CHANNEL(p) NPE_ID(p->id)92 93/* TX Control Registers */94#define TX_CNTRL0_TX_EN 0x0195#define TX_CNTRL0_HALFDUPLEX 0x0296#define TX_CNTRL0_RETRY 0x0497#define TX_CNTRL0_PAD_EN 0x0898#define TX_CNTRL0_APPEND_FCS 0x1099#define TX_CNTRL0_2DEFER 0x20100#define TX_CNTRL0_RMII 0x40 /* reduced MII */101#define TX_CNTRL1_RETRIES 0x0F /* 4 bits */102 103/* RX Control Registers */104#define RX_CNTRL0_RX_EN 0x01105#define RX_CNTRL0_PADSTRIP_EN 0x02106#define RX_CNTRL0_SEND_FCS 0x04107#define RX_CNTRL0_PAUSE_EN 0x08108#define RX_CNTRL0_LOOP_EN 0x10109#define RX_CNTRL0_ADDR_FLTR_EN 0x20110#define RX_CNTRL0_RX_RUNT_EN 0x40111#define RX_CNTRL0_BCAST_DIS 0x80112#define RX_CNTRL1_DEFER_EN 0x01113 114/* Core Control Register */115#define CORE_RESET 0x01116#define CORE_RX_FIFO_FLUSH 0x02117#define CORE_TX_FIFO_FLUSH 0x04118#define CORE_SEND_JAM 0x08119#define CORE_MDC_EN 0x10 /* MDIO using NPE-B ETH-0 only */120 121#define DEFAULT_TX_CNTRL0 (TX_CNTRL0_TX_EN | TX_CNTRL0_RETRY | \122 TX_CNTRL0_PAD_EN | TX_CNTRL0_APPEND_FCS | \123 TX_CNTRL0_2DEFER)124#define DEFAULT_RX_CNTRL0 RX_CNTRL0_RX_EN125#define DEFAULT_CORE_CNTRL CORE_MDC_EN126 127 128/* NPE message codes */129#define NPE_GETSTATUS 0x00130#define NPE_EDB_SETPORTADDRESS 0x01131#define NPE_EDB_GETMACADDRESSDATABASE 0x02132#define NPE_EDB_SETMACADDRESSSDATABASE 0x03133#define NPE_GETSTATS 0x04134#define NPE_RESETSTATS 0x05135#define NPE_SETMAXFRAMELENGTHS 0x06136#define NPE_VLAN_SETRXTAGMODE 0x07137#define NPE_VLAN_SETDEFAULTRXVID 0x08138#define NPE_VLAN_SETPORTVLANTABLEENTRY 0x09139#define NPE_VLAN_SETPORTVLANTABLERANGE 0x0A140#define NPE_VLAN_SETRXQOSENTRY 0x0B141#define NPE_VLAN_SETPORTIDEXTRACTIONMODE 0x0C142#define NPE_STP_SETBLOCKINGSTATE 0x0D143#define NPE_FW_SETFIREWALLMODE 0x0E144#define NPE_PC_SETFRAMECONTROLDURATIONID 0x0F145#define NPE_PC_SETAPMACTABLE 0x11146#define NPE_SETLOOPBACK_MODE 0x12147#define NPE_PC_SETBSSIDTABLE 0x13148#define NPE_ADDRESS_FILTER_CONFIG 0x14149#define NPE_APPENDFCSCONFIG 0x15150#define NPE_NOTIFY_MAC_RECOVERY_DONE 0x16151#define NPE_MAC_RECOVERY_START 0x17152 153 154#ifdef __ARMEB__155typedef struct sk_buff buffer_t;156#define free_buffer dev_kfree_skb157#define free_buffer_irq dev_consume_skb_irq158#else159typedef void buffer_t;160#define free_buffer kfree161#define free_buffer_irq kfree162#endif163 164/* Information about built-in Ethernet MAC interfaces */165struct eth_plat_info {166 u8 rxq; /* configurable, currently 0 - 31 only */167 u8 txreadyq;168 u8 hwaddr[ETH_ALEN];169 u8 npe; /* NPE instance used by this interface */170 bool has_mdio; /* If this instance has an MDIO bus */171};172 173struct eth_regs {174 u32 tx_control[2], __res1[2]; /* 000 */175 u32 rx_control[2], __res2[2]; /* 010 */176 u32 random_seed, __res3[3]; /* 020 */177 u32 partial_empty_threshold, __res4; /* 030 */178 u32 partial_full_threshold, __res5; /* 038 */179 u32 tx_start_bytes, __res6[3]; /* 040 */180 u32 tx_deferral, rx_deferral, __res7[2];/* 050 */181 u32 tx_2part_deferral[2], __res8[2]; /* 060 */182 u32 slot_time, __res9[3]; /* 070 */183 u32 mdio_command[4]; /* 080 */184 u32 mdio_status[4]; /* 090 */185 u32 mcast_mask[6], __res10[2]; /* 0A0 */186 u32 mcast_addr[6], __res11[2]; /* 0C0 */187 u32 int_clock_threshold, __res12[3]; /* 0E0 */188 u32 hw_addr[6], __res13[61]; /* 0F0 */189 u32 core_control; /* 1FC */190};191 192struct port {193 struct eth_regs __iomem *regs;194 struct ixp46x_ts_regs __iomem *timesync_regs;195 int phc_index;196 struct npe *npe;197 struct net_device *netdev;198 struct napi_struct napi;199 struct eth_plat_info *plat;200 buffer_t *rx_buff_tab[RX_DESCS], *tx_buff_tab[TX_DESCS];201 struct desc *desc_tab; /* coherent */202 dma_addr_t desc_tab_phys;203 int id; /* logical port ID */204 int speed, duplex;205 u8 firmware[4];206 int hwts_tx_en;207 int hwts_rx_en;208};209 210/* NPE message structure */211struct msg {212#ifdef __ARMEB__213 u8 cmd, eth_id, byte2, byte3;214 u8 byte4, byte5, byte6, byte7;215#else216 u8 byte3, byte2, eth_id, cmd;217 u8 byte7, byte6, byte5, byte4;218#endif219};220 221/* Ethernet packet descriptor */222struct desc {223 u32 next; /* pointer to next buffer, unused */224 225#ifdef __ARMEB__226 u16 buf_len; /* buffer length */227 u16 pkt_len; /* packet length */228 u32 data; /* pointer to data buffer in RAM */229 u8 dest_id;230 u8 src_id;231 u16 flags;232 u8 qos;233 u8 padlen;234 u16 vlan_tci;235#else236 u16 pkt_len; /* packet length */237 u16 buf_len; /* buffer length */238 u32 data; /* pointer to data buffer in RAM */239 u16 flags;240 u8 src_id;241 u8 dest_id;242 u16 vlan_tci;243 u8 padlen;244 u8 qos;245#endif246 247#ifdef __ARMEB__248 u8 dst_mac_0, dst_mac_1, dst_mac_2, dst_mac_3;249 u8 dst_mac_4, dst_mac_5, src_mac_0, src_mac_1;250 u8 src_mac_2, src_mac_3, src_mac_4, src_mac_5;251#else252 u8 dst_mac_3, dst_mac_2, dst_mac_1, dst_mac_0;253 u8 src_mac_1, src_mac_0, dst_mac_5, dst_mac_4;254 u8 src_mac_5, src_mac_4, src_mac_3, src_mac_2;255#endif256};257 258 259#define rx_desc_phys(port, n) ((port)->desc_tab_phys + \260 (n) * sizeof(struct desc))261#define rx_desc_ptr(port, n) (&(port)->desc_tab[n])262 263#define tx_desc_phys(port, n) ((port)->desc_tab_phys + \264 ((n) + RX_DESCS) * sizeof(struct desc))265#define tx_desc_ptr(port, n) (&(port)->desc_tab[(n) + RX_DESCS])266 267#ifndef __ARMEB__268static inline void memcpy_swab32(u32 *dest, u32 *src, int cnt)269{270 int i;271 for (i = 0; i < cnt; i++)272 dest[i] = swab32(src[i]);273}274#endif275 276static DEFINE_SPINLOCK(mdio_lock);277static struct eth_regs __iomem *mdio_regs; /* mdio command and status only */278static struct mii_bus *mdio_bus;279static struct device_node *mdio_bus_np;280static int ports_open;281static struct port *npe_port_tab[MAX_NPES];282static struct dma_pool *dma_pool;283 284static int ixp_ptp_match(struct sk_buff *skb, u16 uid_hi, u32 uid_lo, u16 seqid)285{286 u8 *data = skb->data;287 unsigned int offset;288 u16 *hi, *id;289 u32 lo;290 291 if (ptp_classify_raw(skb) != PTP_CLASS_V1_IPV4)292 return 0;293 294 offset = ETH_HLEN + IPV4_HLEN(data) + UDP_HLEN;295 296 if (skb->len < offset + OFF_PTP_SEQUENCE_ID + sizeof(seqid))297 return 0;298 299 hi = (u16 *)(data + offset + OFF_PTP_SOURCE_UUID);300 id = (u16 *)(data + offset + OFF_PTP_SEQUENCE_ID);301 302 memcpy(&lo, &hi[1], sizeof(lo));303 304 return (uid_hi == ntohs(*hi) &&305 uid_lo == ntohl(lo) &&306 seqid == ntohs(*id));307}308 309static void ixp_rx_timestamp(struct port *port, struct sk_buff *skb)310{311 struct skb_shared_hwtstamps *shhwtstamps;312 struct ixp46x_ts_regs *regs;313 u64 ns;314 u32 ch, hi, lo, val;315 u16 uid, seq;316 317 if (!port->hwts_rx_en)318 return;319 320 ch = PORT2CHANNEL(port);321 322 regs = port->timesync_regs;323 324 val = __raw_readl(®s->channel[ch].ch_event);325 326 if (!(val & RX_SNAPSHOT_LOCKED))327 return;328 329 lo = __raw_readl(®s->channel[ch].src_uuid_lo);330 hi = __raw_readl(®s->channel[ch].src_uuid_hi);331 332 uid = hi & 0xffff;333 seq = (hi >> 16) & 0xffff;334 335 if (!ixp_ptp_match(skb, htons(uid), htonl(lo), htons(seq)))336 goto out;337 338 lo = __raw_readl(®s->channel[ch].rx_snap_lo);339 hi = __raw_readl(®s->channel[ch].rx_snap_hi);340 ns = ((u64) hi) << 32;341 ns |= lo;342 ns <<= TICKS_NS_SHIFT;343 344 shhwtstamps = skb_hwtstamps(skb);345 memset(shhwtstamps, 0, sizeof(*shhwtstamps));346 shhwtstamps->hwtstamp = ns_to_ktime(ns);347out:348 __raw_writel(RX_SNAPSHOT_LOCKED, ®s->channel[ch].ch_event);349}350 351static void ixp_tx_timestamp(struct port *port, struct sk_buff *skb)352{353 struct skb_shared_hwtstamps shhwtstamps;354 struct ixp46x_ts_regs *regs;355 struct skb_shared_info *shtx;356 u64 ns;357 u32 ch, cnt, hi, lo, val;358 359 shtx = skb_shinfo(skb);360 if (unlikely(shtx->tx_flags & SKBTX_HW_TSTAMP && port->hwts_tx_en))361 shtx->tx_flags |= SKBTX_IN_PROGRESS;362 else363 return;364 365 ch = PORT2CHANNEL(port);366 367 regs = port->timesync_regs;368 369 /*370 * This really stinks, but we have to poll for the Tx time stamp.371 * Usually, the time stamp is ready after 4 to 6 microseconds.372 */373 for (cnt = 0; cnt < 100; cnt++) {374 val = __raw_readl(®s->channel[ch].ch_event);375 if (val & TX_SNAPSHOT_LOCKED)376 break;377 udelay(1);378 }379 if (!(val & TX_SNAPSHOT_LOCKED)) {380 shtx->tx_flags &= ~SKBTX_IN_PROGRESS;381 return;382 }383 384 lo = __raw_readl(®s->channel[ch].tx_snap_lo);385 hi = __raw_readl(®s->channel[ch].tx_snap_hi);386 ns = ((u64) hi) << 32;387 ns |= lo;388 ns <<= TICKS_NS_SHIFT;389 390 memset(&shhwtstamps, 0, sizeof(shhwtstamps));391 shhwtstamps.hwtstamp = ns_to_ktime(ns);392 skb_tstamp_tx(skb, &shhwtstamps);393 394 __raw_writel(TX_SNAPSHOT_LOCKED, ®s->channel[ch].ch_event);395}396 397static int hwtstamp_set(struct net_device *netdev, struct ifreq *ifr)398{399 struct hwtstamp_config cfg;400 struct ixp46x_ts_regs *regs;401 struct port *port = netdev_priv(netdev);402 int ret;403 int ch;404 405 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))406 return -EFAULT;407 408 ret = ixp46x_ptp_find(&port->timesync_regs, &port->phc_index);409 if (ret)410 return ret;411 412 ch = PORT2CHANNEL(port);413 regs = port->timesync_regs;414 415 if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)416 return -ERANGE;417 418 switch (cfg.rx_filter) {419 case HWTSTAMP_FILTER_NONE:420 port->hwts_rx_en = 0;421 break;422 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:423 port->hwts_rx_en = PTP_SLAVE_MODE;424 __raw_writel(0, ®s->channel[ch].ch_control);425 break;426 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:427 port->hwts_rx_en = PTP_MASTER_MODE;428 __raw_writel(MASTER_MODE, ®s->channel[ch].ch_control);429 break;430 default:431 return -ERANGE;432 }433 434 port->hwts_tx_en = cfg.tx_type == HWTSTAMP_TX_ON;435 436 /* Clear out any old time stamps. */437 __raw_writel(TX_SNAPSHOT_LOCKED | RX_SNAPSHOT_LOCKED,438 ®s->channel[ch].ch_event);439 440 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;441}442 443static int hwtstamp_get(struct net_device *netdev, struct ifreq *ifr)444{445 struct hwtstamp_config cfg;446 struct port *port = netdev_priv(netdev);447 448 cfg.flags = 0;449 cfg.tx_type = port->hwts_tx_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;450 451 switch (port->hwts_rx_en) {452 case 0:453 cfg.rx_filter = HWTSTAMP_FILTER_NONE;454 break;455 case PTP_SLAVE_MODE:456 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;457 break;458 case PTP_MASTER_MODE:459 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;460 break;461 default:462 WARN_ON_ONCE(1);463 return -ERANGE;464 }465 466 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;467}468 469static int ixp4xx_mdio_cmd(struct mii_bus *bus, int phy_id, int location,470 int write, u16 cmd)471{472 int cycles = 0;473 474 if (__raw_readl(&mdio_regs->mdio_command[3]) & 0x80) {475 printk(KERN_ERR "%s: MII not ready to transmit\n", bus->name);476 return -1;477 }478 479 if (write) {480 __raw_writel(cmd & 0xFF, &mdio_regs->mdio_command[0]);481 __raw_writel(cmd >> 8, &mdio_regs->mdio_command[1]);482 }483 __raw_writel(((phy_id << 5) | location) & 0xFF,484 &mdio_regs->mdio_command[2]);485 __raw_writel((phy_id >> 3) | (write << 2) | 0x80 /* GO */,486 &mdio_regs->mdio_command[3]);487 488 while ((cycles < MAX_MDIO_RETRIES) &&489 (__raw_readl(&mdio_regs->mdio_command[3]) & 0x80)) {490 udelay(1);491 cycles++;492 }493 494 if (cycles == MAX_MDIO_RETRIES) {495 printk(KERN_ERR "%s #%i: MII write failed\n", bus->name,496 phy_id);497 return -1;498 }499 500#if DEBUG_MDIO501 printk(KERN_DEBUG "%s #%i: mdio_%s() took %i cycles\n", bus->name,502 phy_id, write ? "write" : "read", cycles);503#endif504 505 if (write)506 return 0;507 508 if (__raw_readl(&mdio_regs->mdio_status[3]) & 0x80) {509#if DEBUG_MDIO510 printk(KERN_DEBUG "%s #%i: MII read failed\n", bus->name,511 phy_id);512#endif513 return 0xFFFF; /* don't return error */514 }515 516 return (__raw_readl(&mdio_regs->mdio_status[0]) & 0xFF) |517 ((__raw_readl(&mdio_regs->mdio_status[1]) & 0xFF) << 8);518}519 520static int ixp4xx_mdio_read(struct mii_bus *bus, int phy_id, int location)521{522 unsigned long flags;523 int ret;524 525 spin_lock_irqsave(&mdio_lock, flags);526 ret = ixp4xx_mdio_cmd(bus, phy_id, location, 0, 0);527 spin_unlock_irqrestore(&mdio_lock, flags);528#if DEBUG_MDIO529 printk(KERN_DEBUG "%s #%i: MII read [%i] -> 0x%X\n", bus->name,530 phy_id, location, ret);531#endif532 return ret;533}534 535static int ixp4xx_mdio_write(struct mii_bus *bus, int phy_id, int location,536 u16 val)537{538 unsigned long flags;539 int ret;540 541 spin_lock_irqsave(&mdio_lock, flags);542 ret = ixp4xx_mdio_cmd(bus, phy_id, location, 1, val);543 spin_unlock_irqrestore(&mdio_lock, flags);544#if DEBUG_MDIO545 printk(KERN_DEBUG "%s #%i: MII write [%i] <- 0x%X, err = %i\n",546 bus->name, phy_id, location, val, ret);547#endif548 return ret;549}550 551static int ixp4xx_mdio_register(struct eth_regs __iomem *regs)552{553 int err;554 555 if (!(mdio_bus = mdiobus_alloc()))556 return -ENOMEM;557 558 mdio_regs = regs;559 __raw_writel(DEFAULT_CORE_CNTRL, &mdio_regs->core_control);560 mdio_bus->name = "IXP4xx MII Bus";561 mdio_bus->read = &ixp4xx_mdio_read;562 mdio_bus->write = &ixp4xx_mdio_write;563 snprintf(mdio_bus->id, MII_BUS_ID_SIZE, "ixp4xx-eth-0");564 565 err = of_mdiobus_register(mdio_bus, mdio_bus_np);566 if (err)567 mdiobus_free(mdio_bus);568 return err;569}570 571static void ixp4xx_mdio_remove(void)572{573 mdiobus_unregister(mdio_bus);574 mdiobus_free(mdio_bus);575}576 577 578static void ixp4xx_adjust_link(struct net_device *dev)579{580 struct port *port = netdev_priv(dev);581 struct phy_device *phydev = dev->phydev;582 583 if (!phydev->link) {584 if (port->speed) {585 port->speed = 0;586 printk(KERN_INFO "%s: link down\n", dev->name);587 }588 return;589 }590 591 if (port->speed == phydev->speed && port->duplex == phydev->duplex)592 return;593 594 port->speed = phydev->speed;595 port->duplex = phydev->duplex;596 597 if (port->duplex)598 __raw_writel(DEFAULT_TX_CNTRL0 & ~TX_CNTRL0_HALFDUPLEX,599 &port->regs->tx_control[0]);600 else601 __raw_writel(DEFAULT_TX_CNTRL0 | TX_CNTRL0_HALFDUPLEX,602 &port->regs->tx_control[0]);603 604 netdev_info(dev, "%s: link up, speed %u Mb/s, %s duplex\n",605 dev->name, port->speed, port->duplex ? "full" : "half");606}607 608 609static inline void debug_pkt(struct net_device *dev, const char *func,610 u8 *data, int len)611{612#if DEBUG_PKT_BYTES613 int i;614 615 netdev_debug(dev, "%s(%i) ", func, len);616 for (i = 0; i < len; i++) {617 if (i >= DEBUG_PKT_BYTES)618 break;619 printk("%s%02X",620 ((i == 6) || (i == 12) || (i >= 14)) ? " " : "",621 data[i]);622 }623 printk("\n");624#endif625}626 627 628static inline void debug_desc(u32 phys, struct desc *desc)629{630#if DEBUG_DESC631 printk(KERN_DEBUG "%X: %X %3X %3X %08X %2X < %2X %4X %X"632 " %X %X %02X%02X%02X%02X%02X%02X < %02X%02X%02X%02X%02X%02X\n",633 phys, desc->next, desc->buf_len, desc->pkt_len,634 desc->data, desc->dest_id, desc->src_id, desc->flags,635 desc->qos, desc->padlen, desc->vlan_tci,636 desc->dst_mac_0, desc->dst_mac_1, desc->dst_mac_2,637 desc->dst_mac_3, desc->dst_mac_4, desc->dst_mac_5,638 desc->src_mac_0, desc->src_mac_1, desc->src_mac_2,639 desc->src_mac_3, desc->src_mac_4, desc->src_mac_5);640#endif641}642 643static inline int queue_get_desc(unsigned int queue, struct port *port,644 int is_tx)645{646 u32 phys, tab_phys, n_desc;647 struct desc *tab;648 649 if (!(phys = qmgr_get_entry(queue)))650 return -1;651 652 phys &= ~0x1F; /* mask out non-address bits */653 tab_phys = is_tx ? tx_desc_phys(port, 0) : rx_desc_phys(port, 0);654 tab = is_tx ? tx_desc_ptr(port, 0) : rx_desc_ptr(port, 0);655 n_desc = (phys - tab_phys) / sizeof(struct desc);656 BUG_ON(n_desc >= (is_tx ? TX_DESCS : RX_DESCS));657 debug_desc(phys, &tab[n_desc]);658 BUG_ON(tab[n_desc].next);659 return n_desc;660}661 662static inline void queue_put_desc(unsigned int queue, u32 phys,663 struct desc *desc)664{665 debug_desc(phys, desc);666 BUG_ON(phys & 0x1F);667 qmgr_put_entry(queue, phys);668 /* Don't check for queue overflow here, we've allocated sufficient669 length and queues >= 32 don't support this check anyway. */670}671 672 673static inline void dma_unmap_tx(struct port *port, struct desc *desc)674{675#ifdef __ARMEB__676 dma_unmap_single(&port->netdev->dev, desc->data,677 desc->buf_len, DMA_TO_DEVICE);678#else679 dma_unmap_single(&port->netdev->dev, desc->data & ~3,680 ALIGN((desc->data & 3) + desc->buf_len, 4),681 DMA_TO_DEVICE);682#endif683}684 685 686static void eth_rx_irq(void *pdev)687{688 struct net_device *dev = pdev;689 struct port *port = netdev_priv(dev);690 691#if DEBUG_RX692 printk(KERN_DEBUG "%s: eth_rx_irq\n", dev->name);693#endif694 qmgr_disable_irq(port->plat->rxq);695 napi_schedule(&port->napi);696}697 698static int eth_poll(struct napi_struct *napi, int budget)699{700 struct port *port = container_of(napi, struct port, napi);701 struct net_device *dev = port->netdev;702 unsigned int rxq = port->plat->rxq, rxfreeq = RXFREE_QUEUE(port->id);703 int received = 0;704 705#if DEBUG_RX706 netdev_debug(dev, "eth_poll\n");707#endif708 709 while (received < budget) {710 struct sk_buff *skb;711 struct desc *desc;712 int n;713#ifdef __ARMEB__714 struct sk_buff *temp;715 u32 phys;716#endif717 718 if ((n = queue_get_desc(rxq, port, 0)) < 0) {719#if DEBUG_RX720 netdev_debug(dev, "eth_poll napi_complete\n");721#endif722 napi_complete(napi);723 qmgr_enable_irq(rxq);724 if (!qmgr_stat_below_low_watermark(rxq) &&725 napi_schedule(napi)) { /* not empty again */726#if DEBUG_RX727 netdev_debug(dev, "eth_poll napi_schedule succeeded\n");728#endif729 qmgr_disable_irq(rxq);730 continue;731 }732#if DEBUG_RX733 netdev_debug(dev, "eth_poll all done\n");734#endif735 return received; /* all work done */736 }737 738 desc = rx_desc_ptr(port, n);739 740#ifdef __ARMEB__741 if ((skb = netdev_alloc_skb(dev, RX_BUFF_SIZE))) {742 phys = dma_map_single(&dev->dev, skb->data,743 RX_BUFF_SIZE, DMA_FROM_DEVICE);744 if (dma_mapping_error(&dev->dev, phys)) {745 dev_kfree_skb(skb);746 skb = NULL;747 }748 }749#else750 skb = netdev_alloc_skb(dev,751 ALIGN(NET_IP_ALIGN + desc->pkt_len, 4));752#endif753 754 if (!skb) {755 dev->stats.rx_dropped++;756 /* put the desc back on RX-ready queue */757 desc->buf_len = MAX_MRU;758 desc->pkt_len = 0;759 queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);760 continue;761 }762 763 /* process received frame */764#ifdef __ARMEB__765 temp = skb;766 skb = port->rx_buff_tab[n];767 dma_unmap_single(&dev->dev, desc->data - NET_IP_ALIGN,768 RX_BUFF_SIZE, DMA_FROM_DEVICE);769#else770 dma_sync_single_for_cpu(&dev->dev, desc->data - NET_IP_ALIGN,771 RX_BUFF_SIZE, DMA_FROM_DEVICE);772 memcpy_swab32((u32 *)skb->data, (u32 *)port->rx_buff_tab[n],773 ALIGN(NET_IP_ALIGN + desc->pkt_len, 4) / 4);774#endif775 skb_reserve(skb, NET_IP_ALIGN);776 skb_put(skb, desc->pkt_len);777 778 debug_pkt(dev, "eth_poll", skb->data, skb->len);779 780 ixp_rx_timestamp(port, skb);781 skb->protocol = eth_type_trans(skb, dev);782 dev->stats.rx_packets++;783 dev->stats.rx_bytes += skb->len;784 netif_receive_skb(skb);785 786 /* put the new buffer on RX-free queue */787#ifdef __ARMEB__788 port->rx_buff_tab[n] = temp;789 desc->data = phys + NET_IP_ALIGN;790#endif791 desc->buf_len = MAX_MRU;792 desc->pkt_len = 0;793 queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);794 received++;795 }796 797#if DEBUG_RX798 netdev_debug(dev, "eth_poll(): end, not all work done\n");799#endif800 return received; /* not all work done */801}802 803 804static void eth_txdone_irq(void *unused)805{806 u32 phys;807 808#if DEBUG_TX809 printk(KERN_DEBUG DRV_NAME ": eth_txdone_irq\n");810#endif811 while ((phys = qmgr_get_entry(TXDONE_QUEUE)) != 0) {812 u32 npe_id, n_desc;813 struct port *port;814 struct desc *desc;815 int start;816 817 npe_id = phys & 3;818 BUG_ON(npe_id >= MAX_NPES);819 port = npe_port_tab[npe_id];820 BUG_ON(!port);821 phys &= ~0x1F; /* mask out non-address bits */822 n_desc = (phys - tx_desc_phys(port, 0)) / sizeof(struct desc);823 BUG_ON(n_desc >= TX_DESCS);824 desc = tx_desc_ptr(port, n_desc);825 debug_desc(phys, desc);826 827 if (port->tx_buff_tab[n_desc]) { /* not the draining packet */828 port->netdev->stats.tx_packets++;829 port->netdev->stats.tx_bytes += desc->pkt_len;830 831 dma_unmap_tx(port, desc);832#if DEBUG_TX833 printk(KERN_DEBUG "%s: eth_txdone_irq free %p\n",834 port->netdev->name, port->tx_buff_tab[n_desc]);835#endif836 free_buffer_irq(port->tx_buff_tab[n_desc]);837 port->tx_buff_tab[n_desc] = NULL;838 }839 840 start = qmgr_stat_below_low_watermark(port->plat->txreadyq);841 queue_put_desc(port->plat->txreadyq, phys, desc);842 if (start) { /* TX-ready queue was empty */843#if DEBUG_TX844 printk(KERN_DEBUG "%s: eth_txdone_irq xmit ready\n",845 port->netdev->name);846#endif847 netif_wake_queue(port->netdev);848 }849 }850}851 852static netdev_tx_t eth_xmit(struct sk_buff *skb, struct net_device *dev)853{854 struct port *port = netdev_priv(dev);855 unsigned int txreadyq = port->plat->txreadyq;856 int len, offset, bytes, n;857 void *mem;858 u32 phys;859 struct desc *desc;860 861#if DEBUG_TX862 netdev_debug(dev, "eth_xmit\n");863#endif864 865 if (unlikely(skb->len > MAX_MRU)) {866 dev_kfree_skb(skb);867 dev->stats.tx_errors++;868 return NETDEV_TX_OK;869 }870 871 debug_pkt(dev, "eth_xmit", skb->data, skb->len);872 873 len = skb->len;874#ifdef __ARMEB__875 offset = 0; /* no need to keep alignment */876 bytes = len;877 mem = skb->data;878#else879 offset = (uintptr_t)skb->data & 3; /* keep 32-bit alignment */880 bytes = ALIGN(offset + len, 4);881 if (!(mem = kmalloc(bytes, GFP_ATOMIC))) {882 dev_kfree_skb(skb);883 dev->stats.tx_dropped++;884 return NETDEV_TX_OK;885 }886 memcpy_swab32(mem, (u32 *)((uintptr_t)skb->data & ~3), bytes / 4);887#endif888 889 phys = dma_map_single(&dev->dev, mem, bytes, DMA_TO_DEVICE);890 if (dma_mapping_error(&dev->dev, phys)) {891 dev_kfree_skb(skb);892#ifndef __ARMEB__893 kfree(mem);894#endif895 dev->stats.tx_dropped++;896 return NETDEV_TX_OK;897 }898 899 n = queue_get_desc(txreadyq, port, 1);900 BUG_ON(n < 0);901 desc = tx_desc_ptr(port, n);902 903#ifdef __ARMEB__904 port->tx_buff_tab[n] = skb;905#else906 port->tx_buff_tab[n] = mem;907#endif908 desc->data = phys + offset;909 desc->buf_len = desc->pkt_len = len;910 911 /* NPE firmware pads short frames with zeros internally */912 wmb();913 queue_put_desc(TX_QUEUE(port->id), tx_desc_phys(port, n), desc);914 915 if (qmgr_stat_below_low_watermark(txreadyq)) { /* empty */916#if DEBUG_TX917 netdev_debug(dev, "eth_xmit queue full\n");918#endif919 netif_stop_queue(dev);920 /* we could miss TX ready interrupt */921 /* really empty in fact */922 if (!qmgr_stat_below_low_watermark(txreadyq)) {923#if DEBUG_TX924 netdev_debug(dev, "eth_xmit ready again\n");925#endif926 netif_wake_queue(dev);927 }928 }929 930#if DEBUG_TX931 netdev_debug(dev, "eth_xmit end\n");932#endif933 934 ixp_tx_timestamp(port, skb);935 skb_tx_timestamp(skb);936 937#ifndef __ARMEB__938 dev_kfree_skb(skb);939#endif940 return NETDEV_TX_OK;941}942 943 944static void eth_set_mcast_list(struct net_device *dev)945{946 struct port *port = netdev_priv(dev);947 struct netdev_hw_addr *ha;948 u8 diffs[ETH_ALEN], *addr;949 int i;950 static const u8 allmulti[] = { 0x01, 0x00, 0x00, 0x00, 0x00, 0x00 };951 952 if ((dev->flags & IFF_ALLMULTI) && !(dev->flags & IFF_PROMISC)) {953 for (i = 0; i < ETH_ALEN; i++) {954 __raw_writel(allmulti[i], &port->regs->mcast_addr[i]);955 __raw_writel(allmulti[i], &port->regs->mcast_mask[i]);956 }957 __raw_writel(DEFAULT_RX_CNTRL0 | RX_CNTRL0_ADDR_FLTR_EN,958 &port->regs->rx_control[0]);959 return;960 }961 962 if ((dev->flags & IFF_PROMISC) || netdev_mc_empty(dev)) {963 __raw_writel(DEFAULT_RX_CNTRL0 & ~RX_CNTRL0_ADDR_FLTR_EN,964 &port->regs->rx_control[0]);965 return;966 }967 968 eth_zero_addr(diffs);969 970 addr = NULL;971 netdev_for_each_mc_addr(ha, dev) {972 if (!addr)973 addr = ha->addr; /* first MAC address */974 for (i = 0; i < ETH_ALEN; i++)975 diffs[i] |= addr[i] ^ ha->addr[i];976 }977 978 for (i = 0; i < ETH_ALEN; i++) {979 __raw_writel(addr[i], &port->regs->mcast_addr[i]);980 __raw_writel(~diffs[i], &port->regs->mcast_mask[i]);981 }982 983 __raw_writel(DEFAULT_RX_CNTRL0 | RX_CNTRL0_ADDR_FLTR_EN,984 &port->regs->rx_control[0]);985}986 987 988static int eth_ioctl(struct net_device *dev, struct ifreq *req, int cmd)989{990 if (!netif_running(dev))991 return -EINVAL;992 993 if (cpu_is_ixp46x()) {994 if (cmd == SIOCSHWTSTAMP)995 return hwtstamp_set(dev, req);996 if (cmd == SIOCGHWTSTAMP)997 return hwtstamp_get(dev, req);998 }999 1000 return phy_mii_ioctl(dev->phydev, req, cmd);1001}1002 1003/* ethtool support */1004 1005static void ixp4xx_get_drvinfo(struct net_device *dev,1006 struct ethtool_drvinfo *info)1007{1008 struct port *port = netdev_priv(dev);1009 1010 strscpy(info->driver, DRV_NAME, sizeof(info->driver));1011 snprintf(info->fw_version, sizeof(info->fw_version), "%u:%u:%u:%u",1012 port->firmware[0], port->firmware[1],1013 port->firmware[2], port->firmware[3]);1014 strscpy(info->bus_info, "internal", sizeof(info->bus_info));1015}1016 1017static int ixp4xx_get_ts_info(struct net_device *dev,1018 struct kernel_ethtool_ts_info *info)1019{1020 struct port *port = netdev_priv(dev);1021 1022 if (port->phc_index < 0)1023 ixp46x_ptp_find(&port->timesync_regs, &port->phc_index);1024 1025 info->phc_index = port->phc_index;1026 1027 if (info->phc_index < 0) {1028 info->so_timestamping =1029 SOF_TIMESTAMPING_TX_SOFTWARE;1030 return 0;1031 }1032 info->so_timestamping =1033 SOF_TIMESTAMPING_TX_HARDWARE |1034 SOF_TIMESTAMPING_RX_HARDWARE |1035 SOF_TIMESTAMPING_RAW_HARDWARE;1036 info->tx_types =1037 (1 << HWTSTAMP_TX_OFF) |1038 (1 << HWTSTAMP_TX_ON);1039 info->rx_filters =1040 (1 << HWTSTAMP_FILTER_NONE) |1041 (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |1042 (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ);1043 return 0;1044}1045 1046static const struct ethtool_ops ixp4xx_ethtool_ops = {1047 .get_drvinfo = ixp4xx_get_drvinfo,1048 .nway_reset = phy_ethtool_nway_reset,1049 .get_link = ethtool_op_get_link,1050 .get_ts_info = ixp4xx_get_ts_info,1051 .get_link_ksettings = phy_ethtool_get_link_ksettings,1052 .set_link_ksettings = phy_ethtool_set_link_ksettings,1053};1054 1055 1056static int request_queues(struct port *port)1057{1058 int err;1059 1060 err = qmgr_request_queue(RXFREE_QUEUE(port->id), RX_DESCS, 0, 0,1061 "%s:RX-free", port->netdev->name);1062 if (err)1063 return err;1064 1065 err = qmgr_request_queue(port->plat->rxq, RX_DESCS, 0, 0,1066 "%s:RX", port->netdev->name);1067 if (err)1068 goto rel_rxfree;1069 1070 err = qmgr_request_queue(TX_QUEUE(port->id), TX_DESCS, 0, 0,1071 "%s:TX", port->netdev->name);1072 if (err)1073 goto rel_rx;1074 1075 err = qmgr_request_queue(port->plat->txreadyq, TX_DESCS, 0, 0,1076 "%s:TX-ready", port->netdev->name);1077 if (err)1078 goto rel_tx;1079 1080 /* TX-done queue handles skbs sent out by the NPEs */1081 if (!ports_open) {1082 err = qmgr_request_queue(TXDONE_QUEUE, TXDONE_QUEUE_LEN, 0, 0,1083 "%s:TX-done", DRV_NAME);1084 if (err)1085 goto rel_txready;1086 }1087 return 0;1088 1089rel_txready:1090 qmgr_release_queue(port->plat->txreadyq);1091rel_tx:1092 qmgr_release_queue(TX_QUEUE(port->id));1093rel_rx:1094 qmgr_release_queue(port->plat->rxq);1095rel_rxfree:1096 qmgr_release_queue(RXFREE_QUEUE(port->id));1097 printk(KERN_DEBUG "%s: unable to request hardware queues\n",1098 port->netdev->name);1099 return err;1100}1101 1102static void release_queues(struct port *port)1103{1104 qmgr_release_queue(RXFREE_QUEUE(port->id));1105 qmgr_release_queue(port->plat->rxq);1106 qmgr_release_queue(TX_QUEUE(port->id));1107 qmgr_release_queue(port->plat->txreadyq);1108 1109 if (!ports_open)1110 qmgr_release_queue(TXDONE_QUEUE);1111}1112 1113static int init_queues(struct port *port)1114{1115 int i;1116 1117 if (!ports_open) {1118 dma_pool = dma_pool_create(DRV_NAME, &port->netdev->dev,1119 POOL_ALLOC_SIZE, 32, 0);1120 if (!dma_pool)1121 return -ENOMEM;1122 }1123 1124 port->desc_tab = dma_pool_zalloc(dma_pool, GFP_KERNEL, &port->desc_tab_phys);1125 if (!port->desc_tab)1126 return -ENOMEM;1127 memset(port->rx_buff_tab, 0, sizeof(port->rx_buff_tab)); /* tables */1128 memset(port->tx_buff_tab, 0, sizeof(port->tx_buff_tab));1129 1130 /* Setup RX buffers */1131 for (i = 0; i < RX_DESCS; i++) {1132 struct desc *desc = rx_desc_ptr(port, i);1133 buffer_t *buff; /* skb or kmalloc()ated memory */1134 void *data;1135#ifdef __ARMEB__1136 if (!(buff = netdev_alloc_skb(port->netdev, RX_BUFF_SIZE)))1137 return -ENOMEM;1138 data = buff->data;1139#else1140 if (!(buff = kmalloc(RX_BUFF_SIZE, GFP_KERNEL)))1141 return -ENOMEM;1142 data = buff;1143#endif1144 desc->buf_len = MAX_MRU;1145 desc->data = dma_map_single(&port->netdev->dev, data,1146 RX_BUFF_SIZE, DMA_FROM_DEVICE);1147 if (dma_mapping_error(&port->netdev->dev, desc->data)) {1148 free_buffer(buff);1149 return -EIO;1150 }1151 desc->data += NET_IP_ALIGN;1152 port->rx_buff_tab[i] = buff;1153 }1154 1155 return 0;1156}1157 1158static void destroy_queues(struct port *port)1159{1160 int i;1161 1162 if (port->desc_tab) {1163 for (i = 0; i < RX_DESCS; i++) {1164 struct desc *desc = rx_desc_ptr(port, i);1165 buffer_t *buff = port->rx_buff_tab[i];1166 if (buff) {1167 dma_unmap_single(&port->netdev->dev,1168 desc->data - NET_IP_ALIGN,1169 RX_BUFF_SIZE, DMA_FROM_DEVICE);1170 free_buffer(buff);1171 }1172 }1173 for (i = 0; i < TX_DESCS; i++) {1174 struct desc *desc = tx_desc_ptr(port, i);1175 buffer_t *buff = port->tx_buff_tab[i];1176 if (buff) {1177 dma_unmap_tx(port, desc);1178 free_buffer(buff);1179 }1180 }1181 dma_pool_free(dma_pool, port->desc_tab, port->desc_tab_phys);1182 port->desc_tab = NULL;1183 }1184 1185 if (!ports_open && dma_pool) {1186 dma_pool_destroy(dma_pool);1187 dma_pool = NULL;1188 }1189}1190 1191static int ixp4xx_do_change_mtu(struct net_device *dev, int new_mtu)1192{1193 struct port *port = netdev_priv(dev);1194 struct npe *npe = port->npe;1195 int framesize, chunks;1196 struct msg msg = {};1197 1198 /* adjust for ethernet headers */1199 framesize = new_mtu + VLAN_ETH_HLEN;1200 /* max rx/tx 64 byte chunks */1201 chunks = DIV_ROUND_UP(framesize, 64);1202 1203 msg.cmd = NPE_SETMAXFRAMELENGTHS;1204 msg.eth_id = port->id;1205 1206 /* Firmware wants to know buffer size in 64 byte chunks */1207 msg.byte2 = chunks << 8;1208 msg.byte3 = chunks << 8;1209 1210 msg.byte4 = msg.byte6 = framesize >> 8;1211 msg.byte5 = msg.byte7 = framesize & 0xff;1212 1213 if (npe_send_recv_message(npe, &msg, "ETH_SET_MAX_FRAME_LENGTH"))1214 return -EIO;1215 netdev_dbg(dev, "set MTU on NPE %s to %d bytes\n",1216 npe_name(npe), new_mtu);1217 1218 return 0;1219}1220 1221static int ixp4xx_eth_change_mtu(struct net_device *dev, int new_mtu)1222{1223 int ret;1224 1225 /* MTU can only be changed when the interface is up. We also1226 * set the MTU from dev->mtu when opening the device.1227 */1228 if (dev->flags & IFF_UP) {1229 ret = ixp4xx_do_change_mtu(dev, new_mtu);1230 if (ret < 0)1231 return ret;1232 }1233 1234 WRITE_ONCE(dev->mtu, new_mtu);1235 1236 return 0;1237}1238 1239static int eth_open(struct net_device *dev)1240{1241 struct port *port = netdev_priv(dev);1242 struct npe *npe = port->npe;1243 struct msg msg;1244 int i, err;1245 1246 if (!npe_running(npe)) {1247 err = npe_load_firmware(npe, npe_name(npe), &dev->dev);1248 if (err)1249 return err;1250 1251 if (npe_recv_message(npe, &msg, "ETH_GET_STATUS")) {1252 netdev_err(dev, "%s not responding\n", npe_name(npe));1253 return -EIO;1254 }1255 port->firmware[0] = msg.byte4;1256 port->firmware[1] = msg.byte5;1257 port->firmware[2] = msg.byte6;1258 port->firmware[3] = msg.byte7;1259 }1260 1261 memset(&msg, 0, sizeof(msg));1262 msg.cmd = NPE_VLAN_SETRXQOSENTRY;1263 msg.eth_id = port->id;1264 msg.byte5 = port->plat->rxq | 0x80;1265 msg.byte7 = port->plat->rxq << 4;1266 for (i = 0; i < 8; i++) {1267 msg.byte3 = i;1268 if (npe_send_recv_message(port->npe, &msg, "ETH_SET_RXQ"))1269 return -EIO;1270 }1271 1272 msg.cmd = NPE_EDB_SETPORTADDRESS;1273 msg.eth_id = PHYSICAL_ID(port->id);1274 msg.byte2 = dev->dev_addr[0];1275 msg.byte3 = dev->dev_addr[1];1276 msg.byte4 = dev->dev_addr[2];1277 msg.byte5 = dev->dev_addr[3];1278 msg.byte6 = dev->dev_addr[4];1279 msg.byte7 = dev->dev_addr[5];1280 if (npe_send_recv_message(port->npe, &msg, "ETH_SET_MAC"))1281 return -EIO;1282 1283 memset(&msg, 0, sizeof(msg));1284 msg.cmd = NPE_FW_SETFIREWALLMODE;1285 msg.eth_id = port->id;1286 if (npe_send_recv_message(port->npe, &msg, "ETH_SET_FIREWALL_MODE"))1287 return -EIO;1288 1289 ixp4xx_do_change_mtu(dev, dev->mtu);1290 1291 if ((err = request_queues(port)) != 0)1292 return err;1293 1294 if ((err = init_queues(port)) != 0) {1295 destroy_queues(port);1296 release_queues(port);1297 return err;1298 }1299 1300 port->speed = 0; /* force "link up" message */1301 phy_start(dev->phydev);1302 1303 for (i = 0; i < ETH_ALEN; i++)1304 __raw_writel(dev->dev_addr[i], &port->regs->hw_addr[i]);1305 __raw_writel(0x08, &port->regs->random_seed);1306 __raw_writel(0x12, &port->regs->partial_empty_threshold);1307 __raw_writel(0x30, &port->regs->partial_full_threshold);1308 __raw_writel(0x08, &port->regs->tx_start_bytes);1309 __raw_writel(0x15, &port->regs->tx_deferral);1310 __raw_writel(0x08, &port->regs->tx_2part_deferral[0]);1311 __raw_writel(0x07, &port->regs->tx_2part_deferral[1]);1312 __raw_writel(0x80, &port->regs->slot_time);1313 __raw_writel(0x01, &port->regs->int_clock_threshold);1314 1315 /* Populate queues with buffers, no failure after this point */1316 for (i = 0; i < TX_DESCS; i++)1317 queue_put_desc(port->plat->txreadyq,1318 tx_desc_phys(port, i), tx_desc_ptr(port, i));1319 1320 for (i = 0; i < RX_DESCS; i++)1321 queue_put_desc(RXFREE_QUEUE(port->id),1322 rx_desc_phys(port, i), rx_desc_ptr(port, i));1323 1324 __raw_writel(TX_CNTRL1_RETRIES, &port->regs->tx_control[1]);1325 __raw_writel(DEFAULT_TX_CNTRL0, &port->regs->tx_control[0]);1326 __raw_writel(0, &port->regs->rx_control[1]);1327 __raw_writel(DEFAULT_RX_CNTRL0, &port->regs->rx_control[0]);1328 1329 napi_enable(&port->napi);1330 eth_set_mcast_list(dev);1331 netif_start_queue(dev);1332 1333 qmgr_set_irq(port->plat->rxq, QUEUE_IRQ_SRC_NOT_EMPTY,1334 eth_rx_irq, dev);1335 if (!ports_open) {1336 qmgr_set_irq(TXDONE_QUEUE, QUEUE_IRQ_SRC_NOT_EMPTY,1337 eth_txdone_irq, NULL);1338 qmgr_enable_irq(TXDONE_QUEUE);1339 }1340 ports_open++;1341 /* we may already have RX data, enables IRQ */1342 napi_schedule(&port->napi);1343 return 0;1344}1345 1346static int eth_close(struct net_device *dev)1347{1348 struct port *port = netdev_priv(dev);1349 struct msg msg;1350 int buffs = RX_DESCS; /* allocated RX buffers */1351 int i;1352 1353 ports_open--;1354 qmgr_disable_irq(port->plat->rxq);1355 napi_disable(&port->napi);1356 netif_stop_queue(dev);1357 1358 while (queue_get_desc(RXFREE_QUEUE(port->id), port, 0) >= 0)1359 buffs--;1360 1361 memset(&msg, 0, sizeof(msg));1362 msg.cmd = NPE_SETLOOPBACK_MODE;1363 msg.eth_id = port->id;1364 msg.byte3 = 1;1365 if (npe_send_recv_message(port->npe, &msg, "ETH_ENABLE_LOOPBACK"))1366 netdev_crit(dev, "unable to enable loopback\n");1367 1368 i = 0;1369 do { /* drain RX buffers */1370 while (queue_get_desc(port->plat->rxq, port, 0) >= 0)1371 buffs--;1372 if (!buffs)1373 break;1374 if (qmgr_stat_empty(TX_QUEUE(port->id))) {1375 /* we have to inject some packet */1376 struct desc *desc;1377 u32 phys;1378 int n = queue_get_desc(port->plat->txreadyq, port, 1);1379 BUG_ON(n < 0);1380 desc = tx_desc_ptr(port, n);1381 phys = tx_desc_phys(port, n);1382 desc->buf_len = desc->pkt_len = 1;1383 wmb();1384 queue_put_desc(TX_QUEUE(port->id), phys, desc);1385 }1386 udelay(1);1387 } while (++i < MAX_CLOSE_WAIT);1388 1389 if (buffs)1390 netdev_crit(dev, "unable to drain RX queue, %i buffer(s)"1391 " left in NPE\n", buffs);1392#if DEBUG_CLOSE1393 if (!buffs)1394 netdev_debug(dev, "draining RX queue took %i cycles\n", i);1395#endif1396 1397 buffs = TX_DESCS;1398 while (queue_get_desc(TX_QUEUE(port->id), port, 1) >= 0)1399 buffs--; /* cancel TX */1400 1401 i = 0;1402 do {1403 while (queue_get_desc(port->plat->txreadyq, port, 1) >= 0)1404 buffs--;1405 if (!buffs)1406 break;1407 } while (++i < MAX_CLOSE_WAIT);1408 1409 if (buffs)1410 netdev_crit(dev, "unable to drain TX queue, %i buffer(s) "1411 "left in NPE\n", buffs);1412#if DEBUG_CLOSE1413 if (!buffs)1414 netdev_debug(dev, "draining TX queues took %i cycles\n", i);1415#endif1416 1417 msg.byte3 = 0;1418 if (npe_send_recv_message(port->npe, &msg, "ETH_DISABLE_LOOPBACK"))1419 netdev_crit(dev, "unable to disable loopback\n");1420 1421 phy_stop(dev->phydev);1422 1423 if (!ports_open)1424 qmgr_disable_irq(TXDONE_QUEUE);1425 destroy_queues(port);1426 release_queues(port);1427 return 0;1428}1429 1430static const struct net_device_ops ixp4xx_netdev_ops = {1431 .ndo_open = eth_open,1432 .ndo_stop = eth_close,1433 .ndo_change_mtu = ixp4xx_eth_change_mtu,1434 .ndo_start_xmit = eth_xmit,1435 .ndo_set_rx_mode = eth_set_mcast_list,1436 .ndo_eth_ioctl = eth_ioctl,1437 .ndo_set_mac_address = eth_mac_addr,1438 .ndo_validate_addr = eth_validate_addr,1439};1440 1441static struct eth_plat_info *ixp4xx_of_get_platdata(struct device *dev)1442{1443 struct device_node *np = dev->of_node;1444 struct of_phandle_args queue_spec;1445 struct of_phandle_args npe_spec;1446 struct device_node *mdio_np;1447 struct eth_plat_info *plat;1448 u8 mac[ETH_ALEN];1449 int ret;1450 1451 plat = devm_kzalloc(dev, sizeof(*plat), GFP_KERNEL);1452 if (!plat)1453 return NULL;1454 1455 ret = of_parse_phandle_with_fixed_args(np, "intel,npe-handle", 1, 0,1456 &npe_spec);1457 if (ret) {1458 dev_err(dev, "no NPE engine specified\n");1459 return NULL;1460 }1461 /* NPE ID 0x00, 0x10, 0x20... */1462 plat->npe = (npe_spec.args[0] << 4);1463 1464 /* Check if this device has an MDIO bus */1465 mdio_np = of_get_child_by_name(np, "mdio");1466 if (mdio_np) {1467 plat->has_mdio = true;1468 mdio_bus_np = mdio_np;1469 /* DO NOT put the mdio_np, it will be used */1470 }1471 1472 /* Get the rx queue as a resource from queue manager */1473 ret = of_parse_phandle_with_fixed_args(np, "queue-rx", 1, 0,1474 &queue_spec);1475 if (ret) {1476 dev_err(dev, "no rx queue phandle\n");1477 return NULL;1478 }1479 plat->rxq = queue_spec.args[0];1480 1481 /* Get the txready queue as resource from queue manager */1482 ret = of_parse_phandle_with_fixed_args(np, "queue-txready", 1, 0,1483 &queue_spec);1484 if (ret) {1485 dev_err(dev, "no txready queue phandle\n");1486 return NULL;1487 }1488 plat->txreadyq = queue_spec.args[0];1489 1490 ret = of_get_mac_address(np, mac);1491 if (!ret) {1492 dev_info(dev, "Setting macaddr from DT %pM\n", mac);1493 memcpy(plat->hwaddr, mac, ETH_ALEN);1494 }1495 1496 return plat;1497}1498 1499static int ixp4xx_eth_probe(struct platform_device *pdev)1500{1501 struct phy_device *phydev = NULL;1502 struct device *dev = &pdev->dev;1503 struct device_node *np = dev->of_node;1504 struct eth_plat_info *plat;1505 struct net_device *ndev;1506 struct port *port;1507 int err;1508 1509 plat = ixp4xx_of_get_platdata(dev);1510 if (!plat)1511 return -ENODEV;1512 1513 if (!(ndev = devm_alloc_etherdev(dev, sizeof(struct port))))1514 return -ENOMEM;1515 1516 SET_NETDEV_DEV(ndev, dev);1517 port = netdev_priv(ndev);1518 port->netdev = ndev;1519 port->id = plat->npe;1520 port->phc_index = -1;1521 1522 /* Get the port resource and remap */1523 port->regs = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);1524 if (IS_ERR(port->regs))1525 return PTR_ERR(port->regs);1526 1527 /* Register the MDIO bus if we have it */1528 if (plat->has_mdio) {1529 err = ixp4xx_mdio_register(port->regs);1530 if (err) {1531 dev_err(dev, "failed to register MDIO bus\n");1532 return err;1533 }1534 }1535 /* If the instance with the MDIO bus has not yet appeared,1536 * defer probing until it gets probed.1537 */1538 if (!mdio_bus)1539 return -EPROBE_DEFER;1540 1541 ndev->netdev_ops = &ixp4xx_netdev_ops;1542 ndev->ethtool_ops = &ixp4xx_ethtool_ops;1543 ndev->tx_queue_len = 100;1544 /* Inherit the DMA masks from the platform device */1545 ndev->dev.dma_mask = dev->dma_mask;1546 ndev->dev.coherent_dma_mask = dev->coherent_dma_mask;1547 1548 ndev->min_mtu = ETH_MIN_MTU;1549 ndev->max_mtu = MAX_MRU;1550 1551 netif_napi_add_weight(ndev, &port->napi, eth_poll, NAPI_WEIGHT);1552 1553 if (!(port->npe = npe_request(NPE_ID(port->id))))1554 return -EIO;1555 1556 port->plat = plat;1557 npe_port_tab[NPE_ID(port->id)] = port;1558 if (is_valid_ether_addr(plat->hwaddr))1559 eth_hw_addr_set(ndev, plat->hwaddr);1560 else1561 eth_hw_addr_random(ndev);1562 1563 platform_set_drvdata(pdev, ndev);1564 1565 __raw_writel(DEFAULT_CORE_CNTRL | CORE_RESET,1566 &port->regs->core_control);1567 udelay(50);1568 __raw_writel(DEFAULT_CORE_CNTRL, &port->regs->core_control);1569 udelay(50);1570 1571 phydev = of_phy_get_and_connect(ndev, np, ixp4xx_adjust_link);1572 if (!phydev) {1573 err = -ENODEV;1574 dev_err(dev, "no phydev\n");1575 goto err_free_mem;1576 }1577 1578 phydev->irq = PHY_POLL;1579 1580 if ((err = register_netdev(ndev)))1581 goto err_phy_dis;1582 1583 netdev_info(ndev, "%s: MII PHY %s on %s\n", ndev->name, phydev_name(phydev),1584 npe_name(port->npe));1585 1586 return 0;1587 1588err_phy_dis:1589 phy_disconnect(phydev);1590err_free_mem:1591 npe_port_tab[NPE_ID(port->id)] = NULL;1592 npe_release(port->npe);1593 return err;1594}1595 1596static void ixp4xx_eth_remove(struct platform_device *pdev)1597{1598 struct net_device *ndev = platform_get_drvdata(pdev);1599 struct phy_device *phydev = ndev->phydev;1600 struct port *port = netdev_priv(ndev);1601 1602 unregister_netdev(ndev);1603 phy_disconnect(phydev);1604 ixp4xx_mdio_remove();1605 npe_port_tab[NPE_ID(port->id)] = NULL;1606 npe_release(port->npe);1607}1608 1609static const struct of_device_id ixp4xx_eth_of_match[] = {1610 {1611 .compatible = "intel,ixp4xx-ethernet",1612 },1613 { },1614};1615 1616static struct platform_driver ixp4xx_eth_driver = {1617 .driver = {1618 .name = DRV_NAME,1619 .of_match_table = of_match_ptr(ixp4xx_eth_of_match),1620 },1621 .probe = ixp4xx_eth_probe,1622 .remove_new = ixp4xx_eth_remove,1623};1624module_platform_driver(ixp4xx_eth_driver);1625 1626MODULE_AUTHOR("Krzysztof Halasa");1627MODULE_DESCRIPTION("Intel IXP4xx Ethernet driver");1628MODULE_LICENSE("GPL v2");1629MODULE_ALIAS("platform:ixp4xx_eth");1630