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1/* SPDX-License-Identifier: GPL-2.0-or-later */2/******************************************************************************3 *4 * (C)Copyright 1998,1999 SysKonnect,5 * a business unit of Schneider & Koch & Co. Datensysteme GmbH.6 *7 * The information in this file is provided "AS IS" without warranty.8 *9 ******************************************************************************/10 11/*12 * AMD Fplus in tag mode data structs13 * defs for fplustm.c14 */15 16#ifndef _FPLUS_17#define _FPLUS_18 19#ifndef HW_PTR20#define HW_PTR void __iomem *21#endif22 23/*24 * fplus error statistic structure25 */26struct err_st {27 u_long err_valid ; /* memory status valid */28 u_long err_abort ; /* memory status receive abort */29 u_long err_e_indicator ; /* error indicator */30 u_long err_crc ; /* error detected (CRC or length) */31 u_long err_llc_frame ; /* LLC frame */32 u_long err_mac_frame ; /* MAC frame */33 u_long err_smt_frame ; /* SMT frame */34 u_long err_imp_frame ; /* implementer frame */35 u_long err_no_buf ; /* no buffer available */36 u_long err_too_long ; /* longer than max. buffer */37 u_long err_bec_stat ; /* beacon state entered */38 u_long err_clm_stat ; /* claim state entered */39 u_long err_sifg_det ; /* short interframe gap detect */40 u_long err_phinv ; /* PHY invalid */41 u_long err_tkiss ; /* token issued */42 u_long err_tkerr ; /* token error */43} ;44 45/*46 * Transmit Descriptor struct47 */48struct s_smt_fp_txd {49 __le32 txd_tbctrl ; /* transmit buffer control */50 __le32 txd_txdscr ; /* transmit frame status word */51 __le32 txd_tbadr ; /* physical tx buffer address */52 __le32 txd_ntdadr ; /* physical pointer to the next TxD */53#ifdef ENA_64BIT_SUP54 __le32 txd_tbadr_hi ; /* physical tx buffer addr (high dword)*/55#endif56 char far *txd_virt ; /* virtual pointer to the data frag */57 /* virt pointer to the next TxD */58 struct s_smt_fp_txd volatile far *txd_next ;59 struct s_txd_os txd_os ; /* OS - specific struct */60} ;61 62/*63 * Receive Descriptor struct64 */65struct s_smt_fp_rxd {66 __le32 rxd_rbctrl ; /* receive buffer control */67 __le32 rxd_rfsw ; /* receive frame status word */68 __le32 rxd_rbadr ; /* physical rx buffer address */69 __le32 rxd_nrdadr ; /* physical pointer to the next RxD */70#ifdef ENA_64BIT_SUP71 __le32 rxd_rbadr_hi ; /* physical tx buffer addr (high dword)*/72#endif73 char far *rxd_virt ; /* virtual pointer to the data frag */74 /* virt pointer to the next RxD */75 struct s_smt_fp_rxd volatile far *rxd_next ;76 struct s_rxd_os rxd_os ; /* OS - specific struct */77} ;78 79/*80 * Descriptor Union Definition81 */82union s_fp_descr {83 struct s_smt_fp_txd t ; /* pointer to the TxD */84 struct s_smt_fp_rxd r ; /* pointer to the RxD */85} ;86 87/*88 * TxD Ring Control struct89 */90struct s_smt_tx_queue {91 struct s_smt_fp_txd volatile *tx_curr_put ; /* next free TxD */92 struct s_smt_fp_txd volatile *tx_prev_put ; /* shadow put pointer */93 struct s_smt_fp_txd volatile *tx_curr_get ; /* next TxD to release*/94 u_short tx_free ; /* count of free TxD's */95 u_short tx_used ; /* count of used TxD's */96 HW_PTR tx_bmu_ctl ; /* BMU addr for tx start */97 HW_PTR tx_bmu_dsc ; /* BMU addr for curr dsc. */98} ;99 100/*101 * RxD Ring Control struct102 */103struct s_smt_rx_queue {104 struct s_smt_fp_rxd volatile *rx_curr_put ; /* next RxD to queue into */105 struct s_smt_fp_rxd volatile *rx_prev_put ; /* shadow put pointer */106 struct s_smt_fp_rxd volatile *rx_curr_get ; /* next RxD to fill */107 u_short rx_free ; /* count of free RxD's */108 u_short rx_used ; /* count of used RxD's */109 HW_PTR rx_bmu_ctl ; /* BMU addr for rx start */110 HW_PTR rx_bmu_dsc ; /* BMU addr for curr dsc. */111} ;112 113#define VOID_FRAME_OFF 0x00114#define CLAIM_FRAME_OFF 0x08115#define BEACON_FRAME_OFF 0x10116#define DBEACON_FRAME_OFF 0x18117#define RX_FIFO_OFF 0x21 /* to get a prime number for */118 /* the RX_FIFO_SPACE */119 120#define RBC_MEM_SIZE 0x8000121#define SEND_ASYNC_AS_SYNC 0x1122#define SYNC_TRAFFIC_ON 0x2123 124/* big FIFO memory */125#define RX_FIFO_SPACE 0x4000 - RX_FIFO_OFF126#define TX_FIFO_SPACE 0x4000127 128#define TX_SMALL_FIFO 0x0900129#define TX_MEDIUM_FIFO TX_FIFO_SPACE / 2 130#define TX_LARGE_FIFO TX_FIFO_SPACE - TX_SMALL_FIFO 131 132#define RX_SMALL_FIFO 0x0900133#define RX_LARGE_FIFO RX_FIFO_SPACE - RX_SMALL_FIFO 134 135struct s_smt_fifo_conf {136 u_short rbc_ram_start ; /* FIFO start address */137 u_short rbc_ram_end ; /* FIFO size */138 u_short rx1_fifo_start ; /* rx queue start address */139 u_short rx1_fifo_size ; /* rx queue size */140 u_short rx2_fifo_start ; /* rx queue start address */141 u_short rx2_fifo_size ; /* rx queue size */142 u_short tx_s_start ; /* sync queue start address */143 u_short tx_s_size ; /* sync queue size */144 u_short tx_a0_start ; /* async queue A0 start address */145 u_short tx_a0_size ; /* async queue A0 size */146 u_short fifo_config_mode ; /* FIFO configuration mode */147} ;148 149#define FM_ADDRX (FM_ADDET|FM_EXGPA0|FM_EXGPA1)150 151struct s_smt_fp {152 u_short mdr2init ; /* mode register 2 init value */153 u_short mdr3init ; /* mode register 3 init value */154 u_short frselreg_init ; /* frame selection register init val */155 u_short rx_mode ; /* address mode broad/multi/promisc */156 u_short nsa_mode ;157 u_short rx_prom ;158 u_short exgpa ;159 160 struct err_st err_stats ; /* error statistics */161 162 /*163 * MAC buffers164 */165 struct fddi_mac_sf { /* special frame build buffer */166 u_char mac_fc ;167 struct fddi_addr mac_dest ;168 struct fddi_addr mac_source ;169 u_char mac_info[0x20] ;170 } mac_sfb ;171 172 173 /*174 * queues175 */176#define QUEUE_S 0177#define QUEUE_A0 1178#define QUEUE_R1 0179#define QUEUE_R2 1180#define USED_QUEUES 2181 182 /*183 * queue pointers; points to the queue dependent variables184 */185 struct s_smt_tx_queue *tx[USED_QUEUES] ;186 struct s_smt_rx_queue *rx[USED_QUEUES] ;187 188 /*189 * queue dependent variables190 */191 struct s_smt_tx_queue tx_q[USED_QUEUES] ;192 struct s_smt_rx_queue rx_q[USED_QUEUES] ;193 194 /*195 * FIFO configuration struct196 */197 struct s_smt_fifo_conf fifo ;198 199 /* last formac status */200 u_short s2u ;201 u_short s2l ;202 203 /* calculated FORMAC+ reg.addr. */204 HW_PTR fm_st1u ;205 HW_PTR fm_st1l ;206 HW_PTR fm_st2u ;207 HW_PTR fm_st2l ;208 HW_PTR fm_st3u ;209 HW_PTR fm_st3l ;210 211 212 /*213 * multicast table214 */215#define FPMAX_MULTICAST 32 216#define SMT_MAX_MULTI 4217 struct {218 struct s_fpmc {219 struct fddi_addr a ; /* mc address */220 u_char n ; /* usage counter */221 u_char perm ; /* flag: permanent */222 } table[FPMAX_MULTICAST] ;223 } mc ;224 struct fddi_addr group_addr ;225 u_long func_addr ; /* functional address */226 int smt_slots_used ; /* count of table entries for the SMT */227 int os_slots_used ; /* count of table entries */ 228 /* used by the os-specific module */229} ;230 231/*232 * modes for mac_set_rx_mode()233 */234#define RX_ENABLE_ALLMULTI 1 /* enable all multicasts */235#define RX_DISABLE_ALLMULTI 2 /* disable "enable all multicasts" */236#define RX_ENABLE_PROMISC 3 /* enable promiscuous */237#define RX_DISABLE_PROMISC 4 /* disable promiscuous */238#define RX_ENABLE_NSA 5 /* enable reception of NSA frames */239#define RX_DISABLE_NSA 6 /* disable reception of NSA frames */240 241 242/*243 * support for byte reversal in AIX244 * (descriptors and pointers must be byte reversed in memory245 * CPU is big endian; M-Channel is little endian)246 */247#ifdef AIX248#define MDR_REV249#define AIX_REVERSE(x) ((((x)<<24L)&0xff000000L) + \250 (((x)<< 8L)&0x00ff0000L) + \251 (((x)>> 8L)&0x0000ff00L) + \252 (((x)>>24L)&0x000000ffL))253#else254#ifndef AIX_REVERSE255#define AIX_REVERSE(x) (x)256#endif257#endif258 259#ifdef MDR_REV 260#define MDR_REVERSE(x) ((((x)<<24L)&0xff000000L) + \261 (((x)<< 8L)&0x00ff0000L) + \262 (((x)>> 8L)&0x0000ff00L) + \263 (((x)>>24L)&0x000000ffL))264#else265#ifndef MDR_REVERSE266#define MDR_REVERSE(x) (x)267#endif268#endif269 270#endif271