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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * AT86RF230/RF231 driver4 *5 * Copyright (C) 2009-2012 Siemens AG6 *7 * Written by:8 * Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>9 * Alexander Smirnov <alex.bluesman.smirnov@gmail.com>10 */11 12#ifndef _AT86RF230_H13#define _AT86RF230_H14 15#define RG_TRX_STATUS (0x01)16#define SR_TRX_STATUS 0x01, 0x1f, 017#define SR_RESERVED_01_3 0x01, 0x20, 518#define SR_CCA_STATUS 0x01, 0x40, 619#define SR_CCA_DONE 0x01, 0x80, 720#define RG_TRX_STATE (0x02)21#define SR_TRX_CMD 0x02, 0x1f, 022#define SR_TRAC_STATUS 0x02, 0xe0, 523#define RG_TRX_CTRL_0 (0x03)24#define SR_CLKM_CTRL 0x03, 0x07, 025#define SR_CLKM_SHA_SEL 0x03, 0x08, 326#define SR_PAD_IO_CLKM 0x03, 0x30, 427#define SR_PAD_IO 0x03, 0xc0, 628#define RG_TRX_CTRL_1 (0x04)29#define SR_IRQ_POLARITY 0x04, 0x01, 030#define SR_IRQ_MASK_MODE 0x04, 0x02, 131#define SR_SPI_CMD_MODE 0x04, 0x0c, 232#define SR_RX_BL_CTRL 0x04, 0x10, 433#define SR_TX_AUTO_CRC_ON 0x04, 0x20, 534#define SR_IRQ_2_EXT_EN 0x04, 0x40, 635#define SR_PA_EXT_EN 0x04, 0x80, 736#define RG_PHY_TX_PWR (0x05)37#define SR_TX_PWR_23X 0x05, 0x0f, 038#define SR_PA_LT_230 0x05, 0x30, 439#define SR_PA_BUF_LT_230 0x05, 0xc0, 640#define SR_TX_PWR_212 0x05, 0x1f, 041#define SR_GC_PA_212 0x05, 0x60, 542#define SR_PA_BOOST_LT_212 0x05, 0x80, 743#define RG_PHY_RSSI (0x06)44#define SR_RSSI 0x06, 0x1f, 045#define SR_RND_VALUE 0x06, 0x60, 546#define SR_RX_CRC_VALID 0x06, 0x80, 747#define RG_PHY_ED_LEVEL (0x07)48#define SR_ED_LEVEL 0x07, 0xff, 049#define RG_PHY_CC_CCA (0x08)50#define SR_CHANNEL 0x08, 0x1f, 051#define SR_CCA_MODE 0x08, 0x60, 552#define SR_CCA_REQUEST 0x08, 0x80, 753#define RG_CCA_THRES (0x09)54#define SR_CCA_ED_THRES 0x09, 0x0f, 055#define SR_RESERVED_09_1 0x09, 0xf0, 456#define RG_RX_CTRL (0x0a)57#define SR_PDT_THRES 0x0a, 0x0f, 058#define SR_RESERVED_0a_1 0x0a, 0xf0, 459#define RG_SFD_VALUE (0x0b)60#define SR_SFD_VALUE 0x0b, 0xff, 061#define RG_TRX_CTRL_2 (0x0c)62#define SR_OQPSK_DATA_RATE 0x0c, 0x03, 063#define SR_SUB_MODE 0x0c, 0x04, 264#define SR_BPSK_QPSK 0x0c, 0x08, 365#define SR_OQPSK_SUB1_RC_EN 0x0c, 0x10, 466#define SR_RESERVED_0c_5 0x0c, 0x60, 567#define SR_RX_SAFE_MODE 0x0c, 0x80, 768#define RG_ANT_DIV (0x0d)69#define SR_ANT_CTRL 0x0d, 0x03, 070#define SR_ANT_EXT_SW_EN 0x0d, 0x04, 271#define SR_ANT_DIV_EN 0x0d, 0x08, 372#define SR_RESERVED_0d_2 0x0d, 0x70, 473#define SR_ANT_SEL 0x0d, 0x80, 774#define RG_IRQ_MASK (0x0e)75#define SR_IRQ_MASK 0x0e, 0xff, 076#define RG_IRQ_STATUS (0x0f)77#define SR_IRQ_0_PLL_LOCK 0x0f, 0x01, 078#define SR_IRQ_1_PLL_UNLOCK 0x0f, 0x02, 179#define SR_IRQ_2_RX_START 0x0f, 0x04, 280#define SR_IRQ_3_TRX_END 0x0f, 0x08, 381#define SR_IRQ_4_CCA_ED_DONE 0x0f, 0x10, 482#define SR_IRQ_5_AMI 0x0f, 0x20, 583#define SR_IRQ_6_TRX_UR 0x0f, 0x40, 684#define SR_IRQ_7_BAT_LOW 0x0f, 0x80, 785#define RG_VREG_CTRL (0x10)86#define SR_RESERVED_10_6 0x10, 0x03, 087#define SR_DVDD_OK 0x10, 0x04, 288#define SR_DVREG_EXT 0x10, 0x08, 389#define SR_RESERVED_10_3 0x10, 0x30, 490#define SR_AVDD_OK 0x10, 0x40, 691#define SR_AVREG_EXT 0x10, 0x80, 792#define RG_BATMON (0x11)93#define SR_BATMON_VTH 0x11, 0x0f, 094#define SR_BATMON_HR 0x11, 0x10, 495#define SR_BATMON_OK 0x11, 0x20, 596#define SR_RESERVED_11_1 0x11, 0xc0, 697#define RG_XOSC_CTRL (0x12)98#define SR_XTAL_TRIM 0x12, 0x0f, 099#define SR_XTAL_MODE 0x12, 0xf0, 4100#define RG_RX_SYN (0x15)101#define SR_RX_PDT_LEVEL 0x15, 0x0f, 0102#define SR_RESERVED_15_2 0x15, 0x70, 4103#define SR_RX_PDT_DIS 0x15, 0x80, 7104#define RG_XAH_CTRL_1 (0x17)105#define SR_RESERVED_17_8 0x17, 0x01, 0106#define SR_AACK_PROM_MODE 0x17, 0x02, 1107#define SR_AACK_ACK_TIME 0x17, 0x04, 2108#define SR_RESERVED_17_5 0x17, 0x08, 3109#define SR_AACK_UPLD_RES_FT 0x17, 0x10, 4110#define SR_AACK_FLTR_RES_FT 0x17, 0x20, 5111#define SR_CSMA_LBT_MODE 0x17, 0x40, 6112#define SR_RESERVED_17_1 0x17, 0x80, 7113#define RG_FTN_CTRL (0x18)114#define SR_RESERVED_18_2 0x18, 0x7f, 0115#define SR_FTN_START 0x18, 0x80, 7116#define RG_PLL_CF (0x1a)117#define SR_RESERVED_1a_2 0x1a, 0x7f, 0118#define SR_PLL_CF_START 0x1a, 0x80, 7119#define RG_PLL_DCU (0x1b)120#define SR_RESERVED_1b_3 0x1b, 0x3f, 0121#define SR_RESERVED_1b_2 0x1b, 0x40, 6122#define SR_PLL_DCU_START 0x1b, 0x80, 7123#define RG_PART_NUM (0x1c)124#define SR_PART_NUM 0x1c, 0xff, 0125#define RG_VERSION_NUM (0x1d)126#define SR_VERSION_NUM 0x1d, 0xff, 0127#define RG_MAN_ID_0 (0x1e)128#define SR_MAN_ID_0 0x1e, 0xff, 0129#define RG_MAN_ID_1 (0x1f)130#define SR_MAN_ID_1 0x1f, 0xff, 0131#define RG_SHORT_ADDR_0 (0x20)132#define SR_SHORT_ADDR_0 0x20, 0xff, 0133#define RG_SHORT_ADDR_1 (0x21)134#define SR_SHORT_ADDR_1 0x21, 0xff, 0135#define RG_PAN_ID_0 (0x22)136#define SR_PAN_ID_0 0x22, 0xff, 0137#define RG_PAN_ID_1 (0x23)138#define SR_PAN_ID_1 0x23, 0xff, 0139#define RG_IEEE_ADDR_0 (0x24)140#define SR_IEEE_ADDR_0 0x24, 0xff, 0141#define RG_IEEE_ADDR_1 (0x25)142#define SR_IEEE_ADDR_1 0x25, 0xff, 0143#define RG_IEEE_ADDR_2 (0x26)144#define SR_IEEE_ADDR_2 0x26, 0xff, 0145#define RG_IEEE_ADDR_3 (0x27)146#define SR_IEEE_ADDR_3 0x27, 0xff, 0147#define RG_IEEE_ADDR_4 (0x28)148#define SR_IEEE_ADDR_4 0x28, 0xff, 0149#define RG_IEEE_ADDR_5 (0x29)150#define SR_IEEE_ADDR_5 0x29, 0xff, 0151#define RG_IEEE_ADDR_6 (0x2a)152#define SR_IEEE_ADDR_6 0x2a, 0xff, 0153#define RG_IEEE_ADDR_7 (0x2b)154#define SR_IEEE_ADDR_7 0x2b, 0xff, 0155#define RG_XAH_CTRL_0 (0x2c)156#define SR_SLOTTED_OPERATION 0x2c, 0x01, 0157#define SR_MAX_CSMA_RETRIES 0x2c, 0x0e, 1158#define SR_MAX_FRAME_RETRIES 0x2c, 0xf0, 4159#define RG_CSMA_SEED_0 (0x2d)160#define SR_CSMA_SEED_0 0x2d, 0xff, 0161#define RG_CSMA_SEED_1 (0x2e)162#define SR_CSMA_SEED_1 0x2e, 0x07, 0163#define SR_AACK_I_AM_COORD 0x2e, 0x08, 3164#define SR_AACK_DIS_ACK 0x2e, 0x10, 4165#define SR_AACK_SET_PD 0x2e, 0x20, 5166#define SR_AACK_FVN_MODE 0x2e, 0xc0, 6167#define RG_CSMA_BE (0x2f)168#define SR_MIN_BE 0x2f, 0x0f, 0169#define SR_MAX_BE 0x2f, 0xf0, 4170 171#define CMD_REG 0x80172#define CMD_REG_MASK 0x3f173#define CMD_WRITE 0x40174#define CMD_FB 0x20175 176#define IRQ_BAT_LOW BIT(7)177#define IRQ_TRX_UR BIT(6)178#define IRQ_AMI BIT(5)179#define IRQ_CCA_ED BIT(4)180#define IRQ_TRX_END BIT(3)181#define IRQ_RX_START BIT(2)182#define IRQ_PLL_UNL BIT(1)183#define IRQ_PLL_LOCK BIT(0)184 185#define IRQ_ACTIVE_HIGH 0186#define IRQ_ACTIVE_LOW 1187 188#define STATE_P_ON 0x00 /* BUSY */189#define STATE_BUSY_RX 0x01190#define STATE_BUSY_TX 0x02191#define STATE_FORCE_TRX_OFF 0x03192#define STATE_FORCE_TX_ON 0x04 /* IDLE */193/* 0x05 */ /* INVALID_PARAMETER */194#define STATE_RX_ON 0x06195/* 0x07 */ /* SUCCESS */196#define STATE_TRX_OFF 0x08197#define STATE_TX_ON 0x09198/* 0x0a - 0x0e */ /* 0x0a - UNSUPPORTED_ATTRIBUTE */199#define STATE_SLEEP 0x0F200#define STATE_PREP_DEEP_SLEEP 0x10201#define STATE_BUSY_RX_AACK 0x11202#define STATE_BUSY_TX_ARET 0x12203#define STATE_RX_AACK_ON 0x16204#define STATE_TX_ARET_ON 0x19205#define STATE_RX_ON_NOCLK 0x1C206#define STATE_RX_AACK_ON_NOCLK 0x1D207#define STATE_BUSY_RX_AACK_NOCLK 0x1E208#define STATE_TRANSITION_IN_PROGRESS 0x1F209 210#define TRX_STATE_MASK (0x1F)211#define TRAC_MASK(x) ((x & 0xe0) >> 5)212 213#define TRAC_SUCCESS 0214#define TRAC_SUCCESS_DATA_PENDING 1215#define TRAC_SUCCESS_WAIT_FOR_ACK 2216#define TRAC_CHANNEL_ACCESS_FAILURE 3217#define TRAC_NO_ACK 5218#define TRAC_INVALID 7219 220#endif /* !_AT86RF230_H */221