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1// SPDX-License-Identifier: GPL-2.0-or-later2/*3 * Driver for Microchip MRF24J40 802.15.4 Wireless-PAN Networking controller4 *5 * Copyright (C) 2012 Alan Ott <alan@signal11.us>6 * Signal 11 Software7 */8 9#include <linux/spi/spi.h>10#include <linux/interrupt.h>11#include <linux/mod_devicetable.h>12#include <linux/module.h>13#include <linux/regmap.h>14#include <linux/ieee802154.h>15#include <linux/irq.h>16#include <net/cfg802154.h>17#include <net/mac802154.h>18 19/* MRF24J40 Short Address Registers */20#define REG_RXMCR 0x00 /* Receive MAC control */21#define BIT_PROMI BIT(0)22#define BIT_ERRPKT BIT(1)23#define BIT_NOACKRSP BIT(5)24#define BIT_PANCOORD BIT(3)25 26#define REG_PANIDL 0x01 /* PAN ID (low) */27#define REG_PANIDH 0x02 /* PAN ID (high) */28#define REG_SADRL 0x03 /* Short address (low) */29#define REG_SADRH 0x04 /* Short address (high) */30#define REG_EADR0 0x05 /* Long address (low) (high is EADR7) */31#define REG_EADR1 0x0632#define REG_EADR2 0x0733#define REG_EADR3 0x0834#define REG_EADR4 0x0935#define REG_EADR5 0x0A36#define REG_EADR6 0x0B37#define REG_EADR7 0x0C38#define REG_RXFLUSH 0x0D39#define REG_ORDER 0x1040#define REG_TXMCR 0x11 /* Transmit MAC control */41#define TXMCR_MIN_BE_SHIFT 342#define TXMCR_MIN_BE_MASK 0x1843#define TXMCR_CSMA_RETRIES_SHIFT 044#define TXMCR_CSMA_RETRIES_MASK 0x0745 46#define REG_ACKTMOUT 0x1247#define REG_ESLOTG1 0x1348#define REG_SYMTICKL 0x1449#define REG_SYMTICKH 0x1550#define REG_PACON0 0x16 /* Power Amplifier Control */51#define REG_PACON1 0x17 /* Power Amplifier Control */52#define REG_PACON2 0x18 /* Power Amplifier Control */53#define REG_TXBCON0 0x1A54#define REG_TXNCON 0x1B /* Transmit Normal FIFO Control */55#define BIT_TXNTRIG BIT(0)56#define BIT_TXNSECEN BIT(1)57#define BIT_TXNACKREQ BIT(2)58 59#define REG_TXG1CON 0x1C60#define REG_TXG2CON 0x1D61#define REG_ESLOTG23 0x1E62#define REG_ESLOTG45 0x1F63#define REG_ESLOTG67 0x2064#define REG_TXPEND 0x2165#define REG_WAKECON 0x2266#define REG_FROMOFFSET 0x2367#define REG_TXSTAT 0x24 /* TX MAC Status Register */68#define REG_TXBCON1 0x2569#define REG_GATECLK 0x2670#define REG_TXTIME 0x2771#define REG_HSYMTMRL 0x2872#define REG_HSYMTMRH 0x2973#define REG_SOFTRST 0x2A /* Soft Reset */74#define REG_SECCON0 0x2C75#define REG_SECCON1 0x2D76#define REG_TXSTBL 0x2E /* TX Stabilization */77#define REG_RXSR 0x3078#define REG_INTSTAT 0x31 /* Interrupt Status */79#define BIT_TXNIF BIT(0)80#define BIT_RXIF BIT(3)81#define BIT_SECIF BIT(4)82#define BIT_SECIGNORE BIT(7)83 84#define REG_INTCON 0x32 /* Interrupt Control */85#define BIT_TXNIE BIT(0)86#define BIT_RXIE BIT(3)87#define BIT_SECIE BIT(4)88 89#define REG_GPIO 0x33 /* GPIO */90#define REG_TRISGPIO 0x34 /* GPIO direction */91#define REG_SLPACK 0x3592#define REG_RFCTL 0x36 /* RF Control Mode Register */93#define BIT_RFRST BIT(2)94 95#define REG_SECCR2 0x3796#define REG_BBREG0 0x3897#define REG_BBREG1 0x39 /* Baseband Registers */98#define BIT_RXDECINV BIT(2)99 100#define REG_BBREG2 0x3A /* */101#define BBREG2_CCA_MODE_SHIFT 6102#define BBREG2_CCA_MODE_MASK 0xc0103 104#define REG_BBREG3 0x3B105#define REG_BBREG4 0x3C106#define REG_BBREG6 0x3E /* */107#define REG_CCAEDTH 0x3F /* Energy Detection Threshold */108 109/* MRF24J40 Long Address Registers */110#define REG_RFCON0 0x200 /* RF Control Registers */111#define RFCON0_CH_SHIFT 4112#define RFCON0_CH_MASK 0xf0113#define RFOPT_RECOMMEND 3114 115#define REG_RFCON1 0x201116#define REG_RFCON2 0x202117#define REG_RFCON3 0x203118 119#define TXPWRL_MASK 0xc0120#define TXPWRL_SHIFT 6121#define TXPWRL_30 0x3122#define TXPWRL_20 0x2123#define TXPWRL_10 0x1124#define TXPWRL_0 0x0125 126#define TXPWRS_MASK 0x38127#define TXPWRS_SHIFT 3128#define TXPWRS_6_3 0x7129#define TXPWRS_4_9 0x6130#define TXPWRS_3_7 0x5131#define TXPWRS_2_8 0x4132#define TXPWRS_1_9 0x3133#define TXPWRS_1_2 0x2134#define TXPWRS_0_5 0x1135#define TXPWRS_0 0x0136 137#define REG_RFCON5 0x205138#define REG_RFCON6 0x206139#define REG_RFCON7 0x207140#define REG_RFCON8 0x208141#define REG_SLPCAL0 0x209142#define REG_SLPCAL1 0x20A143#define REG_SLPCAL2 0x20B144#define REG_RFSTATE 0x20F145#define REG_RSSI 0x210146#define REG_SLPCON0 0x211 /* Sleep Clock Control Registers */147#define BIT_INTEDGE BIT(1)148 149#define REG_SLPCON1 0x220150#define REG_WAKETIMEL 0x222 /* Wake-up Time Match Value Low */151#define REG_WAKETIMEH 0x223 /* Wake-up Time Match Value High */152#define REG_REMCNTL 0x224153#define REG_REMCNTH 0x225154#define REG_MAINCNT0 0x226155#define REG_MAINCNT1 0x227156#define REG_MAINCNT2 0x228157#define REG_MAINCNT3 0x229158#define REG_TESTMODE 0x22F /* Test mode */159#define REG_ASSOEAR0 0x230160#define REG_ASSOEAR1 0x231161#define REG_ASSOEAR2 0x232162#define REG_ASSOEAR3 0x233163#define REG_ASSOEAR4 0x234164#define REG_ASSOEAR5 0x235165#define REG_ASSOEAR6 0x236166#define REG_ASSOEAR7 0x237167#define REG_ASSOSAR0 0x238168#define REG_ASSOSAR1 0x239169#define REG_UNONCE0 0x240170#define REG_UNONCE1 0x241171#define REG_UNONCE2 0x242172#define REG_UNONCE3 0x243173#define REG_UNONCE4 0x244174#define REG_UNONCE5 0x245175#define REG_UNONCE6 0x246176#define REG_UNONCE7 0x247177#define REG_UNONCE8 0x248178#define REG_UNONCE9 0x249179#define REG_UNONCE10 0x24A180#define REG_UNONCE11 0x24B181#define REG_UNONCE12 0x24C182#define REG_RX_FIFO 0x300 /* Receive FIFO */183 184/* Device configuration: Only channels 11-26 on page 0 are supported. */185#define MRF24J40_CHAN_MIN 11186#define MRF24J40_CHAN_MAX 26187#define CHANNEL_MASK (((u32)1 << (MRF24J40_CHAN_MAX + 1)) \188 - ((u32)1 << MRF24J40_CHAN_MIN))189 190#define TX_FIFO_SIZE 128 /* From datasheet */191#define RX_FIFO_SIZE 144 /* From datasheet */192#define SET_CHANNEL_DELAY_US 192 /* From datasheet */193 194enum mrf24j40_modules { MRF24J40, MRF24J40MA, MRF24J40MC };195 196/* Device Private Data */197struct mrf24j40 {198 struct spi_device *spi;199 struct ieee802154_hw *hw;200 201 struct regmap *regmap_short;202 struct regmap *regmap_long;203 204 /* for writing txfifo */205 struct spi_message tx_msg;206 u8 tx_hdr_buf[2];207 struct spi_transfer tx_hdr_trx;208 u8 tx_len_buf[2];209 struct spi_transfer tx_len_trx;210 struct spi_transfer tx_buf_trx;211 struct sk_buff *tx_skb;212 213 /* post transmit message to send frame out */214 struct spi_message tx_post_msg;215 u8 tx_post_buf[2];216 struct spi_transfer tx_post_trx;217 218 /* for protect/unprotect/read length rxfifo */219 struct spi_message rx_msg;220 u8 rx_buf[3];221 struct spi_transfer rx_trx;222 223 /* receive handling */224 struct spi_message rx_buf_msg;225 u8 rx_addr_buf[2];226 struct spi_transfer rx_addr_trx;227 u8 rx_lqi_buf[2];228 struct spi_transfer rx_lqi_trx;229 u8 rx_fifo_buf[RX_FIFO_SIZE];230 struct spi_transfer rx_fifo_buf_trx;231 232 /* isr handling for reading intstat */233 struct spi_message irq_msg;234 u8 irq_buf[2];235 struct spi_transfer irq_trx;236};237 238/* regmap information for short address register access */239#define MRF24J40_SHORT_WRITE 0x01240#define MRF24J40_SHORT_READ 0x00241#define MRF24J40_SHORT_NUMREGS 0x3F242 243/* regmap information for long address register access */244#define MRF24J40_LONG_ACCESS 0x80245#define MRF24J40_LONG_NUMREGS 0x38F246 247/* Read/Write SPI Commands for Short and Long Address registers. */248#define MRF24J40_READSHORT(reg) ((reg) << 1)249#define MRF24J40_WRITESHORT(reg) ((reg) << 1 | 1)250#define MRF24J40_READLONG(reg) (1 << 15 | (reg) << 5)251#define MRF24J40_WRITELONG(reg) (1 << 15 | (reg) << 5 | 1 << 4)252 253/* The datasheet indicates the theoretical maximum for SCK to be 10MHz */254#define MAX_SPI_SPEED_HZ 10000000255 256#define printdev(X) (&X->spi->dev)257 258static bool259mrf24j40_short_reg_writeable(struct device *dev, unsigned int reg)260{261 switch (reg) {262 case REG_RXMCR:263 case REG_PANIDL:264 case REG_PANIDH:265 case REG_SADRL:266 case REG_SADRH:267 case REG_EADR0:268 case REG_EADR1:269 case REG_EADR2:270 case REG_EADR3:271 case REG_EADR4:272 case REG_EADR5:273 case REG_EADR6:274 case REG_EADR7:275 case REG_RXFLUSH:276 case REG_ORDER:277 case REG_TXMCR:278 case REG_ACKTMOUT:279 case REG_ESLOTG1:280 case REG_SYMTICKL:281 case REG_SYMTICKH:282 case REG_PACON0:283 case REG_PACON1:284 case REG_PACON2:285 case REG_TXBCON0:286 case REG_TXNCON:287 case REG_TXG1CON:288 case REG_TXG2CON:289 case REG_ESLOTG23:290 case REG_ESLOTG45:291 case REG_ESLOTG67:292 case REG_TXPEND:293 case REG_WAKECON:294 case REG_FROMOFFSET:295 case REG_TXBCON1:296 case REG_GATECLK:297 case REG_TXTIME:298 case REG_HSYMTMRL:299 case REG_HSYMTMRH:300 case REG_SOFTRST:301 case REG_SECCON0:302 case REG_SECCON1:303 case REG_TXSTBL:304 case REG_RXSR:305 case REG_INTCON:306 case REG_TRISGPIO:307 case REG_GPIO:308 case REG_RFCTL:309 case REG_SECCR2:310 case REG_SLPACK:311 case REG_BBREG0:312 case REG_BBREG1:313 case REG_BBREG2:314 case REG_BBREG3:315 case REG_BBREG4:316 case REG_BBREG6:317 case REG_CCAEDTH:318 return true;319 default:320 return false;321 }322}323 324static bool325mrf24j40_short_reg_readable(struct device *dev, unsigned int reg)326{327 bool rc;328 329 /* all writeable are also readable */330 rc = mrf24j40_short_reg_writeable(dev, reg);331 if (rc)332 return rc;333 334 /* readonly regs */335 switch (reg) {336 case REG_TXSTAT:337 case REG_INTSTAT:338 return true;339 default:340 return false;341 }342}343 344static bool345mrf24j40_short_reg_volatile(struct device *dev, unsigned int reg)346{347 /* can be changed during runtime */348 switch (reg) {349 case REG_TXSTAT:350 case REG_INTSTAT:351 case REG_RXFLUSH:352 case REG_TXNCON:353 case REG_SOFTRST:354 case REG_RFCTL:355 case REG_TXBCON0:356 case REG_TXG1CON:357 case REG_TXG2CON:358 case REG_TXBCON1:359 case REG_SECCON0:360 case REG_RXSR:361 case REG_SLPACK:362 case REG_SECCR2:363 case REG_BBREG6:364 /* use them in spi_async and regmap so it's volatile */365 case REG_BBREG1:366 return true;367 default:368 return false;369 }370}371 372static bool373mrf24j40_short_reg_precious(struct device *dev, unsigned int reg)374{375 /* don't clear irq line on read */376 switch (reg) {377 case REG_INTSTAT:378 return true;379 default:380 return false;381 }382}383 384static const struct regmap_config mrf24j40_short_regmap = {385 .name = "mrf24j40_short",386 .reg_bits = 7,387 .val_bits = 8,388 .pad_bits = 1,389 .write_flag_mask = MRF24J40_SHORT_WRITE,390 .read_flag_mask = MRF24J40_SHORT_READ,391 .cache_type = REGCACHE_MAPLE,392 .max_register = MRF24J40_SHORT_NUMREGS,393 .writeable_reg = mrf24j40_short_reg_writeable,394 .readable_reg = mrf24j40_short_reg_readable,395 .volatile_reg = mrf24j40_short_reg_volatile,396 .precious_reg = mrf24j40_short_reg_precious,397};398 399static bool400mrf24j40_long_reg_writeable(struct device *dev, unsigned int reg)401{402 switch (reg) {403 case REG_RFCON0:404 case REG_RFCON1:405 case REG_RFCON2:406 case REG_RFCON3:407 case REG_RFCON5:408 case REG_RFCON6:409 case REG_RFCON7:410 case REG_RFCON8:411 case REG_SLPCAL2:412 case REG_SLPCON0:413 case REG_SLPCON1:414 case REG_WAKETIMEL:415 case REG_WAKETIMEH:416 case REG_REMCNTL:417 case REG_REMCNTH:418 case REG_MAINCNT0:419 case REG_MAINCNT1:420 case REG_MAINCNT2:421 case REG_MAINCNT3:422 case REG_TESTMODE:423 case REG_ASSOEAR0:424 case REG_ASSOEAR1:425 case REG_ASSOEAR2:426 case REG_ASSOEAR3:427 case REG_ASSOEAR4:428 case REG_ASSOEAR5:429 case REG_ASSOEAR6:430 case REG_ASSOEAR7:431 case REG_ASSOSAR0:432 case REG_ASSOSAR1:433 case REG_UNONCE0:434 case REG_UNONCE1:435 case REG_UNONCE2:436 case REG_UNONCE3:437 case REG_UNONCE4:438 case REG_UNONCE5:439 case REG_UNONCE6:440 case REG_UNONCE7:441 case REG_UNONCE8:442 case REG_UNONCE9:443 case REG_UNONCE10:444 case REG_UNONCE11:445 case REG_UNONCE12:446 return true;447 default:448 return false;449 }450}451 452static bool453mrf24j40_long_reg_readable(struct device *dev, unsigned int reg)454{455 bool rc;456 457 /* all writeable are also readable */458 rc = mrf24j40_long_reg_writeable(dev, reg);459 if (rc)460 return rc;461 462 /* readonly regs */463 switch (reg) {464 case REG_SLPCAL0:465 case REG_SLPCAL1:466 case REG_RFSTATE:467 case REG_RSSI:468 return true;469 default:470 return false;471 }472}473 474static bool475mrf24j40_long_reg_volatile(struct device *dev, unsigned int reg)476{477 /* can be changed during runtime */478 switch (reg) {479 case REG_SLPCAL0:480 case REG_SLPCAL1:481 case REG_SLPCAL2:482 case REG_RFSTATE:483 case REG_RSSI:484 case REG_MAINCNT3:485 return true;486 default:487 return false;488 }489}490 491static const struct regmap_config mrf24j40_long_regmap = {492 .name = "mrf24j40_long",493 .reg_bits = 11,494 .val_bits = 8,495 .pad_bits = 5,496 .write_flag_mask = MRF24J40_LONG_ACCESS,497 .read_flag_mask = MRF24J40_LONG_ACCESS,498 .cache_type = REGCACHE_MAPLE,499 .max_register = MRF24J40_LONG_NUMREGS,500 .writeable_reg = mrf24j40_long_reg_writeable,501 .readable_reg = mrf24j40_long_reg_readable,502 .volatile_reg = mrf24j40_long_reg_volatile,503};504 505static int mrf24j40_long_regmap_write(void *context, const void *data,506 size_t count)507{508 struct spi_device *spi = context;509 u8 buf[3];510 511 if (count > 3)512 return -EINVAL;513 514 /* regmap supports read/write mask only in frist byte515 * long write access need to set the 12th bit, so we516 * make special handling for write.517 */518 memcpy(buf, data, count);519 buf[1] |= (1 << 4);520 521 return spi_write(spi, buf, count);522}523 524static int525mrf24j40_long_regmap_read(void *context, const void *reg, size_t reg_size,526 void *val, size_t val_size)527{528 struct spi_device *spi = context;529 530 return spi_write_then_read(spi, reg, reg_size, val, val_size);531}532 533static const struct regmap_bus mrf24j40_long_regmap_bus = {534 .write = mrf24j40_long_regmap_write,535 .read = mrf24j40_long_regmap_read,536 .reg_format_endian_default = REGMAP_ENDIAN_BIG,537 .val_format_endian_default = REGMAP_ENDIAN_BIG,538};539 540static void write_tx_buf_complete(void *context)541{542 struct mrf24j40 *devrec = context;543 __le16 fc = ieee802154_get_fc_from_skb(devrec->tx_skb);544 u8 val = BIT_TXNTRIG;545 int ret;546 547 if (ieee802154_is_secen(fc))548 val |= BIT_TXNSECEN;549 550 if (ieee802154_is_ackreq(fc))551 val |= BIT_TXNACKREQ;552 553 devrec->tx_post_msg.complete = NULL;554 devrec->tx_post_buf[0] = MRF24J40_WRITESHORT(REG_TXNCON);555 devrec->tx_post_buf[1] = val;556 557 ret = spi_async(devrec->spi, &devrec->tx_post_msg);558 if (ret)559 dev_err(printdev(devrec), "SPI write Failed for transmit buf\n");560}561 562/* This function relies on an undocumented write method. Once a write command563 and address is set, as many bytes of data as desired can be clocked into564 the device. The datasheet only shows setting one byte at a time. */565static int write_tx_buf(struct mrf24j40 *devrec, u16 reg,566 const u8 *data, size_t length)567{568 u16 cmd;569 int ret;570 571 /* Range check the length. 2 bytes are used for the length fields.*/572 if (length > TX_FIFO_SIZE-2) {573 dev_err(printdev(devrec), "write_tx_buf() was passed too large a buffer. Performing short write.\n");574 length = TX_FIFO_SIZE-2;575 }576 577 cmd = MRF24J40_WRITELONG(reg);578 devrec->tx_hdr_buf[0] = cmd >> 8 & 0xff;579 devrec->tx_hdr_buf[1] = cmd & 0xff;580 devrec->tx_len_buf[0] = 0x0; /* Header Length. Set to 0 for now. TODO */581 devrec->tx_len_buf[1] = length; /* Total length */582 devrec->tx_buf_trx.tx_buf = data;583 devrec->tx_buf_trx.len = length;584 585 ret = spi_async(devrec->spi, &devrec->tx_msg);586 if (ret)587 dev_err(printdev(devrec), "SPI write Failed for TX buf\n");588 589 return ret;590}591 592static int mrf24j40_tx(struct ieee802154_hw *hw, struct sk_buff *skb)593{594 struct mrf24j40 *devrec = hw->priv;595 596 dev_dbg(printdev(devrec), "tx packet of %d bytes\n", skb->len);597 devrec->tx_skb = skb;598 599 return write_tx_buf(devrec, 0x000, skb->data, skb->len);600}601 602static int mrf24j40_ed(struct ieee802154_hw *hw, u8 *level)603{604 /* TODO: */605 pr_warn("mrf24j40: ed not implemented\n");606 *level = 0;607 return 0;608}609 610static int mrf24j40_start(struct ieee802154_hw *hw)611{612 struct mrf24j40 *devrec = hw->priv;613 614 dev_dbg(printdev(devrec), "start\n");615 616 /* Clear TXNIE and RXIE. Enable interrupts */617 return regmap_update_bits(devrec->regmap_short, REG_INTCON,618 BIT_TXNIE | BIT_RXIE | BIT_SECIE, 0);619}620 621static void mrf24j40_stop(struct ieee802154_hw *hw)622{623 struct mrf24j40 *devrec = hw->priv;624 625 dev_dbg(printdev(devrec), "stop\n");626 627 /* Set TXNIE and RXIE. Disable Interrupts */628 regmap_update_bits(devrec->regmap_short, REG_INTCON,629 BIT_TXNIE | BIT_RXIE, BIT_TXNIE | BIT_RXIE);630}631 632static int mrf24j40_set_channel(struct ieee802154_hw *hw, u8 page, u8 channel)633{634 struct mrf24j40 *devrec = hw->priv;635 u8 val;636 int ret;637 638 dev_dbg(printdev(devrec), "Set Channel %d\n", channel);639 640 WARN_ON(page != 0);641 WARN_ON(channel < MRF24J40_CHAN_MIN);642 WARN_ON(channel > MRF24J40_CHAN_MAX);643 644 /* Set Channel TODO */645 val = (channel - 11) << RFCON0_CH_SHIFT | RFOPT_RECOMMEND;646 ret = regmap_update_bits(devrec->regmap_long, REG_RFCON0,647 RFCON0_CH_MASK, val);648 if (ret)649 return ret;650 651 /* RF Reset */652 ret = regmap_update_bits(devrec->regmap_short, REG_RFCTL, BIT_RFRST,653 BIT_RFRST);654 if (ret)655 return ret;656 657 ret = regmap_update_bits(devrec->regmap_short, REG_RFCTL, BIT_RFRST, 0);658 if (!ret)659 udelay(SET_CHANNEL_DELAY_US); /* per datasheet */660 661 return ret;662}663 664static int mrf24j40_filter(struct ieee802154_hw *hw,665 struct ieee802154_hw_addr_filt *filt,666 unsigned long changed)667{668 struct mrf24j40 *devrec = hw->priv;669 670 dev_dbg(printdev(devrec), "filter\n");671 672 if (changed & IEEE802154_AFILT_SADDR_CHANGED) {673 /* Short Addr */674 u8 addrh, addrl;675 676 addrh = le16_to_cpu(filt->short_addr) >> 8 & 0xff;677 addrl = le16_to_cpu(filt->short_addr) & 0xff;678 679 regmap_write(devrec->regmap_short, REG_SADRH, addrh);680 regmap_write(devrec->regmap_short, REG_SADRL, addrl);681 dev_dbg(printdev(devrec),682 "Set short addr to %04hx\n", filt->short_addr);683 }684 685 if (changed & IEEE802154_AFILT_IEEEADDR_CHANGED) {686 /* Device Address */687 u8 i, addr[8];688 689 memcpy(addr, &filt->ieee_addr, 8);690 for (i = 0; i < 8; i++)691 regmap_write(devrec->regmap_short, REG_EADR0 + i,692 addr[i]);693 694#ifdef DEBUG695 pr_debug("Set long addr to: ");696 for (i = 0; i < 8; i++)697 pr_debug("%02hhx ", addr[7 - i]);698 pr_debug("\n");699#endif700 }701 702 if (changed & IEEE802154_AFILT_PANID_CHANGED) {703 /* PAN ID */704 u8 panidl, panidh;705 706 panidh = le16_to_cpu(filt->pan_id) >> 8 & 0xff;707 panidl = le16_to_cpu(filt->pan_id) & 0xff;708 regmap_write(devrec->regmap_short, REG_PANIDH, panidh);709 regmap_write(devrec->regmap_short, REG_PANIDL, panidl);710 711 dev_dbg(printdev(devrec), "Set PANID to %04hx\n", filt->pan_id);712 }713 714 if (changed & IEEE802154_AFILT_PANC_CHANGED) {715 /* Pan Coordinator */716 u8 val;717 int ret;718 719 if (filt->pan_coord)720 val = BIT_PANCOORD;721 else722 val = 0;723 ret = regmap_update_bits(devrec->regmap_short, REG_RXMCR,724 BIT_PANCOORD, val);725 if (ret)726 return ret;727 728 /* REG_SLOTTED is maintained as default (unslotted/CSMA-CA).729 * REG_ORDER is maintained as default (no beacon/superframe).730 */731 732 dev_dbg(printdev(devrec), "Set Pan Coord to %s\n",733 filt->pan_coord ? "on" : "off");734 }735 736 return 0;737}738 739static void mrf24j40_handle_rx_read_buf_unlock(struct mrf24j40 *devrec)740{741 int ret;742 743 /* Turn back on reception of packets off the air. */744 devrec->rx_msg.complete = NULL;745 devrec->rx_buf[0] = MRF24J40_WRITESHORT(REG_BBREG1);746 devrec->rx_buf[1] = 0x00; /* CLR RXDECINV */747 ret = spi_async(devrec->spi, &devrec->rx_msg);748 if (ret)749 dev_err(printdev(devrec), "failed to unlock rx buffer\n");750}751 752static void mrf24j40_handle_rx_read_buf_complete(void *context)753{754 struct mrf24j40 *devrec = context;755 u8 len = devrec->rx_buf[2];756 u8 rx_local_buf[RX_FIFO_SIZE];757 struct sk_buff *skb;758 759 memcpy(rx_local_buf, devrec->rx_fifo_buf, len);760 mrf24j40_handle_rx_read_buf_unlock(devrec);761 762 skb = dev_alloc_skb(IEEE802154_MTU);763 if (!skb) {764 dev_err(printdev(devrec), "failed to allocate skb\n");765 return;766 }767 768 skb_put_data(skb, rx_local_buf, len);769 ieee802154_rx_irqsafe(devrec->hw, skb, 0);770 771#ifdef DEBUG772 print_hex_dump(KERN_DEBUG, "mrf24j40 rx: ", DUMP_PREFIX_OFFSET, 16, 1,773 rx_local_buf, len, 0);774 pr_debug("mrf24j40 rx: lqi: %02hhx rssi: %02hhx\n",775 devrec->rx_lqi_buf[0], devrec->rx_lqi_buf[1]);776#endif777}778 779static void mrf24j40_handle_rx_read_buf(void *context)780{781 struct mrf24j40 *devrec = context;782 u16 cmd;783 int ret;784 785 /* if length is invalid read the full MTU */786 if (!ieee802154_is_valid_psdu_len(devrec->rx_buf[2]))787 devrec->rx_buf[2] = IEEE802154_MTU;788 789 cmd = MRF24J40_READLONG(REG_RX_FIFO + 1);790 devrec->rx_addr_buf[0] = cmd >> 8 & 0xff;791 devrec->rx_addr_buf[1] = cmd & 0xff;792 devrec->rx_fifo_buf_trx.len = devrec->rx_buf[2];793 ret = spi_async(devrec->spi, &devrec->rx_buf_msg);794 if (ret) {795 dev_err(printdev(devrec), "failed to read rx buffer\n");796 mrf24j40_handle_rx_read_buf_unlock(devrec);797 }798}799 800static void mrf24j40_handle_rx_read_len(void *context)801{802 struct mrf24j40 *devrec = context;803 u16 cmd;804 int ret;805 806 /* read the length of received frame */807 devrec->rx_msg.complete = mrf24j40_handle_rx_read_buf;808 devrec->rx_trx.len = 3;809 cmd = MRF24J40_READLONG(REG_RX_FIFO);810 devrec->rx_buf[0] = cmd >> 8 & 0xff;811 devrec->rx_buf[1] = cmd & 0xff;812 813 ret = spi_async(devrec->spi, &devrec->rx_msg);814 if (ret) {815 dev_err(printdev(devrec), "failed to read rx buffer length\n");816 mrf24j40_handle_rx_read_buf_unlock(devrec);817 }818}819 820static int mrf24j40_handle_rx(struct mrf24j40 *devrec)821{822 /* Turn off reception of packets off the air. This prevents the823 * device from overwriting the buffer while we're reading it.824 */825 devrec->rx_msg.complete = mrf24j40_handle_rx_read_len;826 devrec->rx_trx.len = 2;827 devrec->rx_buf[0] = MRF24J40_WRITESHORT(REG_BBREG1);828 devrec->rx_buf[1] = BIT_RXDECINV; /* SET RXDECINV */829 830 return spi_async(devrec->spi, &devrec->rx_msg);831}832 833static int834mrf24j40_csma_params(struct ieee802154_hw *hw, u8 min_be, u8 max_be,835 u8 retries)836{837 struct mrf24j40 *devrec = hw->priv;838 u8 val;839 840 /* min_be */841 val = min_be << TXMCR_MIN_BE_SHIFT;842 /* csma backoffs */843 val |= retries << TXMCR_CSMA_RETRIES_SHIFT;844 845 return regmap_update_bits(devrec->regmap_short, REG_TXMCR,846 TXMCR_MIN_BE_MASK | TXMCR_CSMA_RETRIES_MASK,847 val);848}849 850static int mrf24j40_set_cca_mode(struct ieee802154_hw *hw,851 const struct wpan_phy_cca *cca)852{853 struct mrf24j40 *devrec = hw->priv;854 u8 val;855 856 /* mapping 802.15.4 to driver spec */857 switch (cca->mode) {858 case NL802154_CCA_ENERGY:859 val = 2;860 break;861 case NL802154_CCA_CARRIER:862 val = 1;863 break;864 case NL802154_CCA_ENERGY_CARRIER:865 switch (cca->opt) {866 case NL802154_CCA_OPT_ENERGY_CARRIER_AND:867 val = 3;868 break;869 default:870 return -EINVAL;871 }872 break;873 default:874 return -EINVAL;875 }876 877 return regmap_update_bits(devrec->regmap_short, REG_BBREG2,878 BBREG2_CCA_MODE_MASK,879 val << BBREG2_CCA_MODE_SHIFT);880}881 882/* array for representing ed levels */883static const s32 mrf24j40_ed_levels[] = {884 -9000, -8900, -8800, -8700, -8600, -8500, -8400, -8300, -8200, -8100,885 -8000, -7900, -7800, -7700, -7600, -7500, -7400, -7300, -7200, -7100,886 -7000, -6900, -6800, -6700, -6600, -6500, -6400, -6300, -6200, -6100,887 -6000, -5900, -5800, -5700, -5600, -5500, -5400, -5300, -5200, -5100,888 -5000, -4900, -4800, -4700, -4600, -4500, -4400, -4300, -4200, -4100,889 -4000, -3900, -3800, -3700, -3600, -3500890};891 892/* map ed levels to register value */893static const s32 mrf24j40_ed_levels_map[][2] = {894 { -9000, 0 }, { -8900, 1 }, { -8800, 2 }, { -8700, 5 }, { -8600, 9 },895 { -8500, 13 }, { -8400, 18 }, { -8300, 23 }, { -8200, 27 },896 { -8100, 32 }, { -8000, 37 }, { -7900, 43 }, { -7800, 48 },897 { -7700, 53 }, { -7600, 58 }, { -7500, 63 }, { -7400, 68 },898 { -7300, 73 }, { -7200, 78 }, { -7100, 83 }, { -7000, 89 },899 { -6900, 95 }, { -6800, 100 }, { -6700, 107 }, { -6600, 111 },900 { -6500, 117 }, { -6400, 121 }, { -6300, 125 }, { -6200, 129 },901 { -6100, 133 }, { -6000, 138 }, { -5900, 143 }, { -5800, 148 },902 { -5700, 153 }, { -5600, 159 }, { -5500, 165 }, { -5400, 170 },903 { -5300, 176 }, { -5200, 183 }, { -5100, 188 }, { -5000, 193 },904 { -4900, 198 }, { -4800, 203 }, { -4700, 207 }, { -4600, 212 },905 { -4500, 216 }, { -4400, 221 }, { -4300, 225 }, { -4200, 228 },906 { -4100, 233 }, { -4000, 239 }, { -3900, 245 }, { -3800, 250 },907 { -3700, 253 }, { -3600, 254 }, { -3500, 255 },908};909 910static int mrf24j40_set_cca_ed_level(struct ieee802154_hw *hw, s32 mbm)911{912 struct mrf24j40 *devrec = hw->priv;913 int i;914 915 for (i = 0; i < ARRAY_SIZE(mrf24j40_ed_levels_map); i++) {916 if (mrf24j40_ed_levels_map[i][0] == mbm)917 return regmap_write(devrec->regmap_short, REG_CCAEDTH,918 mrf24j40_ed_levels_map[i][1]);919 }920 921 return -EINVAL;922}923 924static const s32 mrf24j40ma_powers[] = {925 0, -50, -120, -190, -280, -370, -490, -630, -1000, -1050, -1120, -1190,926 -1280, -1370, -1490, -1630, -2000, -2050, -2120, -2190, -2280, -2370,927 -2490, -2630, -3000, -3050, -3120, -3190, -3280, -3370, -3490, -3630,928};929 930static int mrf24j40_set_txpower(struct ieee802154_hw *hw, s32 mbm)931{932 struct mrf24j40 *devrec = hw->priv;933 s32 small_scale;934 u8 val;935 936 if (0 >= mbm && mbm > -1000) {937 val = TXPWRL_0 << TXPWRL_SHIFT;938 small_scale = mbm;939 } else if (-1000 >= mbm && mbm > -2000) {940 val = TXPWRL_10 << TXPWRL_SHIFT;941 small_scale = mbm + 1000;942 } else if (-2000 >= mbm && mbm > -3000) {943 val = TXPWRL_20 << TXPWRL_SHIFT;944 small_scale = mbm + 2000;945 } else if (-3000 >= mbm && mbm > -4000) {946 val = TXPWRL_30 << TXPWRL_SHIFT;947 small_scale = mbm + 3000;948 } else {949 return -EINVAL;950 }951 952 switch (small_scale) {953 case 0:954 val |= (TXPWRS_0 << TXPWRS_SHIFT);955 break;956 case -50:957 val |= (TXPWRS_0_5 << TXPWRS_SHIFT);958 break;959 case -120:960 val |= (TXPWRS_1_2 << TXPWRS_SHIFT);961 break;962 case -190:963 val |= (TXPWRS_1_9 << TXPWRS_SHIFT);964 break;965 case -280:966 val |= (TXPWRS_2_8 << TXPWRS_SHIFT);967 break;968 case -370:969 val |= (TXPWRS_3_7 << TXPWRS_SHIFT);970 break;971 case -490:972 val |= (TXPWRS_4_9 << TXPWRS_SHIFT);973 break;974 case -630:975 val |= (TXPWRS_6_3 << TXPWRS_SHIFT);976 break;977 default:978 return -EINVAL;979 }980 981 return regmap_update_bits(devrec->regmap_long, REG_RFCON3,982 TXPWRL_MASK | TXPWRS_MASK, val);983}984 985static int mrf24j40_set_promiscuous_mode(struct ieee802154_hw *hw, bool on)986{987 struct mrf24j40 *devrec = hw->priv;988 int ret;989 990 if (on) {991 /* set PROMI, ERRPKT and NOACKRSP */992 ret = regmap_update_bits(devrec->regmap_short, REG_RXMCR,993 BIT_PROMI | BIT_ERRPKT | BIT_NOACKRSP,994 BIT_PROMI | BIT_ERRPKT | BIT_NOACKRSP);995 } else {996 /* clear PROMI, ERRPKT and NOACKRSP */997 ret = regmap_update_bits(devrec->regmap_short, REG_RXMCR,998 BIT_PROMI | BIT_ERRPKT | BIT_NOACKRSP,999 0);1000 }1001 1002 return ret;1003}1004 1005static const struct ieee802154_ops mrf24j40_ops = {1006 .owner = THIS_MODULE,1007 .xmit_async = mrf24j40_tx,1008 .ed = mrf24j40_ed,1009 .start = mrf24j40_start,1010 .stop = mrf24j40_stop,1011 .set_channel = mrf24j40_set_channel,1012 .set_hw_addr_filt = mrf24j40_filter,1013 .set_csma_params = mrf24j40_csma_params,1014 .set_cca_mode = mrf24j40_set_cca_mode,1015 .set_cca_ed_level = mrf24j40_set_cca_ed_level,1016 .set_txpower = mrf24j40_set_txpower,1017 .set_promiscuous_mode = mrf24j40_set_promiscuous_mode,1018};1019 1020static void mrf24j40_intstat_complete(void *context)1021{1022 struct mrf24j40 *devrec = context;1023 u8 intstat = devrec->irq_buf[1];1024 1025 enable_irq(devrec->spi->irq);1026 1027 /* Ignore Rx security decryption */1028 if (intstat & BIT_SECIF)1029 regmap_write_async(devrec->regmap_short, REG_SECCON0,1030 BIT_SECIGNORE);1031 1032 /* Check for TX complete */1033 if (intstat & BIT_TXNIF)1034 ieee802154_xmit_complete(devrec->hw, devrec->tx_skb, false);1035 1036 /* Check for Rx */1037 if (intstat & BIT_RXIF)1038 mrf24j40_handle_rx(devrec);1039}1040 1041static irqreturn_t mrf24j40_isr(int irq, void *data)1042{1043 struct mrf24j40 *devrec = data;1044 int ret;1045 1046 disable_irq_nosync(irq);1047 1048 devrec->irq_buf[0] = MRF24J40_READSHORT(REG_INTSTAT);1049 devrec->irq_buf[1] = 0;1050 1051 /* Read the interrupt status */1052 ret = spi_async(devrec->spi, &devrec->irq_msg);1053 if (ret) {1054 enable_irq(irq);1055 return IRQ_NONE;1056 }1057 1058 return IRQ_HANDLED;1059}1060 1061static int mrf24j40_hw_init(struct mrf24j40 *devrec)1062{1063 u32 irq_type;1064 int ret;1065 1066 /* Initialize the device.1067 From datasheet section 3.2: Initialization. */1068 ret = regmap_write(devrec->regmap_short, REG_SOFTRST, 0x07);1069 if (ret)1070 goto err_ret;1071 1072 ret = regmap_write(devrec->regmap_short, REG_PACON2, 0x98);1073 if (ret)1074 goto err_ret;1075 1076 ret = regmap_write(devrec->regmap_short, REG_TXSTBL, 0x95);1077 if (ret)1078 goto err_ret;1079 1080 ret = regmap_write(devrec->regmap_long, REG_RFCON0, 0x03);1081 if (ret)1082 goto err_ret;1083 1084 ret = regmap_write(devrec->regmap_long, REG_RFCON1, 0x01);1085 if (ret)1086 goto err_ret;1087 1088 ret = regmap_write(devrec->regmap_long, REG_RFCON2, 0x80);1089 if (ret)1090 goto err_ret;1091 1092 ret = regmap_write(devrec->regmap_long, REG_RFCON6, 0x90);1093 if (ret)1094 goto err_ret;1095 1096 ret = regmap_write(devrec->regmap_long, REG_RFCON7, 0x80);1097 if (ret)1098 goto err_ret;1099 1100 ret = regmap_write(devrec->regmap_long, REG_RFCON8, 0x10);1101 if (ret)1102 goto err_ret;1103 1104 ret = regmap_write(devrec->regmap_long, REG_SLPCON1, 0x21);1105 if (ret)1106 goto err_ret;1107 1108 ret = regmap_write(devrec->regmap_short, REG_BBREG2, 0x80);1109 if (ret)1110 goto err_ret;1111 1112 ret = regmap_write(devrec->regmap_short, REG_CCAEDTH, 0x60);1113 if (ret)1114 goto err_ret;1115 1116 ret = regmap_write(devrec->regmap_short, REG_BBREG6, 0x40);1117 if (ret)1118 goto err_ret;1119 1120 ret = regmap_write(devrec->regmap_short, REG_RFCTL, 0x04);1121 if (ret)1122 goto err_ret;1123 1124 ret = regmap_write(devrec->regmap_short, REG_RFCTL, 0x0);1125 if (ret)1126 goto err_ret;1127 1128 udelay(192);1129 1130 /* Set RX Mode. RXMCR<1:0>: 0x0 normal, 0x1 promisc, 0x2 error */1131 ret = regmap_update_bits(devrec->regmap_short, REG_RXMCR, 0x03, 0x00);1132 if (ret)1133 goto err_ret;1134 1135 if (spi_get_device_id(devrec->spi)->driver_data == MRF24J40MC) {1136 /* Enable external amplifier.1137 * From MRF24J40MC datasheet section 1.3: Operation.1138 */1139 regmap_update_bits(devrec->regmap_long, REG_TESTMODE, 0x07,1140 0x07);1141 1142 /* Set GPIO3 as output. */1143 regmap_update_bits(devrec->regmap_short, REG_TRISGPIO, 0x08,1144 0x08);1145 1146 /* Set GPIO3 HIGH to enable U5 voltage regulator */1147 regmap_update_bits(devrec->regmap_short, REG_GPIO, 0x08, 0x08);1148 1149 /* Reduce TX pwr to meet FCC requirements.1150 * From MRF24J40MC datasheet section 3.1.11151 */1152 regmap_write(devrec->regmap_long, REG_RFCON3, 0x28);1153 }1154 1155 irq_type = irq_get_trigger_type(devrec->spi->irq);1156 if (irq_type == IRQ_TYPE_EDGE_RISING ||1157 irq_type == IRQ_TYPE_EDGE_FALLING)1158 dev_warn(&devrec->spi->dev,1159 "Using edge triggered irq's are not recommended, because it can cause races and result in a non-functional driver!\n");1160 switch (irq_type) {1161 case IRQ_TYPE_EDGE_RISING:1162 case IRQ_TYPE_LEVEL_HIGH:1163 /* set interrupt polarity to rising */1164 ret = regmap_update_bits(devrec->regmap_long, REG_SLPCON0,1165 BIT_INTEDGE, BIT_INTEDGE);1166 if (ret)1167 goto err_ret;1168 break;1169 default:1170 /* default is falling edge */1171 break;1172 }1173 1174 return 0;1175 1176err_ret:1177 return ret;1178}1179 1180static void1181mrf24j40_setup_tx_spi_messages(struct mrf24j40 *devrec)1182{1183 spi_message_init(&devrec->tx_msg);1184 devrec->tx_msg.context = devrec;1185 devrec->tx_msg.complete = write_tx_buf_complete;1186 devrec->tx_hdr_trx.len = 2;1187 devrec->tx_hdr_trx.tx_buf = devrec->tx_hdr_buf;1188 spi_message_add_tail(&devrec->tx_hdr_trx, &devrec->tx_msg);1189 devrec->tx_len_trx.len = 2;1190 devrec->tx_len_trx.tx_buf = devrec->tx_len_buf;1191 spi_message_add_tail(&devrec->tx_len_trx, &devrec->tx_msg);1192 spi_message_add_tail(&devrec->tx_buf_trx, &devrec->tx_msg);1193 1194 spi_message_init(&devrec->tx_post_msg);1195 devrec->tx_post_msg.context = devrec;1196 devrec->tx_post_trx.len = 2;1197 devrec->tx_post_trx.tx_buf = devrec->tx_post_buf;1198 spi_message_add_tail(&devrec->tx_post_trx, &devrec->tx_post_msg);1199}1200 1201static void1202mrf24j40_setup_rx_spi_messages(struct mrf24j40 *devrec)1203{1204 spi_message_init(&devrec->rx_msg);1205 devrec->rx_msg.context = devrec;1206 devrec->rx_trx.len = 2;1207 devrec->rx_trx.tx_buf = devrec->rx_buf;1208 devrec->rx_trx.rx_buf = devrec->rx_buf;1209 spi_message_add_tail(&devrec->rx_trx, &devrec->rx_msg);1210 1211 spi_message_init(&devrec->rx_buf_msg);1212 devrec->rx_buf_msg.context = devrec;1213 devrec->rx_buf_msg.complete = mrf24j40_handle_rx_read_buf_complete;1214 devrec->rx_addr_trx.len = 2;1215 devrec->rx_addr_trx.tx_buf = devrec->rx_addr_buf;1216 spi_message_add_tail(&devrec->rx_addr_trx, &devrec->rx_buf_msg);1217 devrec->rx_fifo_buf_trx.rx_buf = devrec->rx_fifo_buf;1218 spi_message_add_tail(&devrec->rx_fifo_buf_trx, &devrec->rx_buf_msg);1219 devrec->rx_lqi_trx.len = 2;1220 devrec->rx_lqi_trx.rx_buf = devrec->rx_lqi_buf;1221 spi_message_add_tail(&devrec->rx_lqi_trx, &devrec->rx_buf_msg);1222}1223 1224static void1225mrf24j40_setup_irq_spi_messages(struct mrf24j40 *devrec)1226{1227 spi_message_init(&devrec->irq_msg);1228 devrec->irq_msg.context = devrec;1229 devrec->irq_msg.complete = mrf24j40_intstat_complete;1230 devrec->irq_trx.len = 2;1231 devrec->irq_trx.tx_buf = devrec->irq_buf;1232 devrec->irq_trx.rx_buf = devrec->irq_buf;1233 spi_message_add_tail(&devrec->irq_trx, &devrec->irq_msg);1234}1235 1236static void mrf24j40_phy_setup(struct mrf24j40 *devrec)1237{1238 ieee802154_random_extended_addr(&devrec->hw->phy->perm_extended_addr);1239 devrec->hw->phy->current_channel = 11;1240 1241 /* mrf24j40 supports max_minbe 0 - 3 */1242 devrec->hw->phy->supported.max_minbe = 3;1243 /* datasheet doesn't say anything about max_be, but we have min_be1244 * So we assume the max_be default.1245 */1246 devrec->hw->phy->supported.min_maxbe = 5;1247 devrec->hw->phy->supported.max_maxbe = 5;1248 1249 devrec->hw->phy->cca.mode = NL802154_CCA_CARRIER;1250 devrec->hw->phy->supported.cca_modes = BIT(NL802154_CCA_ENERGY) |1251 BIT(NL802154_CCA_CARRIER) |1252 BIT(NL802154_CCA_ENERGY_CARRIER);1253 devrec->hw->phy->supported.cca_opts = BIT(NL802154_CCA_OPT_ENERGY_CARRIER_AND);1254 1255 devrec->hw->phy->cca_ed_level = -6900;1256 devrec->hw->phy->supported.cca_ed_levels = mrf24j40_ed_levels;1257 devrec->hw->phy->supported.cca_ed_levels_size = ARRAY_SIZE(mrf24j40_ed_levels);1258 1259 switch (spi_get_device_id(devrec->spi)->driver_data) {1260 case MRF24J40:1261 case MRF24J40MA:1262 devrec->hw->phy->supported.tx_powers = mrf24j40ma_powers;1263 devrec->hw->phy->supported.tx_powers_size = ARRAY_SIZE(mrf24j40ma_powers);1264 devrec->hw->phy->flags |= WPAN_PHY_FLAG_TXPOWER;1265 break;1266 default:1267 break;1268 }1269}1270 1271static int mrf24j40_probe(struct spi_device *spi)1272{1273 int ret = -ENOMEM, irq_type;1274 struct ieee802154_hw *hw;1275 struct mrf24j40 *devrec;1276 1277 dev_info(&spi->dev, "probe(). IRQ: %d\n", spi->irq);1278 1279 /* Register with the 802154 subsystem */1280 1281 hw = ieee802154_alloc_hw(sizeof(*devrec), &mrf24j40_ops);1282 if (!hw)1283 goto err_ret;1284 1285 devrec = hw->priv;1286 devrec->spi = spi;1287 spi_set_drvdata(spi, devrec);1288 devrec->hw = hw;1289 devrec->hw->parent = &spi->dev;1290 devrec->hw->phy->supported.channels[0] = CHANNEL_MASK;1291 devrec->hw->flags = IEEE802154_HW_TX_OMIT_CKSUM | IEEE802154_HW_AFILT |1292 IEEE802154_HW_CSMA_PARAMS |1293 IEEE802154_HW_PROMISCUOUS;1294 1295 devrec->hw->phy->flags = WPAN_PHY_FLAG_CCA_MODE |1296 WPAN_PHY_FLAG_CCA_ED_LEVEL;1297 1298 mrf24j40_setup_tx_spi_messages(devrec);1299 mrf24j40_setup_rx_spi_messages(devrec);1300 mrf24j40_setup_irq_spi_messages(devrec);1301 1302 devrec->regmap_short = devm_regmap_init_spi(spi,1303 &mrf24j40_short_regmap);1304 if (IS_ERR(devrec->regmap_short)) {1305 ret = PTR_ERR(devrec->regmap_short);1306 dev_err(&spi->dev, "Failed to allocate short register map: %d\n",1307 ret);1308 goto err_register_device;1309 }1310 1311 devrec->regmap_long = devm_regmap_init(&spi->dev,1312 &mrf24j40_long_regmap_bus,1313 spi, &mrf24j40_long_regmap);1314 if (IS_ERR(devrec->regmap_long)) {1315 ret = PTR_ERR(devrec->regmap_long);1316 dev_err(&spi->dev, "Failed to allocate long register map: %d\n",1317 ret);1318 goto err_register_device;1319 }1320 1321 if (spi->max_speed_hz > MAX_SPI_SPEED_HZ) {1322 dev_warn(&spi->dev, "spi clock above possible maximum: %d",1323 MAX_SPI_SPEED_HZ);1324 ret = -EINVAL;1325 goto err_register_device;1326 }1327 1328 ret = mrf24j40_hw_init(devrec);1329 if (ret)1330 goto err_register_device;1331 1332 mrf24j40_phy_setup(devrec);1333 1334 /* request IRQF_TRIGGER_LOW as fallback default */1335 irq_type = irq_get_trigger_type(spi->irq);1336 if (!irq_type)1337 irq_type = IRQF_TRIGGER_LOW;1338 1339 ret = devm_request_irq(&spi->dev, spi->irq, mrf24j40_isr,1340 irq_type, dev_name(&spi->dev), devrec);1341 if (ret) {1342 dev_err(printdev(devrec), "Unable to get IRQ");1343 goto err_register_device;1344 }1345 1346 dev_dbg(printdev(devrec), "registered mrf24j40\n");1347 ret = ieee802154_register_hw(devrec->hw);1348 if (ret)1349 goto err_register_device;1350 1351 return 0;1352 1353err_register_device:1354 ieee802154_free_hw(devrec->hw);1355err_ret:1356 return ret;1357}1358 1359static void mrf24j40_remove(struct spi_device *spi)1360{1361 struct mrf24j40 *devrec = spi_get_drvdata(spi);1362 1363 dev_dbg(printdev(devrec), "remove\n");1364 1365 ieee802154_unregister_hw(devrec->hw);1366 ieee802154_free_hw(devrec->hw);1367 /* TODO: Will ieee802154_free_device() wait until ->xmit() is1368 * complete? */1369}1370 1371static const struct of_device_id mrf24j40_of_match[] = {1372 { .compatible = "microchip,mrf24j40", .data = (void *)MRF24J40 },1373 { .compatible = "microchip,mrf24j40ma", .data = (void *)MRF24J40MA },1374 { .compatible = "microchip,mrf24j40mc", .data = (void *)MRF24J40MC },1375 { },1376};1377MODULE_DEVICE_TABLE(of, mrf24j40_of_match);1378 1379static const struct spi_device_id mrf24j40_ids[] = {1380 { "mrf24j40", MRF24J40 },1381 { "mrf24j40ma", MRF24J40MA },1382 { "mrf24j40mc", MRF24J40MC },1383 { },1384};1385MODULE_DEVICE_TABLE(spi, mrf24j40_ids);1386 1387static struct spi_driver mrf24j40_driver = {1388 .driver = {1389 .of_match_table = mrf24j40_of_match,1390 .name = "mrf24j40",1391 },1392 .id_table = mrf24j40_ids,1393 .probe = mrf24j40_probe,1394 .remove = mrf24j40_remove,1395};1396 1397module_spi_driver(mrf24j40_driver);1398 1399MODULE_LICENSE("GPL");1400MODULE_AUTHOR("Alan Ott");1401MODULE_DESCRIPTION("MRF24J40 SPI 802.15.4 Controller Driver");1402