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1// SPDX-License-Identifier: GPL-2.02 3/* Copyright (C) 2021-2024 Linaro Ltd. */4 5#include <linux/array_size.h>6#include <linux/log2.h>7 8#include "../ipa_data.h"9#include "../ipa_endpoint.h"10#include "../ipa_mem.h"11#include "../ipa_version.h"12 13/** enum ipa_resource_type - IPA resource types for an SoC having IPA v4.5 */14enum ipa_resource_type {15 /* Source resource types; first must have value 0 */16 IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS = 0,17 IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS,18 IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF,19 IPA_RESOURCE_TYPE_SRC_HPS_DMARS,20 IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES,21 22 /* Destination resource types; first must have value 0 */23 IPA_RESOURCE_TYPE_DST_DATA_SECTORS = 0,24 IPA_RESOURCE_TYPE_DST_DPS_DMARS,25};26 27/* Resource groups used for an SoC having IPA v4.5 */28enum ipa_rsrc_group_id {29 /* Source resource group identifiers */30 IPA_RSRC_GROUP_SRC_UNUSED_0 = 0,31 IPA_RSRC_GROUP_SRC_UL_DL,32 IPA_RSRC_GROUP_SRC_UNUSED_2,33 IPA_RSRC_GROUP_SRC_UNUSED_3,34 IPA_RSRC_GROUP_SRC_UC_RX_Q,35 IPA_RSRC_GROUP_SRC_COUNT, /* Last in set; not a source group */36 37 /* Destination resource group identifiers */38 IPA_RSRC_GROUP_DST_UNUSED_0 = 0,39 IPA_RSRC_GROUP_DST_UL_DL_DPL,40 IPA_RSRC_GROUP_DST_UNUSED_2,41 IPA_RSRC_GROUP_DST_UNUSED_3,42 IPA_RSRC_GROUP_DST_UC,43 IPA_RSRC_GROUP_DST_COUNT, /* Last; not a destination group */44};45 46/* QSB configuration data for an SoC having IPA v4.5 */47static const struct ipa_qsb_data ipa_qsb_data[] = {48 [IPA_QSB_MASTER_DDR] = {49 .max_writes = 8,50 .max_reads = 0, /* no limit (hardware max) */51 .max_reads_beats = 120,52 },53 [IPA_QSB_MASTER_PCIE] = {54 .max_writes = 8,55 .max_reads = 12,56 /* no outstanding read byte (beat) limit */57 },58};59 60/* Endpoint configuration data for an SoC having IPA v4.5 */61static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = {62 [IPA_ENDPOINT_AP_COMMAND_TX] = {63 .ee_id = GSI_EE_AP,64 .channel_id = 9,65 .endpoint_id = 7,66 .toward_ipa = true,67 .channel = {68 .tre_count = 256,69 .event_count = 256,70 .tlv_count = 20,71 },72 .endpoint = {73 .config = {74 .resource_group = IPA_RSRC_GROUP_SRC_UL_DL,75 .dma_mode = true,76 .dma_endpoint = IPA_ENDPOINT_AP_LAN_RX,77 .tx = {78 .seq_type = IPA_SEQ_DMA,79 },80 },81 },82 },83 [IPA_ENDPOINT_AP_LAN_RX] = {84 .ee_id = GSI_EE_AP,85 .channel_id = 10,86 .endpoint_id = 16,87 .toward_ipa = false,88 .channel = {89 .tre_count = 256,90 .event_count = 256,91 .tlv_count = 9,92 },93 .endpoint = {94 .config = {95 .resource_group = IPA_RSRC_GROUP_DST_UL_DL_DPL,96 .aggregation = true,97 .status_enable = true,98 .rx = {99 .buffer_size = 8192,100 .pad_align = ilog2(sizeof(u32)),101 .aggr_time_limit = 500,102 },103 },104 },105 },106 [IPA_ENDPOINT_AP_MODEM_TX] = {107 .ee_id = GSI_EE_AP,108 .channel_id = 7,109 .endpoint_id = 2,110 .toward_ipa = true,111 .channel = {112 .tre_count = 512,113 .event_count = 512,114 .tlv_count = 16,115 },116 .endpoint = {117 .filter_support = true,118 .config = {119 .resource_group = IPA_RSRC_GROUP_SRC_UL_DL,120 .checksum = true,121 .qmap = true,122 .status_enable = true,123 .tx = {124 .seq_type = IPA_SEQ_2_PASS_SKIP_LAST_UC,125 .status_endpoint =126 IPA_ENDPOINT_MODEM_AP_RX,127 },128 },129 },130 },131 [IPA_ENDPOINT_AP_MODEM_RX] = {132 .ee_id = GSI_EE_AP,133 .channel_id = 1,134 .endpoint_id = 14,135 .toward_ipa = false,136 .channel = {137 .tre_count = 256,138 .event_count = 256,139 .tlv_count = 9,140 },141 .endpoint = {142 .config = {143 .resource_group = IPA_RSRC_GROUP_DST_UL_DL_DPL,144 .checksum = true,145 .qmap = true,146 .aggregation = true,147 .rx = {148 .buffer_size = 8192,149 .aggr_time_limit = 500,150 .aggr_close_eof = true,151 },152 },153 },154 },155 [IPA_ENDPOINT_MODEM_AP_TX] = {156 .ee_id = GSI_EE_MODEM,157 .channel_id = 0,158 .endpoint_id = 5,159 .toward_ipa = true,160 .endpoint = {161 .filter_support = true,162 },163 },164 [IPA_ENDPOINT_MODEM_AP_RX] = {165 .ee_id = GSI_EE_MODEM,166 .channel_id = 7,167 .endpoint_id = 21,168 .toward_ipa = false,169 },170 [IPA_ENDPOINT_MODEM_DL_NLO_TX] = {171 .ee_id = GSI_EE_MODEM,172 .channel_id = 2,173 .endpoint_id = 8,174 .toward_ipa = true,175 .endpoint = {176 .filter_support = true,177 },178 },179};180 181/* Source resource configuration data for an SoC having IPA v4.5 */182static const struct ipa_resource ipa_resource_src[] = {183 [IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS] = {184 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {185 .min = 1, .max = 11,186 },187 .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {188 .min = 1, .max = 63,189 },190 },191 [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS] = {192 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {193 .min = 14, .max = 14,194 },195 .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {196 .min = 3, .max = 3,197 },198 },199 [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF] = {200 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {201 .min = 18, .max = 18,202 },203 .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {204 .min = 8, .max = 8,205 },206 },207 [IPA_RESOURCE_TYPE_SRC_HPS_DMARS] = {208 .limits[IPA_RSRC_GROUP_SRC_UNUSED_0] = {209 .min = 0, .max = 63,210 },211 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {212 .min = 0, .max = 63,213 },214 .limits[IPA_RSRC_GROUP_SRC_UNUSED_2] = {215 .min = 0, .max = 63,216 },217 .limits[IPA_RSRC_GROUP_SRC_UNUSED_3] = {218 .min = 0, .max = 63,219 },220 .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {221 .min = 0, .max = 63,222 },223 },224 [IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES] = {225 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {226 .min = 24, .max = 24,227 },228 .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {229 .min = 8, .max = 8,230 },231 },232};233 234/* Destination resource configuration data for an SoC having IPA v4.5 */235static const struct ipa_resource ipa_resource_dst[] = {236 [IPA_RESOURCE_TYPE_DST_DATA_SECTORS] = {237 .limits[IPA_RSRC_GROUP_DST_UL_DL_DPL] = {238 .min = 16, .max = 16,239 },240 .limits[IPA_RSRC_GROUP_DST_UNUSED_2] = {241 .min = 2, .max = 2,242 },243 .limits[IPA_RSRC_GROUP_DST_UNUSED_3] = {244 .min = 2, .max = 2,245 },246 },247 [IPA_RESOURCE_TYPE_DST_DPS_DMARS] = {248 .limits[IPA_RSRC_GROUP_DST_UL_DL_DPL] = {249 .min = 2, .max = 63,250 },251 .limits[IPA_RSRC_GROUP_DST_UNUSED_2] = {252 .min = 1, .max = 2,253 },254 .limits[IPA_RSRC_GROUP_DST_UNUSED_3] = {255 .min = 1, .max = 2,256 },257 .limits[IPA_RSRC_GROUP_DST_UC] = {258 .min = 0, .max = 2,259 },260 },261};262 263/* Resource configuration data for an SoC having IPA v4.5 */264static const struct ipa_resource_data ipa_resource_data = {265 .rsrc_group_src_count = IPA_RSRC_GROUP_SRC_COUNT,266 .rsrc_group_dst_count = IPA_RSRC_GROUP_DST_COUNT,267 .resource_src_count = ARRAY_SIZE(ipa_resource_src),268 .resource_src = ipa_resource_src,269 .resource_dst_count = ARRAY_SIZE(ipa_resource_dst),270 .resource_dst = ipa_resource_dst,271};272 273/* IPA-resident memory region data for an SoC having IPA v4.5 */274static const struct ipa_mem ipa_mem_local_data[] = {275 {276 .id = IPA_MEM_UC_SHARED,277 .offset = 0x0000,278 .size = 0x0080,279 .canary_count = 0,280 },281 {282 .id = IPA_MEM_UC_INFO,283 .offset = 0x0080,284 .size = 0x0200,285 .canary_count = 0,286 },287 {288 .id = IPA_MEM_V4_FILTER_HASHED,289 .offset = 0x0288,290 .size = 0x0078,291 .canary_count = 2,292 },293 {294 .id = IPA_MEM_V4_FILTER,295 .offset = 0x0308,296 .size = 0x0078,297 .canary_count = 2,298 },299 {300 .id = IPA_MEM_V6_FILTER_HASHED,301 .offset = 0x0388,302 .size = 0x0078,303 .canary_count = 2,304 },305 {306 .id = IPA_MEM_V6_FILTER,307 .offset = 0x0408,308 .size = 0x0078,309 .canary_count = 2,310 },311 {312 .id = IPA_MEM_V4_ROUTE_HASHED,313 .offset = 0x0488,314 .size = 0x0078,315 .canary_count = 2,316 },317 {318 .id = IPA_MEM_V4_ROUTE,319 .offset = 0x0508,320 .size = 0x0078,321 .canary_count = 2,322 },323 {324 .id = IPA_MEM_V6_ROUTE_HASHED,325 .offset = 0x0588,326 .size = 0x0078,327 .canary_count = 2,328 },329 {330 .id = IPA_MEM_V6_ROUTE,331 .offset = 0x0608,332 .size = 0x0078,333 .canary_count = 2,334 },335 {336 .id = IPA_MEM_MODEM_HEADER,337 .offset = 0x0688,338 .size = 0x0240,339 .canary_count = 2,340 },341 {342 .id = IPA_MEM_AP_HEADER,343 .offset = 0x08c8,344 .size = 0x0200,345 .canary_count = 0,346 },347 {348 .id = IPA_MEM_MODEM_PROC_CTX,349 .offset = 0x0ad0,350 .size = 0x0b20,351 .canary_count = 2,352 },353 {354 .id = IPA_MEM_AP_PROC_CTX,355 .offset = 0x15f0,356 .size = 0x0200,357 .canary_count = 0,358 },359 {360 .id = IPA_MEM_NAT_TABLE,361 .offset = 0x1800,362 .size = 0x0d00,363 .canary_count = 4,364 },365 {366 .id = IPA_MEM_STATS_QUOTA_MODEM,367 .offset = 0x2510,368 .size = 0x0030,369 .canary_count = 4,370 },371 {372 .id = IPA_MEM_STATS_QUOTA_AP,373 .offset = 0x2540,374 .size = 0x0048,375 .canary_count = 0,376 },377 {378 .id = IPA_MEM_STATS_TETHERING,379 .offset = 0x2588,380 .size = 0x0238,381 .canary_count = 0,382 },383 {384 .id = IPA_MEM_STATS_FILTER_ROUTE,385 .offset = 0x27c0,386 .size = 0x0800,387 .canary_count = 0,388 },389 {390 .id = IPA_MEM_STATS_DROP,391 .offset = 0x2fc0,392 .size = 0x0020,393 .canary_count = 0,394 },395 {396 .id = IPA_MEM_MODEM,397 .offset = 0x2fe8,398 .size = 0x0800,399 .canary_count = 2,400 },401 {402 .id = IPA_MEM_UC_EVENT_RING,403 .offset = 0x3800,404 .size = 0x1000,405 .canary_count = 1,406 },407 {408 .id = IPA_MEM_PDN_CONFIG,409 .offset = 0x4800,410 .size = 0x0050,411 .canary_count = 0,412 },413};414 415/* Memory configuration data for an SoC having IPA v4.5 */416static const struct ipa_mem_data ipa_mem_data = {417 .local_count = ARRAY_SIZE(ipa_mem_local_data),418 .local = ipa_mem_local_data,419 .imem_addr = 0x14688000,420 .imem_size = 0x00003000,421 .smem_id = 497,422 .smem_size = 0x00009000,423};424 425/* Interconnect rates are in 1000 byte/second units */426static const struct ipa_interconnect_data ipa_interconnect_data[] = {427 {428 .name = "memory",429 .peak_bandwidth = 600000, /* 600 MBps */430 .average_bandwidth = 150000, /* 150 MBps */431 },432 /* Average rate is unused for the next two interconnects */433 {434 .name = "imem",435 .peak_bandwidth = 450000, /* 450 MBps */436 .average_bandwidth = 75000, /* 75 MBps (unused?) */437 },438 {439 .name = "config",440 .peak_bandwidth = 171400, /* 171.4 MBps */441 .average_bandwidth = 0, /* unused */442 },443};444 445/* Clock and interconnect configuration data for an SoC having IPA v4.5 */446static const struct ipa_power_data ipa_power_data = {447 .core_clock_rate = 150 * 1000 * 1000, /* Hz (150? 60?) */448 .interconnect_count = ARRAY_SIZE(ipa_interconnect_data),449 .interconnect_data = ipa_interconnect_data,450};451 452/* Configuration data for an SoC having IPA v4.5 */453const struct ipa_data ipa_data_v4_5 = {454 .version = IPA_VERSION_4_5,455 .qsb_count = ARRAY_SIZE(ipa_qsb_data),456 .qsb_data = ipa_qsb_data,457 .modem_route_count = 8,458 .endpoint_count = ARRAY_SIZE(ipa_gsi_endpoint_data),459 .endpoint_data = ipa_gsi_endpoint_data,460 .resource_data = &ipa_resource_data,461 .mem_data = &ipa_mem_data,462 .power_data = &ipa_power_data,463};464