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1// SPDX-License-Identifier: GPL-2.02 3/* Copyright (C) 2022-2024 Linaro Ltd. */4 5#include <linux/array_size.h>6#include <linux/bits.h>7#include <linux/types.h>8 9#include "../ipa_reg.h"10#include "../ipa_version.h"11 12static const u32 reg_comp_cfg_fmask[] = {13 [RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS] = BIT(0),14 [GSI_SNOC_BYPASS_DIS] = BIT(1),15 [GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2),16 [GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3),17 /* Bit 4 reserved */18 [IPA_QMB_SELECT_CONS_EN] = BIT(5),19 [IPA_QMB_SELECT_PROD_EN] = BIT(6),20 [GSI_MULTI_INORDER_RD_DIS] = BIT(7),21 [GSI_MULTI_INORDER_WR_DIS] = BIT(8),22 [GEN_QMB_0_MULTI_INORDER_RD_DIS] = BIT(9),23 [GEN_QMB_1_MULTI_INORDER_RD_DIS] = BIT(10),24 [GEN_QMB_0_MULTI_INORDER_WR_DIS] = BIT(11),25 [GEN_QMB_1_MULTI_INORDER_WR_DIS] = BIT(12),26 [GEN_QMB_0_SNOC_CNOC_LOOP_PROT_DIS] = BIT(13),27 [GSI_SNOC_CNOC_LOOP_PROT_DISABLE] = BIT(14),28 [GSI_MULTI_AXI_MASTERS_DIS] = BIT(15),29 [IPA_QMB_SELECT_GLOBAL_EN] = BIT(16),30 [FULL_FLUSH_WAIT_RS_CLOSURE_EN] = BIT(17),31 /* Bit 18 reserved */32 [QMB_RAM_RD_CACHE_DISABLE] = BIT(19),33 [GENQMB_AOOOWR] = BIT(20),34 [IF_OUT_OF_BUF_STOP_RESET_MASK_EN] = BIT(21),35 [ATOMIC_FETCHER_ARB_LOCK_DIS] = GENMASK(23, 22),36 /* Bits 24-29 reserved */37 [GEN_QMB_1_DYNAMIC_ASIZE] = BIT(30),38 [GEN_QMB_0_DYNAMIC_ASIZE] = BIT(31),39};40 41REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c);42 43static const u32 reg_clkon_cfg_fmask[] = {44 [CLKON_RX] = BIT(0),45 [CLKON_PROC] = BIT(1),46 [TX_WRAPPER] = BIT(2),47 [CLKON_MISC] = BIT(3),48 [RAM_ARB] = BIT(4),49 [FTCH_HPS] = BIT(5),50 [FTCH_DPS] = BIT(6),51 [CLKON_HPS] = BIT(7),52 [CLKON_DPS] = BIT(8),53 [RX_HPS_CMDQS] = BIT(9),54 [HPS_DPS_CMDQS] = BIT(10),55 [DPS_TX_CMDQS] = BIT(11),56 [RSRC_MNGR] = BIT(12),57 [CTX_HANDLER] = BIT(13),58 [ACK_MNGR] = BIT(14),59 [D_DCPH] = BIT(15),60 [H_DCPH] = BIT(16),61 /* Bit 17 reserved */62 [NTF_TX_CMDQS] = BIT(18),63 [CLKON_TX_0] = BIT(19),64 [CLKON_TX_1] = BIT(20),65 [CLKON_FNR] = BIT(21),66 [QSB2AXI_CMDQ_L] = BIT(22),67 [AGGR_WRAPPER] = BIT(23),68 [RAM_SLAVEWAY] = BIT(24),69 [CLKON_QMB] = BIT(25),70 [WEIGHT_ARB] = BIT(26),71 [GSI_IF] = BIT(27),72 [CLKON_GLOBAL] = BIT(28),73 [GLOBAL_2X_CLK] = BIT(29),74 [DPL_FIFO] = BIT(30),75 [DRBIP] = BIT(31),76};77 78REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044);79 80static const u32 reg_route_fmask[] = {81 [ROUTE_DIS] = BIT(0),82 [ROUTE_DEF_PIPE] = GENMASK(5, 1),83 [ROUTE_DEF_HDR_TABLE] = BIT(6),84 [ROUTE_DEF_HDR_OFST] = GENMASK(16, 7),85 [ROUTE_FRAG_DEF_PIPE] = GENMASK(21, 17),86 /* Bits 22-23 reserved */87 [ROUTE_DEF_RETAIN_HDR] = BIT(24),88 /* Bits 25-31 reserved */89};90 91REG_FIELDS(ROUTE, route, 0x00000048);92 93static const u32 reg_shared_mem_size_fmask[] = {94 [MEM_SIZE] = GENMASK(15, 0),95 [MEM_BADDR] = GENMASK(31, 16),96};97 98REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054);99 100static const u32 reg_qsb_max_writes_fmask[] = {101 [GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0),102 [GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4),103 /* Bits 8-31 reserved */104};105 106REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074);107 108static const u32 reg_qsb_max_reads_fmask[] = {109 [GEN_QMB_0_MAX_READS] = GENMASK(3, 0),110 [GEN_QMB_1_MAX_READS] = GENMASK(7, 4),111 /* Bits 8-15 reserved */112 [GEN_QMB_0_MAX_READS_BEATS] = GENMASK(23, 16),113 [GEN_QMB_1_MAX_READS_BEATS] = GENMASK(31, 24),114};115 116REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000078);117 118static const u32 reg_filt_rout_hash_flush_fmask[] = {119 [IPV6_ROUTER_HASH] = BIT(0),120 /* Bits 1-3 reserved */121 [IPV6_FILTER_HASH] = BIT(4),122 /* Bits 5-7 reserved */123 [IPV4_ROUTER_HASH] = BIT(8),124 /* Bits 9-11 reserved */125 [IPV4_FILTER_HASH] = BIT(12),126 /* Bits 13-31 reserved */127};128 129REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x000014c);130 131/* Valid bits defined by ipa->available */132REG_STRIDE(STATE_AGGR_ACTIVE, state_aggr_active, 0x000000b4, 0x0004);133 134static const u32 reg_local_pkt_proc_cntxt_fmask[] = {135 [IPA_BASE_ADDR] = GENMASK(17, 0),136 /* Bits 18-31 reserved */137};138 139/* Offset must be a multiple of 8 */140REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8);141 142/* Valid bits defined by ipa->available */143REG_STRIDE(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec, 0x0004);144 145static const u32 reg_ipa_tx_cfg_fmask[] = {146 /* Bits 0-1 reserved */147 [PREFETCH_ALMOST_EMPTY_SIZE_TX0] = GENMASK(5, 2),148 [DMAW_SCND_OUTSD_PRED_THRESHOLD] = GENMASK(9, 6),149 [DMAW_SCND_OUTSD_PRED_EN] = BIT(10),150 [DMAW_MAX_BEATS_256_DIS] = BIT(11),151 [PA_MASK_EN] = BIT(12),152 [PREFETCH_ALMOST_EMPTY_SIZE_TX1] = GENMASK(16, 13),153 [DUAL_TX_ENABLE] = BIT(17),154 [SSPND_PA_NO_START_STATE] = BIT(18),155 /* Bits 19-31 reserved */156};157 158REG_FIELDS(IPA_TX_CFG, ipa_tx_cfg, 0x000001fc);159 160static const u32 reg_flavor_0_fmask[] = {161 [MAX_PIPES] = GENMASK(4, 0),162 /* Bits 5-7 reserved */163 [MAX_CONS_PIPES] = GENMASK(12, 8),164 /* Bits 13-15 reserved */165 [MAX_PROD_PIPES] = GENMASK(20, 16),166 /* Bits 21-23 reserved */167 [PROD_LOWEST] = GENMASK(27, 24),168 /* Bits 28-31 reserved */169};170 171REG_FIELDS(FLAVOR_0, flavor_0, 0x00000210);172 173static const u32 reg_idle_indication_cfg_fmask[] = {174 [ENTER_IDLE_DEBOUNCE_THRESH] = GENMASK(15, 0),175 [CONST_NON_IDLE_ENABLE] = BIT(16),176 /* Bits 17-31 reserved */177};178 179REG_FIELDS(IDLE_INDICATION_CFG, idle_indication_cfg, 0x00000240);180 181static const u32 reg_qtime_timestamp_cfg_fmask[] = {182 [DPL_TIMESTAMP_LSB] = GENMASK(4, 0),183 /* Bits 5-6 reserved */184 [DPL_TIMESTAMP_SEL] = BIT(7),185 [TAG_TIMESTAMP_LSB] = GENMASK(12, 8),186 /* Bits 13-15 reserved */187 [NAT_TIMESTAMP_LSB] = GENMASK(20, 16),188 /* Bits 21-31 reserved */189};190 191REG_FIELDS(QTIME_TIMESTAMP_CFG, qtime_timestamp_cfg, 0x0000024c);192 193static const u32 reg_timers_xo_clk_div_cfg_fmask[] = {194 [DIV_VALUE] = GENMASK(8, 0),195 /* Bits 9-30 reserved */196 [DIV_ENABLE] = BIT(31),197};198 199REG_FIELDS(TIMERS_XO_CLK_DIV_CFG, timers_xo_clk_div_cfg, 0x00000250);200 201static const u32 reg_timers_pulse_gran_cfg_fmask[] = {202 [PULSE_GRAN_0] = GENMASK(2, 0),203 [PULSE_GRAN_1] = GENMASK(5, 3),204 [PULSE_GRAN_2] = GENMASK(8, 6),205 /* Bits 9-31 reserved */206};207 208REG_FIELDS(TIMERS_PULSE_GRAN_CFG, timers_pulse_gran_cfg, 0x00000254);209 210static const u32 reg_src_rsrc_grp_01_rsrc_type_fmask[] = {211 [X_MIN_LIM] = GENMASK(5, 0),212 /* Bits 6-7 reserved */213 [X_MAX_LIM] = GENMASK(13, 8),214 /* Bits 14-15 reserved */215 [Y_MIN_LIM] = GENMASK(21, 16),216 /* Bits 22-23 reserved */217 [Y_MAX_LIM] = GENMASK(29, 24),218 /* Bits 30-31 reserved */219};220 221REG_STRIDE_FIELDS(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type,222 0x00000400, 0x0020);223 224static const u32 reg_src_rsrc_grp_23_rsrc_type_fmask[] = {225 [X_MIN_LIM] = GENMASK(5, 0),226 /* Bits 6-7 reserved */227 [X_MAX_LIM] = GENMASK(13, 8),228 /* Bits 14-15 reserved */229 [Y_MIN_LIM] = GENMASK(21, 16),230 /* Bits 22-23 reserved */231 [Y_MAX_LIM] = GENMASK(29, 24),232 /* Bits 30-31 reserved */233};234 235REG_STRIDE_FIELDS(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type,236 0x00000404, 0x0020);237 238static const u32 reg_dst_rsrc_grp_01_rsrc_type_fmask[] = {239 [X_MIN_LIM] = GENMASK(5, 0),240 /* Bits 6-7 reserved */241 [X_MAX_LIM] = GENMASK(13, 8),242 /* Bits 14-15 reserved */243 [Y_MIN_LIM] = GENMASK(21, 16),244 /* Bits 22-23 reserved */245 [Y_MAX_LIM] = GENMASK(29, 24),246 /* Bits 30-31 reserved */247};248 249REG_STRIDE_FIELDS(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type,250 0x00000500, 0x0020);251 252static const u32 reg_dst_rsrc_grp_23_rsrc_type_fmask[] = {253 [X_MIN_LIM] = GENMASK(5, 0),254 /* Bits 6-7 reserved */255 [X_MAX_LIM] = GENMASK(13, 8),256 /* Bits 14-15 reserved */257 [Y_MIN_LIM] = GENMASK(21, 16),258 /* Bits 22-23 reserved */259 [Y_MAX_LIM] = GENMASK(29, 24),260 /* Bits 30-31 reserved */261};262 263REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type,264 0x00000504, 0x0020);265 266static const u32 reg_endp_init_cfg_fmask[] = {267 [FRAG_OFFLOAD_EN] = BIT(0),268 [CS_OFFLOAD_EN] = GENMASK(2, 1),269 [CS_METADATA_HDR_OFFSET] = GENMASK(6, 3),270 /* Bit 7 reserved */271 [CS_GEN_QMB_MASTER_SEL] = BIT(8),272 /* Bits 9-31 reserved */273};274 275REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070);276 277static const u32 reg_endp_init_nat_fmask[] = {278 [NAT_EN] = GENMASK(1, 0),279 /* Bits 2-31 reserved */280};281 282REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070);283 284static const u32 reg_endp_init_hdr_fmask[] = {285 [HDR_LEN] = GENMASK(5, 0),286 [HDR_OFST_METADATA_VALID] = BIT(6),287 [HDR_OFST_METADATA] = GENMASK(12, 7),288 [HDR_ADDITIONAL_CONST_LEN] = GENMASK(18, 13),289 [HDR_OFST_PKT_SIZE_VALID] = BIT(19),290 [HDR_OFST_PKT_SIZE] = GENMASK(25, 20),291 /* Bit 26 reserved */292 [HDR_LEN_INC_DEAGG_HDR] = BIT(27),293 [HDR_LEN_MSB] = GENMASK(29, 28),294 [HDR_OFST_METADATA_MSB] = GENMASK(31, 30),295};296 297REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070);298 299static const u32 reg_endp_init_hdr_ext_fmask[] = {300 [HDR_ENDIANNESS] = BIT(0),301 [HDR_TOTAL_LEN_OR_PAD_VALID] = BIT(1),302 [HDR_TOTAL_LEN_OR_PAD] = BIT(2),303 [HDR_PAYLOAD_LEN_INC_PADDING] = BIT(3),304 [HDR_TOTAL_LEN_OR_PAD_OFFSET] = GENMASK(9, 4),305 [HDR_PAD_TO_ALIGNMENT] = GENMASK(13, 10),306 /* Bits 14-15 reserved */307 [HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB] = GENMASK(17, 16),308 [HDR_OFST_PKT_SIZE_MSB] = GENMASK(19, 18),309 [HDR_ADDITIONAL_CONST_LEN_MSB] = GENMASK(21, 20),310 /* Bits 22-31 reserved */311};312 313REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070);314 315REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask,316 0x00000818, 0x0070);317 318static const u32 reg_endp_init_mode_fmask[] = {319 [ENDP_MODE] = GENMASK(2, 0),320 [DCPH_ENABLE] = BIT(3),321 [DEST_PIPE_INDEX] = GENMASK(8, 4),322 /* Bits 9-11 reserved */323 [BYTE_THRESHOLD] = GENMASK(27, 12),324 [PIPE_REPLICATION_EN] = BIT(28),325 [PAD_EN] = BIT(29),326 [DRBIP_ACL_ENABLE] = BIT(30),327 /* Bit 31 reserved */328};329 330REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00000820, 0x0070);331 332static const u32 reg_endp_init_aggr_fmask[] = {333 [AGGR_EN] = GENMASK(1, 0),334 [AGGR_TYPE] = GENMASK(4, 2),335 [BYTE_LIMIT] = GENMASK(10, 5),336 /* Bit 11 reserved */337 [TIME_LIMIT] = GENMASK(16, 12),338 [PKT_LIMIT] = GENMASK(22, 17),339 [SW_EOF_ACTIVE] = BIT(23),340 [FORCE_CLOSE] = BIT(24),341 /* Bit 25 reserved */342 [HARD_BYTE_LIMIT_EN] = BIT(26),343 [AGGR_GRAN_SEL] = BIT(27),344 /* Bits 28-31 reserved */345};346 347REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00000824, 0x0070);348 349static const u32 reg_endp_init_hol_block_en_fmask[] = {350 [HOL_BLOCK_EN] = BIT(0),351 /* Bits 1-31 reserved */352};353 354REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_EN, endp_init_hol_block_en,355 0x0000082c, 0x0070);356 357static const u32 reg_endp_init_hol_block_timer_fmask[] = {358 [TIMER_LIMIT] = GENMASK(4, 0),359 /* Bits 5-7 reserved */360 [TIMER_GRAN_SEL] = BIT(8),361 /* Bits 9-31 reserved */362};363 364REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_TIMER, endp_init_hol_block_timer,365 0x00000830, 0x0070);366 367static const u32 reg_endp_init_deaggr_fmask[] = {368 [DEAGGR_HDR_LEN] = GENMASK(5, 0),369 [SYSPIPE_ERR_DETECTION] = BIT(6),370 [PACKET_OFFSET_VALID] = BIT(7),371 [PACKET_OFFSET_LOCATION] = GENMASK(13, 8),372 [IGNORE_MIN_PKT_ERR] = BIT(14),373 /* Bit 15 reserved */374 [MAX_PACKET_LEN] = GENMASK(31, 16),375};376 377REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00000834, 0x0070);378 379static const u32 reg_endp_init_rsrc_grp_fmask[] = {380 [ENDP_RSRC_GRP] = GENMASK(1, 0),381 /* Bits 2-31 reserved */382};383 384REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp, 0x00000838, 0x0070);385 386static const u32 reg_endp_init_seq_fmask[] = {387 [SEQ_TYPE] = GENMASK(7, 0),388 /* Bits 8-31 reserved */389};390 391REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000083c, 0x0070);392 393static const u32 reg_endp_status_fmask[] = {394 [STATUS_EN] = BIT(0),395 [STATUS_ENDP] = GENMASK(5, 1),396 /* Bits 6-8 reserved */397 [STATUS_PKT_SUPPRESS] = BIT(9),398 /* Bits 10-31 reserved */399};400 401REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00000840, 0x0070);402 403static const u32 reg_endp_filter_router_hsh_cfg_fmask[] = {404 [FILTER_HASH_MSK_SRC_ID] = BIT(0),405 [FILTER_HASH_MSK_SRC_IP] = BIT(1),406 [FILTER_HASH_MSK_DST_IP] = BIT(2),407 [FILTER_HASH_MSK_SRC_PORT] = BIT(3),408 [FILTER_HASH_MSK_DST_PORT] = BIT(4),409 [FILTER_HASH_MSK_PROTOCOL] = BIT(5),410 [FILTER_HASH_MSK_METADATA] = BIT(6),411 [FILTER_HASH_MSK_ALL] = GENMASK(6, 0),412 /* Bits 7-15 reserved */413 [ROUTER_HASH_MSK_SRC_ID] = BIT(16),414 [ROUTER_HASH_MSK_SRC_IP] = BIT(17),415 [ROUTER_HASH_MSK_DST_IP] = BIT(18),416 [ROUTER_HASH_MSK_SRC_PORT] = BIT(19),417 [ROUTER_HASH_MSK_DST_PORT] = BIT(20),418 [ROUTER_HASH_MSK_PROTOCOL] = BIT(21),419 [ROUTER_HASH_MSK_METADATA] = BIT(22),420 [ROUTER_HASH_MSK_ALL] = GENMASK(22, 16),421 /* Bits 23-31 reserved */422};423 424REG_STRIDE_FIELDS(ENDP_FILTER_ROUTER_HSH_CFG, endp_filter_router_hsh_cfg,425 0x0000085c, 0x0070);426 427/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */428REG(IPA_IRQ_STTS, ipa_irq_stts, 0x00004008 + 0x1000 * GSI_EE_AP);429 430/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */431REG(IPA_IRQ_EN, ipa_irq_en, 0x0000400c + 0x1000 * GSI_EE_AP);432 433/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */434REG(IPA_IRQ_CLR, ipa_irq_clr, 0x00004010 + 0x1000 * GSI_EE_AP);435 436static const u32 reg_ipa_irq_uc_fmask[] = {437 [UC_INTR] = BIT(0),438 /* Bits 1-31 reserved */439};440 441REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000401c + 0x1000 * GSI_EE_AP);442 443/* Valid bits defined by ipa->available */444REG_STRIDE(IRQ_SUSPEND_INFO, irq_suspend_info,445 0x00004030 + 0x1000 * GSI_EE_AP, 0x0004);446 447/* Valid bits defined by ipa->available */448REG_STRIDE(IRQ_SUSPEND_EN, irq_suspend_en,449 0x00004034 + 0x1000 * GSI_EE_AP, 0x0004);450 451/* Valid bits defined by ipa->available */452REG_STRIDE(IRQ_SUSPEND_CLR, irq_suspend_clr,453 0x00004038 + 0x1000 * GSI_EE_AP, 0x0004);454 455static const struct reg *reg_array[] = {456 [COMP_CFG] = ®_comp_cfg,457 [CLKON_CFG] = ®_clkon_cfg,458 [ROUTE] = ®_route,459 [SHARED_MEM_SIZE] = ®_shared_mem_size,460 [QSB_MAX_WRITES] = ®_qsb_max_writes,461 [QSB_MAX_READS] = ®_qsb_max_reads,462 [FILT_ROUT_HASH_FLUSH] = ®_filt_rout_hash_flush,463 [STATE_AGGR_ACTIVE] = ®_state_aggr_active,464 [LOCAL_PKT_PROC_CNTXT] = ®_local_pkt_proc_cntxt,465 [AGGR_FORCE_CLOSE] = ®_aggr_force_close,466 [IPA_TX_CFG] = ®_ipa_tx_cfg,467 [FLAVOR_0] = ®_flavor_0,468 [IDLE_INDICATION_CFG] = ®_idle_indication_cfg,469 [QTIME_TIMESTAMP_CFG] = ®_qtime_timestamp_cfg,470 [TIMERS_XO_CLK_DIV_CFG] = ®_timers_xo_clk_div_cfg,471 [TIMERS_PULSE_GRAN_CFG] = ®_timers_pulse_gran_cfg,472 [SRC_RSRC_GRP_01_RSRC_TYPE] = ®_src_rsrc_grp_01_rsrc_type,473 [SRC_RSRC_GRP_23_RSRC_TYPE] = ®_src_rsrc_grp_23_rsrc_type,474 [DST_RSRC_GRP_01_RSRC_TYPE] = ®_dst_rsrc_grp_01_rsrc_type,475 [DST_RSRC_GRP_23_RSRC_TYPE] = ®_dst_rsrc_grp_23_rsrc_type,476 [ENDP_INIT_CFG] = ®_endp_init_cfg,477 [ENDP_INIT_NAT] = ®_endp_init_nat,478 [ENDP_INIT_HDR] = ®_endp_init_hdr,479 [ENDP_INIT_HDR_EXT] = ®_endp_init_hdr_ext,480 [ENDP_INIT_HDR_METADATA_MASK] = ®_endp_init_hdr_metadata_mask,481 [ENDP_INIT_MODE] = ®_endp_init_mode,482 [ENDP_INIT_AGGR] = ®_endp_init_aggr,483 [ENDP_INIT_HOL_BLOCK_EN] = ®_endp_init_hol_block_en,484 [ENDP_INIT_HOL_BLOCK_TIMER] = ®_endp_init_hol_block_timer,485 [ENDP_INIT_DEAGGR] = ®_endp_init_deaggr,486 [ENDP_INIT_RSRC_GRP] = ®_endp_init_rsrc_grp,487 [ENDP_INIT_SEQ] = ®_endp_init_seq,488 [ENDP_STATUS] = ®_endp_status,489 [ENDP_FILTER_ROUTER_HSH_CFG] = ®_endp_filter_router_hsh_cfg,490 [IPA_IRQ_STTS] = ®_ipa_irq_stts,491 [IPA_IRQ_EN] = ®_ipa_irq_en,492 [IPA_IRQ_CLR] = ®_ipa_irq_clr,493 [IPA_IRQ_UC] = ®_ipa_irq_uc,494 [IRQ_SUSPEND_INFO] = ®_irq_suspend_info,495 [IRQ_SUSPEND_EN] = ®_irq_suspend_en,496 [IRQ_SUSPEND_CLR] = ®_irq_suspend_clr,497};498 499const struct regs ipa_regs_v4_11 = {500 .reg_count = ARRAY_SIZE(reg_array),501 .reg = reg_array,502};503