524 lines · c
1// SPDX-License-Identifier: GPL-2.02 3/* Copyright (C) 2022-2024 Linaro Ltd. */4 5#include <linux/array_size.h>6#include <linux/bits.h>7#include <linux/types.h>8 9#include "../ipa_reg.h"10#include "../ipa_version.h"11 12static const u32 reg_comp_cfg_fmask[] = {13 /* Bit 0 reserved */14 [GSI_SNOC_BYPASS_DIS] = BIT(1),15 [GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2),16 [GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3),17 /* Bit 4 reserved */18 [IPA_QMB_SELECT_CONS_EN] = BIT(5),19 [IPA_QMB_SELECT_PROD_EN] = BIT(6),20 [GSI_MULTI_INORDER_RD_DIS] = BIT(7),21 [GSI_MULTI_INORDER_WR_DIS] = BIT(8),22 [GEN_QMB_0_MULTI_INORDER_RD_DIS] = BIT(9),23 [GEN_QMB_1_MULTI_INORDER_RD_DIS] = BIT(10),24 [GEN_QMB_0_MULTI_INORDER_WR_DIS] = BIT(11),25 [GEN_QMB_1_MULTI_INORDER_WR_DIS] = BIT(12),26 [GEN_QMB_0_SNOC_CNOC_LOOP_PROT_DIS] = BIT(13),27 [GSI_SNOC_CNOC_LOOP_PROT_DISABLE] = BIT(14),28 [GSI_MULTI_AXI_MASTERS_DIS] = BIT(15),29 [IPA_QMB_SELECT_GLOBAL_EN] = BIT(16),30 [ATOMIC_FETCHER_ARB_LOCK_DIS] = GENMASK(20, 17),31 [FULL_FLUSH_WAIT_RS_CLOSURE_EN] = BIT(21),32 /* Bits 22-31 reserved */33};34 35REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c);36 37static const u32 reg_clkon_cfg_fmask[] = {38 [CLKON_RX] = BIT(0),39 [CLKON_PROC] = BIT(1),40 [TX_WRAPPER] = BIT(2),41 [CLKON_MISC] = BIT(3),42 [RAM_ARB] = BIT(4),43 [FTCH_HPS] = BIT(5),44 [FTCH_DPS] = BIT(6),45 [CLKON_HPS] = BIT(7),46 [CLKON_DPS] = BIT(8),47 [RX_HPS_CMDQS] = BIT(9),48 [HPS_DPS_CMDQS] = BIT(10),49 [DPS_TX_CMDQS] = BIT(11),50 [RSRC_MNGR] = BIT(12),51 [CTX_HANDLER] = BIT(13),52 [ACK_MNGR] = BIT(14),53 [D_DCPH] = BIT(15),54 [H_DCPH] = BIT(16),55 [CLKON_DCMP] = BIT(17),56 [NTF_TX_CMDQS] = BIT(18),57 [CLKON_TX_0] = BIT(19),58 [CLKON_TX_1] = BIT(20),59 [CLKON_FNR] = BIT(21),60 [QSB2AXI_CMDQ_L] = BIT(22),61 [AGGR_WRAPPER] = BIT(23),62 [RAM_SLAVEWAY] = BIT(24),63 [CLKON_QMB] = BIT(25),64 [WEIGHT_ARB] = BIT(26),65 [GSI_IF] = BIT(27),66 [CLKON_GLOBAL] = BIT(28),67 [GLOBAL_2X_CLK] = BIT(29),68 [DPL_FIFO] = BIT(30),69 /* Bit 31 reserved */70};71 72REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044);73 74static const u32 reg_route_fmask[] = {75 [ROUTE_DIS] = BIT(0),76 [ROUTE_DEF_PIPE] = GENMASK(5, 1),77 [ROUTE_DEF_HDR_TABLE] = BIT(6),78 [ROUTE_DEF_HDR_OFST] = GENMASK(16, 7),79 [ROUTE_FRAG_DEF_PIPE] = GENMASK(21, 17),80 /* Bits 22-23 reserved */81 [ROUTE_DEF_RETAIN_HDR] = BIT(24),82 /* Bits 25-31 reserved */83};84 85REG_FIELDS(ROUTE, route, 0x00000048);86 87static const u32 reg_shared_mem_size_fmask[] = {88 [MEM_SIZE] = GENMASK(15, 0),89 [MEM_BADDR] = GENMASK(31, 16),90};91 92REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054);93 94static const u32 reg_qsb_max_writes_fmask[] = {95 [GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0),96 [GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4),97 /* Bits 8-31 reserved */98};99 100REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074);101 102static const u32 reg_qsb_max_reads_fmask[] = {103 [GEN_QMB_0_MAX_READS] = GENMASK(3, 0),104 [GEN_QMB_1_MAX_READS] = GENMASK(7, 4),105 /* Bits 8-15 reserved */106 [GEN_QMB_0_MAX_READS_BEATS] = GENMASK(23, 16),107 [GEN_QMB_1_MAX_READS_BEATS] = GENMASK(31, 24),108};109 110REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000078);111 112static const u32 reg_filt_rout_hash_flush_fmask[] = {113 [IPV6_ROUTER_HASH] = BIT(0),114 /* Bits 1-3 reserved */115 [IPV6_FILTER_HASH] = BIT(4),116 /* Bits 5-7 reserved */117 [IPV4_ROUTER_HASH] = BIT(8),118 /* Bits 9-11 reserved */119 [IPV4_FILTER_HASH] = BIT(12),120 /* Bits 13-31 reserved */121};122 123REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x000014c);124 125/* Valid bits defined by ipa->available */126REG_STRIDE(STATE_AGGR_ACTIVE, state_aggr_active, 0x000000b4, 0x0004);127 128static const u32 reg_local_pkt_proc_cntxt_fmask[] = {129 [IPA_BASE_ADDR] = GENMASK(17, 0),130 /* Bits 18-31 reserved */131};132 133/* Offset must be a multiple of 8 */134REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8);135 136/* Valid bits defined by ipa->available */137REG_STRIDE(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec, 0x0004);138 139static const u32 reg_ipa_tx_cfg_fmask[] = {140 /* Bits 0-1 reserved */141 [PREFETCH_ALMOST_EMPTY_SIZE_TX0] = GENMASK(5, 2),142 [DMAW_SCND_OUTSD_PRED_THRESHOLD] = GENMASK(9, 6),143 [DMAW_SCND_OUTSD_PRED_EN] = BIT(10),144 [DMAW_MAX_BEATS_256_DIS] = BIT(11),145 [PA_MASK_EN] = BIT(12),146 [PREFETCH_ALMOST_EMPTY_SIZE_TX1] = GENMASK(16, 13),147 [DUAL_TX_ENABLE] = BIT(17),148 /* Bits 18-31 reserved */149};150 151REG_FIELDS(IPA_TX_CFG, ipa_tx_cfg, 0x000001fc);152 153static const u32 reg_flavor_0_fmask[] = {154 [MAX_PIPES] = GENMASK(3, 0),155 /* Bits 4-7 reserved */156 [MAX_CONS_PIPES] = GENMASK(12, 8),157 /* Bits 13-15 reserved */158 [MAX_PROD_PIPES] = GENMASK(20, 16),159 /* Bits 21-23 reserved */160 [PROD_LOWEST] = GENMASK(27, 24),161 /* Bits 28-31 reserved */162};163 164REG_FIELDS(FLAVOR_0, flavor_0, 0x00000210);165 166static const u32 reg_idle_indication_cfg_fmask[] = {167 [ENTER_IDLE_DEBOUNCE_THRESH] = GENMASK(15, 0),168 [CONST_NON_IDLE_ENABLE] = BIT(16),169 /* Bits 17-31 reserved */170};171 172REG_FIELDS(IDLE_INDICATION_CFG, idle_indication_cfg, 0x00000240);173 174static const u32 reg_qtime_timestamp_cfg_fmask[] = {175 [DPL_TIMESTAMP_LSB] = GENMASK(4, 0),176 /* Bits 5-6 reserved */177 [DPL_TIMESTAMP_SEL] = BIT(7),178 [TAG_TIMESTAMP_LSB] = GENMASK(12, 8),179 /* Bits 13-15 reserved */180 [NAT_TIMESTAMP_LSB] = GENMASK(20, 16),181 /* Bits 21-31 reserved */182};183 184REG_FIELDS(QTIME_TIMESTAMP_CFG, qtime_timestamp_cfg, 0x0000024c);185 186static const u32 reg_timers_xo_clk_div_cfg_fmask[] = {187 [DIV_VALUE] = GENMASK(8, 0),188 /* Bits 9-30 reserved */189 [DIV_ENABLE] = BIT(31),190};191 192REG_FIELDS(TIMERS_XO_CLK_DIV_CFG, timers_xo_clk_div_cfg, 0x00000250);193 194static const u32 reg_timers_pulse_gran_cfg_fmask[] = {195 [PULSE_GRAN_0] = GENMASK(2, 0),196 [PULSE_GRAN_1] = GENMASK(5, 3),197 [PULSE_GRAN_2] = GENMASK(8, 6),198};199 200REG_FIELDS(TIMERS_PULSE_GRAN_CFG, timers_pulse_gran_cfg, 0x00000254);201 202static const u32 reg_src_rsrc_grp_01_rsrc_type_fmask[] = {203 [X_MIN_LIM] = GENMASK(5, 0),204 /* Bits 6-7 reserved */205 [X_MAX_LIM] = GENMASK(13, 8),206 /* Bits 14-15 reserved */207 [Y_MIN_LIM] = GENMASK(21, 16),208 /* Bits 22-23 reserved */209 [Y_MAX_LIM] = GENMASK(29, 24),210 /* Bits 30-31 reserved */211};212 213REG_STRIDE_FIELDS(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type,214 0x00000400, 0x0020);215 216static const u32 reg_src_rsrc_grp_23_rsrc_type_fmask[] = {217 [X_MIN_LIM] = GENMASK(5, 0),218 /* Bits 6-7 reserved */219 [X_MAX_LIM] = GENMASK(13, 8),220 /* Bits 14-15 reserved */221 [Y_MIN_LIM] = GENMASK(21, 16),222 /* Bits 22-23 reserved */223 [Y_MAX_LIM] = GENMASK(29, 24),224 /* Bits 30-31 reserved */225};226 227REG_STRIDE_FIELDS(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type,228 0x00000404, 0x0020);229 230static const u32 reg_src_rsrc_grp_45_rsrc_type_fmask[] = {231 [X_MIN_LIM] = GENMASK(5, 0),232 /* Bits 6-7 reserved */233 [X_MAX_LIM] = GENMASK(13, 8),234 /* Bits 14-15 reserved */235 [Y_MIN_LIM] = GENMASK(21, 16),236 /* Bits 22-23 reserved */237 [Y_MAX_LIM] = GENMASK(29, 24),238 /* Bits 30-31 reserved */239};240 241REG_STRIDE_FIELDS(SRC_RSRC_GRP_45_RSRC_TYPE, src_rsrc_grp_45_rsrc_type,242 0x00000408, 0x0020);243 244static const u32 reg_dst_rsrc_grp_01_rsrc_type_fmask[] = {245 [X_MIN_LIM] = GENMASK(5, 0),246 /* Bits 6-7 reserved */247 [X_MAX_LIM] = GENMASK(13, 8),248 /* Bits 14-15 reserved */249 [Y_MIN_LIM] = GENMASK(21, 16),250 /* Bits 22-23 reserved */251 [Y_MAX_LIM] = GENMASK(29, 24),252 /* Bits 30-31 reserved */253};254 255REG_STRIDE_FIELDS(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type,256 0x00000500, 0x0020);257 258static const u32 reg_dst_rsrc_grp_23_rsrc_type_fmask[] = {259 [X_MIN_LIM] = GENMASK(5, 0),260 /* Bits 6-7 reserved */261 [X_MAX_LIM] = GENMASK(13, 8),262 /* Bits 14-15 reserved */263 [Y_MIN_LIM] = GENMASK(21, 16),264 /* Bits 22-23 reserved */265 [Y_MAX_LIM] = GENMASK(29, 24),266 /* Bits 30-31 reserved */267};268 269REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type,270 0x00000504, 0x0020);271 272static const u32 reg_dst_rsrc_grp_45_rsrc_type_fmask[] = {273 [X_MIN_LIM] = GENMASK(5, 0),274 /* Bits 6-7 reserved */275 [X_MAX_LIM] = GENMASK(13, 8),276 /* Bits 14-15 reserved */277 [Y_MIN_LIM] = GENMASK(21, 16),278 /* Bits 22-23 reserved */279 [Y_MAX_LIM] = GENMASK(29, 24),280 /* Bits 30-31 reserved */281};282 283REG_STRIDE_FIELDS(DST_RSRC_GRP_45_RSRC_TYPE, dst_rsrc_grp_45_rsrc_type,284 0x00000508, 0x0020);285 286static const u32 reg_endp_init_cfg_fmask[] = {287 [FRAG_OFFLOAD_EN] = BIT(0),288 [CS_OFFLOAD_EN] = GENMASK(2, 1),289 [CS_METADATA_HDR_OFFSET] = GENMASK(6, 3),290 /* Bit 7 reserved */291 [CS_GEN_QMB_MASTER_SEL] = BIT(8),292 /* Bits 9-31 reserved */293};294 295REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070);296 297static const u32 reg_endp_init_nat_fmask[] = {298 [NAT_EN] = GENMASK(1, 0),299 /* Bits 2-31 reserved */300};301 302REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070);303 304static const u32 reg_endp_init_hdr_fmask[] = {305 [HDR_LEN] = GENMASK(5, 0),306 [HDR_OFST_METADATA_VALID] = BIT(6),307 [HDR_OFST_METADATA] = GENMASK(12, 7),308 [HDR_ADDITIONAL_CONST_LEN] = GENMASK(18, 13),309 [HDR_OFST_PKT_SIZE_VALID] = BIT(19),310 [HDR_OFST_PKT_SIZE] = GENMASK(25, 20),311 [HDR_A5_MUX] = BIT(26),312 [HDR_LEN_INC_DEAGG_HDR] = BIT(27),313 [HDR_LEN_MSB] = GENMASK(29, 28),314 [HDR_OFST_METADATA_MSB] = GENMASK(31, 30),315};316 317REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070);318 319static const u32 reg_endp_init_hdr_ext_fmask[] = {320 [HDR_ENDIANNESS] = BIT(0),321 [HDR_TOTAL_LEN_OR_PAD_VALID] = BIT(1),322 [HDR_TOTAL_LEN_OR_PAD] = BIT(2),323 [HDR_PAYLOAD_LEN_INC_PADDING] = BIT(3),324 [HDR_TOTAL_LEN_OR_PAD_OFFSET] = GENMASK(9, 4),325 [HDR_PAD_TO_ALIGNMENT] = GENMASK(13, 10),326 /* Bits 14-15 reserved */327 [HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB] = GENMASK(17, 16),328 [HDR_OFST_PKT_SIZE_MSB] = GENMASK(19, 18),329 [HDR_ADDITIONAL_CONST_LEN_MSB] = GENMASK(21, 20),330 /* Bits 22-31 reserved */331};332 333REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070);334 335REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask,336 0x00000818, 0x0070);337 338static const u32 reg_endp_init_mode_fmask[] = {339 [ENDP_MODE] = GENMASK(2, 0),340 [DCPH_ENABLE] = BIT(3),341 [DEST_PIPE_INDEX] = GENMASK(8, 4),342 /* Bits 9-11 reserved */343 [BYTE_THRESHOLD] = GENMASK(27, 12),344 [PIPE_REPLICATION_EN] = BIT(28),345 [PAD_EN] = BIT(29),346 /* Bits 30-31 reserved */347};348 349REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00000820, 0x0070);350 351static const u32 reg_endp_init_aggr_fmask[] = {352 [AGGR_EN] = GENMASK(1, 0),353 [AGGR_TYPE] = GENMASK(4, 2),354 [BYTE_LIMIT] = GENMASK(10, 5),355 /* Bit 11 reserved */356 [TIME_LIMIT] = GENMASK(16, 12),357 [PKT_LIMIT] = GENMASK(22, 17),358 [SW_EOF_ACTIVE] = BIT(23),359 [FORCE_CLOSE] = BIT(24),360 /* Bit 25 reserved */361 [HARD_BYTE_LIMIT_EN] = BIT(26),362 [AGGR_GRAN_SEL] = BIT(27),363 /* Bits 28-31 reserved */364};365 366REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00000824, 0x0070);367 368static const u32 reg_endp_init_hol_block_en_fmask[] = {369 [HOL_BLOCK_EN] = BIT(0),370 /* Bits 1-31 reserved */371};372 373REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_EN, endp_init_hol_block_en,374 0x0000082c, 0x0070);375 376static const u32 reg_endp_init_hol_block_timer_fmask[] = {377 [TIMER_LIMIT] = GENMASK(4, 0),378 /* Bits 5-7 reserved */379 [TIMER_GRAN_SEL] = BIT(8),380 /* Bits 9-31 reserved */381};382 383REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_TIMER, endp_init_hol_block_timer,384 0x00000830, 0x0070);385 386static const u32 reg_endp_init_deaggr_fmask[] = {387 [DEAGGR_HDR_LEN] = GENMASK(5, 0),388 [SYSPIPE_ERR_DETECTION] = BIT(6),389 [PACKET_OFFSET_VALID] = BIT(7),390 [PACKET_OFFSET_LOCATION] = GENMASK(13, 8),391 [IGNORE_MIN_PKT_ERR] = BIT(14),392 /* Bit 15 reserved */393 [MAX_PACKET_LEN] = GENMASK(31, 16),394};395 396REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00000834, 0x0070);397 398static const u32 reg_endp_init_rsrc_grp_fmask[] = {399 [ENDP_RSRC_GRP] = GENMASK(2, 0),400 /* Bits 3-31 reserved */401};402 403REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp, 0x00000838, 0x0070);404 405static const u32 reg_endp_init_seq_fmask[] = {406 [SEQ_TYPE] = GENMASK(7, 0),407 /* Bits 8-31 reserved */408};409 410REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000083c, 0x0070);411 412static const u32 reg_endp_status_fmask[] = {413 [STATUS_EN] = BIT(0),414 [STATUS_ENDP] = GENMASK(5, 1),415 /* Bits 6-8 reserved */416 [STATUS_PKT_SUPPRESS] = BIT(9),417 /* Bits 10-31 reserved */418};419 420REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00000840, 0x0070);421 422static const u32 reg_endp_filter_router_hsh_cfg_fmask[] = {423 [FILTER_HASH_MSK_SRC_ID] = BIT(0),424 [FILTER_HASH_MSK_SRC_IP] = BIT(1),425 [FILTER_HASH_MSK_DST_IP] = BIT(2),426 [FILTER_HASH_MSK_SRC_PORT] = BIT(3),427 [FILTER_HASH_MSK_DST_PORT] = BIT(4),428 [FILTER_HASH_MSK_PROTOCOL] = BIT(5),429 [FILTER_HASH_MSK_METADATA] = BIT(6),430 [FILTER_HASH_MSK_ALL] = GENMASK(6, 0),431 /* Bits 7-15 reserved */432 [ROUTER_HASH_MSK_SRC_ID] = BIT(16),433 [ROUTER_HASH_MSK_SRC_IP] = BIT(17),434 [ROUTER_HASH_MSK_DST_IP] = BIT(18),435 [ROUTER_HASH_MSK_SRC_PORT] = BIT(19),436 [ROUTER_HASH_MSK_DST_PORT] = BIT(20),437 [ROUTER_HASH_MSK_PROTOCOL] = BIT(21),438 [ROUTER_HASH_MSK_METADATA] = BIT(22),439 [ROUTER_HASH_MSK_ALL] = GENMASK(22, 16),440 /* Bits 23-31 reserved */441};442 443REG_STRIDE_FIELDS(ENDP_FILTER_ROUTER_HSH_CFG, endp_filter_router_hsh_cfg,444 0x0000085c, 0x0070);445 446/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */447REG(IPA_IRQ_STTS, ipa_irq_stts, 0x00003008 + 0x1000 * GSI_EE_AP);448 449/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */450REG(IPA_IRQ_EN, ipa_irq_en, 0x0000300c + 0x1000 * GSI_EE_AP);451 452/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */453REG(IPA_IRQ_CLR, ipa_irq_clr, 0x00003010 + 0x1000 * GSI_EE_AP);454 455static const u32 reg_ipa_irq_uc_fmask[] = {456 [UC_INTR] = BIT(0),457 /* Bits 1-31 reserved */458};459 460REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000301c + 0x1000 * GSI_EE_AP);461 462/* Valid bits defined by ipa->available */463REG_STRIDE(IRQ_SUSPEND_INFO, irq_suspend_info,464 0x00003030 + 0x1000 * GSI_EE_AP, 0x0004);465 466/* Valid bits defined by ipa->available */467REG_STRIDE(IRQ_SUSPEND_EN, irq_suspend_en,468 0x00003034 + 0x1000 * GSI_EE_AP, 0x0004);469 470/* Valid bits defined by ipa->available */471REG_STRIDE(IRQ_SUSPEND_CLR, irq_suspend_clr,472 0x00003038 + 0x1000 * GSI_EE_AP, 0x0004);473 474static const struct reg *reg_array[] = {475 [COMP_CFG] = ®_comp_cfg,476 [CLKON_CFG] = ®_clkon_cfg,477 [ROUTE] = ®_route,478 [SHARED_MEM_SIZE] = ®_shared_mem_size,479 [QSB_MAX_WRITES] = ®_qsb_max_writes,480 [QSB_MAX_READS] = ®_qsb_max_reads,481 [FILT_ROUT_HASH_FLUSH] = ®_filt_rout_hash_flush,482 [STATE_AGGR_ACTIVE] = ®_state_aggr_active,483 [LOCAL_PKT_PROC_CNTXT] = ®_local_pkt_proc_cntxt,484 [AGGR_FORCE_CLOSE] = ®_aggr_force_close,485 [IPA_TX_CFG] = ®_ipa_tx_cfg,486 [FLAVOR_0] = ®_flavor_0,487 [IDLE_INDICATION_CFG] = ®_idle_indication_cfg,488 [QTIME_TIMESTAMP_CFG] = ®_qtime_timestamp_cfg,489 [TIMERS_XO_CLK_DIV_CFG] = ®_timers_xo_clk_div_cfg,490 [TIMERS_PULSE_GRAN_CFG] = ®_timers_pulse_gran_cfg,491 [SRC_RSRC_GRP_01_RSRC_TYPE] = ®_src_rsrc_grp_01_rsrc_type,492 [SRC_RSRC_GRP_23_RSRC_TYPE] = ®_src_rsrc_grp_23_rsrc_type,493 [SRC_RSRC_GRP_45_RSRC_TYPE] = ®_src_rsrc_grp_45_rsrc_type,494 [DST_RSRC_GRP_01_RSRC_TYPE] = ®_dst_rsrc_grp_01_rsrc_type,495 [DST_RSRC_GRP_23_RSRC_TYPE] = ®_dst_rsrc_grp_23_rsrc_type,496 [DST_RSRC_GRP_45_RSRC_TYPE] = ®_dst_rsrc_grp_45_rsrc_type,497 [ENDP_INIT_CFG] = ®_endp_init_cfg,498 [ENDP_INIT_NAT] = ®_endp_init_nat,499 [ENDP_INIT_HDR] = ®_endp_init_hdr,500 [ENDP_INIT_HDR_EXT] = ®_endp_init_hdr_ext,501 [ENDP_INIT_HDR_METADATA_MASK] = ®_endp_init_hdr_metadata_mask,502 [ENDP_INIT_MODE] = ®_endp_init_mode,503 [ENDP_INIT_AGGR] = ®_endp_init_aggr,504 [ENDP_INIT_HOL_BLOCK_EN] = ®_endp_init_hol_block_en,505 [ENDP_INIT_HOL_BLOCK_TIMER] = ®_endp_init_hol_block_timer,506 [ENDP_INIT_DEAGGR] = ®_endp_init_deaggr,507 [ENDP_INIT_RSRC_GRP] = ®_endp_init_rsrc_grp,508 [ENDP_INIT_SEQ] = ®_endp_init_seq,509 [ENDP_STATUS] = ®_endp_status,510 [ENDP_FILTER_ROUTER_HSH_CFG] = ®_endp_filter_router_hsh_cfg,511 [IPA_IRQ_STTS] = ®_ipa_irq_stts,512 [IPA_IRQ_EN] = ®_ipa_irq_en,513 [IPA_IRQ_CLR] = ®_ipa_irq_clr,514 [IPA_IRQ_UC] = ®_ipa_irq_uc,515 [IRQ_SUSPEND_INFO] = ®_irq_suspend_info,516 [IRQ_SUSPEND_EN] = ®_irq_suspend_en,517 [IRQ_SUSPEND_CLR] = ®_irq_suspend_clr,518};519 520const struct regs ipa_regs_v4_5 = {521 .reg_count = ARRAY_SIZE(reg_array),522 .reg = reg_array,523};524