353 lines · c
1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)2/*3 * Driver for Analog Devices Industrial Ethernet T1L PHYs4 *5 * Copyright 2020 Analog Devices Inc.6 */7#include <linux/kernel.h>8#include <linux/bitfield.h>9#include <linux/delay.h>10#include <linux/errno.h>11#include <linux/init.h>12#include <linux/module.h>13#include <linux/mii.h>14#include <linux/phy.h>15#include <linux/property.h>16 17#define PHY_ID_ADIN1100 0x0283bc8118#define PHY_ID_ADIN1110 0x0283bc9119#define PHY_ID_ADIN2111 0x0283bca120 21#define ADIN_PHY_SUBSYS_IRQ_MASK 0x002122#define ADIN_LINK_STAT_CHNG_IRQ_EN BIT(1)23 24#define ADIN_PHY_SUBSYS_IRQ_STATUS 0x001125#define ADIN_LINK_STAT_CHNG BIT(1)26 27#define ADIN_FORCED_MODE 0x800028#define ADIN_FORCED_MODE_EN BIT(0)29 30#define ADIN_CRSM_SFT_RST 0x881031#define ADIN_CRSM_SFT_RST_EN BIT(0)32 33#define ADIN_CRSM_SFT_PD_CNTRL 0x881234#define ADIN_CRSM_SFT_PD_CNTRL_EN BIT(0)35 36#define ADIN_AN_PHY_INST_STATUS 0x803037#define ADIN_IS_CFG_SLV BIT(2)38#define ADIN_IS_CFG_MST BIT(3)39 40#define ADIN_CRSM_STAT 0x881841#define ADIN_CRSM_SFT_PD_RDY BIT(1)42#define ADIN_CRSM_SYS_RDY BIT(0)43 44#define ADIN_MSE_VAL 0x830B45 46#define ADIN_SQI_MAX 747 48struct adin_mse_sqi_range {49 u16 start;50 u16 end;51};52 53static const struct adin_mse_sqi_range adin_mse_sqi_map[] = {54 { 0x0A74, 0xFFFF },55 { 0x084E, 0x0A74 },56 { 0x0698, 0x084E },57 { 0x053D, 0x0698 },58 { 0x0429, 0x053D },59 { 0x034E, 0x0429 },60 { 0x02A0, 0x034E },61 { 0x0000, 0x02A0 },62};63 64/**65 * struct adin_priv - ADIN PHY driver private data66 * @tx_level_2v4_able: set if the PHY supports 2.4V TX levels (10BASE-T1L)67 * @tx_level_2v4: set if the PHY requests 2.4V TX levels (10BASE-T1L)68 * @tx_level_prop_present: set if the TX level is specified in DT69 */70struct adin_priv {71 unsigned int tx_level_2v4_able:1;72 unsigned int tx_level_2v4:1;73 unsigned int tx_level_prop_present:1;74};75 76static int adin_read_status(struct phy_device *phydev)77{78 int ret;79 80 ret = genphy_c45_read_status(phydev);81 if (ret)82 return ret;83 84 ret = phy_read_mmd(phydev, MDIO_MMD_AN, ADIN_AN_PHY_INST_STATUS);85 if (ret < 0)86 return ret;87 88 if (ret & ADIN_IS_CFG_SLV)89 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE;90 91 if (ret & ADIN_IS_CFG_MST)92 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER;93 94 return 0;95}96 97static int adin_config_aneg(struct phy_device *phydev)98{99 struct adin_priv *priv = phydev->priv;100 int ret;101 102 if (phydev->autoneg == AUTONEG_DISABLE) {103 ret = genphy_c45_pma_setup_forced(phydev);104 if (ret < 0)105 return ret;106 107 if (priv->tx_level_prop_present && priv->tx_level_2v4)108 ret = phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_B10L_PMA_CTRL,109 MDIO_PMA_10T1L_CTRL_2V4_EN);110 else111 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_B10L_PMA_CTRL,112 MDIO_PMA_10T1L_CTRL_2V4_EN);113 if (ret < 0)114 return ret;115 116 /* Force PHY to use above configurations */117 return phy_set_bits_mmd(phydev, MDIO_MMD_AN, ADIN_FORCED_MODE, ADIN_FORCED_MODE_EN);118 }119 120 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_AN, ADIN_FORCED_MODE, ADIN_FORCED_MODE_EN);121 if (ret < 0)122 return ret;123 124 /* Request increased transmit level from LP. */125 if (priv->tx_level_prop_present && priv->tx_level_2v4) {126 ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_H,127 MDIO_AN_T1_ADV_H_10L_TX_HI |128 MDIO_AN_T1_ADV_H_10L_TX_HI_REQ);129 if (ret < 0)130 return ret;131 }132 133 /* Disable 2.4 Vpp transmit level. */134 if ((priv->tx_level_prop_present && !priv->tx_level_2v4) || !priv->tx_level_2v4_able) {135 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_H,136 MDIO_AN_T1_ADV_H_10L_TX_HI |137 MDIO_AN_T1_ADV_H_10L_TX_HI_REQ);138 if (ret < 0)139 return ret;140 }141 142 return genphy_c45_config_aneg(phydev);143}144 145static int adin_phy_ack_intr(struct phy_device *phydev)146{147 /* Clear pending interrupts */148 int rc = phy_read_mmd(phydev, MDIO_MMD_VEND2,149 ADIN_PHY_SUBSYS_IRQ_STATUS);150 151 return rc < 0 ? rc : 0;152}153 154static int adin_config_intr(struct phy_device *phydev)155{156 u16 irq_mask;157 int ret;158 159 ret = adin_phy_ack_intr(phydev);160 if (ret)161 return ret;162 163 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)164 irq_mask = ADIN_LINK_STAT_CHNG_IRQ_EN;165 else166 irq_mask = 0;167 168 return phy_modify_mmd(phydev, MDIO_MMD_VEND2,169 ADIN_PHY_SUBSYS_IRQ_MASK,170 ADIN_LINK_STAT_CHNG_IRQ_EN, irq_mask);171}172 173static irqreturn_t adin_phy_handle_interrupt(struct phy_device *phydev)174{175 int irq_status;176 177 irq_status = phy_read_mmd(phydev, MDIO_MMD_VEND2,178 ADIN_PHY_SUBSYS_IRQ_STATUS);179 if (irq_status < 0) {180 phy_error(phydev);181 return IRQ_NONE;182 }183 184 if (!(irq_status & ADIN_LINK_STAT_CHNG))185 return IRQ_NONE;186 187 phy_trigger_machine(phydev);188 189 return IRQ_HANDLED;190}191 192static int adin_set_powerdown_mode(struct phy_device *phydev, bool en)193{194 int ret;195 int val;196 197 val = en ? ADIN_CRSM_SFT_PD_CNTRL_EN : 0;198 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1,199 ADIN_CRSM_SFT_PD_CNTRL, val);200 if (ret < 0)201 return ret;202 203 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, ADIN_CRSM_STAT, ret,204 (ret & ADIN_CRSM_SFT_PD_RDY) == val,205 1000, 30000, true);206}207 208static int adin_suspend(struct phy_device *phydev)209{210 return adin_set_powerdown_mode(phydev, true);211}212 213static int adin_resume(struct phy_device *phydev)214{215 return adin_set_powerdown_mode(phydev, false);216}217 218static int adin_set_loopback(struct phy_device *phydev, bool enable)219{220 if (enable)221 return phy_set_bits_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_10T1L_CTRL,222 BMCR_LOOPBACK);223 224 /* PCS loopback (according to 10BASE-T1L spec) */225 return phy_clear_bits_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_10T1L_CTRL,226 BMCR_LOOPBACK);227}228 229static int adin_soft_reset(struct phy_device *phydev)230{231 int ret;232 233 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, ADIN_CRSM_SFT_RST, ADIN_CRSM_SFT_RST_EN);234 if (ret < 0)235 return ret;236 237 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, ADIN_CRSM_STAT, ret,238 (ret & ADIN_CRSM_SYS_RDY),239 10000, 30000, true);240}241 242static int adin_get_features(struct phy_device *phydev)243{244 struct adin_priv *priv = phydev->priv;245 struct device *dev = &phydev->mdio.dev;246 int ret;247 u8 val;248 249 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10T1L_STAT);250 if (ret < 0)251 return ret;252 253 /* This depends on the voltage level from the power source */254 priv->tx_level_2v4_able = !!(ret & MDIO_PMA_10T1L_STAT_2V4_ABLE);255 256 phydev_dbg(phydev, "PHY supports 2.4V TX level: %s\n",257 priv->tx_level_2v4_able ? "yes" : "no");258 259 priv->tx_level_prop_present = device_property_present(dev, "phy-10base-t1l-2.4vpp");260 if (priv->tx_level_prop_present) {261 ret = device_property_read_u8(dev, "phy-10base-t1l-2.4vpp", &val);262 if (ret < 0)263 return ret;264 265 priv->tx_level_2v4 = val;266 if (!priv->tx_level_2v4 && priv->tx_level_2v4_able)267 phydev_info(phydev,268 "PHY supports 2.4V TX level, but disabled via config\n");269 }270 271 linkmode_set_bit_array(phy_basic_ports_array, ARRAY_SIZE(phy_basic_ports_array),272 phydev->supported);273 274 return genphy_c45_pma_read_abilities(phydev);275}276 277static int adin_get_sqi(struct phy_device *phydev)278{279 u16 mse_val;280 int sqi;281 int ret;282 283 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_STAT1);284 if (ret < 0)285 return ret;286 else if (!(ret & MDIO_STAT1_LSTATUS))287 return 0;288 289 ret = phy_read_mmd(phydev, MDIO_STAT1, ADIN_MSE_VAL);290 if (ret < 0)291 return ret;292 293 mse_val = 0xFFFF & ret;294 for (sqi = 0; sqi < ARRAY_SIZE(adin_mse_sqi_map); sqi++) {295 if (mse_val >= adin_mse_sqi_map[sqi].start && mse_val <= adin_mse_sqi_map[sqi].end)296 return sqi;297 }298 299 return -EINVAL;300}301 302static int adin_get_sqi_max(struct phy_device *phydev)303{304 return ADIN_SQI_MAX;305}306 307static int adin_probe(struct phy_device *phydev)308{309 struct device *dev = &phydev->mdio.dev;310 struct adin_priv *priv;311 312 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);313 if (!priv)314 return -ENOMEM;315 316 phydev->priv = priv;317 318 return 0;319}320 321static struct phy_driver adin_driver[] = {322 {323 .phy_id = PHY_ID_ADIN1100,324 .phy_id_mask = 0xffffffcf,325 .name = "ADIN1100",326 .get_features = adin_get_features,327 .soft_reset = adin_soft_reset,328 .probe = adin_probe,329 .config_aneg = adin_config_aneg,330 .read_status = adin_read_status,331 .config_intr = adin_config_intr,332 .handle_interrupt = adin_phy_handle_interrupt,333 .set_loopback = adin_set_loopback,334 .suspend = adin_suspend,335 .resume = adin_resume,336 .get_sqi = adin_get_sqi,337 .get_sqi_max = adin_get_sqi_max,338 },339};340 341module_phy_driver(adin_driver);342 343static struct mdio_device_id __maybe_unused adin_tbl[] = {344 { PHY_ID_MATCH_MODEL(PHY_ID_ADIN1100) },345 { PHY_ID_MATCH_MODEL(PHY_ID_ADIN1110) },346 { PHY_ID_MATCH_MODEL(PHY_ID_ADIN2111) },347 { }348};349 350MODULE_DEVICE_TABLE(mdio, adin_tbl);351MODULE_DESCRIPTION("Analog Devices Industrial Ethernet T1L PHY driver");352MODULE_LICENSE("Dual BSD/GPL");353