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1// SPDX-License-Identifier: GPL-2.0+2/*3 * Driver for the National Semiconductor DP83640 PHYTER4 *5 * Copyright (C) 2010 OMICRON electronics GmbH6 */7 8#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt9 10#include <linux/crc32.h>11#include <linux/ethtool.h>12#include <linux/kernel.h>13#include <linux/list.h>14#include <linux/mii.h>15#include <linux/module.h>16#include <linux/net_tstamp.h>17#include <linux/netdevice.h>18#include <linux/if_vlan.h>19#include <linux/phy.h>20#include <linux/ptp_classify.h>21#include <linux/ptp_clock_kernel.h>22 23#include "dp83640_reg.h"24 25#define DP83640_PHY_ID 0x20005ce126#define PAGESEL 0x1327#define MAX_RXTS 6428#define N_EXT_TS 629#define N_PER_OUT 730#define PSF_PTPVER 231#define PSF_EVNT 0x400032#define PSF_RX 0x200033#define PSF_TX 0x100034#define EXT_EVENT 135#define CAL_EVENT 736#define CAL_TRIGGER 137#define DP83640_N_PINS 1238 39#define MII_DP83640_MICR 0x1140#define MII_DP83640_MISR 0x1241 42#define MII_DP83640_MICR_OE 0x143#define MII_DP83640_MICR_IE 0x244 45#define MII_DP83640_MISR_RHF_INT_EN 0x0146#define MII_DP83640_MISR_FHF_INT_EN 0x0247#define MII_DP83640_MISR_ANC_INT_EN 0x0448#define MII_DP83640_MISR_DUP_INT_EN 0x0849#define MII_DP83640_MISR_SPD_INT_EN 0x1050#define MII_DP83640_MISR_LINK_INT_EN 0x2051#define MII_DP83640_MISR_ED_INT_EN 0x4052#define MII_DP83640_MISR_LQ_INT_EN 0x8053#define MII_DP83640_MISR_ANC_INT 0x40054#define MII_DP83640_MISR_DUP_INT 0x80055#define MII_DP83640_MISR_SPD_INT 0x100056#define MII_DP83640_MISR_LINK_INT 0x200057#define MII_DP83640_MISR_INT_MASK (MII_DP83640_MISR_ANC_INT |\58 MII_DP83640_MISR_DUP_INT |\59 MII_DP83640_MISR_SPD_INT |\60 MII_DP83640_MISR_LINK_INT)61 62/* phyter seems to miss the mark by 16 ns */63#define ADJTIME_FIX 1664 65#define SKB_TIMESTAMP_TIMEOUT 2 /* jiffies */66 67#if defined(__BIG_ENDIAN)68#define ENDIAN_FLAG 069#elif defined(__LITTLE_ENDIAN)70#define ENDIAN_FLAG PSF_ENDIAN71#endif72 73struct dp83640_skb_info {74 int ptp_type;75 unsigned long tmo;76};77 78struct phy_rxts {79 u16 ns_lo; /* ns[15:0] */80 u16 ns_hi; /* overflow[1:0], ns[29:16] */81 u16 sec_lo; /* sec[15:0] */82 u16 sec_hi; /* sec[31:16] */83 u16 seqid; /* sequenceId[15:0] */84 u16 msgtype; /* messageType[3:0], hash[11:0] */85};86 87struct phy_txts {88 u16 ns_lo; /* ns[15:0] */89 u16 ns_hi; /* overflow[1:0], ns[29:16] */90 u16 sec_lo; /* sec[15:0] */91 u16 sec_hi; /* sec[31:16] */92};93 94struct rxts {95 struct list_head list;96 unsigned long tmo;97 u64 ns;98 u16 seqid;99 u8 msgtype;100 u16 hash;101};102 103struct dp83640_clock;104 105struct dp83640_private {106 struct list_head list;107 struct dp83640_clock *clock;108 struct phy_device *phydev;109 struct mii_timestamper mii_ts;110 struct delayed_work ts_work;111 int hwts_tx_en;112 int hwts_rx_en;113 int layer;114 int version;115 /* remember state of cfg0 during calibration */116 int cfg0;117 /* remember the last event time stamp */118 struct phy_txts edata;119 /* list of rx timestamps */120 struct list_head rxts;121 struct list_head rxpool;122 struct rxts rx_pool_data[MAX_RXTS];123 /* protects above three fields from concurrent access */124 spinlock_t rx_lock;125 /* queues of incoming and outgoing packets */126 struct sk_buff_head rx_queue;127 struct sk_buff_head tx_queue;128};129 130struct dp83640_clock {131 /* keeps the instance in the 'phyter_clocks' list */132 struct list_head list;133 /* we create one clock instance per MII bus */134 struct mii_bus *bus;135 /* protects extended registers from concurrent access */136 struct mutex extreg_lock;137 /* remembers which page was last selected */138 int page;139 /* our advertised capabilities */140 struct ptp_clock_info caps;141 /* protects the three fields below from concurrent access */142 struct mutex clock_lock;143 /* the one phyter from which we shall read */144 struct dp83640_private *chosen;145 /* list of the other attached phyters, not chosen */146 struct list_head phylist;147 /* reference to our PTP hardware clock */148 struct ptp_clock *ptp_clock;149};150 151/* globals */152 153enum {154 CALIBRATE_GPIO,155 PEROUT_GPIO,156 EXTTS0_GPIO,157 EXTTS1_GPIO,158 EXTTS2_GPIO,159 EXTTS3_GPIO,160 EXTTS4_GPIO,161 EXTTS5_GPIO,162 GPIO_TABLE_SIZE163};164 165static int chosen_phy = -1;166static ushort gpio_tab[GPIO_TABLE_SIZE] = {167 1, 2, 3, 4, 8, 9, 10, 11168};169 170module_param(chosen_phy, int, 0444);171module_param_array(gpio_tab, ushort, NULL, 0444);172 173MODULE_PARM_DESC(chosen_phy,174 "The address of the PHY to use for the ancillary clock features");175MODULE_PARM_DESC(gpio_tab,176 "Which GPIO line to use for which purpose: cal,perout,extts1,...,extts6");177 178static void dp83640_gpio_defaults(struct ptp_pin_desc *pd)179{180 int i, index;181 182 for (i = 0; i < DP83640_N_PINS; i++) {183 snprintf(pd[i].name, sizeof(pd[i].name), "GPIO%d", 1 + i);184 pd[i].index = i;185 }186 187 for (i = 0; i < GPIO_TABLE_SIZE; i++) {188 if (gpio_tab[i] < 1 || gpio_tab[i] > DP83640_N_PINS) {189 pr_err("gpio_tab[%d]=%hu out of range", i, gpio_tab[i]);190 return;191 }192 }193 194 index = gpio_tab[CALIBRATE_GPIO] - 1;195 pd[index].func = PTP_PF_PHYSYNC;196 pd[index].chan = 0;197 198 index = gpio_tab[PEROUT_GPIO] - 1;199 pd[index].func = PTP_PF_PEROUT;200 pd[index].chan = 0;201 202 for (i = EXTTS0_GPIO; i < GPIO_TABLE_SIZE; i++) {203 index = gpio_tab[i] - 1;204 pd[index].func = PTP_PF_EXTTS;205 pd[index].chan = i - EXTTS0_GPIO;206 }207}208 209/* a list of clocks and a mutex to protect it */210static LIST_HEAD(phyter_clocks);211static DEFINE_MUTEX(phyter_clocks_lock);212 213static void rx_timestamp_work(struct work_struct *work);214 215/* extended register access functions */216 217#define BROADCAST_ADDR 31218 219static inline int broadcast_write(struct phy_device *phydev, u32 regnum,220 u16 val)221{222 return mdiobus_write(phydev->mdio.bus, BROADCAST_ADDR, regnum, val);223}224 225/* Caller must hold extreg_lock. */226static int ext_read(struct phy_device *phydev, int page, u32 regnum)227{228 struct dp83640_private *dp83640 = phydev->priv;229 int val;230 231 if (dp83640->clock->page != page) {232 broadcast_write(phydev, PAGESEL, page);233 dp83640->clock->page = page;234 }235 val = phy_read(phydev, regnum);236 237 return val;238}239 240/* Caller must hold extreg_lock. */241static void ext_write(int broadcast, struct phy_device *phydev,242 int page, u32 regnum, u16 val)243{244 struct dp83640_private *dp83640 = phydev->priv;245 246 if (dp83640->clock->page != page) {247 broadcast_write(phydev, PAGESEL, page);248 dp83640->clock->page = page;249 }250 if (broadcast)251 broadcast_write(phydev, regnum, val);252 else253 phy_write(phydev, regnum, val);254}255 256/* Caller must hold extreg_lock. */257static int tdr_write(int bc, struct phy_device *dev,258 const struct timespec64 *ts, u16 cmd)259{260 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_nsec & 0xffff);/* ns[15:0] */261 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_nsec >> 16); /* ns[31:16] */262 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_sec & 0xffff); /* sec[15:0] */263 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_sec >> 16); /* sec[31:16]*/264 265 ext_write(bc, dev, PAGE4, PTP_CTL, cmd);266 267 return 0;268}269 270/* convert phy timestamps into driver timestamps */271 272static void phy2rxts(struct phy_rxts *p, struct rxts *rxts)273{274 u32 sec;275 276 sec = p->sec_lo;277 sec |= p->sec_hi << 16;278 279 rxts->ns = p->ns_lo;280 rxts->ns |= (p->ns_hi & 0x3fff) << 16;281 rxts->ns += ((u64)sec) * 1000000000ULL;282 rxts->seqid = p->seqid;283 rxts->msgtype = (p->msgtype >> 12) & 0xf;284 rxts->hash = p->msgtype & 0x0fff;285 rxts->tmo = jiffies + SKB_TIMESTAMP_TIMEOUT;286}287 288static u64 phy2txts(struct phy_txts *p)289{290 u64 ns;291 u32 sec;292 293 sec = p->sec_lo;294 sec |= p->sec_hi << 16;295 296 ns = p->ns_lo;297 ns |= (p->ns_hi & 0x3fff) << 16;298 ns += ((u64)sec) * 1000000000ULL;299 300 return ns;301}302 303static int periodic_output(struct dp83640_clock *clock,304 struct ptp_clock_request *clkreq, bool on,305 int trigger)306{307 struct dp83640_private *dp83640 = clock->chosen;308 struct phy_device *phydev = dp83640->phydev;309 u32 sec, nsec, pwidth;310 u16 gpio, ptp_trig, val;311 312 if (on) {313 gpio = 1 + ptp_find_pin(clock->ptp_clock, PTP_PF_PEROUT,314 trigger);315 if (gpio < 1)316 return -EINVAL;317 } else {318 gpio = 0;319 }320 321 ptp_trig = TRIG_WR |322 (trigger & TRIG_CSEL_MASK) << TRIG_CSEL_SHIFT |323 (gpio & TRIG_GPIO_MASK) << TRIG_GPIO_SHIFT |324 TRIG_PER |325 TRIG_PULSE;326 327 val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT;328 329 if (!on) {330 val |= TRIG_DIS;331 mutex_lock(&clock->extreg_lock);332 ext_write(0, phydev, PAGE5, PTP_TRIG, ptp_trig);333 ext_write(0, phydev, PAGE4, PTP_CTL, val);334 mutex_unlock(&clock->extreg_lock);335 return 0;336 }337 338 sec = clkreq->perout.start.sec;339 nsec = clkreq->perout.start.nsec;340 pwidth = clkreq->perout.period.sec * 1000000000UL;341 pwidth += clkreq->perout.period.nsec;342 pwidth /= 2;343 344 mutex_lock(&clock->extreg_lock);345 346 ext_write(0, phydev, PAGE5, PTP_TRIG, ptp_trig);347 348 /*load trigger*/349 val |= TRIG_LOAD;350 ext_write(0, phydev, PAGE4, PTP_CTL, val);351 ext_write(0, phydev, PAGE4, PTP_TDR, nsec & 0xffff); /* ns[15:0] */352 ext_write(0, phydev, PAGE4, PTP_TDR, nsec >> 16); /* ns[31:16] */353 ext_write(0, phydev, PAGE4, PTP_TDR, sec & 0xffff); /* sec[15:0] */354 ext_write(0, phydev, PAGE4, PTP_TDR, sec >> 16); /* sec[31:16] */355 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth & 0xffff); /* ns[15:0] */356 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth >> 16); /* ns[31:16] */357 /* Triggers 0 and 1 has programmable pulsewidth2 */358 if (trigger < 2) {359 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth & 0xffff);360 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth >> 16);361 }362 363 /*enable trigger*/364 val &= ~TRIG_LOAD;365 val |= TRIG_EN;366 ext_write(0, phydev, PAGE4, PTP_CTL, val);367 368 mutex_unlock(&clock->extreg_lock);369 return 0;370}371 372/* ptp clock methods */373 374static int ptp_dp83640_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)375{376 struct dp83640_clock *clock =377 container_of(ptp, struct dp83640_clock, caps);378 struct phy_device *phydev = clock->chosen->phydev;379 u64 rate;380 int neg_adj = 0;381 u16 hi, lo;382 383 if (scaled_ppm < 0) {384 neg_adj = 1;385 scaled_ppm = -scaled_ppm;386 }387 rate = scaled_ppm;388 rate <<= 13;389 rate = div_u64(rate, 15625);390 391 hi = (rate >> 16) & PTP_RATE_HI_MASK;392 if (neg_adj)393 hi |= PTP_RATE_DIR;394 395 lo = rate & 0xffff;396 397 mutex_lock(&clock->extreg_lock);398 399 ext_write(1, phydev, PAGE4, PTP_RATEH, hi);400 ext_write(1, phydev, PAGE4, PTP_RATEL, lo);401 402 mutex_unlock(&clock->extreg_lock);403 404 return 0;405}406 407static int ptp_dp83640_adjtime(struct ptp_clock_info *ptp, s64 delta)408{409 struct dp83640_clock *clock =410 container_of(ptp, struct dp83640_clock, caps);411 struct phy_device *phydev = clock->chosen->phydev;412 struct timespec64 ts;413 int err;414 415 delta += ADJTIME_FIX;416 417 ts = ns_to_timespec64(delta);418 419 mutex_lock(&clock->extreg_lock);420 421 err = tdr_write(1, phydev, &ts, PTP_STEP_CLK);422 423 mutex_unlock(&clock->extreg_lock);424 425 return err;426}427 428static int ptp_dp83640_gettime(struct ptp_clock_info *ptp,429 struct timespec64 *ts)430{431 struct dp83640_clock *clock =432 container_of(ptp, struct dp83640_clock, caps);433 struct phy_device *phydev = clock->chosen->phydev;434 unsigned int val[4];435 436 mutex_lock(&clock->extreg_lock);437 438 ext_write(0, phydev, PAGE4, PTP_CTL, PTP_RD_CLK);439 440 val[0] = ext_read(phydev, PAGE4, PTP_TDR); /* ns[15:0] */441 val[1] = ext_read(phydev, PAGE4, PTP_TDR); /* ns[31:16] */442 val[2] = ext_read(phydev, PAGE4, PTP_TDR); /* sec[15:0] */443 val[3] = ext_read(phydev, PAGE4, PTP_TDR); /* sec[31:16] */444 445 mutex_unlock(&clock->extreg_lock);446 447 ts->tv_nsec = val[0] | (val[1] << 16);448 ts->tv_sec = val[2] | (val[3] << 16);449 450 return 0;451}452 453static int ptp_dp83640_settime(struct ptp_clock_info *ptp,454 const struct timespec64 *ts)455{456 struct dp83640_clock *clock =457 container_of(ptp, struct dp83640_clock, caps);458 struct phy_device *phydev = clock->chosen->phydev;459 int err;460 461 mutex_lock(&clock->extreg_lock);462 463 err = tdr_write(1, phydev, ts, PTP_LOAD_CLK);464 465 mutex_unlock(&clock->extreg_lock);466 467 return err;468}469 470static int ptp_dp83640_enable(struct ptp_clock_info *ptp,471 struct ptp_clock_request *rq, int on)472{473 struct dp83640_clock *clock =474 container_of(ptp, struct dp83640_clock, caps);475 struct phy_device *phydev = clock->chosen->phydev;476 unsigned int index;477 u16 evnt, event_num, gpio_num;478 479 switch (rq->type) {480 case PTP_CLK_REQ_EXTTS:481 /* Reject requests with unsupported flags */482 if (rq->extts.flags & ~(PTP_ENABLE_FEATURE |483 PTP_RISING_EDGE |484 PTP_FALLING_EDGE |485 PTP_STRICT_FLAGS))486 return -EOPNOTSUPP;487 488 /* Reject requests to enable time stamping on both edges. */489 if ((rq->extts.flags & PTP_STRICT_FLAGS) &&490 (rq->extts.flags & PTP_ENABLE_FEATURE) &&491 (rq->extts.flags & PTP_EXTTS_EDGES) == PTP_EXTTS_EDGES)492 return -EOPNOTSUPP;493 494 index = rq->extts.index;495 if (index >= N_EXT_TS)496 return -EINVAL;497 event_num = EXT_EVENT + index;498 evnt = EVNT_WR | (event_num & EVNT_SEL_MASK) << EVNT_SEL_SHIFT;499 if (on) {500 gpio_num = 1 + ptp_find_pin(clock->ptp_clock,501 PTP_PF_EXTTS, index);502 if (gpio_num < 1)503 return -EINVAL;504 evnt |= (gpio_num & EVNT_GPIO_MASK) << EVNT_GPIO_SHIFT;505 if (rq->extts.flags & PTP_FALLING_EDGE)506 evnt |= EVNT_FALL;507 else508 evnt |= EVNT_RISE;509 }510 mutex_lock(&clock->extreg_lock);511 ext_write(0, phydev, PAGE5, PTP_EVNT, evnt);512 mutex_unlock(&clock->extreg_lock);513 return 0;514 515 case PTP_CLK_REQ_PEROUT:516 /* Reject requests with unsupported flags */517 if (rq->perout.flags)518 return -EOPNOTSUPP;519 if (rq->perout.index >= N_PER_OUT)520 return -EINVAL;521 return periodic_output(clock, rq, on, rq->perout.index);522 523 default:524 break;525 }526 527 return -EOPNOTSUPP;528}529 530static int ptp_dp83640_verify(struct ptp_clock_info *ptp, unsigned int pin,531 enum ptp_pin_function func, unsigned int chan)532{533 struct dp83640_clock *clock =534 container_of(ptp, struct dp83640_clock, caps);535 536 if (clock->caps.pin_config[pin].func == PTP_PF_PHYSYNC &&537 !list_empty(&clock->phylist))538 return 1;539 540 if (func == PTP_PF_PHYSYNC)541 return 1;542 543 return 0;544}545 546static u8 status_frame_dst[6] = { 0x01, 0x1B, 0x19, 0x00, 0x00, 0x00 };547static u8 status_frame_src[6] = { 0x08, 0x00, 0x17, 0x0B, 0x6B, 0x0F };548 549static void enable_status_frames(struct phy_device *phydev, bool on)550{551 struct dp83640_private *dp83640 = phydev->priv;552 struct dp83640_clock *clock = dp83640->clock;553 u16 cfg0 = 0, ver;554 555 if (on)556 cfg0 = PSF_EVNT_EN | PSF_RXTS_EN | PSF_TXTS_EN | ENDIAN_FLAG;557 558 ver = (PSF_PTPVER & VERSIONPTP_MASK) << VERSIONPTP_SHIFT;559 560 mutex_lock(&clock->extreg_lock);561 562 ext_write(0, phydev, PAGE5, PSF_CFG0, cfg0);563 ext_write(0, phydev, PAGE6, PSF_CFG1, ver);564 565 mutex_unlock(&clock->extreg_lock);566 567 if (!phydev->attached_dev) {568 phydev_warn(phydev,569 "expected to find an attached netdevice\n");570 return;571 }572 573 if (on) {574 if (dev_mc_add(phydev->attached_dev, status_frame_dst))575 phydev_warn(phydev, "failed to add mc address\n");576 } else {577 if (dev_mc_del(phydev->attached_dev, status_frame_dst))578 phydev_warn(phydev, "failed to delete mc address\n");579 }580}581 582static bool is_status_frame(struct sk_buff *skb, int type)583{584 struct ethhdr *h = eth_hdr(skb);585 586 if (PTP_CLASS_V2_L2 == type &&587 !memcmp(h->h_source, status_frame_src, sizeof(status_frame_src)))588 return true;589 else590 return false;591}592 593static int expired(struct rxts *rxts)594{595 return time_after(jiffies, rxts->tmo);596}597 598/* Caller must hold rx_lock. */599static void prune_rx_ts(struct dp83640_private *dp83640)600{601 struct list_head *this, *next;602 struct rxts *rxts;603 604 list_for_each_safe(this, next, &dp83640->rxts) {605 rxts = list_entry(this, struct rxts, list);606 if (expired(rxts)) {607 list_del_init(&rxts->list);608 list_add(&rxts->list, &dp83640->rxpool);609 }610 }611}612 613/* synchronize the phyters so they act as one clock */614 615static void enable_broadcast(struct phy_device *phydev, int init_page, int on)616{617 int val;618 619 phy_write(phydev, PAGESEL, 0);620 val = phy_read(phydev, PHYCR2);621 if (on)622 val |= BC_WRITE;623 else624 val &= ~BC_WRITE;625 phy_write(phydev, PHYCR2, val);626 phy_write(phydev, PAGESEL, init_page);627}628 629static void recalibrate(struct dp83640_clock *clock)630{631 s64 now, diff;632 struct phy_txts event_ts;633 struct timespec64 ts;634 struct dp83640_private *tmp;635 struct phy_device *master = clock->chosen->phydev;636 u16 cal_gpio, cfg0, evnt, ptp_trig, trigger, val;637 638 trigger = CAL_TRIGGER;639 cal_gpio = 1 + ptp_find_pin_unlocked(clock->ptp_clock, PTP_PF_PHYSYNC, 0);640 if (cal_gpio < 1) {641 pr_err("PHY calibration pin not available - PHY is not calibrated.");642 return;643 }644 645 mutex_lock(&clock->extreg_lock);646 647 /*648 * enable broadcast, disable status frames, enable ptp clock649 */650 list_for_each_entry(tmp, &clock->phylist, list) {651 enable_broadcast(tmp->phydev, clock->page, 1);652 tmp->cfg0 = ext_read(tmp->phydev, PAGE5, PSF_CFG0);653 ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, 0);654 ext_write(0, tmp->phydev, PAGE4, PTP_CTL, PTP_ENABLE);655 }656 enable_broadcast(master, clock->page, 1);657 cfg0 = ext_read(master, PAGE5, PSF_CFG0);658 ext_write(0, master, PAGE5, PSF_CFG0, 0);659 ext_write(0, master, PAGE4, PTP_CTL, PTP_ENABLE);660 661 /*662 * enable an event timestamp663 */664 evnt = EVNT_WR | EVNT_RISE | EVNT_SINGLE;665 evnt |= (CAL_EVENT & EVNT_SEL_MASK) << EVNT_SEL_SHIFT;666 evnt |= (cal_gpio & EVNT_GPIO_MASK) << EVNT_GPIO_SHIFT;667 668 list_for_each_entry(tmp, &clock->phylist, list)669 ext_write(0, tmp->phydev, PAGE5, PTP_EVNT, evnt);670 ext_write(0, master, PAGE5, PTP_EVNT, evnt);671 672 /*673 * configure a trigger674 */675 ptp_trig = TRIG_WR | TRIG_IF_LATE | TRIG_PULSE;676 ptp_trig |= (trigger & TRIG_CSEL_MASK) << TRIG_CSEL_SHIFT;677 ptp_trig |= (cal_gpio & TRIG_GPIO_MASK) << TRIG_GPIO_SHIFT;678 ext_write(0, master, PAGE5, PTP_TRIG, ptp_trig);679 680 /* load trigger */681 val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT;682 val |= TRIG_LOAD;683 ext_write(0, master, PAGE4, PTP_CTL, val);684 685 /* enable trigger */686 val &= ~TRIG_LOAD;687 val |= TRIG_EN;688 ext_write(0, master, PAGE4, PTP_CTL, val);689 690 /* disable trigger */691 val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT;692 val |= TRIG_DIS;693 ext_write(0, master, PAGE4, PTP_CTL, val);694 695 /*696 * read out and correct offsets697 */698 val = ext_read(master, PAGE4, PTP_STS);699 phydev_info(master, "master PTP_STS 0x%04hx\n", val);700 val = ext_read(master, PAGE4, PTP_ESTS);701 phydev_info(master, "master PTP_ESTS 0x%04hx\n", val);702 event_ts.ns_lo = ext_read(master, PAGE4, PTP_EDATA);703 event_ts.ns_hi = ext_read(master, PAGE4, PTP_EDATA);704 event_ts.sec_lo = ext_read(master, PAGE4, PTP_EDATA);705 event_ts.sec_hi = ext_read(master, PAGE4, PTP_EDATA);706 now = phy2txts(&event_ts);707 708 list_for_each_entry(tmp, &clock->phylist, list) {709 val = ext_read(tmp->phydev, PAGE4, PTP_STS);710 phydev_info(tmp->phydev, "slave PTP_STS 0x%04hx\n", val);711 val = ext_read(tmp->phydev, PAGE4, PTP_ESTS);712 phydev_info(tmp->phydev, "slave PTP_ESTS 0x%04hx\n", val);713 event_ts.ns_lo = ext_read(tmp->phydev, PAGE4, PTP_EDATA);714 event_ts.ns_hi = ext_read(tmp->phydev, PAGE4, PTP_EDATA);715 event_ts.sec_lo = ext_read(tmp->phydev, PAGE4, PTP_EDATA);716 event_ts.sec_hi = ext_read(tmp->phydev, PAGE4, PTP_EDATA);717 diff = now - (s64) phy2txts(&event_ts);718 phydev_info(tmp->phydev, "slave offset %lld nanoseconds\n",719 diff);720 diff += ADJTIME_FIX;721 ts = ns_to_timespec64(diff);722 tdr_write(0, tmp->phydev, &ts, PTP_STEP_CLK);723 }724 725 /*726 * restore status frames727 */728 list_for_each_entry(tmp, &clock->phylist, list)729 ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, tmp->cfg0);730 ext_write(0, master, PAGE5, PSF_CFG0, cfg0);731 732 mutex_unlock(&clock->extreg_lock);733}734 735/* time stamping methods */736 737static inline u16 exts_chan_to_edata(int ch)738{739 return 1 << ((ch + EXT_EVENT) * 2);740}741 742static int decode_evnt(struct dp83640_private *dp83640,743 void *data, int len, u16 ests)744{745 struct phy_txts *phy_txts;746 struct ptp_clock_event event;747 int i, parsed;748 int words = (ests >> EVNT_TS_LEN_SHIFT) & EVNT_TS_LEN_MASK;749 u16 ext_status = 0;750 751 /* calculate length of the event timestamp status message */752 if (ests & MULT_EVNT)753 parsed = (words + 2) * sizeof(u16);754 else755 parsed = (words + 1) * sizeof(u16);756 757 /* check if enough data is available */758 if (len < parsed)759 return len;760 761 if (ests & MULT_EVNT) {762 ext_status = *(u16 *) data;763 data += sizeof(ext_status);764 }765 766 phy_txts = data;767 768 switch (words) {769 case 3:770 dp83640->edata.sec_hi = phy_txts->sec_hi;771 fallthrough;772 case 2:773 dp83640->edata.sec_lo = phy_txts->sec_lo;774 fallthrough;775 case 1:776 dp83640->edata.ns_hi = phy_txts->ns_hi;777 fallthrough;778 case 0:779 dp83640->edata.ns_lo = phy_txts->ns_lo;780 }781 782 if (!ext_status) {783 i = ((ests >> EVNT_NUM_SHIFT) & EVNT_NUM_MASK) - EXT_EVENT;784 ext_status = exts_chan_to_edata(i);785 }786 787 event.type = PTP_CLOCK_EXTTS;788 event.timestamp = phy2txts(&dp83640->edata);789 790 /* Compensate for input path and synchronization delays */791 event.timestamp -= 35;792 793 for (i = 0; i < N_EXT_TS; i++) {794 if (ext_status & exts_chan_to_edata(i)) {795 event.index = i;796 ptp_clock_event(dp83640->clock->ptp_clock, &event);797 }798 }799 800 return parsed;801}802 803#define DP83640_PACKET_HASH_LEN 10804 805static int match(struct sk_buff *skb, unsigned int type, struct rxts *rxts)806{807 struct ptp_header *hdr;808 u8 msgtype;809 u16 seqid;810 u16 hash;811 812 /* check sequenceID, messageType, 12 bit hash of offset 20-29 */813 814 hdr = ptp_parse_header(skb, type);815 if (!hdr)816 return 0;817 818 msgtype = ptp_get_msgtype(hdr, type);819 820 if (rxts->msgtype != (msgtype & 0xf))821 return 0;822 823 seqid = be16_to_cpu(hdr->sequence_id);824 if (rxts->seqid != seqid)825 return 0;826 827 hash = ether_crc(DP83640_PACKET_HASH_LEN,828 (unsigned char *)&hdr->source_port_identity) >> 20;829 if (rxts->hash != hash)830 return 0;831 832 return 1;833}834 835static void decode_rxts(struct dp83640_private *dp83640,836 struct phy_rxts *phy_rxts)837{838 struct rxts *rxts;839 struct skb_shared_hwtstamps *shhwtstamps = NULL;840 struct sk_buff *skb;841 unsigned long flags;842 u8 overflow;843 844 overflow = (phy_rxts->ns_hi >> 14) & 0x3;845 if (overflow)846 pr_debug("rx timestamp queue overflow, count %d\n", overflow);847 848 spin_lock_irqsave(&dp83640->rx_lock, flags);849 850 prune_rx_ts(dp83640);851 852 if (list_empty(&dp83640->rxpool)) {853 pr_debug("rx timestamp pool is empty\n");854 goto out;855 }856 rxts = list_first_entry(&dp83640->rxpool, struct rxts, list);857 list_del_init(&rxts->list);858 phy2rxts(phy_rxts, rxts);859 860 spin_lock(&dp83640->rx_queue.lock);861 skb_queue_walk(&dp83640->rx_queue, skb) {862 struct dp83640_skb_info *skb_info;863 864 skb_info = (struct dp83640_skb_info *)skb->cb;865 if (match(skb, skb_info->ptp_type, rxts)) {866 __skb_unlink(skb, &dp83640->rx_queue);867 shhwtstamps = skb_hwtstamps(skb);868 memset(shhwtstamps, 0, sizeof(*shhwtstamps));869 shhwtstamps->hwtstamp = ns_to_ktime(rxts->ns);870 list_add(&rxts->list, &dp83640->rxpool);871 break;872 }873 }874 spin_unlock(&dp83640->rx_queue.lock);875 876 if (!shhwtstamps)877 list_add_tail(&rxts->list, &dp83640->rxts);878out:879 spin_unlock_irqrestore(&dp83640->rx_lock, flags);880 881 if (shhwtstamps)882 netif_rx(skb);883}884 885static void decode_txts(struct dp83640_private *dp83640,886 struct phy_txts *phy_txts)887{888 struct skb_shared_hwtstamps shhwtstamps;889 struct dp83640_skb_info *skb_info;890 struct sk_buff *skb;891 u8 overflow;892 u64 ns;893 894 /* We must already have the skb that triggered this. */895again:896 skb = skb_dequeue(&dp83640->tx_queue);897 if (!skb) {898 pr_debug("have timestamp but tx_queue empty\n");899 return;900 }901 902 overflow = (phy_txts->ns_hi >> 14) & 0x3;903 if (overflow) {904 pr_debug("tx timestamp queue overflow, count %d\n", overflow);905 while (skb) {906 kfree_skb(skb);907 skb = skb_dequeue(&dp83640->tx_queue);908 }909 return;910 }911 skb_info = (struct dp83640_skb_info *)skb->cb;912 if (time_after(jiffies, skb_info->tmo)) {913 kfree_skb(skb);914 goto again;915 }916 917 ns = phy2txts(phy_txts);918 memset(&shhwtstamps, 0, sizeof(shhwtstamps));919 shhwtstamps.hwtstamp = ns_to_ktime(ns);920 skb_complete_tx_timestamp(skb, &shhwtstamps);921}922 923static void decode_status_frame(struct dp83640_private *dp83640,924 struct sk_buff *skb)925{926 struct phy_rxts *phy_rxts;927 struct phy_txts *phy_txts;928 u8 *ptr;929 int len, size;930 u16 ests, type;931 932 ptr = skb->data + 2;933 934 for (len = skb_headlen(skb) - 2; len > sizeof(type); len -= size) {935 936 type = *(u16 *)ptr;937 ests = type & 0x0fff;938 type = type & 0xf000;939 len -= sizeof(type);940 ptr += sizeof(type);941 942 if (PSF_RX == type && len >= sizeof(*phy_rxts)) {943 944 phy_rxts = (struct phy_rxts *) ptr;945 decode_rxts(dp83640, phy_rxts);946 size = sizeof(*phy_rxts);947 948 } else if (PSF_TX == type && len >= sizeof(*phy_txts)) {949 950 phy_txts = (struct phy_txts *) ptr;951 decode_txts(dp83640, phy_txts);952 size = sizeof(*phy_txts);953 954 } else if (PSF_EVNT == type) {955 956 size = decode_evnt(dp83640, ptr, len, ests);957 958 } else {959 size = 0;960 break;961 }962 ptr += size;963 }964}965 966static void dp83640_free_clocks(void)967{968 struct dp83640_clock *clock;969 struct list_head *this, *next;970 971 mutex_lock(&phyter_clocks_lock);972 973 list_for_each_safe(this, next, &phyter_clocks) {974 clock = list_entry(this, struct dp83640_clock, list);975 if (!list_empty(&clock->phylist)) {976 pr_warn("phy list non-empty while unloading\n");977 BUG();978 }979 list_del(&clock->list);980 mutex_destroy(&clock->extreg_lock);981 mutex_destroy(&clock->clock_lock);982 put_device(&clock->bus->dev);983 kfree(clock->caps.pin_config);984 kfree(clock);985 }986 987 mutex_unlock(&phyter_clocks_lock);988}989 990static void dp83640_clock_init(struct dp83640_clock *clock, struct mii_bus *bus)991{992 INIT_LIST_HEAD(&clock->list);993 clock->bus = bus;994 mutex_init(&clock->extreg_lock);995 mutex_init(&clock->clock_lock);996 INIT_LIST_HEAD(&clock->phylist);997 clock->caps.owner = THIS_MODULE;998 sprintf(clock->caps.name, "dp83640 timer");999 clock->caps.max_adj = 1953124;1000 clock->caps.n_alarm = 0;1001 clock->caps.n_ext_ts = N_EXT_TS;1002 clock->caps.n_per_out = N_PER_OUT;1003 clock->caps.n_pins = DP83640_N_PINS;1004 clock->caps.pps = 0;1005 clock->caps.adjfine = ptp_dp83640_adjfine;1006 clock->caps.adjtime = ptp_dp83640_adjtime;1007 clock->caps.gettime64 = ptp_dp83640_gettime;1008 clock->caps.settime64 = ptp_dp83640_settime;1009 clock->caps.enable = ptp_dp83640_enable;1010 clock->caps.verify = ptp_dp83640_verify;1011 /*1012 * Convert the module param defaults into a dynamic pin configuration.1013 */1014 dp83640_gpio_defaults(clock->caps.pin_config);1015 /*1016 * Get a reference to this bus instance.1017 */1018 get_device(&bus->dev);1019}1020 1021static int choose_this_phy(struct dp83640_clock *clock,1022 struct phy_device *phydev)1023{1024 if (chosen_phy == -1 && !clock->chosen)1025 return 1;1026 1027 if (chosen_phy == phydev->mdio.addr)1028 return 1;1029 1030 return 0;1031}1032 1033static struct dp83640_clock *dp83640_clock_get(struct dp83640_clock *clock)1034{1035 if (clock)1036 mutex_lock(&clock->clock_lock);1037 return clock;1038}1039 1040/*1041 * Look up and lock a clock by bus instance.1042 * If there is no clock for this bus, then create it first.1043 */1044static struct dp83640_clock *dp83640_clock_get_bus(struct mii_bus *bus)1045{1046 struct dp83640_clock *clock = NULL, *tmp;1047 struct list_head *this;1048 1049 mutex_lock(&phyter_clocks_lock);1050 1051 list_for_each(this, &phyter_clocks) {1052 tmp = list_entry(this, struct dp83640_clock, list);1053 if (tmp->bus == bus) {1054 clock = tmp;1055 break;1056 }1057 }1058 if (clock)1059 goto out;1060 1061 clock = kzalloc(sizeof(struct dp83640_clock), GFP_KERNEL);1062 if (!clock)1063 goto out;1064 1065 clock->caps.pin_config = kcalloc(DP83640_N_PINS,1066 sizeof(struct ptp_pin_desc),1067 GFP_KERNEL);1068 if (!clock->caps.pin_config) {1069 kfree(clock);1070 clock = NULL;1071 goto out;1072 }1073 dp83640_clock_init(clock, bus);1074 list_add_tail(&clock->list, &phyter_clocks);1075out:1076 mutex_unlock(&phyter_clocks_lock);1077 1078 return dp83640_clock_get(clock);1079}1080 1081static void dp83640_clock_put(struct dp83640_clock *clock)1082{1083 mutex_unlock(&clock->clock_lock);1084}1085 1086static int dp83640_soft_reset(struct phy_device *phydev)1087{1088 int ret;1089 1090 ret = genphy_soft_reset(phydev);1091 if (ret < 0)1092 return ret;1093 1094 /* From DP83640 datasheet: "Software driver code must wait 3 us1095 * following a software reset before allowing further serial MII1096 * operations with the DP83640."1097 */1098 udelay(10); /* Taking udelay inaccuracy into account */1099 1100 return 0;1101}1102 1103static int dp83640_config_init(struct phy_device *phydev)1104{1105 struct dp83640_private *dp83640 = phydev->priv;1106 struct dp83640_clock *clock = dp83640->clock;1107 1108 if (clock->chosen && !list_empty(&clock->phylist))1109 recalibrate(clock);1110 else {1111 mutex_lock(&clock->extreg_lock);1112 enable_broadcast(phydev, clock->page, 1);1113 mutex_unlock(&clock->extreg_lock);1114 }1115 1116 enable_status_frames(phydev, true);1117 1118 mutex_lock(&clock->extreg_lock);1119 ext_write(0, phydev, PAGE4, PTP_CTL, PTP_ENABLE);1120 mutex_unlock(&clock->extreg_lock);1121 1122 return 0;1123}1124 1125static int dp83640_ack_interrupt(struct phy_device *phydev)1126{1127 int err = phy_read(phydev, MII_DP83640_MISR);1128 1129 if (err < 0)1130 return err;1131 1132 return 0;1133}1134 1135static int dp83640_config_intr(struct phy_device *phydev)1136{1137 int micr;1138 int misr;1139 int err;1140 1141 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {1142 err = dp83640_ack_interrupt(phydev);1143 if (err)1144 return err;1145 1146 misr = phy_read(phydev, MII_DP83640_MISR);1147 if (misr < 0)1148 return misr;1149 misr |=1150 (MII_DP83640_MISR_ANC_INT_EN |1151 MII_DP83640_MISR_DUP_INT_EN |1152 MII_DP83640_MISR_SPD_INT_EN |1153 MII_DP83640_MISR_LINK_INT_EN);1154 err = phy_write(phydev, MII_DP83640_MISR, misr);1155 if (err < 0)1156 return err;1157 1158 micr = phy_read(phydev, MII_DP83640_MICR);1159 if (micr < 0)1160 return micr;1161 micr |=1162 (MII_DP83640_MICR_OE |1163 MII_DP83640_MICR_IE);1164 return phy_write(phydev, MII_DP83640_MICR, micr);1165 } else {1166 micr = phy_read(phydev, MII_DP83640_MICR);1167 if (micr < 0)1168 return micr;1169 micr &=1170 ~(MII_DP83640_MICR_OE |1171 MII_DP83640_MICR_IE);1172 err = phy_write(phydev, MII_DP83640_MICR, micr);1173 if (err < 0)1174 return err;1175 1176 misr = phy_read(phydev, MII_DP83640_MISR);1177 if (misr < 0)1178 return misr;1179 misr &=1180 ~(MII_DP83640_MISR_ANC_INT_EN |1181 MII_DP83640_MISR_DUP_INT_EN |1182 MII_DP83640_MISR_SPD_INT_EN |1183 MII_DP83640_MISR_LINK_INT_EN);1184 err = phy_write(phydev, MII_DP83640_MISR, misr);1185 if (err)1186 return err;1187 1188 return dp83640_ack_interrupt(phydev);1189 }1190}1191 1192static irqreturn_t dp83640_handle_interrupt(struct phy_device *phydev)1193{1194 int irq_status;1195 1196 irq_status = phy_read(phydev, MII_DP83640_MISR);1197 if (irq_status < 0) {1198 phy_error(phydev);1199 return IRQ_NONE;1200 }1201 1202 if (!(irq_status & MII_DP83640_MISR_INT_MASK))1203 return IRQ_NONE;1204 1205 phy_trigger_machine(phydev);1206 1207 return IRQ_HANDLED;1208}1209 1210static int dp83640_hwtstamp(struct mii_timestamper *mii_ts,1211 struct kernel_hwtstamp_config *cfg,1212 struct netlink_ext_ack *extack)1213{1214 struct dp83640_private *dp83640 =1215 container_of(mii_ts, struct dp83640_private, mii_ts);1216 u16 txcfg0, rxcfg0;1217 1218 if (cfg->tx_type < 0 || cfg->tx_type > HWTSTAMP_TX_ONESTEP_SYNC)1219 return -ERANGE;1220 1221 dp83640->hwts_tx_en = cfg->tx_type;1222 1223 switch (cfg->rx_filter) {1224 case HWTSTAMP_FILTER_NONE:1225 dp83640->hwts_rx_en = 0;1226 dp83640->layer = 0;1227 dp83640->version = 0;1228 break;1229 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:1230 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:1231 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:1232 dp83640->hwts_rx_en = 1;1233 dp83640->layer = PTP_CLASS_L4;1234 dp83640->version = PTP_CLASS_V1;1235 cfg->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;1236 break;1237 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:1238 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:1239 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:1240 dp83640->hwts_rx_en = 1;1241 dp83640->layer = PTP_CLASS_L4;1242 dp83640->version = PTP_CLASS_V2;1243 cfg->rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;1244 break;1245 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:1246 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:1247 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:1248 dp83640->hwts_rx_en = 1;1249 dp83640->layer = PTP_CLASS_L2;1250 dp83640->version = PTP_CLASS_V2;1251 cfg->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;1252 break;1253 case HWTSTAMP_FILTER_PTP_V2_EVENT:1254 case HWTSTAMP_FILTER_PTP_V2_SYNC:1255 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:1256 dp83640->hwts_rx_en = 1;1257 dp83640->layer = PTP_CLASS_L4 | PTP_CLASS_L2;1258 dp83640->version = PTP_CLASS_V2;1259 cfg->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;1260 break;1261 default:1262 return -ERANGE;1263 }1264 1265 txcfg0 = (dp83640->version & TX_PTP_VER_MASK) << TX_PTP_VER_SHIFT;1266 rxcfg0 = (dp83640->version & TX_PTP_VER_MASK) << TX_PTP_VER_SHIFT;1267 1268 if (dp83640->layer & PTP_CLASS_L2) {1269 txcfg0 |= TX_L2_EN;1270 rxcfg0 |= RX_L2_EN;1271 }1272 if (dp83640->layer & PTP_CLASS_L4) {1273 txcfg0 |= TX_IPV6_EN | TX_IPV4_EN;1274 rxcfg0 |= RX_IPV6_EN | RX_IPV4_EN;1275 }1276 1277 if (dp83640->hwts_tx_en)1278 txcfg0 |= TX_TS_EN;1279 1280 if (dp83640->hwts_tx_en == HWTSTAMP_TX_ONESTEP_SYNC)1281 txcfg0 |= SYNC_1STEP | CHK_1STEP;1282 1283 if (dp83640->hwts_rx_en)1284 rxcfg0 |= RX_TS_EN;1285 1286 mutex_lock(&dp83640->clock->extreg_lock);1287 1288 ext_write(0, dp83640->phydev, PAGE5, PTP_TXCFG0, txcfg0);1289 ext_write(0, dp83640->phydev, PAGE5, PTP_RXCFG0, rxcfg0);1290 1291 mutex_unlock(&dp83640->clock->extreg_lock);1292 1293 return 0;1294}1295 1296static void rx_timestamp_work(struct work_struct *work)1297{1298 struct dp83640_private *dp83640 =1299 container_of(work, struct dp83640_private, ts_work.work);1300 struct sk_buff *skb;1301 1302 /* Deliver expired packets. */1303 while ((skb = skb_dequeue(&dp83640->rx_queue))) {1304 struct dp83640_skb_info *skb_info;1305 1306 skb_info = (struct dp83640_skb_info *)skb->cb;1307 if (!time_after(jiffies, skb_info->tmo)) {1308 skb_queue_head(&dp83640->rx_queue, skb);1309 break;1310 }1311 1312 netif_rx(skb);1313 }1314 1315 if (!skb_queue_empty(&dp83640->rx_queue))1316 schedule_delayed_work(&dp83640->ts_work, SKB_TIMESTAMP_TIMEOUT);1317}1318 1319static bool dp83640_rxtstamp(struct mii_timestamper *mii_ts,1320 struct sk_buff *skb, int type)1321{1322 struct dp83640_private *dp83640 =1323 container_of(mii_ts, struct dp83640_private, mii_ts);1324 struct dp83640_skb_info *skb_info = (struct dp83640_skb_info *)skb->cb;1325 struct list_head *this, *next;1326 struct rxts *rxts;1327 struct skb_shared_hwtstamps *shhwtstamps = NULL;1328 unsigned long flags;1329 1330 if (is_status_frame(skb, type)) {1331 decode_status_frame(dp83640, skb);1332 kfree_skb(skb);1333 return true;1334 }1335 1336 if (!dp83640->hwts_rx_en)1337 return false;1338 1339 if ((type & dp83640->version) == 0 || (type & dp83640->layer) == 0)1340 return false;1341 1342 spin_lock_irqsave(&dp83640->rx_lock, flags);1343 prune_rx_ts(dp83640);1344 list_for_each_safe(this, next, &dp83640->rxts) {1345 rxts = list_entry(this, struct rxts, list);1346 if (match(skb, type, rxts)) {1347 shhwtstamps = skb_hwtstamps(skb);1348 memset(shhwtstamps, 0, sizeof(*shhwtstamps));1349 shhwtstamps->hwtstamp = ns_to_ktime(rxts->ns);1350 list_del_init(&rxts->list);1351 list_add(&rxts->list, &dp83640->rxpool);1352 break;1353 }1354 }1355 spin_unlock_irqrestore(&dp83640->rx_lock, flags);1356 1357 if (!shhwtstamps) {1358 skb_info->ptp_type = type;1359 skb_info->tmo = jiffies + SKB_TIMESTAMP_TIMEOUT;1360 skb_queue_tail(&dp83640->rx_queue, skb);1361 schedule_delayed_work(&dp83640->ts_work, SKB_TIMESTAMP_TIMEOUT);1362 } else {1363 netif_rx(skb);1364 }1365 1366 return true;1367}1368 1369static void dp83640_txtstamp(struct mii_timestamper *mii_ts,1370 struct sk_buff *skb, int type)1371{1372 struct dp83640_skb_info *skb_info = (struct dp83640_skb_info *)skb->cb;1373 struct dp83640_private *dp83640 =1374 container_of(mii_ts, struct dp83640_private, mii_ts);1375 1376 switch (dp83640->hwts_tx_en) {1377 1378 case HWTSTAMP_TX_ONESTEP_SYNC:1379 if (ptp_msg_is_sync(skb, type)) {1380 kfree_skb(skb);1381 return;1382 }1383 fallthrough;1384 case HWTSTAMP_TX_ON:1385 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;1386 skb_info->tmo = jiffies + SKB_TIMESTAMP_TIMEOUT;1387 skb_queue_tail(&dp83640->tx_queue, skb);1388 break;1389 1390 case HWTSTAMP_TX_OFF:1391 default:1392 kfree_skb(skb);1393 break;1394 }1395}1396 1397static int dp83640_ts_info(struct mii_timestamper *mii_ts,1398 struct kernel_ethtool_ts_info *info)1399{1400 struct dp83640_private *dp83640 =1401 container_of(mii_ts, struct dp83640_private, mii_ts);1402 1403 info->so_timestamping =1404 SOF_TIMESTAMPING_TX_HARDWARE |1405 SOF_TIMESTAMPING_RX_HARDWARE |1406 SOF_TIMESTAMPING_RAW_HARDWARE;1407 info->phc_index = ptp_clock_index(dp83640->clock->ptp_clock);1408 info->tx_types =1409 (1 << HWTSTAMP_TX_OFF) |1410 (1 << HWTSTAMP_TX_ON) |1411 (1 << HWTSTAMP_TX_ONESTEP_SYNC);1412 info->rx_filters =1413 (1 << HWTSTAMP_FILTER_NONE) |1414 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |1415 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |1416 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |1417 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);1418 return 0;1419}1420 1421static int dp83640_probe(struct phy_device *phydev)1422{1423 struct dp83640_clock *clock;1424 struct dp83640_private *dp83640;1425 int err = -ENOMEM, i;1426 1427 if (phydev->mdio.addr == BROADCAST_ADDR)1428 return 0;1429 1430 clock = dp83640_clock_get_bus(phydev->mdio.bus);1431 if (!clock)1432 goto no_clock;1433 1434 dp83640 = kzalloc(sizeof(struct dp83640_private), GFP_KERNEL);1435 if (!dp83640)1436 goto no_memory;1437 1438 dp83640->phydev = phydev;1439 dp83640->mii_ts.rxtstamp = dp83640_rxtstamp;1440 dp83640->mii_ts.txtstamp = dp83640_txtstamp;1441 dp83640->mii_ts.hwtstamp = dp83640_hwtstamp;1442 dp83640->mii_ts.ts_info = dp83640_ts_info;1443 1444 INIT_DELAYED_WORK(&dp83640->ts_work, rx_timestamp_work);1445 INIT_LIST_HEAD(&dp83640->rxts);1446 INIT_LIST_HEAD(&dp83640->rxpool);1447 for (i = 0; i < MAX_RXTS; i++)1448 list_add(&dp83640->rx_pool_data[i].list, &dp83640->rxpool);1449 1450 /* Timestamp selected by default to keep legacy API */1451 phydev->default_timestamp = true;1452 phydev->mii_ts = &dp83640->mii_ts;1453 phydev->priv = dp83640;1454 1455 spin_lock_init(&dp83640->rx_lock);1456 skb_queue_head_init(&dp83640->rx_queue);1457 skb_queue_head_init(&dp83640->tx_queue);1458 1459 dp83640->clock = clock;1460 1461 if (choose_this_phy(clock, phydev)) {1462 clock->chosen = dp83640;1463 clock->ptp_clock = ptp_clock_register(&clock->caps,1464 &phydev->mdio.dev);1465 if (IS_ERR(clock->ptp_clock)) {1466 err = PTR_ERR(clock->ptp_clock);1467 goto no_register;1468 }1469 } else1470 list_add_tail(&dp83640->list, &clock->phylist);1471 1472 dp83640_clock_put(clock);1473 return 0;1474 1475no_register:1476 clock->chosen = NULL;1477 kfree(dp83640);1478no_memory:1479 dp83640_clock_put(clock);1480no_clock:1481 return err;1482}1483 1484static void dp83640_remove(struct phy_device *phydev)1485{1486 struct dp83640_clock *clock;1487 struct list_head *this, *next;1488 struct dp83640_private *tmp, *dp83640 = phydev->priv;1489 1490 if (phydev->mdio.addr == BROADCAST_ADDR)1491 return;1492 1493 phydev->mii_ts = NULL;1494 1495 enable_status_frames(phydev, false);1496 cancel_delayed_work_sync(&dp83640->ts_work);1497 1498 skb_queue_purge(&dp83640->rx_queue);1499 skb_queue_purge(&dp83640->tx_queue);1500 1501 clock = dp83640_clock_get(dp83640->clock);1502 1503 if (dp83640 == clock->chosen) {1504 ptp_clock_unregister(clock->ptp_clock);1505 clock->chosen = NULL;1506 } else {1507 list_for_each_safe(this, next, &clock->phylist) {1508 tmp = list_entry(this, struct dp83640_private, list);1509 if (tmp == dp83640) {1510 list_del_init(&tmp->list);1511 break;1512 }1513 }1514 }1515 1516 dp83640_clock_put(clock);1517 kfree(dp83640);1518}1519 1520static struct phy_driver dp83640_driver = {1521 .phy_id = DP83640_PHY_ID,1522 .phy_id_mask = 0xfffffff0,1523 .name = "NatSemi DP83640",1524 /* PHY_BASIC_FEATURES */1525 .probe = dp83640_probe,1526 .remove = dp83640_remove,1527 .soft_reset = dp83640_soft_reset,1528 .config_init = dp83640_config_init,1529 .config_intr = dp83640_config_intr,1530 .handle_interrupt = dp83640_handle_interrupt,1531};1532 1533static int __init dp83640_init(void)1534{1535 return phy_driver_register(&dp83640_driver, THIS_MODULE);1536}1537 1538static void __exit dp83640_exit(void)1539{1540 dp83640_free_clocks();1541 phy_driver_unregister(&dp83640_driver);1542}1543 1544MODULE_DESCRIPTION("National Semiconductor DP83640 PHY driver");1545MODULE_AUTHOR("Richard Cochran <richardcochran@gmail.com>");1546MODULE_LICENSE("GPL");1547 1548module_init(dp83640_init);1549module_exit(dp83640_exit);1550 1551static struct mdio_device_id __maybe_unused dp83640_tbl[] = {1552 { DP83640_PHY_ID, 0xfffffff0 },1553 { }1554};1555 1556MODULE_DEVICE_TABLE(mdio, dp83640_tbl);1557