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1// SPDX-License-Identifier: GPL-2.0+2#include <linux/bitfield.h>3#include <linux/module.h>4#include <linux/phy.h>5 6#define MTK_EXT_PAGE_ACCESS 0x1f7#define MTK_PHY_PAGE_STANDARD 0x00008#define MTK_PHY_PAGE_EXTENDED 0x00019#define MTK_PHY_PAGE_EXTENDED_2 0x000210#define MTK_PHY_PAGE_EXTENDED_3 0x000311#define MTK_PHY_PAGE_EXTENDED_2A30 0x2a3012#define MTK_PHY_PAGE_EXTENDED_52B5 0x52b513 14static int mtk_gephy_read_page(struct phy_device *phydev)15{16 return __phy_read(phydev, MTK_EXT_PAGE_ACCESS);17}18 19static int mtk_gephy_write_page(struct phy_device *phydev, int page)20{21 return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page);22}23 24static void mtk_gephy_config_init(struct phy_device *phydev)25{26 /* Enable HW auto downshift */27 phy_modify_paged(phydev, MTK_PHY_PAGE_EXTENDED, 0x14, 0, BIT(4));28 29 /* Increase SlvDPSready time */30 phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);31 __phy_write(phydev, 0x10, 0xafae);32 __phy_write(phydev, 0x12, 0x2f);33 __phy_write(phydev, 0x10, 0x8fae);34 phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);35 36 /* Adjust 100_mse_threshold */37 phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x123, 0xffff);38 39 /* Disable mcc */40 phy_write_mmd(phydev, MDIO_MMD_VEND1, 0xa6, 0x300);41}42 43static int mt7530_phy_config_init(struct phy_device *phydev)44{45 mtk_gephy_config_init(phydev);46 47 /* Increase post_update_timer */48 phy_write_paged(phydev, MTK_PHY_PAGE_EXTENDED_3, 0x11, 0x4b);49 50 return 0;51}52 53static int mt7531_phy_config_init(struct phy_device *phydev)54{55 mtk_gephy_config_init(phydev);56 57 /* PHY link down power saving enable */58 phy_set_bits(phydev, 0x17, BIT(4));59 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 0xc6, 0x300);60 61 /* Set TX Pair delay selection */62 phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x13, 0x404);63 phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x14, 0x404);64 65 return 0;66}67 68static struct phy_driver mtk_gephy_driver[] = {69 {70 PHY_ID_MATCH_EXACT(0x03a29412),71 .name = "MediaTek MT7530 PHY",72 .config_init = mt7530_phy_config_init,73 /* Interrupts are handled by the switch, not the PHY74 * itself.75 */76 .config_intr = genphy_no_config_intr,77 .handle_interrupt = genphy_handle_interrupt_no_ack,78 .suspend = genphy_suspend,79 .resume = genphy_resume,80 .read_page = mtk_gephy_read_page,81 .write_page = mtk_gephy_write_page,82 },83 {84 PHY_ID_MATCH_EXACT(0x03a29441),85 .name = "MediaTek MT7531 PHY",86 .config_init = mt7531_phy_config_init,87 /* Interrupts are handled by the switch, not the PHY88 * itself.89 */90 .config_intr = genphy_no_config_intr,91 .handle_interrupt = genphy_handle_interrupt_no_ack,92 .suspend = genphy_suspend,93 .resume = genphy_resume,94 .read_page = mtk_gephy_read_page,95 .write_page = mtk_gephy_write_page,96 },97};98 99module_phy_driver(mtk_gephy_driver);100 101static struct mdio_device_id __maybe_unused mtk_gephy_tbl[] = {102 { PHY_ID_MATCH_EXACT(0x03a29441) },103 { PHY_ID_MATCH_EXACT(0x03a29412) },104 { }105};106 107MODULE_DESCRIPTION("MediaTek Gigabit Ethernet PHY driver");108MODULE_AUTHOR("DENG, Qingfang <dqfext@gmail.com>");109MODULE_LICENSE("GPL");110 111MODULE_DEVICE_TABLE(mdio, mtk_gephy_tbl);112