brintos / linux-shallow public Read only

1// SPDX-License-Identifier: GPL-2.0+2/*3 * drivers/net/phy/micrel.c4 *5 * Driver for Micrel PHYs6 *7 * Author: David J. Choi8 *9 * Copyright (c) 2010-2013 Micrel, Inc.10 * Copyright (c) 2014 Johan Hovold <johan@kernel.org>11 *12 * Support : Micrel Phys:13 *		Giga phys: ksz9021, ksz9031, ksz9131, lan8841, lan881414 *		100/10 Phys : ksz8001, ksz8721, ksz8737, ksz804115 *			   ksz8021, ksz8031, ksz8051,16 *			   ksz8081, ksz8091,17 *			   ksz8061,18 *		Switch : ksz8873, ksz886x19 *			 ksz9477, lan880420 */21 22#include <linux/bitfield.h>23#include <linux/ethtool_netlink.h>24#include <linux/kernel.h>25#include <linux/module.h>26#include <linux/phy.h>27#include <linux/micrel_phy.h>28#include <linux/of.h>29#include <linux/clk.h>30#include <linux/delay.h>31#include <linux/ptp_clock_kernel.h>32#include <linux/ptp_clock.h>33#include <linux/ptp_classify.h>34#include <linux/net_tstamp.h>35#include <linux/gpio/consumer.h>36 37/* Operation Mode Strap Override */38#define MII_KSZPHY_OMSO				0x1639#define KSZPHY_OMSO_FACTORY_TEST		BIT(15)40#define KSZPHY_OMSO_B_CAST_OFF			BIT(9)41#define KSZPHY_OMSO_NAND_TREE_ON		BIT(5)42#define KSZPHY_OMSO_RMII_OVERRIDE		BIT(1)43#define KSZPHY_OMSO_MII_OVERRIDE		BIT(0)44 45/* general Interrupt control/status reg in vendor specific block. */46#define MII_KSZPHY_INTCS			0x1B47#define KSZPHY_INTCS_JABBER			BIT(15)48#define KSZPHY_INTCS_RECEIVE_ERR		BIT(14)49#define KSZPHY_INTCS_PAGE_RECEIVE		BIT(13)50#define KSZPHY_INTCS_PARELLEL			BIT(12)51#define KSZPHY_INTCS_LINK_PARTNER_ACK		BIT(11)52#define KSZPHY_INTCS_LINK_DOWN			BIT(10)53#define KSZPHY_INTCS_REMOTE_FAULT		BIT(9)54#define KSZPHY_INTCS_LINK_UP			BIT(8)55#define KSZPHY_INTCS_ALL			(KSZPHY_INTCS_LINK_UP |\56						KSZPHY_INTCS_LINK_DOWN)57#define KSZPHY_INTCS_LINK_DOWN_STATUS		BIT(2)58#define KSZPHY_INTCS_LINK_UP_STATUS		BIT(0)59#define KSZPHY_INTCS_STATUS			(KSZPHY_INTCS_LINK_DOWN_STATUS |\60						 KSZPHY_INTCS_LINK_UP_STATUS)61 62/* LinkMD Control/Status */63#define KSZ8081_LMD				0x1d64#define KSZ8081_LMD_ENABLE_TEST			BIT(15)65#define KSZ8081_LMD_STAT_NORMAL			066#define KSZ8081_LMD_STAT_OPEN			167#define KSZ8081_LMD_STAT_SHORT			268#define KSZ8081_LMD_STAT_FAIL			369#define KSZ8081_LMD_STAT_MASK			GENMASK(14, 13)70/* Short cable (<10 meter) has been detected by LinkMD */71#define KSZ8081_LMD_SHORT_INDICATOR		BIT(12)72#define KSZ8081_LMD_DELTA_TIME_MASK		GENMASK(8, 0)73 74#define KSZ9x31_LMD				0x1275#define KSZ9x31_LMD_VCT_EN			BIT(15)76#define KSZ9x31_LMD_VCT_DIS_TX			BIT(14)77#define KSZ9x31_LMD_VCT_PAIR(n)			(((n) & 0x3) << 12)78#define KSZ9x31_LMD_VCT_SEL_RESULT		079#define KSZ9x31_LMD_VCT_SEL_THRES_HI		BIT(10)80#define KSZ9x31_LMD_VCT_SEL_THRES_LO		BIT(11)81#define KSZ9x31_LMD_VCT_SEL_MASK		GENMASK(11, 10)82#define KSZ9x31_LMD_VCT_ST_NORMAL		083#define KSZ9x31_LMD_VCT_ST_OPEN			184#define KSZ9x31_LMD_VCT_ST_SHORT		285#define KSZ9x31_LMD_VCT_ST_FAIL			386#define KSZ9x31_LMD_VCT_ST_MASK			GENMASK(9, 8)87#define KSZ9x31_LMD_VCT_DATA_REFLECTED_INVALID	BIT(7)88#define KSZ9x31_LMD_VCT_DATA_SIG_WAIT_TOO_LONG	BIT(6)89#define KSZ9x31_LMD_VCT_DATA_MASK100		BIT(5)90#define KSZ9x31_LMD_VCT_DATA_NLP_FLP		BIT(4)91#define KSZ9x31_LMD_VCT_DATA_LO_PULSE_MASK	GENMASK(3, 2)92#define KSZ9x31_LMD_VCT_DATA_HI_PULSE_MASK	GENMASK(1, 0)93#define KSZ9x31_LMD_VCT_DATA_MASK		GENMASK(7, 0)94 95#define KSZPHY_WIRE_PAIR_MASK			0x396 97#define LAN8814_CABLE_DIAG			0x1298#define LAN8814_CABLE_DIAG_STAT_MASK		GENMASK(9, 8)99#define LAN8814_CABLE_DIAG_VCT_DATA_MASK	GENMASK(7, 0)100#define LAN8814_PAIR_BIT_SHIFT			12101 102#define LAN8814_WIRE_PAIR_MASK			0xF103 104/* Lan8814 general Interrupt control/status reg in GPHY specific block. */105#define LAN8814_INTC				0x18106#define LAN8814_INTS				0x1B107 108#define LAN8814_INT_LINK_DOWN			BIT(2)109#define LAN8814_INT_LINK_UP			BIT(0)110#define LAN8814_INT_LINK			(LAN8814_INT_LINK_UP |\111						 LAN8814_INT_LINK_DOWN)112 113#define LAN8814_INTR_CTRL_REG			0x34114#define LAN8814_INTR_CTRL_REG_POLARITY		BIT(1)115#define LAN8814_INTR_CTRL_REG_INTR_ENABLE	BIT(0)116 117#define LAN8814_EEE_STATE			0x38118#define LAN8814_EEE_STATE_MASK2P5P		BIT(10)119 120#define LAN8814_PD_CONTROLS			0x9d121#define LAN8814_PD_CONTROLS_PD_MEAS_TIME_MASK	GENMASK(3, 0)122#define LAN8814_PD_CONTROLS_PD_MEAS_TIME_VAL	0xb123 124/* Represents 1ppm adjustment in 2^32 format with125 * each nsec contains 4 clock cycles.126 * The value is calculated as following: (1/1000000)/((2^-32)/4)127 */128#define LAN8814_1PPM_FORMAT			17179129 130/* Represents 1ppm adjustment in 2^32 format with131 * each nsec contains 8 clock cycles.132 * The value is calculated as following: (1/1000000)/((2^-32)/8)133 */134#define LAN8841_1PPM_FORMAT			34360135 136#define PTP_RX_VERSION				0x0248137#define PTP_TX_VERSION				0x0288138#define PTP_MAX_VERSION(x)			(((x) & GENMASK(7, 0)) << 8)139#define PTP_MIN_VERSION(x)			((x) & GENMASK(7, 0))140 141#define PTP_RX_MOD				0x024F142#define PTP_RX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_ BIT(3)143#define PTP_RX_TIMESTAMP_EN			0x024D144#define PTP_TX_TIMESTAMP_EN			0x028D145 146#define PTP_TIMESTAMP_EN_SYNC_			BIT(0)147#define PTP_TIMESTAMP_EN_DREQ_			BIT(1)148#define PTP_TIMESTAMP_EN_PDREQ_			BIT(2)149#define PTP_TIMESTAMP_EN_PDRES_			BIT(3)150 151#define PTP_TX_PARSE_L2_ADDR_EN			0x0284152#define PTP_RX_PARSE_L2_ADDR_EN			0x0244153 154#define PTP_TX_PARSE_IP_ADDR_EN			0x0285155#define PTP_RX_PARSE_IP_ADDR_EN			0x0245156#define LTC_HARD_RESET				0x023F157#define LTC_HARD_RESET_				BIT(0)158 159#define TSU_HARD_RESET				0x02C1160#define TSU_HARD_RESET_				BIT(0)161 162#define PTP_CMD_CTL				0x0200163#define PTP_CMD_CTL_PTP_DISABLE_		BIT(0)164#define PTP_CMD_CTL_PTP_ENABLE_			BIT(1)165#define PTP_CMD_CTL_PTP_CLOCK_READ_		BIT(3)166#define PTP_CMD_CTL_PTP_CLOCK_LOAD_		BIT(4)167#define PTP_CMD_CTL_PTP_LTC_STEP_SEC_		BIT(5)168#define PTP_CMD_CTL_PTP_LTC_STEP_NSEC_		BIT(6)169 170#define PTP_COMMON_INT_ENA			0x0204171#define PTP_COMMON_INT_ENA_GPIO_CAP_EN		BIT(2)172 173#define PTP_CLOCK_SET_SEC_HI			0x0205174#define PTP_CLOCK_SET_SEC_MID			0x0206175#define PTP_CLOCK_SET_SEC_LO			0x0207176#define PTP_CLOCK_SET_NS_HI			0x0208177#define PTP_CLOCK_SET_NS_LO			0x0209178 179#define PTP_CLOCK_READ_SEC_HI			0x0229180#define PTP_CLOCK_READ_SEC_MID			0x022A181#define PTP_CLOCK_READ_SEC_LO			0x022B182#define PTP_CLOCK_READ_NS_HI			0x022C183#define PTP_CLOCK_READ_NS_LO			0x022D184 185#define PTP_GPIO_SEL				0x0230186#define PTP_GPIO_SEL_GPIO_SEL(pin)		((pin) << 8)187#define PTP_GPIO_CAP_MAP_LO			0x0232188 189#define PTP_GPIO_CAP_EN				0x0233190#define PTP_GPIO_CAP_EN_GPIO_RE_CAPTURE_ENABLE(gpio)	BIT(gpio)191#define PTP_GPIO_CAP_EN_GPIO_FE_CAPTURE_ENABLE(gpio)	(BIT(gpio) << 8)192 193#define PTP_GPIO_RE_LTC_SEC_HI_CAP		0x0235194#define PTP_GPIO_RE_LTC_SEC_LO_CAP		0x0236195#define PTP_GPIO_RE_LTC_NS_HI_CAP		0x0237196#define PTP_GPIO_RE_LTC_NS_LO_CAP		0x0238197#define PTP_GPIO_FE_LTC_SEC_HI_CAP		0x0239198#define PTP_GPIO_FE_LTC_SEC_LO_CAP		0x023A199#define PTP_GPIO_FE_LTC_NS_HI_CAP		0x023B200#define PTP_GPIO_FE_LTC_NS_LO_CAP		0x023C201 202#define PTP_GPIO_CAP_STS			0x023D203#define PTP_GPIO_CAP_STS_PTP_GPIO_RE_STS(gpio)	BIT(gpio)204#define PTP_GPIO_CAP_STS_PTP_GPIO_FE_STS(gpio)	(BIT(gpio) << 8)205 206#define PTP_OPERATING_MODE			0x0241207#define PTP_OPERATING_MODE_STANDALONE_		BIT(0)208 209#define PTP_TX_MOD				0x028F210#define PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_	BIT(12)211#define PTP_TX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_ BIT(3)212 213#define PTP_RX_PARSE_CONFIG			0x0242214#define PTP_RX_PARSE_CONFIG_LAYER2_EN_		BIT(0)215#define PTP_RX_PARSE_CONFIG_IPV4_EN_		BIT(1)216#define PTP_RX_PARSE_CONFIG_IPV6_EN_		BIT(2)217 218#define PTP_TX_PARSE_CONFIG			0x0282219#define PTP_TX_PARSE_CONFIG_LAYER2_EN_		BIT(0)220#define PTP_TX_PARSE_CONFIG_IPV4_EN_		BIT(1)221#define PTP_TX_PARSE_CONFIG_IPV6_EN_		BIT(2)222 223#define PTP_CLOCK_RATE_ADJ_HI			0x020C224#define PTP_CLOCK_RATE_ADJ_LO			0x020D225#define PTP_CLOCK_RATE_ADJ_DIR_			BIT(15)226 227#define PTP_LTC_STEP_ADJ_HI			0x0212228#define PTP_LTC_STEP_ADJ_LO			0x0213229#define PTP_LTC_STEP_ADJ_DIR_			BIT(15)230 231#define LAN8814_INTR_STS_REG			0x0033232#define LAN8814_INTR_STS_REG_1588_TSU0_		BIT(0)233#define LAN8814_INTR_STS_REG_1588_TSU1_		BIT(1)234#define LAN8814_INTR_STS_REG_1588_TSU2_		BIT(2)235#define LAN8814_INTR_STS_REG_1588_TSU3_		BIT(3)236 237#define PTP_CAP_INFO				0x022A238#define PTP_CAP_INFO_TX_TS_CNT_GET_(reg_val)	(((reg_val) & 0x0f00) >> 8)239#define PTP_CAP_INFO_RX_TS_CNT_GET_(reg_val)	((reg_val) & 0x000f)240 241#define PTP_TX_EGRESS_SEC_HI			0x0296242#define PTP_TX_EGRESS_SEC_LO			0x0297243#define PTP_TX_EGRESS_NS_HI			0x0294244#define PTP_TX_EGRESS_NS_LO			0x0295245#define PTP_TX_MSG_HEADER2			0x0299246 247#define PTP_RX_INGRESS_SEC_HI			0x0256248#define PTP_RX_INGRESS_SEC_LO			0x0257249#define PTP_RX_INGRESS_NS_HI			0x0254250#define PTP_RX_INGRESS_NS_LO			0x0255251#define PTP_RX_MSG_HEADER2			0x0259252 253#define PTP_TSU_INT_EN				0x0200254#define PTP_TSU_INT_EN_PTP_TX_TS_OVRFL_EN_	BIT(3)255#define PTP_TSU_INT_EN_PTP_TX_TS_EN_		BIT(2)256#define PTP_TSU_INT_EN_PTP_RX_TS_OVRFL_EN_	BIT(1)257#define PTP_TSU_INT_EN_PTP_RX_TS_EN_		BIT(0)258 259#define PTP_TSU_INT_STS				0x0201260#define PTP_TSU_INT_STS_PTP_TX_TS_OVRFL_INT_	BIT(3)261#define PTP_TSU_INT_STS_PTP_TX_TS_EN_		BIT(2)262#define PTP_TSU_INT_STS_PTP_RX_TS_OVRFL_INT_	BIT(1)263#define PTP_TSU_INT_STS_PTP_RX_TS_EN_		BIT(0)264 265#define LAN8814_LED_CTRL_1			0x0266#define LAN8814_LED_CTRL_1_KSZ9031_LED_MODE_	BIT(6)267 268/* PHY Control 1 */269#define MII_KSZPHY_CTRL_1			0x1e270#define KSZ8081_CTRL1_MDIX_STAT			BIT(4)271 272/* PHY Control 2 / PHY Control (if no PHY Control 1) */273#define MII_KSZPHY_CTRL_2			0x1f274#define MII_KSZPHY_CTRL				MII_KSZPHY_CTRL_2275/* bitmap of PHY register to set interrupt mode */276#define KSZ8081_CTRL2_HP_MDIX			BIT(15)277#define KSZ8081_CTRL2_MDI_MDI_X_SELECT		BIT(14)278#define KSZ8081_CTRL2_DISABLE_AUTO_MDIX		BIT(13)279#define KSZ8081_CTRL2_FORCE_LINK		BIT(11)280#define KSZ8081_CTRL2_POWER_SAVING		BIT(10)281#define KSZPHY_CTRL_INT_ACTIVE_HIGH		BIT(9)282#define KSZPHY_RMII_REF_CLK_SEL			BIT(7)283 284/* Write/read to/from extended registers */285#define MII_KSZPHY_EXTREG			0x0b286#define KSZPHY_EXTREG_WRITE			0x8000287 288#define MII_KSZPHY_EXTREG_WRITE			0x0c289#define MII_KSZPHY_EXTREG_READ			0x0d290 291/* Extended registers */292#define MII_KSZPHY_CLK_CONTROL_PAD_SKEW		0x104293#define MII_KSZPHY_RX_DATA_PAD_SKEW		0x105294#define MII_KSZPHY_TX_DATA_PAD_SKEW		0x106295 296#define PS_TO_REG				200297#define FIFO_SIZE				8298 299#define LAN8814_PTP_GPIO_NUM			24300#define LAN8814_PTP_PEROUT_NUM			2301#define LAN8814_PTP_EXTTS_NUM			3302 303#define LAN8814_BUFFER_TIME			2304 305#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_200MS	13306#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100MS	12307#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_50MS	11308#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_10MS	10309#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_5MS	9310#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_1MS	8311#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_500US	7312#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100US	6313#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_50US	5314#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_10US	4315#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_5US	3316#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_1US	2317#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_500NS	1318#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100NS	0319 320#define LAN8814_GPIO_EN1			0x20321#define LAN8814_GPIO_EN2			0x21322#define LAN8814_GPIO_DIR1			0x22323#define LAN8814_GPIO_DIR2			0x23324#define LAN8814_GPIO_BUF1			0x24325#define LAN8814_GPIO_BUF2			0x25326 327#define LAN8814_GPIO_EN_ADDR(pin) \328	((pin) > 15 ? LAN8814_GPIO_EN1 : LAN8814_GPIO_EN2)329#define LAN8814_GPIO_EN_BIT(pin)		BIT(pin)330#define LAN8814_GPIO_DIR_ADDR(pin) \331	((pin) > 15 ? LAN8814_GPIO_DIR1 : LAN8814_GPIO_DIR2)332#define LAN8814_GPIO_DIR_BIT(pin)		BIT(pin)333#define LAN8814_GPIO_BUF_ADDR(pin) \334	((pin) > 15 ? LAN8814_GPIO_BUF1 : LAN8814_GPIO_BUF2)335#define LAN8814_GPIO_BUF_BIT(pin)		BIT(pin)336 337#define LAN8814_EVENT_A				0338#define LAN8814_EVENT_B				1339 340#define LAN8814_PTP_GENERAL_CONFIG		0x0201341#define LAN8814_PTP_GENERAL_CONFIG_LTC_EVENT_MASK(event) \342	((event) ? GENMASK(11, 8) : GENMASK(7, 4))343#define LAN8814_PTP_GENERAL_CONFIG_LTC_EVENT_SET(event, value) \344	(((value) & GENMASK(3, 0)) << (4 + ((event) << 2)))345#define LAN8814_PTP_GENERAL_CONFIG_RELOAD_ADD_X(event) \346	((event) ? BIT(2) : BIT(0))347#define LAN8814_PTP_GENERAL_CONFIG_POLARITY_X(event) \348	((event) ? BIT(3) : BIT(1))349 350#define LAN8814_PTP_CLOCK_TARGET_SEC_HI(event)	((event) ? 0x21F : 0x215)351#define LAN8814_PTP_CLOCK_TARGET_SEC_LO(event)	((event) ? 0x220 : 0x216)352#define LAN8814_PTP_CLOCK_TARGET_NS_HI(event)	((event) ? 0x221 : 0x217)353#define LAN8814_PTP_CLOCK_TARGET_NS_LO(event)	((event) ? 0x222 : 0x218)354 355#define LAN8814_PTP_CLOCK_TARGET_RELOAD_SEC_HI(event)	((event) ? 0x223 : 0x219)356#define LAN8814_PTP_CLOCK_TARGET_RELOAD_SEC_LO(event)	((event) ? 0x224 : 0x21A)357#define LAN8814_PTP_CLOCK_TARGET_RELOAD_NS_HI(event)	((event) ? 0x225 : 0x21B)358#define LAN8814_PTP_CLOCK_TARGET_RELOAD_NS_LO(event)	((event) ? 0x226 : 0x21C)359 360/* Delay used to get the second part from the LTC */361#define LAN8841_GET_SEC_LTC_DELAY		(500 * NSEC_PER_MSEC)362 363struct kszphy_hw_stat {364	const char *string;365	u8 reg;366	u8 bits;367};368 369static struct kszphy_hw_stat kszphy_hw_stats[] = {370	{ "phy_receive_errors", 21, 16},371	{ "phy_idle_errors", 10, 8 },372};373 374struct kszphy_type {375	u32 led_mode_reg;376	u16 interrupt_level_mask;377	u16 cable_diag_reg;378	unsigned long pair_mask;379	u16 disable_dll_tx_bit;380	u16 disable_dll_rx_bit;381	u16 disable_dll_mask;382	bool has_broadcast_disable;383	bool has_nand_tree_disable;384	bool has_rmii_ref_clk_sel;385};386 387/* Shared structure between the PHYs of the same package. */388struct lan8814_shared_priv {389	struct phy_device *phydev;390	struct ptp_clock *ptp_clock;391	struct ptp_clock_info ptp_clock_info;392	struct ptp_pin_desc *pin_config;393 394	/* Lock for ptp_clock */395	struct mutex shared_lock;396};397 398struct lan8814_ptp_rx_ts {399	struct list_head list;400	u32 seconds;401	u32 nsec;402	u16 seq_id;403};404 405struct kszphy_ptp_priv {406	struct mii_timestamper mii_ts;407	struct phy_device *phydev;408 409	struct sk_buff_head tx_queue;410	struct sk_buff_head rx_queue;411 412	struct list_head rx_ts_list;413	/* Lock for Rx ts fifo */414	spinlock_t rx_ts_lock;415 416	int hwts_tx_type;417	enum hwtstamp_rx_filters rx_filter;418	int layer;419	int version;420 421	struct ptp_clock *ptp_clock;422	struct ptp_clock_info ptp_clock_info;423	/* Lock for ptp_clock */424	struct mutex ptp_lock;425	struct ptp_pin_desc *pin_config;426 427	s64 seconds;428	/* Lock for accessing seconds */429	spinlock_t seconds_lock;430};431 432struct kszphy_priv {433	struct kszphy_ptp_priv ptp_priv;434	const struct kszphy_type *type;435	int led_mode;436	u16 vct_ctrl1000;437	bool rmii_ref_clk_sel;438	bool rmii_ref_clk_sel_val;439	u64 stats[ARRAY_SIZE(kszphy_hw_stats)];440};441 442static const struct kszphy_type lan8814_type = {443	.led_mode_reg		= ~LAN8814_LED_CTRL_1,444	.cable_diag_reg		= LAN8814_CABLE_DIAG,445	.pair_mask		= LAN8814_WIRE_PAIR_MASK,446};447 448static const struct kszphy_type ksz886x_type = {449	.cable_diag_reg		= KSZ8081_LMD,450	.pair_mask		= KSZPHY_WIRE_PAIR_MASK,451};452 453static const struct kszphy_type ksz8021_type = {454	.led_mode_reg		= MII_KSZPHY_CTRL_2,455	.has_broadcast_disable	= true,456	.has_nand_tree_disable	= true,457	.has_rmii_ref_clk_sel	= true,458};459 460static const struct kszphy_type ksz8041_type = {461	.led_mode_reg		= MII_KSZPHY_CTRL_1,462};463 464static const struct kszphy_type ksz8051_type = {465	.led_mode_reg		= MII_KSZPHY_CTRL_2,466	.has_nand_tree_disable	= true,467};468 469static const struct kszphy_type ksz8081_type = {470	.led_mode_reg		= MII_KSZPHY_CTRL_2,471	.has_broadcast_disable	= true,472	.has_nand_tree_disable	= true,473	.has_rmii_ref_clk_sel	= true,474};475 476static const struct kszphy_type ks8737_type = {477	.interrupt_level_mask	= BIT(14),478};479 480static const struct kszphy_type ksz9021_type = {481	.interrupt_level_mask	= BIT(14),482};483 484static const struct kszphy_type ksz9131_type = {485	.interrupt_level_mask	= BIT(14),486	.disable_dll_tx_bit	= BIT(12),487	.disable_dll_rx_bit	= BIT(12),488	.disable_dll_mask	= BIT_MASK(12),489};490 491static const struct kszphy_type lan8841_type = {492	.disable_dll_tx_bit	= BIT(14),493	.disable_dll_rx_bit	= BIT(14),494	.disable_dll_mask	= BIT_MASK(14),495	.cable_diag_reg		= LAN8814_CABLE_DIAG,496	.pair_mask		= LAN8814_WIRE_PAIR_MASK,497};498 499static int kszphy_extended_write(struct phy_device *phydev,500				u32 regnum, u16 val)501{502	phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum);503	return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val);504}505 506static int kszphy_extended_read(struct phy_device *phydev,507				u32 regnum)508{509	phy_write(phydev, MII_KSZPHY_EXTREG, regnum);510	return phy_read(phydev, MII_KSZPHY_EXTREG_READ);511}512 513static int kszphy_ack_interrupt(struct phy_device *phydev)514{515	/* bit[7..0] int status, which is a read and clear register. */516	int rc;517 518	rc = phy_read(phydev, MII_KSZPHY_INTCS);519 520	return (rc < 0) ? rc : 0;521}522 523static int kszphy_config_intr(struct phy_device *phydev)524{525	const struct kszphy_type *type = phydev->drv->driver_data;526	int temp, err;527	u16 mask;528 529	if (type && type->interrupt_level_mask)530		mask = type->interrupt_level_mask;531	else532		mask = KSZPHY_CTRL_INT_ACTIVE_HIGH;533 534	/* set the interrupt pin active low */535	temp = phy_read(phydev, MII_KSZPHY_CTRL);536	if (temp < 0)537		return temp;538	temp &= ~mask;539	phy_write(phydev, MII_KSZPHY_CTRL, temp);540 541	/* enable / disable interrupts */542	if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {543		err = kszphy_ack_interrupt(phydev);544		if (err)545			return err;546 547		err = phy_write(phydev, MII_KSZPHY_INTCS, KSZPHY_INTCS_ALL);548	} else {549		err = phy_write(phydev, MII_KSZPHY_INTCS, 0);550		if (err)551			return err;552 553		err = kszphy_ack_interrupt(phydev);554	}555 556	return err;557}558 559static irqreturn_t kszphy_handle_interrupt(struct phy_device *phydev)560{561	int irq_status;562 563	irq_status = phy_read(phydev, MII_KSZPHY_INTCS);564	if (irq_status < 0) {565		phy_error(phydev);566		return IRQ_NONE;567	}568 569	if (!(irq_status & KSZPHY_INTCS_STATUS))570		return IRQ_NONE;571 572	phy_trigger_machine(phydev);573 574	return IRQ_HANDLED;575}576 577static int kszphy_rmii_clk_sel(struct phy_device *phydev, bool val)578{579	int ctrl;580 581	ctrl = phy_read(phydev, MII_KSZPHY_CTRL);582	if (ctrl < 0)583		return ctrl;584 585	if (val)586		ctrl |= KSZPHY_RMII_REF_CLK_SEL;587	else588		ctrl &= ~KSZPHY_RMII_REF_CLK_SEL;589 590	return phy_write(phydev, MII_KSZPHY_CTRL, ctrl);591}592 593static int kszphy_setup_led(struct phy_device *phydev, u32 reg, int val)594{595	int rc, temp, shift;596 597	switch (reg) {598	case MII_KSZPHY_CTRL_1:599		shift = 14;600		break;601	case MII_KSZPHY_CTRL_2:602		shift = 4;603		break;604	default:605		return -EINVAL;606	}607 608	temp = phy_read(phydev, reg);609	if (temp < 0) {610		rc = temp;611		goto out;612	}613 614	temp &= ~(3 << shift);615	temp |= val << shift;616	rc = phy_write(phydev, reg, temp);617out:618	if (rc < 0)619		phydev_err(phydev, "failed to set led mode\n");620 621	return rc;622}623 624/* Disable PHY address 0 as the broadcast address, so that it can be used as a625 * unique (non-broadcast) address on a shared bus.626 */627static int kszphy_broadcast_disable(struct phy_device *phydev)628{629	int ret;630 631	ret = phy_read(phydev, MII_KSZPHY_OMSO);632	if (ret < 0)633		goto out;634 635	ret = phy_write(phydev, MII_KSZPHY_OMSO, ret | KSZPHY_OMSO_B_CAST_OFF);636out:637	if (ret)638		phydev_err(phydev, "failed to disable broadcast address\n");639 640	return ret;641}642 643static int kszphy_nand_tree_disable(struct phy_device *phydev)644{645	int ret;646 647	ret = phy_read(phydev, MII_KSZPHY_OMSO);648	if (ret < 0)649		goto out;650 651	if (!(ret & KSZPHY_OMSO_NAND_TREE_ON))652		return 0;653 654	ret = phy_write(phydev, MII_KSZPHY_OMSO,655			ret & ~KSZPHY_OMSO_NAND_TREE_ON);656out:657	if (ret)658		phydev_err(phydev, "failed to disable NAND tree mode\n");659 660	return ret;661}662 663/* Some config bits need to be set again on resume, handle them here. */664static int kszphy_config_reset(struct phy_device *phydev)665{666	struct kszphy_priv *priv = phydev->priv;667	int ret;668 669	if (priv->rmii_ref_clk_sel) {670		ret = kszphy_rmii_clk_sel(phydev, priv->rmii_ref_clk_sel_val);671		if (ret) {672			phydev_err(phydev,673				   "failed to set rmii reference clock\n");674			return ret;675		}676	}677 678	if (priv->type && priv->led_mode >= 0)679		kszphy_setup_led(phydev, priv->type->led_mode_reg, priv->led_mode);680 681	return 0;682}683 684static int kszphy_config_init(struct phy_device *phydev)685{686	struct kszphy_priv *priv = phydev->priv;687	const struct kszphy_type *type;688 689	if (!priv)690		return 0;691 692	type = priv->type;693 694	if (type && type->has_broadcast_disable)695		kszphy_broadcast_disable(phydev);696 697	if (type && type->has_nand_tree_disable)698		kszphy_nand_tree_disable(phydev);699 700	return kszphy_config_reset(phydev);701}702 703static int ksz8041_fiber_mode(struct phy_device *phydev)704{705	struct device_node *of_node = phydev->mdio.dev.of_node;706 707	return of_property_read_bool(of_node, "micrel,fiber-mode");708}709 710static int ksz8041_config_init(struct phy_device *phydev)711{712	__ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };713 714	/* Limit supported and advertised modes in fiber mode */715	if (ksz8041_fiber_mode(phydev)) {716		phydev->dev_flags |= MICREL_PHY_FXEN;717		linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, mask);718		linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, mask);719 720		linkmode_and(phydev->supported, phydev->supported, mask);721		linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,722				 phydev->supported);723		linkmode_and(phydev->advertising, phydev->advertising, mask);724		linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,725				 phydev->advertising);726		phydev->autoneg = AUTONEG_DISABLE;727	}728 729	return kszphy_config_init(phydev);730}731 732static int ksz8041_config_aneg(struct phy_device *phydev)733{734	/* Skip auto-negotiation in fiber mode */735	if (phydev->dev_flags & MICREL_PHY_FXEN) {736		phydev->speed = SPEED_100;737		return 0;738	}739 740	return genphy_config_aneg(phydev);741}742 743static int ksz8051_ksz8795_match_phy_device(struct phy_device *phydev,744					    const bool ksz_8051)745{746	int ret;747 748	if (!phy_id_compare(phydev->phy_id, PHY_ID_KSZ8051, MICREL_PHY_ID_MASK))749		return 0;750 751	ret = phy_read(phydev, MII_BMSR);752	if (ret < 0)753		return ret;754 755	/* KSZ8051 PHY and KSZ8794/KSZ8795/KSZ8765 switch share the same756	 * exact PHY ID. However, they can be told apart by the extended757	 * capability registers presence. The KSZ8051 PHY has them while758	 * the switch does not.759	 */760	ret &= BMSR_ERCAP;761	if (ksz_8051)762		return ret;763	else764		return !ret;765}766 767static int ksz8051_match_phy_device(struct phy_device *phydev)768{769	return ksz8051_ksz8795_match_phy_device(phydev, true);770}771 772static int ksz8081_config_init(struct phy_device *phydev)773{774	/* KSZPHY_OMSO_FACTORY_TEST is set at de-assertion of the reset line775	 * based on the RXER (KSZ8081RNA/RND) or TXC (KSZ8081MNX/RNB) pin. If a776	 * pull-down is missing, the factory test mode should be cleared by777	 * manually writing a 0.778	 */779	phy_clear_bits(phydev, MII_KSZPHY_OMSO, KSZPHY_OMSO_FACTORY_TEST);780 781	return kszphy_config_init(phydev);782}783 784static int ksz8081_config_mdix(struct phy_device *phydev, u8 ctrl)785{786	u16 val;787 788	switch (ctrl) {789	case ETH_TP_MDI:790		val = KSZ8081_CTRL2_DISABLE_AUTO_MDIX;791		break;792	case ETH_TP_MDI_X:793		val = KSZ8081_CTRL2_DISABLE_AUTO_MDIX |794			KSZ8081_CTRL2_MDI_MDI_X_SELECT;795		break;796	case ETH_TP_MDI_AUTO:797		val = 0;798		break;799	default:800		return 0;801	}802 803	return phy_modify(phydev, MII_KSZPHY_CTRL_2,804			  KSZ8081_CTRL2_HP_MDIX |805			  KSZ8081_CTRL2_MDI_MDI_X_SELECT |806			  KSZ8081_CTRL2_DISABLE_AUTO_MDIX,807			  KSZ8081_CTRL2_HP_MDIX | val);808}809 810static int ksz8081_config_aneg(struct phy_device *phydev)811{812	int ret;813 814	ret = genphy_config_aneg(phydev);815	if (ret)816		return ret;817 818	/* The MDI-X configuration is automatically changed by the PHY after819	 * switching from autoneg off to on. So, take MDI-X configuration under820	 * own control and set it after autoneg configuration was done.821	 */822	return ksz8081_config_mdix(phydev, phydev->mdix_ctrl);823}824 825static int ksz8081_mdix_update(struct phy_device *phydev)826{827	int ret;828 829	ret = phy_read(phydev, MII_KSZPHY_CTRL_2);830	if (ret < 0)831		return ret;832 833	if (ret & KSZ8081_CTRL2_DISABLE_AUTO_MDIX) {834		if (ret & KSZ8081_CTRL2_MDI_MDI_X_SELECT)835			phydev->mdix_ctrl = ETH_TP_MDI_X;836		else837			phydev->mdix_ctrl = ETH_TP_MDI;838	} else {839		phydev->mdix_ctrl = ETH_TP_MDI_AUTO;840	}841 842	ret = phy_read(phydev, MII_KSZPHY_CTRL_1);843	if (ret < 0)844		return ret;845 846	if (ret & KSZ8081_CTRL1_MDIX_STAT)847		phydev->mdix = ETH_TP_MDI;848	else849		phydev->mdix = ETH_TP_MDI_X;850 851	return 0;852}853 854static int ksz8081_read_status(struct phy_device *phydev)855{856	int ret;857 858	ret = ksz8081_mdix_update(phydev);859	if (ret < 0)860		return ret;861 862	return genphy_read_status(phydev);863}864 865static int ksz8061_config_init(struct phy_device *phydev)866{867	int ret;868 869	/* Chip can be powered down by the bootstrap code. */870	ret = phy_read(phydev, MII_BMCR);871	if (ret < 0)872		return ret;873	if (ret & BMCR_PDOWN) {874		ret = phy_write(phydev, MII_BMCR, ret & ~BMCR_PDOWN);875		if (ret < 0)876			return ret;877		usleep_range(1000, 2000);878	}879 880	ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_DEVID1, 0xB61A);881	if (ret)882		return ret;883 884	return kszphy_config_init(phydev);885}886 887static int ksz8795_match_phy_device(struct phy_device *phydev)888{889	return ksz8051_ksz8795_match_phy_device(phydev, false);890}891 892static int ksz9021_load_values_from_of(struct phy_device *phydev,893				       const struct device_node *of_node,894				       u16 reg,895				       const char *field1, const char *field2,896				       const char *field3, const char *field4)897{898	int val1 = -1;899	int val2 = -2;900	int val3 = -3;901	int val4 = -4;902	int newval;903	int matches = 0;904 905	if (!of_property_read_u32(of_node, field1, &val1))906		matches++;907 908	if (!of_property_read_u32(of_node, field2, &val2))909		matches++;910 911	if (!of_property_read_u32(of_node, field3, &val3))912		matches++;913 914	if (!of_property_read_u32(of_node, field4, &val4))915		matches++;916 917	if (!matches)918		return 0;919 920	if (matches < 4)921		newval = kszphy_extended_read(phydev, reg);922	else923		newval = 0;924 925	if (val1 != -1)926		newval = ((newval & 0xfff0) | ((val1 / PS_TO_REG) & 0xf) << 0);927 928	if (val2 != -2)929		newval = ((newval & 0xff0f) | ((val2 / PS_TO_REG) & 0xf) << 4);930 931	if (val3 != -3)932		newval = ((newval & 0xf0ff) | ((val3 / PS_TO_REG) & 0xf) << 8);933 934	if (val4 != -4)935		newval = ((newval & 0x0fff) | ((val4 / PS_TO_REG) & 0xf) << 12);936 937	return kszphy_extended_write(phydev, reg, newval);938}939 940static int ksz9021_config_init(struct phy_device *phydev)941{942	const struct device_node *of_node;943	const struct device *dev_walker;944 945	/* The Micrel driver has a deprecated option to place phy OF946	 * properties in the MAC node. Walk up the tree of devices to947	 * find a device with an OF node.948	 */949	dev_walker = &phydev->mdio.dev;950	do {951		of_node = dev_walker->of_node;952		dev_walker = dev_walker->parent;953 954	} while (!of_node && dev_walker);955 956	if (of_node) {957		ksz9021_load_values_from_of(phydev, of_node,958				    MII_KSZPHY_CLK_CONTROL_PAD_SKEW,959				    "txen-skew-ps", "txc-skew-ps",960				    "rxdv-skew-ps", "rxc-skew-ps");961		ksz9021_load_values_from_of(phydev, of_node,962				    MII_KSZPHY_RX_DATA_PAD_SKEW,963				    "rxd0-skew-ps", "rxd1-skew-ps",964				    "rxd2-skew-ps", "rxd3-skew-ps");965		ksz9021_load_values_from_of(phydev, of_node,966				    MII_KSZPHY_TX_DATA_PAD_SKEW,967				    "txd0-skew-ps", "txd1-skew-ps",968				    "txd2-skew-ps", "txd3-skew-ps");969	}970	return 0;971}972 973#define KSZ9031_PS_TO_REG		60974 975/* Extended registers */976/* MMD Address 0x0 */977#define MII_KSZ9031RN_FLP_BURST_TX_LO	3978#define MII_KSZ9031RN_FLP_BURST_TX_HI	4979 980/* MMD Address 0x2 */981#define MII_KSZ9031RN_CONTROL_PAD_SKEW	4982#define MII_KSZ9031RN_RX_CTL_M		GENMASK(7, 4)983#define MII_KSZ9031RN_TX_CTL_M		GENMASK(3, 0)984 985#define MII_KSZ9031RN_RX_DATA_PAD_SKEW	5986#define MII_KSZ9031RN_RXD3		GENMASK(15, 12)987#define MII_KSZ9031RN_RXD2		GENMASK(11, 8)988#define MII_KSZ9031RN_RXD1		GENMASK(7, 4)989#define MII_KSZ9031RN_RXD0		GENMASK(3, 0)990 991#define MII_KSZ9031RN_TX_DATA_PAD_SKEW	6992#define MII_KSZ9031RN_TXD3		GENMASK(15, 12)993#define MII_KSZ9031RN_TXD2		GENMASK(11, 8)994#define MII_KSZ9031RN_TXD1		GENMASK(7, 4)995#define MII_KSZ9031RN_TXD0		GENMASK(3, 0)996 997#define MII_KSZ9031RN_CLK_PAD_SKEW	8998#define MII_KSZ9031RN_GTX_CLK		GENMASK(9, 5)999#define MII_KSZ9031RN_RX_CLK		GENMASK(4, 0)1000 1001/* KSZ9031 has internal RGMII_IDRX = 1.2ns and RGMII_IDTX = 0ns. To1002 * provide different RGMII options we need to configure delay offset1003 * for each pad relative to build in delay.1004 */1005/* keep rx as "No delay adjustment" and set rx_clk to +0.60ns to get delays of1006 * 1.80ns1007 */1008#define RX_ID				0x71009#define RX_CLK_ID			0x191010 1011/* set rx to +0.30ns and rx_clk to -0.90ns to compensate the1012 * internal 1.2ns delay.1013 */1014#define RX_ND				0xc1015#define RX_CLK_ND			0x01016 1017/* set tx to -0.42ns and tx_clk to +0.96ns to get 1.38ns delay */1018#define TX_ID				0x01019#define TX_CLK_ID			0x1f1020 1021/* set tx and tx_clk to "No delay adjustment" to keep 0ns1022 * dealy1023 */1024#define TX_ND				0x71025#define TX_CLK_ND			0xf1026 1027/* MMD Address 0x1C */1028#define MII_KSZ9031RN_EDPD		0x231029#define MII_KSZ9031RN_EDPD_ENABLE	BIT(0)1030 1031static int ksz9031_of_load_skew_values(struct phy_device *phydev,1032				       const struct device_node *of_node,1033				       u16 reg, size_t field_sz,1034				       const char *field[], u8 numfields,1035				       bool *update)1036{1037	int val[4] = {-1, -2, -3, -4};1038	int matches = 0;1039	u16 mask;1040	u16 maxval;1041	u16 newval;1042	int i;1043 1044	for (i = 0; i < numfields; i++)1045		if (!of_property_read_u32(of_node, field[i], val + i))1046			matches++;1047 1048	if (!matches)1049		return 0;1050 1051	*update |= true;1052 1053	if (matches < numfields)1054		newval = phy_read_mmd(phydev, 2, reg);1055	else1056		newval = 0;1057 1058	maxval = (field_sz == 4) ? 0xf : 0x1f;1059	for (i = 0; i < numfields; i++)1060		if (val[i] != -(i + 1)) {1061			mask = 0xffff;1062			mask ^= maxval << (field_sz * i);1063			newval = (newval & mask) |1064				(((val[i] / KSZ9031_PS_TO_REG) & maxval)1065					<< (field_sz * i));1066		}1067 1068	return phy_write_mmd(phydev, 2, reg, newval);1069}1070 1071/* Center KSZ9031RNX FLP timing at 16ms. */1072static int ksz9031_center_flp_timing(struct phy_device *phydev)1073{1074	int result;1075 1076	result = phy_write_mmd(phydev, 0, MII_KSZ9031RN_FLP_BURST_TX_HI,1077			       0x0006);1078	if (result)1079		return result;1080 1081	result = phy_write_mmd(phydev, 0, MII_KSZ9031RN_FLP_BURST_TX_LO,1082			       0x1A80);1083	if (result)1084		return result;1085 1086	return genphy_restart_aneg(phydev);1087}1088 1089/* Enable energy-detect power-down mode */1090static int ksz9031_enable_edpd(struct phy_device *phydev)1091{1092	int reg;1093 1094	reg = phy_read_mmd(phydev, 0x1C, MII_KSZ9031RN_EDPD);1095	if (reg < 0)1096		return reg;1097	return phy_write_mmd(phydev, 0x1C, MII_KSZ9031RN_EDPD,1098			     reg | MII_KSZ9031RN_EDPD_ENABLE);1099}1100 1101static int ksz9031_config_rgmii_delay(struct phy_device *phydev)1102{1103	u16 rx, tx, rx_clk, tx_clk;1104	int ret;1105 1106	switch (phydev->interface) {1107	case PHY_INTERFACE_MODE_RGMII:1108		tx = TX_ND;1109		tx_clk = TX_CLK_ND;1110		rx = RX_ND;1111		rx_clk = RX_CLK_ND;1112		break;1113	case PHY_INTERFACE_MODE_RGMII_ID:1114		tx = TX_ID;1115		tx_clk = TX_CLK_ID;1116		rx = RX_ID;1117		rx_clk = RX_CLK_ID;1118		break;1119	case PHY_INTERFACE_MODE_RGMII_RXID:1120		tx = TX_ND;1121		tx_clk = TX_CLK_ND;1122		rx = RX_ID;1123		rx_clk = RX_CLK_ID;1124		break;1125	case PHY_INTERFACE_MODE_RGMII_TXID:1126		tx = TX_ID;1127		tx_clk = TX_CLK_ID;1128		rx = RX_ND;1129		rx_clk = RX_CLK_ND;1130		break;1131	default:1132		return 0;1133	}1134 1135	ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_CONTROL_PAD_SKEW,1136			    FIELD_PREP(MII_KSZ9031RN_RX_CTL_M, rx) |1137			    FIELD_PREP(MII_KSZ9031RN_TX_CTL_M, tx));1138	if (ret < 0)1139		return ret;1140 1141	ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_RX_DATA_PAD_SKEW,1142			    FIELD_PREP(MII_KSZ9031RN_RXD3, rx) |1143			    FIELD_PREP(MII_KSZ9031RN_RXD2, rx) |1144			    FIELD_PREP(MII_KSZ9031RN_RXD1, rx) |1145			    FIELD_PREP(MII_KSZ9031RN_RXD0, rx));1146	if (ret < 0)1147		return ret;1148 1149	ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_TX_DATA_PAD_SKEW,1150			    FIELD_PREP(MII_KSZ9031RN_TXD3, tx) |1151			    FIELD_PREP(MII_KSZ9031RN_TXD2, tx) |1152			    FIELD_PREP(MII_KSZ9031RN_TXD1, tx) |1153			    FIELD_PREP(MII_KSZ9031RN_TXD0, tx));1154	if (ret < 0)1155		return ret;1156 1157	return phy_write_mmd(phydev, 2, MII_KSZ9031RN_CLK_PAD_SKEW,1158			     FIELD_PREP(MII_KSZ9031RN_GTX_CLK, tx_clk) |1159			     FIELD_PREP(MII_KSZ9031RN_RX_CLK, rx_clk));1160}1161 1162static int ksz9031_config_init(struct phy_device *phydev)1163{1164	const struct device_node *of_node;1165	static const char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"};1166	static const char *rx_data_skews[4] = {1167		"rxd0-skew-ps", "rxd1-skew-ps",1168		"rxd2-skew-ps", "rxd3-skew-ps"1169	};1170	static const char *tx_data_skews[4] = {1171		"txd0-skew-ps", "txd1-skew-ps",1172		"txd2-skew-ps", "txd3-skew-ps"1173	};1174	static const char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"};1175	const struct device *dev_walker;1176	int result;1177 1178	result = ksz9031_enable_edpd(phydev);1179	if (result < 0)1180		return result;1181 1182	/* The Micrel driver has a deprecated option to place phy OF1183	 * properties in the MAC node. Walk up the tree of devices to1184	 * find a device with an OF node.1185	 */1186	dev_walker = &phydev->mdio.dev;1187	do {1188		of_node = dev_walker->of_node;1189		dev_walker = dev_walker->parent;1190	} while (!of_node && dev_walker);1191 1192	if (of_node) {1193		bool update = false;1194 1195		if (phy_interface_is_rgmii(phydev)) {1196			result = ksz9031_config_rgmii_delay(phydev);1197			if (result < 0)1198				return result;1199		}1200 1201		ksz9031_of_load_skew_values(phydev, of_node,1202				MII_KSZ9031RN_CLK_PAD_SKEW, 5,1203				clk_skews, 2, &update);1204 1205		ksz9031_of_load_skew_values(phydev, of_node,1206				MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,1207				control_skews, 2, &update);1208 1209		ksz9031_of_load_skew_values(phydev, of_node,1210				MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,1211				rx_data_skews, 4, &update);1212 1213		ksz9031_of_load_skew_values(phydev, of_node,1214				MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,1215				tx_data_skews, 4, &update);1216 1217		if (update && !phy_interface_is_rgmii(phydev))1218			phydev_warn(phydev,1219				    "*-skew-ps values should be used only with RGMII PHY modes\n");1220 1221		/* Silicon Errata Sheet (DS80000691D or DS80000692D):1222		 * When the device links in the 1000BASE-T slave mode only,1223		 * the optional 125MHz reference output clock (CLK125_NDO)1224		 * has wide duty cycle variation.1225		 *1226		 * The optional CLK125_NDO clock does not meet the RGMII1227		 * 45/55 percent (min/max) duty cycle requirement and therefore1228		 * cannot be used directly by the MAC side for clocking1229		 * applications that have setup/hold time requirements on1230		 * rising and falling clock edges.1231		 *1232		 * Workaround:1233		 * Force the phy to be the master to receive a stable clock1234		 * which meets the duty cycle requirement.1235		 */1236		if (of_property_read_bool(of_node, "micrel,force-master")) {1237			result = phy_read(phydev, MII_CTRL1000);1238			if (result < 0)1239				goto err_force_master;1240 1241			/* enable master mode, config & prefer master */1242			result |= CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER;1243			result = phy_write(phydev, MII_CTRL1000, result);1244			if (result < 0)1245				goto err_force_master;1246		}1247	}1248 1249	return ksz9031_center_flp_timing(phydev);1250 1251err_force_master:1252	phydev_err(phydev, "failed to force the phy to master mode\n");1253	return result;1254}1255 1256#define KSZ9131_SKEW_5BIT_MAX	24001257#define KSZ9131_SKEW_4BIT_MAX	8001258#define KSZ9131_OFFSET		7001259#define KSZ9131_STEP		1001260 1261static int ksz9131_of_load_skew_values(struct phy_device *phydev,1262				       struct device_node *of_node,1263				       u16 reg, size_t field_sz,1264				       char *field[], u8 numfields)1265{1266	int val[4] = {-(1 + KSZ9131_OFFSET), -(2 + KSZ9131_OFFSET),1267		      -(3 + KSZ9131_OFFSET), -(4 + KSZ9131_OFFSET)};1268	int skewval, skewmax = 0;1269	int matches = 0;1270	u16 maxval;1271	u16 newval;1272	u16 mask;1273	int i;1274 1275	/* psec properties in dts should mean x pico seconds */1276	if (field_sz == 5)1277		skewmax = KSZ9131_SKEW_5BIT_MAX;1278	else1279		skewmax = KSZ9131_SKEW_4BIT_MAX;1280 1281	for (i = 0; i < numfields; i++)1282		if (!of_property_read_s32(of_node, field[i], &skewval)) {1283			if (skewval < -KSZ9131_OFFSET)1284				skewval = -KSZ9131_OFFSET;1285			else if (skewval > skewmax)1286				skewval = skewmax;1287 1288			val[i] = skewval + KSZ9131_OFFSET;1289			matches++;1290		}1291 1292	if (!matches)1293		return 0;1294 1295	if (matches < numfields)1296		newval = phy_read_mmd(phydev, 2, reg);1297	else1298		newval = 0;1299 1300	maxval = (field_sz == 4) ? 0xf : 0x1f;1301	for (i = 0; i < numfields; i++)1302		if (val[i] != -(i + 1 + KSZ9131_OFFSET)) {1303			mask = 0xffff;1304			mask ^= maxval << (field_sz * i);1305			newval = (newval & mask) |1306				(((val[i] / KSZ9131_STEP) & maxval)1307					<< (field_sz * i));1308		}1309 1310	return phy_write_mmd(phydev, 2, reg, newval);1311}1312 1313#define KSZ9131RN_MMD_COMMON_CTRL_REG	21314#define KSZ9131RN_RXC_DLL_CTRL		761315#define KSZ9131RN_TXC_DLL_CTRL		771316#define KSZ9131RN_DLL_ENABLE_DELAY	01317 1318static int ksz9131_config_rgmii_delay(struct phy_device *phydev)1319{1320	const struct kszphy_type *type = phydev->drv->driver_data;1321	u16 rxcdll_val, txcdll_val;1322	int ret;1323 1324	switch (phydev->interface) {1325	case PHY_INTERFACE_MODE_RGMII:1326		rxcdll_val = type->disable_dll_rx_bit;1327		txcdll_val = type->disable_dll_tx_bit;1328		break;1329	case PHY_INTERFACE_MODE_RGMII_ID:1330		rxcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;1331		txcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;1332		break;1333	case PHY_INTERFACE_MODE_RGMII_RXID:1334		rxcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;1335		txcdll_val = type->disable_dll_tx_bit;1336		break;1337	case PHY_INTERFACE_MODE_RGMII_TXID:1338		rxcdll_val = type->disable_dll_rx_bit;1339		txcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;1340		break;1341	default:1342		return 0;1343	}1344 1345	ret = phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,1346			     KSZ9131RN_RXC_DLL_CTRL, type->disable_dll_mask,1347			     rxcdll_val);1348	if (ret < 0)1349		return ret;1350 1351	return phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,1352			      KSZ9131RN_TXC_DLL_CTRL, type->disable_dll_mask,1353			      txcdll_val);1354}1355 1356/* Silicon Errata DS80000693B1357 *1358 * When LEDs are configured in Individual Mode, LED1 is ON in a no-link1359 * condition. Workaround is to set register 0x1e, bit 9, this way LED1 behaves1360 * according to the datasheet (off if there is no link).1361 */1362static int ksz9131_led_errata(struct phy_device *phydev)1363{1364	int reg;1365 1366	reg = phy_read_mmd(phydev, 2, 0);1367	if (reg < 0)1368		return reg;1369 1370	if (!(reg & BIT(4)))1371		return 0;1372 1373	return phy_set_bits(phydev, 0x1e, BIT(9));1374}1375 1376static int ksz9131_config_init(struct phy_device *phydev)1377{1378	struct device_node *of_node;1379	char *clk_skews[2] = {"rxc-skew-psec", "txc-skew-psec"};1380	char *rx_data_skews[4] = {1381		"rxd0-skew-psec", "rxd1-skew-psec",1382		"rxd2-skew-psec", "rxd3-skew-psec"1383	};1384	char *tx_data_skews[4] = {1385		"txd0-skew-psec", "txd1-skew-psec",1386		"txd2-skew-psec", "txd3-skew-psec"1387	};1388	char *control_skews[2] = {"txen-skew-psec", "rxdv-skew-psec"};1389	const struct device *dev_walker;1390	int ret;1391 1392	phydev->mdix_ctrl = ETH_TP_MDI_AUTO;1393 1394	dev_walker = &phydev->mdio.dev;1395	do {1396		of_node = dev_walker->of_node;1397		dev_walker = dev_walker->parent;1398	} while (!of_node && dev_walker);1399 1400	if (!of_node)1401		return 0;1402 1403	if (phy_interface_is_rgmii(phydev)) {1404		ret = ksz9131_config_rgmii_delay(phydev);1405		if (ret < 0)1406			return ret;1407	}1408 1409	ret = ksz9131_of_load_skew_values(phydev, of_node,1410					  MII_KSZ9031RN_CLK_PAD_SKEW, 5,1411					  clk_skews, 2);1412	if (ret < 0)1413		return ret;1414 1415	ret = ksz9131_of_load_skew_values(phydev, of_node,1416					  MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,1417					  control_skews, 2);1418	if (ret < 0)1419		return ret;1420 1421	ret = ksz9131_of_load_skew_values(phydev, of_node,1422					  MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,1423					  rx_data_skews, 4);1424	if (ret < 0)1425		return ret;1426 1427	ret = ksz9131_of_load_skew_values(phydev, of_node,1428					  MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,1429					  tx_data_skews, 4);1430	if (ret < 0)1431		return ret;1432 1433	ret = ksz9131_led_errata(phydev);1434	if (ret < 0)1435		return ret;1436 1437	return 0;1438}1439 1440#define MII_KSZ9131_AUTO_MDIX		0x1C1441#define MII_KSZ9131_AUTO_MDI_SET	BIT(7)1442#define MII_KSZ9131_AUTO_MDIX_SWAP_OFF	BIT(6)1443#define MII_KSZ9131_DIG_AXAN_STS	0x141444#define MII_KSZ9131_DIG_AXAN_STS_LINK_DET	BIT(14)1445#define MII_KSZ9131_DIG_AXAN_STS_A_SELECT	BIT(12)1446 1447static int ksz9131_mdix_update(struct phy_device *phydev)1448{1449	int ret;1450 1451	if (phydev->mdix_ctrl != ETH_TP_MDI_AUTO) {1452		phydev->mdix = phydev->mdix_ctrl;1453	} else {1454		ret = phy_read(phydev, MII_KSZ9131_DIG_AXAN_STS);1455		if (ret < 0)1456			return ret;1457 1458		if (ret & MII_KSZ9131_DIG_AXAN_STS_LINK_DET) {1459			if (ret & MII_KSZ9131_DIG_AXAN_STS_A_SELECT)1460				phydev->mdix = ETH_TP_MDI;1461			else1462				phydev->mdix = ETH_TP_MDI_X;1463		} else {1464			phydev->mdix = ETH_TP_MDI_INVALID;1465		}1466	}1467 1468	return 0;1469}1470 1471static int ksz9131_config_mdix(struct phy_device *phydev, u8 ctrl)1472{1473	u16 val;1474 1475	switch (ctrl) {1476	case ETH_TP_MDI:1477		val = MII_KSZ9131_AUTO_MDIX_SWAP_OFF |1478		      MII_KSZ9131_AUTO_MDI_SET;1479		break;1480	case ETH_TP_MDI_X:1481		val = MII_KSZ9131_AUTO_MDIX_SWAP_OFF;1482		break;1483	case ETH_TP_MDI_AUTO:1484		val = 0;1485		break;1486	default:1487		return 0;1488	}1489 1490	return phy_modify(phydev, MII_KSZ9131_AUTO_MDIX,1491			  MII_KSZ9131_AUTO_MDIX_SWAP_OFF |1492			  MII_KSZ9131_AUTO_MDI_SET, val);1493}1494 1495static int ksz9131_read_status(struct phy_device *phydev)1496{1497	int ret;1498 1499	ret = ksz9131_mdix_update(phydev);1500	if (ret < 0)1501		return ret;1502 1503	return genphy_read_status(phydev);1504}1505 1506static int ksz9131_config_aneg(struct phy_device *phydev)1507{1508	int ret;1509 1510	ret = ksz9131_config_mdix(phydev, phydev->mdix_ctrl);1511	if (ret)1512		return ret;1513 1514	return genphy_config_aneg(phydev);1515}1516 1517static int ksz9477_get_features(struct phy_device *phydev)1518{1519	int ret;1520 1521	ret = genphy_read_abilities(phydev);1522	if (ret)1523		return ret;1524 1525	/* The "EEE control and capability 1" (Register 3.20) seems to be1526	 * influenced by the "EEE advertisement 1" (Register 7.60). Changes1527	 * on the 7.60 will affect 3.20. So, we need to construct our own list1528	 * of caps.1529	 * KSZ8563R should have 100BaseTX/Full only.1530	 */1531	linkmode_and(phydev->supported_eee, phydev->supported,1532		     PHY_EEE_CAP1_FEATURES);1533 1534	return 0;1535}1536 1537#define KSZ8873MLL_GLOBAL_CONTROL_4	0x061538#define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX	BIT(6)1539#define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED	BIT(4)1540static int ksz8873mll_read_status(struct phy_device *phydev)1541{1542	int regval;1543 1544	/* dummy read */1545	regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);1546 1547	regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);1548 1549	if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX)1550		phydev->duplex = DUPLEX_HALF;1551	else1552		phydev->duplex = DUPLEX_FULL;1553 1554	if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED)1555		phydev->speed = SPEED_10;1556	else1557		phydev->speed = SPEED_100;1558 1559	phydev->link = 1;1560	phydev->pause = phydev->asym_pause = 0;1561 1562	return 0;1563}1564 1565static int ksz9031_get_features(struct phy_device *phydev)1566{1567	int ret;1568 1569	ret = genphy_read_abilities(phydev);1570	if (ret < 0)1571		return ret;1572 1573	/* Silicon Errata Sheet (DS80000691D or DS80000692D):1574	 * Whenever the device's Asymmetric Pause capability is set to 1,1575	 * link-up may fail after a link-up to link-down transition.1576	 *1577	 * The Errata Sheet is for ksz9031, but ksz9021 has the same issue1578	 *1579	 * Workaround:1580	 * Do not enable the Asymmetric Pause capability bit.1581	 */1582	linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, phydev->supported);1583 1584	/* We force setting the Pause capability as the core will force the1585	 * Asymmetric Pause capability to 1 otherwise.1586	 */1587	linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->supported);1588 1589	return 0;1590}1591 1592static int ksz9031_read_status(struct phy_device *phydev)1593{1594	int err;1595	int regval;1596 1597	err = genphy_read_status(phydev);1598	if (err)1599		return err;1600 1601	/* Make sure the PHY is not broken. Read idle error count,1602	 * and reset the PHY if it is maxed out.1603	 */1604	regval = phy_read(phydev, MII_STAT1000);1605	if ((regval & 0xFF) == 0xFF) {1606		phy_init_hw(phydev);1607		phydev->link = 0;1608		if (phydev->drv->config_intr && phy_interrupt_is_valid(phydev))1609			phydev->drv->config_intr(phydev);1610		return genphy_config_aneg(phydev);1611	}1612 1613	return 0;1614}1615 1616static int ksz9x31_cable_test_start(struct phy_device *phydev)1617{1618	struct kszphy_priv *priv = phydev->priv;1619	int ret;1620 1621	/* KSZ9131RNX, DS00002841B-page 38, 4.14 LinkMD (R) Cable Diagnostic1622	 * Prior to running the cable diagnostics, Auto-negotiation should1623	 * be disabled, full duplex set and the link speed set to 1000Mbps1624	 * via the Basic Control Register.1625	 */1626	ret = phy_modify(phydev, MII_BMCR,1627			 BMCR_SPEED1000 | BMCR_FULLDPLX |1628			 BMCR_ANENABLE | BMCR_SPEED100,1629			 BMCR_SPEED1000 | BMCR_FULLDPLX);1630	if (ret)1631		return ret;1632 1633	/* KSZ9131RNX, DS00002841B-page 38, 4.14 LinkMD (R) Cable Diagnostic1634	 * The Master-Slave configuration should be set to Slave by writing1635	 * a value of 0x1000 to the Auto-Negotiation Master Slave Control1636	 * Register.1637	 */1638	ret = phy_read(phydev, MII_CTRL1000);1639	if (ret < 0)1640		return ret;1641 1642	/* Cache these bits, they need to be restored once LinkMD finishes. */1643	priv->vct_ctrl1000 = ret & (CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER);1644	ret &= ~(CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER);1645	ret |= CTL1000_ENABLE_MASTER;1646 1647	return phy_write(phydev, MII_CTRL1000, ret);1648}1649 1650static int ksz9x31_cable_test_result_trans(u16 status)1651{1652	switch (FIELD_GET(KSZ9x31_LMD_VCT_ST_MASK, status)) {1653	case KSZ9x31_LMD_VCT_ST_NORMAL:1654		return ETHTOOL_A_CABLE_RESULT_CODE_OK;1655	case KSZ9x31_LMD_VCT_ST_OPEN:1656		return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;1657	case KSZ9x31_LMD_VCT_ST_SHORT:1658		return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;1659	case KSZ9x31_LMD_VCT_ST_FAIL:1660		fallthrough;1661	default:1662		return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;1663	}1664}1665 1666static bool ksz9x31_cable_test_failed(u16 status)1667{1668	int stat = FIELD_GET(KSZ9x31_LMD_VCT_ST_MASK, status);1669 1670	return stat == KSZ9x31_LMD_VCT_ST_FAIL;1671}1672 1673static bool ksz9x31_cable_test_fault_length_valid(u16 status)1674{1675	switch (FIELD_GET(KSZ9x31_LMD_VCT_ST_MASK, status)) {1676	case KSZ9x31_LMD_VCT_ST_OPEN:1677		fallthrough;1678	case KSZ9x31_LMD_VCT_ST_SHORT:1679		return true;1680	}1681	return false;1682}1683 1684static int ksz9x31_cable_test_fault_length(struct phy_device *phydev, u16 stat)1685{1686	int dt = FIELD_GET(KSZ9x31_LMD_VCT_DATA_MASK, stat);1687 1688	/* KSZ9131RNX, DS00002841B-page 38, 4.14 LinkMD (R) Cable Diagnostic1689	 *1690	 * distance to fault = (VCT_DATA - 22) * 4 / cable propagation velocity1691	 */1692	if (phydev_id_compare(phydev, PHY_ID_KSZ9131))1693		dt = clamp(dt - 22, 0, 255);1694 1695	return (dt * 400) / 10;1696}1697 1698static int ksz9x31_cable_test_wait_for_completion(struct phy_device *phydev)1699{1700	int val, ret;1701 1702	ret = phy_read_poll_timeout(phydev, KSZ9x31_LMD, val,1703				    !(val & KSZ9x31_LMD_VCT_EN),1704				    30000, 100000, true);1705 1706	return ret < 0 ? ret : 0;1707}1708 1709static int ksz9x31_cable_test_get_pair(int pair)1710{1711	static const int ethtool_pair[] = {1712		ETHTOOL_A_CABLE_PAIR_A,1713		ETHTOOL_A_CABLE_PAIR_B,1714		ETHTOOL_A_CABLE_PAIR_C,1715		ETHTOOL_A_CABLE_PAIR_D,1716	};1717 1718	return ethtool_pair[pair];1719}1720 1721static int ksz9x31_cable_test_one_pair(struct phy_device *phydev, int pair)1722{1723	int ret, val;1724 1725	/* KSZ9131RNX, DS00002841B-page 38, 4.14 LinkMD (R) Cable Diagnostic1726	 * To test each individual cable pair, set the cable pair in the Cable1727	 * Diagnostics Test Pair (VCT_PAIR[1:0]) field of the LinkMD Cable1728	 * Diagnostic Register, along with setting the Cable Diagnostics Test1729	 * Enable (VCT_EN) bit. The Cable Diagnostics Test Enable (VCT_EN) bit1730	 * will self clear when the test is concluded.1731	 */1732	ret = phy_write(phydev, KSZ9x31_LMD,1733			KSZ9x31_LMD_VCT_EN | KSZ9x31_LMD_VCT_PAIR(pair));1734	if (ret)1735		return ret;1736 1737	ret = ksz9x31_cable_test_wait_for_completion(phydev);1738	if (ret)1739		return ret;1740 1741	val = phy_read(phydev, KSZ9x31_LMD);1742	if (val < 0)1743		return val;1744 1745	if (ksz9x31_cable_test_failed(val))1746		return -EAGAIN;1747 1748	ret = ethnl_cable_test_result(phydev,1749				      ksz9x31_cable_test_get_pair(pair),1750				      ksz9x31_cable_test_result_trans(val));1751	if (ret)1752		return ret;1753 1754	if (!ksz9x31_cable_test_fault_length_valid(val))1755		return 0;1756 1757	return ethnl_cable_test_fault_length(phydev,1758					     ksz9x31_cable_test_get_pair(pair),1759					     ksz9x31_cable_test_fault_length(phydev, val));1760}1761 1762static int ksz9x31_cable_test_get_status(struct phy_device *phydev,1763					 bool *finished)1764{1765	struct kszphy_priv *priv = phydev->priv;1766	unsigned long pair_mask = 0xf;1767	int retries = 20;1768	int pair, ret, rv;1769 1770	*finished = false;1771 1772	/* Try harder if link partner is active */1773	while (pair_mask && retries--) {1774		for_each_set_bit(pair, &pair_mask, 4) {1775			ret = ksz9x31_cable_test_one_pair(phydev, pair);1776			if (ret == -EAGAIN)1777				continue;1778			if (ret < 0)1779				return ret;1780			clear_bit(pair, &pair_mask);1781		}1782		/* If link partner is in autonegotiation mode it will send 2ms1783		 * of FLPs with at least 6ms of silence.1784		 * Add 2ms sleep to have better chances to hit this silence.1785		 */1786		if (pair_mask)1787			usleep_range(2000, 3000);1788	}1789 1790	/* Report remaining unfinished pair result as unknown. */1791	for_each_set_bit(pair, &pair_mask, 4) {1792		ret = ethnl_cable_test_result(phydev,1793					      ksz9x31_cable_test_get_pair(pair),1794					      ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC);1795	}1796 1797	*finished = true;1798 1799	/* Restore cached bits from before LinkMD got started. */1800	rv = phy_modify(phydev, MII_CTRL1000,1801			CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER,1802			priv->vct_ctrl1000);1803	if (rv)1804		return rv;1805 1806	return ret;1807}1808 1809static int ksz8873mll_config_aneg(struct phy_device *phydev)1810{1811	return 0;1812}1813 1814static int ksz886x_config_mdix(struct phy_device *phydev, u8 ctrl)1815{1816	u16 val;1817 1818	switch (ctrl) {1819	case ETH_TP_MDI:1820		val = KSZ886X_BMCR_DISABLE_AUTO_MDIX;1821		break;1822	case ETH_TP_MDI_X:1823		/* Note: The naming of the bit KSZ886X_BMCR_FORCE_MDI is bit1824		 * counter intuitive, the "-X" in "1 = Force MDI" in the data1825		 * sheet seems to be missing:1826		 * 1 = Force MDI (sic!) (transmit on RX+/RX- pins)1827		 * 0 = Normal operation (transmit on TX+/TX- pins)1828		 */1829		val = KSZ886X_BMCR_DISABLE_AUTO_MDIX | KSZ886X_BMCR_FORCE_MDI;1830		break;1831	case ETH_TP_MDI_AUTO:1832		val = 0;1833		break;1834	default:1835		return 0;1836	}1837 1838	return phy_modify(phydev, MII_BMCR,1839			  KSZ886X_BMCR_HP_MDIX | KSZ886X_BMCR_FORCE_MDI |1840			  KSZ886X_BMCR_DISABLE_AUTO_MDIX,1841			  KSZ886X_BMCR_HP_MDIX | val);1842}1843 1844static int ksz886x_config_aneg(struct phy_device *phydev)1845{1846	int ret;1847 1848	ret = genphy_config_aneg(phydev);1849	if (ret)1850		return ret;1851 1852	if (phydev->autoneg != AUTONEG_ENABLE) {1853		/* When autonegotation is disabled, we need to manually force1854		 * the link state. If we don't do this, the PHY will keep1855		 * sending Fast Link Pulses (FLPs) which are part of the1856		 * autonegotiation process. This is not desired when1857		 * autonegotiation is off.1858		 */1859		ret = phy_set_bits(phydev, MII_KSZPHY_CTRL,1860				   KSZ886X_CTRL_FORCE_LINK);1861		if (ret)1862			return ret;1863	} else {1864		/* If we had previously forced the link state, we need to1865		 * clear KSZ886X_CTRL_FORCE_LINK bit now. Otherwise, the PHY1866		 * will not perform autonegotiation.1867		 */1868		ret = phy_clear_bits(phydev, MII_KSZPHY_CTRL,1869				     KSZ886X_CTRL_FORCE_LINK);1870		if (ret)1871			return ret;1872	}1873 1874	/* The MDI-X configuration is automatically changed by the PHY after1875	 * switching from autoneg off to on. So, take MDI-X configuration under1876	 * own control and set it after autoneg configuration was done.1877	 */1878	return ksz886x_config_mdix(phydev, phydev->mdix_ctrl);1879}1880 1881static int ksz886x_mdix_update(struct phy_device *phydev)1882{1883	int ret;1884 1885	ret = phy_read(phydev, MII_BMCR);1886	if (ret < 0)1887		return ret;1888 1889	if (ret & KSZ886X_BMCR_DISABLE_AUTO_MDIX) {1890		if (ret & KSZ886X_BMCR_FORCE_MDI)1891			phydev->mdix_ctrl = ETH_TP_MDI_X;1892		else1893			phydev->mdix_ctrl = ETH_TP_MDI;1894	} else {1895		phydev->mdix_ctrl = ETH_TP_MDI_AUTO;1896	}1897 1898	ret = phy_read(phydev, MII_KSZPHY_CTRL);1899	if (ret < 0)1900		return ret;1901 1902	/* Same reverse logic as KSZ886X_BMCR_FORCE_MDI */1903	if (ret & KSZ886X_CTRL_MDIX_STAT)1904		phydev->mdix = ETH_TP_MDI_X;1905	else1906		phydev->mdix = ETH_TP_MDI;1907 1908	return 0;1909}1910 1911static int ksz886x_read_status(struct phy_device *phydev)1912{1913	int ret;1914 1915	ret = ksz886x_mdix_update(phydev);1916	if (ret < 0)1917		return ret;1918 1919	return genphy_read_status(phydev);1920}1921 1922struct ksz9477_errata_write {1923	u8 dev_addr;1924	u8 reg_addr;1925	u16 val;1926};1927 1928static const struct ksz9477_errata_write ksz9477_errata_writes[] = {1929	 /* Register settings are needed to improve PHY receive performance */1930	{0x01, 0x6f, 0xdd0b},1931	{0x01, 0x8f, 0x6032},1932	{0x01, 0x9d, 0x248c},1933	{0x01, 0x75, 0x0060},1934	{0x01, 0xd3, 0x7777},1935	{0x1c, 0x06, 0x3008},1936	{0x1c, 0x08, 0x2000},1937 1938	/* Transmit waveform amplitude can be improved (1000BASE-T, 100BASE-TX, 10BASE-Te) */1939	{0x1c, 0x04, 0x00d0},1940 1941	/* Register settings are required to meet data sheet supply current specifications */1942	{0x1c, 0x13, 0x6eff},1943	{0x1c, 0x14, 0xe6ff},1944	{0x1c, 0x15, 0x6eff},1945	{0x1c, 0x16, 0xe6ff},1946	{0x1c, 0x17, 0x00ff},1947	{0x1c, 0x18, 0x43ff},1948	{0x1c, 0x19, 0xc3ff},1949	{0x1c, 0x1a, 0x6fff},1950	{0x1c, 0x1b, 0x07ff},1951	{0x1c, 0x1c, 0x0fff},1952	{0x1c, 0x1d, 0xe7ff},1953	{0x1c, 0x1e, 0xefff},1954	{0x1c, 0x20, 0xeeee},1955};1956 1957static int ksz9477_phy_errata(struct phy_device *phydev)1958{1959	int err;1960	int i;1961 1962	/* Apply PHY settings to address errata listed in1963	 * KSZ9477, KSZ9897, KSZ9896, KSZ9567, KSZ85651964	 * Silicon Errata and Data Sheet Clarification documents.1965	 *1966	 * Document notes: Before configuring the PHY MMD registers, it is1967	 * necessary to set the PHY to 100 Mbps speed with auto-negotiation1968	 * disabled by writing to register 0xN100-0xN101. After writing the1969	 * MMD registers, and after all errata workarounds that involve PHY1970	 * register settings, write register 0xN100-0xN101 again to enable1971	 * and restart auto-negotiation.1972	 */1973	err = phy_write(phydev, MII_BMCR, BMCR_SPEED100 | BMCR_FULLDPLX);1974	if (err)1975		return err;1976 1977	for (i = 0; i < ARRAY_SIZE(ksz9477_errata_writes); ++i) {1978		const struct ksz9477_errata_write *errata = &ksz9477_errata_writes[i];1979 1980		err = phy_write_mmd(phydev, errata->dev_addr, errata->reg_addr, errata->val);1981		if (err)1982			return err;1983	}1984 1985	err = genphy_restart_aneg(phydev);1986	if (err)1987		return err;1988 1989	return err;1990}1991 1992static int ksz9477_config_init(struct phy_device *phydev)1993{1994	int err;1995 1996	/* Only KSZ9897 family of switches needs this fix. */1997	if ((phydev->phy_id & 0xf) == 1) {1998		err = ksz9477_phy_errata(phydev);1999		if (err)2000			return err;2001	}2002 2003	/* According to KSZ9477 Errata DS80000754C (Module 4) all EEE modes2004	 * in this switch shall be regarded as broken.2005	 */2006	if (phydev->dev_flags & MICREL_NO_EEE)2007		phydev->eee_broken_modes = -1;2008 2009	return kszphy_config_init(phydev);2010}2011 2012static int kszphy_get_sset_count(struct phy_device *phydev)2013{2014	return ARRAY_SIZE(kszphy_hw_stats);2015}2016 2017static void kszphy_get_strings(struct phy_device *phydev, u8 *data)2018{2019	int i;2020 2021	for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++) {2022		strscpy(data + i * ETH_GSTRING_LEN,2023			kszphy_hw_stats[i].string, ETH_GSTRING_LEN);2024	}2025}2026 2027static u64 kszphy_get_stat(struct phy_device *phydev, int i)2028{2029	struct kszphy_hw_stat stat = kszphy_hw_stats[i];2030	struct kszphy_priv *priv = phydev->priv;2031	int val;2032	u64 ret;2033 2034	val = phy_read(phydev, stat.reg);2035	if (val < 0) {2036		ret = U64_MAX;2037	} else {2038		val = val & ((1 << stat.bits) - 1);2039		priv->stats[i] += val;2040		ret = priv->stats[i];2041	}2042 2043	return ret;2044}2045 2046static void kszphy_get_stats(struct phy_device *phydev,2047			     struct ethtool_stats *stats, u64 *data)2048{2049	int i;2050 2051	for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++)2052		data[i] = kszphy_get_stat(phydev, i);2053}2054 2055static int kszphy_suspend(struct phy_device *phydev)2056{2057	/* Disable PHY Interrupts */2058	if (phy_interrupt_is_valid(phydev)) {2059		phydev->interrupts = PHY_INTERRUPT_DISABLED;2060		if (phydev->drv->config_intr)2061			phydev->drv->config_intr(phydev);2062	}2063 2064	return genphy_suspend(phydev);2065}2066 2067static void kszphy_parse_led_mode(struct phy_device *phydev)2068{2069	const struct kszphy_type *type = phydev->drv->driver_data;2070	const struct device_node *np = phydev->mdio.dev.of_node;2071	struct kszphy_priv *priv = phydev->priv;2072	int ret;2073 2074	if (type && type->led_mode_reg) {2075		ret = of_property_read_u32(np, "micrel,led-mode",2076					   &priv->led_mode);2077 2078		if (ret)2079			priv->led_mode = -1;2080 2081		if (priv->led_mode > 3) {2082			phydev_err(phydev, "invalid led mode: 0x%02x\n",2083				   priv->led_mode);2084			priv->led_mode = -1;2085		}2086	} else {2087		priv->led_mode = -1;2088	}2089}2090 2091static int kszphy_resume(struct phy_device *phydev)2092{2093	int ret;2094 2095	genphy_resume(phydev);2096 2097	/* After switching from power-down to normal mode, an internal global2098	 * reset is automatically generated. Wait a minimum of 1 ms before2099	 * read/write access to the PHY registers.2100	 */2101	usleep_range(1000, 2000);2102 2103	ret = kszphy_config_reset(phydev);2104	if (ret)2105		return ret;2106 2107	/* Enable PHY Interrupts */2108	if (phy_interrupt_is_valid(phydev)) {2109		phydev->interrupts = PHY_INTERRUPT_ENABLED;2110		if (phydev->drv->config_intr)2111			phydev->drv->config_intr(phydev);2112	}2113 2114	return 0;2115}2116 2117static int ksz9477_resume(struct phy_device *phydev)2118{2119	int ret;2120 2121	/* No need to initialize registers if not powered down. */2122	ret = phy_read(phydev, MII_BMCR);2123	if (ret < 0)2124		return ret;2125	if (!(ret & BMCR_PDOWN))2126		return 0;2127 2128	genphy_resume(phydev);2129 2130	/* After switching from power-down to normal mode, an internal global2131	 * reset is automatically generated. Wait a minimum of 1 ms before2132	 * read/write access to the PHY registers.2133	 */2134	usleep_range(1000, 2000);2135 2136	/* Only KSZ9897 family of switches needs this fix. */2137	if ((phydev->phy_id & 0xf) == 1) {2138		ret = ksz9477_phy_errata(phydev);2139		if (ret)2140			return ret;2141	}2142 2143	/* Enable PHY Interrupts */2144	if (phy_interrupt_is_valid(phydev)) {2145		phydev->interrupts = PHY_INTERRUPT_ENABLED;2146		if (phydev->drv->config_intr)2147			phydev->drv->config_intr(phydev);2148	}2149 2150	return 0;2151}2152 2153static int ksz8061_resume(struct phy_device *phydev)2154{2155	int ret;2156 2157	/* This function can be called twice when the Ethernet device is on. */2158	ret = phy_read(phydev, MII_BMCR);2159	if (ret < 0)2160		return ret;2161	if (!(ret & BMCR_PDOWN))2162		return 0;2163 2164	genphy_resume(phydev);2165	usleep_range(1000, 2000);2166 2167	/* Re-program the value after chip is reset. */2168	ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_DEVID1, 0xB61A);2169	if (ret)2170		return ret;2171 2172	/* Enable PHY Interrupts */2173	if (phy_interrupt_is_valid(phydev)) {2174		phydev->interrupts = PHY_INTERRUPT_ENABLED;2175		if (phydev->drv->config_intr)2176			phydev->drv->config_intr(phydev);2177	}2178 2179	return 0;2180}2181 2182static int kszphy_probe(struct phy_device *phydev)2183{2184	const struct kszphy_type *type = phydev->drv->driver_data;2185	const struct device_node *np = phydev->mdio.dev.of_node;2186	struct kszphy_priv *priv;2187	struct clk *clk;2188 2189	priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);2190	if (!priv)2191		return -ENOMEM;2192 2193	phydev->priv = priv;2194 2195	priv->type = type;2196 2197	kszphy_parse_led_mode(phydev);2198 2199	clk = devm_clk_get_optional_enabled(&phydev->mdio.dev, "rmii-ref");2200	/* NOTE: clk may be NULL if building without CONFIG_HAVE_CLK */2201	if (!IS_ERR_OR_NULL(clk)) {2202		unsigned long rate = clk_get_rate(clk);2203		bool rmii_ref_clk_sel_25_mhz;2204 2205		if (type)2206			priv->rmii_ref_clk_sel = type->has_rmii_ref_clk_sel;2207		rmii_ref_clk_sel_25_mhz = of_property_read_bool(np,2208				"micrel,rmii-reference-clock-select-25-mhz");2209 2210		if (rate > 24500000 && rate < 25500000) {2211			priv->rmii_ref_clk_sel_val = rmii_ref_clk_sel_25_mhz;2212		} else if (rate > 49500000 && rate < 50500000) {2213			priv->rmii_ref_clk_sel_val = !rmii_ref_clk_sel_25_mhz;2214		} else {2215			phydev_err(phydev, "Clock rate out of range: %ld\n",2216				   rate);2217			return -EINVAL;2218		}2219	} else if (!clk) {2220		/* unnamed clock from the generic ethernet-phy binding */2221		clk = devm_clk_get_optional_enabled(&phydev->mdio.dev, NULL);2222		if (IS_ERR(clk))2223			return PTR_ERR(clk);2224	}2225 2226	if (ksz8041_fiber_mode(phydev))2227		phydev->port = PORT_FIBRE;2228 2229	/* Support legacy board-file configuration */2230	if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) {2231		priv->rmii_ref_clk_sel = true;2232		priv->rmii_ref_clk_sel_val = true;2233	}2234 2235	return 0;2236}2237 2238static int lan8814_cable_test_start(struct phy_device *phydev)2239{2240	/* If autoneg is enabled, we won't be able to test cross pair2241	 * short. In this case, the PHY will "detect" a link and2242	 * confuse the internal state machine - disable auto neg here.2243	 * Set the speed to 1000mbit and full duplex.2244	 */2245	return phy_modify(phydev, MII_BMCR, BMCR_ANENABLE | BMCR_SPEED100,2246			  BMCR_SPEED1000 | BMCR_FULLDPLX);2247}2248 2249static int ksz886x_cable_test_start(struct phy_device *phydev)2250{2251	if (phydev->dev_flags & MICREL_KSZ8_P1_ERRATA)2252		return -EOPNOTSUPP;2253 2254	/* If autoneg is enabled, we won't be able to test cross pair2255	 * short. In this case, the PHY will "detect" a link and2256	 * confuse the internal state machine - disable auto neg here.2257	 * If autoneg is disabled, we should set the speed to 10mbit.2258	 */2259	return phy_clear_bits(phydev, MII_BMCR, BMCR_ANENABLE | BMCR_SPEED100);2260}2261 2262static __always_inline int ksz886x_cable_test_result_trans(u16 status, u16 mask)2263{2264	switch (FIELD_GET(mask, status)) {2265	case KSZ8081_LMD_STAT_NORMAL:2266		return ETHTOOL_A_CABLE_RESULT_CODE_OK;2267	case KSZ8081_LMD_STAT_SHORT:2268		return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;2269	case KSZ8081_LMD_STAT_OPEN:2270		return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;2271	case KSZ8081_LMD_STAT_FAIL:2272		fallthrough;2273	default:2274		return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;2275	}2276}2277 2278static __always_inline bool ksz886x_cable_test_failed(u16 status, u16 mask)2279{2280	return FIELD_GET(mask, status) ==2281		KSZ8081_LMD_STAT_FAIL;2282}2283 2284static __always_inline bool ksz886x_cable_test_fault_length_valid(u16 status, u16 mask)2285{2286	switch (FIELD_GET(mask, status)) {2287	case KSZ8081_LMD_STAT_OPEN:2288		fallthrough;2289	case KSZ8081_LMD_STAT_SHORT:2290		return true;2291	}2292	return false;2293}2294 2295static __always_inline int ksz886x_cable_test_fault_length(struct phy_device *phydev,2296							   u16 status, u16 data_mask)2297{2298	int dt;2299 2300	/* According to the data sheet the distance to the fault is2301	 * DELTA_TIME * 0.4 meters for ksz phys.2302	 * (DELTA_TIME - 22) * 0.8 for lan8814 phy.2303	 */2304	dt = FIELD_GET(data_mask, status);2305 2306	if (phydev_id_compare(phydev, PHY_ID_LAN8814))2307		return ((dt - 22) * 800) / 10;2308	else2309		return (dt * 400) / 10;2310}2311 2312static int ksz886x_cable_test_wait_for_completion(struct phy_device *phydev)2313{2314	const struct kszphy_type *type = phydev->drv->driver_data;2315	int val, ret;2316 2317	ret = phy_read_poll_timeout(phydev, type->cable_diag_reg, val,2318				    !(val & KSZ8081_LMD_ENABLE_TEST),2319				    30000, 100000, true);2320 2321	return ret < 0 ? ret : 0;2322}2323 2324static int lan8814_cable_test_one_pair(struct phy_device *phydev, int pair)2325{2326	static const int ethtool_pair[] = { ETHTOOL_A_CABLE_PAIR_A,2327					    ETHTOOL_A_CABLE_PAIR_B,2328					    ETHTOOL_A_CABLE_PAIR_C,2329					    ETHTOOL_A_CABLE_PAIR_D,2330					  };2331	u32 fault_length;2332	int ret;2333	int val;2334 2335	val = KSZ8081_LMD_ENABLE_TEST;2336	val = val | (pair << LAN8814_PAIR_BIT_SHIFT);2337 2338	ret = phy_write(phydev, LAN8814_CABLE_DIAG, val);2339	if (ret < 0)2340		return ret;2341 2342	ret = ksz886x_cable_test_wait_for_completion(phydev);2343	if (ret)2344		return ret;2345 2346	val = phy_read(phydev, LAN8814_CABLE_DIAG);2347	if (val < 0)2348		return val;2349 2350	if (ksz886x_cable_test_failed(val, LAN8814_CABLE_DIAG_STAT_MASK))2351		return -EAGAIN;2352 2353	ret = ethnl_cable_test_result(phydev, ethtool_pair[pair],2354				      ksz886x_cable_test_result_trans(val,2355								      LAN8814_CABLE_DIAG_STAT_MASK2356								      ));2357	if (ret)2358		return ret;2359 2360	if (!ksz886x_cable_test_fault_length_valid(val, LAN8814_CABLE_DIAG_STAT_MASK))2361		return 0;2362 2363	fault_length = ksz886x_cable_test_fault_length(phydev, val,2364						       LAN8814_CABLE_DIAG_VCT_DATA_MASK);2365 2366	return ethnl_cable_test_fault_length(phydev, ethtool_pair[pair], fault_length);2367}2368 2369static int ksz886x_cable_test_one_pair(struct phy_device *phydev, int pair)2370{2371	static const int ethtool_pair[] = {2372		ETHTOOL_A_CABLE_PAIR_A,2373		ETHTOOL_A_CABLE_PAIR_B,2374	};2375	int ret, val, mdix;2376	u32 fault_length;2377 2378	/* There is no way to choice the pair, like we do one ksz9031.2379	 * We can workaround this limitation by using the MDI-X functionality.2380	 */2381	if (pair == 0)2382		mdix = ETH_TP_MDI;2383	else2384		mdix = ETH_TP_MDI_X;2385 2386	switch (phydev->phy_id & MICREL_PHY_ID_MASK) {2387	case PHY_ID_KSZ8081:2388		ret = ksz8081_config_mdix(phydev, mdix);2389		break;2390	case PHY_ID_KSZ886X:2391		ret = ksz886x_config_mdix(phydev, mdix);2392		break;2393	default:2394		ret = -ENODEV;2395	}2396 2397	if (ret)2398		return ret;2399 2400	/* Now we are ready to fire. This command will send a 100ns pulse2401	 * to the pair.2402	 */2403	ret = phy_write(phydev, KSZ8081_LMD, KSZ8081_LMD_ENABLE_TEST);2404	if (ret)2405		return ret;2406 2407	ret = ksz886x_cable_test_wait_for_completion(phydev);2408	if (ret)2409		return ret;2410 2411	val = phy_read(phydev, KSZ8081_LMD);2412	if (val < 0)2413		return val;2414 2415	if (ksz886x_cable_test_failed(val, KSZ8081_LMD_STAT_MASK))2416		return -EAGAIN;2417 2418	ret = ethnl_cable_test_result(phydev, ethtool_pair[pair],2419				      ksz886x_cable_test_result_trans(val, KSZ8081_LMD_STAT_MASK));2420	if (ret)2421		return ret;2422 2423	if (!ksz886x_cable_test_fault_length_valid(val, KSZ8081_LMD_STAT_MASK))2424		return 0;2425 2426	fault_length = ksz886x_cable_test_fault_length(phydev, val, KSZ8081_LMD_DELTA_TIME_MASK);2427 2428	return ethnl_cable_test_fault_length(phydev, ethtool_pair[pair], fault_length);2429}2430 2431static int ksz886x_cable_test_get_status(struct phy_device *phydev,2432					 bool *finished)2433{2434	const struct kszphy_type *type = phydev->drv->driver_data;2435	unsigned long pair_mask = type->pair_mask;2436	int retries = 20;2437	int ret = 0;2438	int pair;2439 2440	*finished = false;2441 2442	/* Try harder if link partner is active */2443	while (pair_mask && retries--) {2444		for_each_set_bit(pair, &pair_mask, 4) {2445			if (type->cable_diag_reg == LAN8814_CABLE_DIAG)2446				ret = lan8814_cable_test_one_pair(phydev, pair);2447			else2448				ret = ksz886x_cable_test_one_pair(phydev, pair);2449			if (ret == -EAGAIN)2450				continue;2451			if (ret < 0)2452				return ret;2453			clear_bit(pair, &pair_mask);2454		}2455		/* If link partner is in autonegotiation mode it will send 2ms2456		 * of FLPs with at least 6ms of silence.2457		 * Add 2ms sleep to have better chances to hit this silence.2458		 */2459		if (pair_mask)2460			msleep(2);2461	}2462 2463	*finished = true;2464 2465	return ret;2466}2467 2468#define LAN_EXT_PAGE_ACCESS_CONTROL			0x162469#define LAN_EXT_PAGE_ACCESS_ADDRESS_DATA		0x172470#define LAN_EXT_PAGE_ACCESS_CTRL_EP_FUNC		0x40002471 2472#define LAN8814_QSGMII_SOFT_RESET			0x432473#define LAN8814_QSGMII_SOFT_RESET_BIT			BIT(0)2474#define LAN8814_QSGMII_PCS1G_ANEG_CONFIG		0x132475#define LAN8814_QSGMII_PCS1G_ANEG_CONFIG_ANEG_ENA	BIT(3)2476#define LAN8814_ALIGN_SWAP				0x4a2477#define LAN8814_ALIGN_TX_A_B_SWAP			0x12478#define LAN8814_ALIGN_TX_A_B_SWAP_MASK			GENMASK(2, 0)2479 2480#define LAN8804_ALIGN_SWAP				0x4a2481#define LAN8804_ALIGN_TX_A_B_SWAP			0x12482#define LAN8804_ALIGN_TX_A_B_SWAP_MASK			GENMASK(2, 0)2483#define LAN8814_CLOCK_MANAGEMENT			0xd2484#define LAN8814_LINK_QUALITY				0x8e2485 2486static int lanphy_read_page_reg(struct phy_device *phydev, int page, u32 addr)2487{2488	int data;2489 2490	phy_lock_mdio_bus(phydev);2491	__phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL, page);2492	__phy_write(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA, addr);2493	__phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL,2494		    (page | LAN_EXT_PAGE_ACCESS_CTRL_EP_FUNC));2495	data = __phy_read(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA);2496	phy_unlock_mdio_bus(phydev);2497 2498	return data;2499}2500 2501static int lanphy_write_page_reg(struct phy_device *phydev, int page, u16 addr,2502				 u16 val)2503{2504	phy_lock_mdio_bus(phydev);2505	__phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL, page);2506	__phy_write(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA, addr);2507	__phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL,2508		    page | LAN_EXT_PAGE_ACCESS_CTRL_EP_FUNC);2509 2510	val = __phy_write(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA, val);2511	if (val != 0)2512		phydev_err(phydev, "Error: phy_write has returned error %d\n",2513			   val);2514	phy_unlock_mdio_bus(phydev);2515	return val;2516}2517 2518static int lan8814_config_ts_intr(struct phy_device *phydev, bool enable)2519{2520	u16 val = 0;2521 2522	if (enable)2523		val = PTP_TSU_INT_EN_PTP_TX_TS_EN_ |2524		      PTP_TSU_INT_EN_PTP_TX_TS_OVRFL_EN_ |2525		      PTP_TSU_INT_EN_PTP_RX_TS_EN_ |2526		      PTP_TSU_INT_EN_PTP_RX_TS_OVRFL_EN_;2527 2528	return lanphy_write_page_reg(phydev, 5, PTP_TSU_INT_EN, val);2529}2530 2531static void lan8814_ptp_rx_ts_get(struct phy_device *phydev,2532				  u32 *seconds, u32 *nano_seconds, u16 *seq_id)2533{2534	*seconds = lanphy_read_page_reg(phydev, 5, PTP_RX_INGRESS_SEC_HI);2535	*seconds = (*seconds << 16) |2536		   lanphy_read_page_reg(phydev, 5, PTP_RX_INGRESS_SEC_LO);2537 2538	*nano_seconds = lanphy_read_page_reg(phydev, 5, PTP_RX_INGRESS_NS_HI);2539	*nano_seconds = ((*nano_seconds & 0x3fff) << 16) |2540			lanphy_read_page_reg(phydev, 5, PTP_RX_INGRESS_NS_LO);2541 2542	*seq_id = lanphy_read_page_reg(phydev, 5, PTP_RX_MSG_HEADER2);2543}2544 2545static void lan8814_ptp_tx_ts_get(struct phy_device *phydev,2546				  u32 *seconds, u32 *nano_seconds, u16 *seq_id)2547{2548	*seconds = lanphy_read_page_reg(phydev, 5, PTP_TX_EGRESS_SEC_HI);2549	*seconds = *seconds << 16 |2550		   lanphy_read_page_reg(phydev, 5, PTP_TX_EGRESS_SEC_LO);2551 2552	*nano_seconds = lanphy_read_page_reg(phydev, 5, PTP_TX_EGRESS_NS_HI);2553	*nano_seconds = ((*nano_seconds & 0x3fff) << 16) |2554			lanphy_read_page_reg(phydev, 5, PTP_TX_EGRESS_NS_LO);2555 2556	*seq_id = lanphy_read_page_reg(phydev, 5, PTP_TX_MSG_HEADER2);2557}2558 2559static int lan8814_ts_info(struct mii_timestamper *mii_ts, struct kernel_ethtool_ts_info *info)2560{2561	struct kszphy_ptp_priv *ptp_priv = container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);2562	struct phy_device *phydev = ptp_priv->phydev;2563	struct lan8814_shared_priv *shared = phydev->shared->priv;2564 2565	info->so_timestamping = SOF_TIMESTAMPING_TX_HARDWARE |2566				SOF_TIMESTAMPING_RX_HARDWARE |2567				SOF_TIMESTAMPING_RAW_HARDWARE;2568 2569	info->phc_index = ptp_clock_index(shared->ptp_clock);2570 2571	info->tx_types =2572		(1 << HWTSTAMP_TX_OFF) |2573		(1 << HWTSTAMP_TX_ON) |2574		(1 << HWTSTAMP_TX_ONESTEP_SYNC);2575 2576	info->rx_filters =2577		(1 << HWTSTAMP_FILTER_NONE) |2578		(1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |2579		(1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |2580		(1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |2581		(1 << HWTSTAMP_FILTER_PTP_V2_EVENT);2582 2583	return 0;2584}2585 2586static void lan8814_flush_fifo(struct phy_device *phydev, bool egress)2587{2588	int i;2589 2590	for (i = 0; i < FIFO_SIZE; ++i)2591		lanphy_read_page_reg(phydev, 5,2592				     egress ? PTP_TX_MSG_HEADER2 : PTP_RX_MSG_HEADER2);2593 2594	/* Read to clear overflow status bit */2595	lanphy_read_page_reg(phydev, 5, PTP_TSU_INT_STS);2596}2597 2598static int lan8814_hwtstamp(struct mii_timestamper *mii_ts,2599			    struct kernel_hwtstamp_config *config,2600			    struct netlink_ext_ack *extack)2601{2602	struct kszphy_ptp_priv *ptp_priv =2603			  container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);2604	struct lan8814_ptp_rx_ts *rx_ts, *tmp;2605	int txcfg = 0, rxcfg = 0;2606	int pkt_ts_enable;2607	int tx_mod;2608 2609	ptp_priv->hwts_tx_type = config->tx_type;2610	ptp_priv->rx_filter = config->rx_filter;2611 2612	switch (config->rx_filter) {2613	case HWTSTAMP_FILTER_NONE:2614		ptp_priv->layer = 0;2615		ptp_priv->version = 0;2616		break;2617	case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:2618	case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:2619	case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:2620		ptp_priv->layer = PTP_CLASS_L4;2621		ptp_priv->version = PTP_CLASS_V2;2622		break;2623	case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:2624	case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:2625	case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:2626		ptp_priv->layer = PTP_CLASS_L2;2627		ptp_priv->version = PTP_CLASS_V2;2628		break;2629	case HWTSTAMP_FILTER_PTP_V2_EVENT:2630	case HWTSTAMP_FILTER_PTP_V2_SYNC:2631	case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:2632		ptp_priv->layer = PTP_CLASS_L4 | PTP_CLASS_L2;2633		ptp_priv->version = PTP_CLASS_V2;2634		break;2635	default:2636		return -ERANGE;2637	}2638 2639	if (ptp_priv->layer & PTP_CLASS_L2) {2640		rxcfg = PTP_RX_PARSE_CONFIG_LAYER2_EN_;2641		txcfg = PTP_TX_PARSE_CONFIG_LAYER2_EN_;2642	} else if (ptp_priv->layer & PTP_CLASS_L4) {2643		rxcfg |= PTP_RX_PARSE_CONFIG_IPV4_EN_ | PTP_RX_PARSE_CONFIG_IPV6_EN_;2644		txcfg |= PTP_TX_PARSE_CONFIG_IPV4_EN_ | PTP_TX_PARSE_CONFIG_IPV6_EN_;2645	}2646	lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_RX_PARSE_CONFIG, rxcfg);2647	lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_TX_PARSE_CONFIG, txcfg);2648 2649	pkt_ts_enable = PTP_TIMESTAMP_EN_SYNC_ | PTP_TIMESTAMP_EN_DREQ_ |2650			PTP_TIMESTAMP_EN_PDREQ_ | PTP_TIMESTAMP_EN_PDRES_;2651	lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_RX_TIMESTAMP_EN, pkt_ts_enable);2652	lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_TX_TIMESTAMP_EN, pkt_ts_enable);2653 2654	tx_mod = lanphy_read_page_reg(ptp_priv->phydev, 5, PTP_TX_MOD);2655	if (ptp_priv->hwts_tx_type == HWTSTAMP_TX_ONESTEP_SYNC) {2656		lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_TX_MOD,2657				      tx_mod | PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_);2658	} else if (ptp_priv->hwts_tx_type == HWTSTAMP_TX_ON) {2659		lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_TX_MOD,2660				      tx_mod & ~PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_);2661	}2662 2663	if (config->rx_filter != HWTSTAMP_FILTER_NONE)2664		lan8814_config_ts_intr(ptp_priv->phydev, true);2665	else2666		lan8814_config_ts_intr(ptp_priv->phydev, false);2667 2668	/* In case of multiple starts and stops, these needs to be cleared */2669	list_for_each_entry_safe(rx_ts, tmp, &ptp_priv->rx_ts_list, list) {2670		list_del(&rx_ts->list);2671		kfree(rx_ts);2672	}2673	skb_queue_purge(&ptp_priv->rx_queue);2674	skb_queue_purge(&ptp_priv->tx_queue);2675 2676	lan8814_flush_fifo(ptp_priv->phydev, false);2677	lan8814_flush_fifo(ptp_priv->phydev, true);2678 2679	return 0;2680}2681 2682static void lan8814_txtstamp(struct mii_timestamper *mii_ts,2683			     struct sk_buff *skb, int type)2684{2685	struct kszphy_ptp_priv *ptp_priv = container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);2686 2687	switch (ptp_priv->hwts_tx_type) {2688	case HWTSTAMP_TX_ONESTEP_SYNC:2689		if (ptp_msg_is_sync(skb, type)) {2690			kfree_skb(skb);2691			return;2692		}2693		fallthrough;2694	case HWTSTAMP_TX_ON:2695		skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;2696		skb_queue_tail(&ptp_priv->tx_queue, skb);2697		break;2698	case HWTSTAMP_TX_OFF:2699	default:2700		kfree_skb(skb);2701		break;2702	}2703}2704 2705static bool lan8814_get_sig_rx(struct sk_buff *skb, u16 *sig)2706{2707	struct ptp_header *ptp_header;2708	u32 type;2709 2710	skb_push(skb, ETH_HLEN);2711	type = ptp_classify_raw(skb);2712	ptp_header = ptp_parse_header(skb, type);2713	skb_pull_inline(skb, ETH_HLEN);2714 2715	if (!ptp_header)2716		return false;2717 2718	*sig = (__force u16)(ntohs(ptp_header->sequence_id));2719	return true;2720}2721 2722static bool lan8814_match_rx_skb(struct kszphy_ptp_priv *ptp_priv,2723				 struct sk_buff *skb)2724{2725	struct skb_shared_hwtstamps *shhwtstamps;2726	struct lan8814_ptp_rx_ts *rx_ts, *tmp;2727	unsigned long flags;2728	bool ret = false;2729	u16 skb_sig;2730 2731	if (!lan8814_get_sig_rx(skb, &skb_sig))2732		return ret;2733 2734	/* Iterate over all RX timestamps and match it with the received skbs */2735	spin_lock_irqsave(&ptp_priv->rx_ts_lock, flags);2736	list_for_each_entry_safe(rx_ts, tmp, &ptp_priv->rx_ts_list, list) {2737		/* Check if we found the signature we were looking for. */2738		if (memcmp(&skb_sig, &rx_ts->seq_id, sizeof(rx_ts->seq_id)))2739			continue;2740 2741		shhwtstamps = skb_hwtstamps(skb);2742		memset(shhwtstamps, 0, sizeof(*shhwtstamps));2743		shhwtstamps->hwtstamp = ktime_set(rx_ts->seconds,2744						  rx_ts->nsec);2745		list_del(&rx_ts->list);2746		kfree(rx_ts);2747 2748		ret = true;2749		break;2750	}2751	spin_unlock_irqrestore(&ptp_priv->rx_ts_lock, flags);2752 2753	if (ret)2754		netif_rx(skb);2755	return ret;2756}2757 2758static bool lan8814_rxtstamp(struct mii_timestamper *mii_ts, struct sk_buff *skb, int type)2759{2760	struct kszphy_ptp_priv *ptp_priv =2761			container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);2762 2763	if (ptp_priv->rx_filter == HWTSTAMP_FILTER_NONE ||2764	    type == PTP_CLASS_NONE)2765		return false;2766 2767	if ((type & ptp_priv->version) == 0 || (type & ptp_priv->layer) == 0)2768		return false;2769 2770	/* If we failed to match then add it to the queue for when the timestamp2771	 * will come2772	 */2773	if (!lan8814_match_rx_skb(ptp_priv, skb))2774		skb_queue_tail(&ptp_priv->rx_queue, skb);2775 2776	return true;2777}2778 2779static void lan8814_ptp_clock_set(struct phy_device *phydev,2780				  time64_t sec, u32 nsec)2781{2782	lanphy_write_page_reg(phydev, 4, PTP_CLOCK_SET_SEC_LO, lower_16_bits(sec));2783	lanphy_write_page_reg(phydev, 4, PTP_CLOCK_SET_SEC_MID, upper_16_bits(sec));2784	lanphy_write_page_reg(phydev, 4, PTP_CLOCK_SET_SEC_HI, upper_32_bits(sec));2785	lanphy_write_page_reg(phydev, 4, PTP_CLOCK_SET_NS_LO, lower_16_bits(nsec));2786	lanphy_write_page_reg(phydev, 4, PTP_CLOCK_SET_NS_HI, upper_16_bits(nsec));2787 2788	lanphy_write_page_reg(phydev, 4, PTP_CMD_CTL, PTP_CMD_CTL_PTP_CLOCK_LOAD_);2789}2790 2791static void lan8814_ptp_clock_get(struct phy_device *phydev,2792				  time64_t *sec, u32 *nsec)2793{2794	lanphy_write_page_reg(phydev, 4, PTP_CMD_CTL, PTP_CMD_CTL_PTP_CLOCK_READ_);2795 2796	*sec = lanphy_read_page_reg(phydev, 4, PTP_CLOCK_READ_SEC_HI);2797	*sec <<= 16;2798	*sec |= lanphy_read_page_reg(phydev, 4, PTP_CLOCK_READ_SEC_MID);2799	*sec <<= 16;2800	*sec |= lanphy_read_page_reg(phydev, 4, PTP_CLOCK_READ_SEC_LO);2801 2802	*nsec = lanphy_read_page_reg(phydev, 4, PTP_CLOCK_READ_NS_HI);2803	*nsec <<= 16;2804	*nsec |= lanphy_read_page_reg(phydev, 4, PTP_CLOCK_READ_NS_LO);2805}2806 2807static int lan8814_ptpci_gettime64(struct ptp_clock_info *ptpci,2808				   struct timespec64 *ts)2809{2810	struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv,2811							  ptp_clock_info);2812	struct phy_device *phydev = shared->phydev;2813	u32 nano_seconds;2814	time64_t seconds;2815 2816	mutex_lock(&shared->shared_lock);2817	lan8814_ptp_clock_get(phydev, &seconds, &nano_seconds);2818	mutex_unlock(&shared->shared_lock);2819	ts->tv_sec = seconds;2820	ts->tv_nsec = nano_seconds;2821 2822	return 0;2823}2824 2825static int lan8814_ptpci_settime64(struct ptp_clock_info *ptpci,2826				   const struct timespec64 *ts)2827{2828	struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv,2829							  ptp_clock_info);2830	struct phy_device *phydev = shared->phydev;2831 2832	mutex_lock(&shared->shared_lock);2833	lan8814_ptp_clock_set(phydev, ts->tv_sec, ts->tv_nsec);2834	mutex_unlock(&shared->shared_lock);2835 2836	return 0;2837}2838 2839static void lan8814_ptp_set_target(struct phy_device *phydev, int event,2840				   s64 start_sec, u32 start_nsec)2841{2842	/* Set the start time */2843	lanphy_write_page_reg(phydev, 4, LAN8814_PTP_CLOCK_TARGET_SEC_LO(event),2844			      lower_16_bits(start_sec));2845	lanphy_write_page_reg(phydev, 4, LAN8814_PTP_CLOCK_TARGET_SEC_HI(event),2846			      upper_16_bits(start_sec));2847 2848	lanphy_write_page_reg(phydev, 4, LAN8814_PTP_CLOCK_TARGET_NS_LO(event),2849			      lower_16_bits(start_nsec));2850	lanphy_write_page_reg(phydev, 4, LAN8814_PTP_CLOCK_TARGET_NS_HI(event),2851			      upper_16_bits(start_nsec) & 0x3fff);2852}2853 2854static void lan8814_ptp_update_target(struct phy_device *phydev, time64_t sec)2855{2856	lan8814_ptp_set_target(phydev, LAN8814_EVENT_A,2857			       sec + LAN8814_BUFFER_TIME, 0);2858	lan8814_ptp_set_target(phydev, LAN8814_EVENT_B,2859			       sec + LAN8814_BUFFER_TIME, 0);2860}2861 2862static void lan8814_ptp_clock_step(struct phy_device *phydev,2863				   s64 time_step_ns)2864{2865	u32 nano_seconds_step;2866	u64 abs_time_step_ns;2867	time64_t set_seconds;2868	u32 nano_seconds;2869	u32 remainder;2870	s32 seconds;2871 2872	if (time_step_ns >  15000000000LL) {2873		/* convert to clock set */2874		lan8814_ptp_clock_get(phydev, &set_seconds, &nano_seconds);2875		set_seconds += div_u64_rem(time_step_ns, 1000000000LL,2876					   &remainder);2877		nano_seconds += remainder;2878		if (nano_seconds >= 1000000000) {2879			set_seconds++;2880			nano_seconds -= 1000000000;2881		}2882		lan8814_ptp_clock_set(phydev, set_seconds, nano_seconds);2883		lan8814_ptp_update_target(phydev, set_seconds);2884		return;2885	} else if (time_step_ns < -15000000000LL) {2886		/* convert to clock set */2887		time_step_ns = -time_step_ns;2888 2889		lan8814_ptp_clock_get(phydev, &set_seconds, &nano_seconds);2890		set_seconds -= div_u64_rem(time_step_ns, 1000000000LL,2891					   &remainder);2892		nano_seconds_step = remainder;2893		if (nano_seconds < nano_seconds_step) {2894			set_seconds--;2895			nano_seconds += 1000000000;2896		}2897		nano_seconds -= nano_seconds_step;2898		lan8814_ptp_clock_set(phydev, set_seconds, nano_seconds);2899		lan8814_ptp_update_target(phydev, set_seconds);2900		return;2901	}2902 2903	/* do clock step */2904	if (time_step_ns >= 0) {2905		abs_time_step_ns = (u64)time_step_ns;2906		seconds = (s32)div_u64_rem(abs_time_step_ns, 1000000000,2907					   &remainder);2908		nano_seconds = remainder;2909	} else {2910		abs_time_step_ns = (u64)(-time_step_ns);2911		seconds = -((s32)div_u64_rem(abs_time_step_ns, 1000000000,2912			    &remainder));2913		nano_seconds = remainder;2914		if (nano_seconds > 0) {2915			/* subtracting nano seconds is not allowed2916			 * convert to subtracting from seconds,2917			 * and adding to nanoseconds2918			 */2919			seconds--;2920			nano_seconds = (1000000000 - nano_seconds);2921		}2922	}2923 2924	if (nano_seconds > 0) {2925		/* add 8 ns to cover the likely normal increment */2926		nano_seconds += 8;2927	}2928 2929	if (nano_seconds >= 1000000000) {2930		/* carry into seconds */2931		seconds++;2932		nano_seconds -= 1000000000;2933	}2934 2935	while (seconds) {2936		u32 nsec;2937 2938		if (seconds > 0) {2939			u32 adjustment_value = (u32)seconds;2940			u16 adjustment_value_lo, adjustment_value_hi;2941 2942			if (adjustment_value > 0xF)2943				adjustment_value = 0xF;2944 2945			adjustment_value_lo = adjustment_value & 0xffff;2946			adjustment_value_hi = (adjustment_value >> 16) & 0x3fff;2947 2948			lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_LO,2949					      adjustment_value_lo);2950			lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_HI,2951					      PTP_LTC_STEP_ADJ_DIR_ |2952					      adjustment_value_hi);2953			seconds -= ((s32)adjustment_value);2954 2955			lan8814_ptp_clock_get(phydev, &set_seconds, &nsec);2956			set_seconds -= adjustment_value;2957			lan8814_ptp_update_target(phydev, set_seconds);2958		} else {2959			u32 adjustment_value = (u32)(-seconds);2960			u16 adjustment_value_lo, adjustment_value_hi;2961 2962			if (adjustment_value > 0xF)2963				adjustment_value = 0xF;2964 2965			adjustment_value_lo = adjustment_value & 0xffff;2966			adjustment_value_hi = (adjustment_value >> 16) & 0x3fff;2967 2968			lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_LO,2969					      adjustment_value_lo);2970			lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_HI,2971					      adjustment_value_hi);2972			seconds += ((s32)adjustment_value);2973 2974			lan8814_ptp_clock_get(phydev, &set_seconds, &nsec);2975			set_seconds += adjustment_value;2976			lan8814_ptp_update_target(phydev, set_seconds);2977		}2978		lanphy_write_page_reg(phydev, 4, PTP_CMD_CTL,2979				      PTP_CMD_CTL_PTP_LTC_STEP_SEC_);2980	}2981	if (nano_seconds) {2982		u16 nano_seconds_lo;2983		u16 nano_seconds_hi;2984 2985		nano_seconds_lo = nano_seconds & 0xffff;2986		nano_seconds_hi = (nano_seconds >> 16) & 0x3fff;2987 2988		lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_LO,2989				      nano_seconds_lo);2990		lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_HI,2991				      PTP_LTC_STEP_ADJ_DIR_ |2992				      nano_seconds_hi);2993		lanphy_write_page_reg(phydev, 4, PTP_CMD_CTL,2994				      PTP_CMD_CTL_PTP_LTC_STEP_NSEC_);2995	}2996}2997 2998static int lan8814_ptpci_adjtime(struct ptp_clock_info *ptpci, s64 delta)2999{3000	struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv,3001							  ptp_clock_info);3002	struct phy_device *phydev = shared->phydev;3003 3004	mutex_lock(&shared->shared_lock);3005	lan8814_ptp_clock_step(phydev, delta);3006	mutex_unlock(&shared->shared_lock);3007 3008	return 0;3009}3010 3011static int lan8814_ptpci_adjfine(struct ptp_clock_info *ptpci, long scaled_ppm)3012{3013	struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv,3014							  ptp_clock_info);3015	struct phy_device *phydev = shared->phydev;3016	u16 kszphy_rate_adj_lo, kszphy_rate_adj_hi;3017	bool positive = true;3018	u32 kszphy_rate_adj;3019 3020	if (scaled_ppm < 0) {3021		scaled_ppm = -scaled_ppm;3022		positive = false;3023	}3024 3025	kszphy_rate_adj = LAN8814_1PPM_FORMAT * (scaled_ppm >> 16);3026	kszphy_rate_adj += (LAN8814_1PPM_FORMAT * (0xffff & scaled_ppm)) >> 16;3027 3028	kszphy_rate_adj_lo = kszphy_rate_adj & 0xffff;3029	kszphy_rate_adj_hi = (kszphy_rate_adj >> 16) & 0x3fff;3030 3031	if (positive)3032		kszphy_rate_adj_hi |= PTP_CLOCK_RATE_ADJ_DIR_;3033 3034	mutex_lock(&shared->shared_lock);3035	lanphy_write_page_reg(phydev, 4, PTP_CLOCK_RATE_ADJ_HI, kszphy_rate_adj_hi);3036	lanphy_write_page_reg(phydev, 4, PTP_CLOCK_RATE_ADJ_LO, kszphy_rate_adj_lo);3037	mutex_unlock(&shared->shared_lock);3038 3039	return 0;3040}3041 3042static void lan8814_ptp_set_reload(struct phy_device *phydev, int event,3043				   s64 period_sec, u32 period_nsec)3044{3045	lanphy_write_page_reg(phydev, 4,3046			      LAN8814_PTP_CLOCK_TARGET_RELOAD_SEC_LO(event),3047			      lower_16_bits(period_sec));3048	lanphy_write_page_reg(phydev, 4,3049			      LAN8814_PTP_CLOCK_TARGET_RELOAD_SEC_HI(event),3050			      upper_16_bits(period_sec));3051 3052	lanphy_write_page_reg(phydev, 4,3053			      LAN8814_PTP_CLOCK_TARGET_RELOAD_NS_LO(event),3054			      lower_16_bits(period_nsec));3055	lanphy_write_page_reg(phydev, 4,3056			      LAN8814_PTP_CLOCK_TARGET_RELOAD_NS_HI(event),3057			      upper_16_bits(period_nsec) & 0x3fff);3058}3059 3060static void lan8814_ptp_enable_event(struct phy_device *phydev, int event,3061				     int pulse_width)3062{3063	u16 val;3064 3065	val = lanphy_read_page_reg(phydev, 4, LAN8814_PTP_GENERAL_CONFIG);3066	/* Set the pulse width of the event */3067	val &= ~(LAN8814_PTP_GENERAL_CONFIG_LTC_EVENT_MASK(event));3068	/* Make sure that the target clock will be incremented each time when3069	 * local time reaches or pass it3070	 */3071	val |= LAN8814_PTP_GENERAL_CONFIG_LTC_EVENT_SET(event, pulse_width);3072	val &= ~(LAN8814_PTP_GENERAL_CONFIG_RELOAD_ADD_X(event));3073	/* Set the polarity high */3074	val |= LAN8814_PTP_GENERAL_CONFIG_POLARITY_X(event);3075	lanphy_write_page_reg(phydev, 4, LAN8814_PTP_GENERAL_CONFIG, val);3076}3077 3078static void lan8814_ptp_disable_event(struct phy_device *phydev, int event)3079{3080	u16 val;3081 3082	/* Set target to too far in the future, effectively disabling it */3083	lan8814_ptp_set_target(phydev, event, 0xFFFFFFFF, 0);3084 3085	/* And then reload once it recheas the target */3086	val = lanphy_read_page_reg(phydev, 4, LAN8814_PTP_GENERAL_CONFIG);3087	val |= LAN8814_PTP_GENERAL_CONFIG_RELOAD_ADD_X(event);3088	lanphy_write_page_reg(phydev, 4, LAN8814_PTP_GENERAL_CONFIG, val);3089}3090 3091static void lan8814_ptp_perout_off(struct phy_device *phydev, int pin)3092{3093	u16 val;3094 3095	/* Disable gpio alternate function,3096	 * 1: select as gpio,3097	 * 0: select alt func3098	 */3099	val = lanphy_read_page_reg(phydev, 4, LAN8814_GPIO_EN_ADDR(pin));3100	val |= LAN8814_GPIO_EN_BIT(pin);3101	lanphy_write_page_reg(phydev, 4, LAN8814_GPIO_EN_ADDR(pin), val);3102 3103	val = lanphy_read_page_reg(phydev, 4, LAN8814_GPIO_DIR_ADDR(pin));3104	val &= ~LAN8814_GPIO_DIR_BIT(pin);3105	lanphy_write_page_reg(phydev, 4, LAN8814_GPIO_DIR_ADDR(pin), val);3106 3107	val = lanphy_read_page_reg(phydev, 4, LAN8814_GPIO_BUF_ADDR(pin));3108	val &= ~LAN8814_GPIO_BUF_BIT(pin);3109	lanphy_write_page_reg(phydev, 4, LAN8814_GPIO_BUF_ADDR(pin), val);3110}3111 3112static void lan8814_ptp_perout_on(struct phy_device *phydev, int pin)3113{3114	int val;3115 3116	/* Set as gpio output */3117	val = lanphy_read_page_reg(phydev, 4, LAN8814_GPIO_DIR_ADDR(pin));3118	val |= LAN8814_GPIO_DIR_BIT(pin);3119	lanphy_write_page_reg(phydev, 4, LAN8814_GPIO_DIR_ADDR(pin), val);3120 3121	/* Enable gpio 0:for alternate function, 1:gpio */3122	val = lanphy_read_page_reg(phydev, 4, LAN8814_GPIO_EN_ADDR(pin));3123	val &= ~LAN8814_GPIO_EN_BIT(pin);3124	lanphy_write_page_reg(phydev, 4, LAN8814_GPIO_EN_ADDR(pin), val);3125 3126	/* Set buffer type to push pull */3127	val = lanphy_read_page_reg(phydev, 4, LAN8814_GPIO_BUF_ADDR(pin));3128	val |= LAN8814_GPIO_BUF_BIT(pin);3129	lanphy_write_page_reg(phydev, 4, LAN8814_GPIO_BUF_ADDR(pin), val);3130}3131 3132static int lan8814_ptp_perout(struct ptp_clock_info *ptpci,3133			      struct ptp_clock_request *rq, int on)3134{3135	struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv,3136							  ptp_clock_info);3137	struct phy_device *phydev = shared->phydev;3138	struct timespec64 ts_on, ts_period;3139	s64 on_nsec, period_nsec;3140	int pulse_width;3141	int pin, event;3142 3143	/* Reject requests with unsupported flags */3144	if (rq->perout.flags & ~PTP_PEROUT_DUTY_CYCLE)3145		return -EOPNOTSUPP;3146 3147	mutex_lock(&shared->shared_lock);3148	event = rq->perout.index;3149	pin = ptp_find_pin(shared->ptp_clock, PTP_PF_PEROUT, event);3150	if (pin < 0 || pin >= LAN8814_PTP_PEROUT_NUM) {3151		mutex_unlock(&shared->shared_lock);3152		return -EBUSY;3153	}3154 3155	if (!on) {3156		lan8814_ptp_perout_off(phydev, pin);3157		lan8814_ptp_disable_event(phydev, event);3158		mutex_unlock(&shared->shared_lock);3159		return 0;3160	}3161 3162	ts_on.tv_sec = rq->perout.on.sec;3163	ts_on.tv_nsec = rq->perout.on.nsec;3164	on_nsec = timespec64_to_ns(&ts_on);3165 3166	ts_period.tv_sec = rq->perout.period.sec;3167	ts_period.tv_nsec = rq->perout.period.nsec;3168	period_nsec = timespec64_to_ns(&ts_period);3169 3170	if (period_nsec < 200) {3171		pr_warn_ratelimited("%s: perout period too small, minimum is 200 nsec\n",3172				    phydev_name(phydev));3173		mutex_unlock(&shared->shared_lock);3174		return -EOPNOTSUPP;3175	}3176 3177	if (on_nsec >= period_nsec) {3178		pr_warn_ratelimited("%s: pulse width must be smaller than period\n",3179				    phydev_name(phydev));3180		mutex_unlock(&shared->shared_lock);3181		return -EINVAL;3182	}3183 3184	switch (on_nsec) {3185	case 200000000:3186		pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_200MS;3187		break;3188	case 100000000:3189		pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100MS;3190		break;3191	case 50000000:3192		pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_50MS;3193		break;3194	case 10000000:3195		pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_10MS;3196		break;3197	case 5000000:3198		pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_5MS;3199		break;3200	case 1000000:3201		pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_1MS;3202		break;3203	case 500000:3204		pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_500US;3205		break;3206	case 100000:3207		pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100US;3208		break;3209	case 50000:3210		pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_50US;3211		break;3212	case 10000:3213		pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_10US;3214		break;3215	case 5000:3216		pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_5US;3217		break;3218	case 1000:3219		pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_1US;3220		break;3221	case 500:3222		pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_500NS;3223		break;3224	case 100:3225		pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100NS;3226		break;3227	default:3228		pr_warn_ratelimited("%s: Use default duty cycle of 100ns\n",3229				    phydev_name(phydev));3230		pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100NS;3231		break;3232	}3233 3234	/* Configure to pulse every period */3235	lan8814_ptp_enable_event(phydev, event, pulse_width);3236	lan8814_ptp_set_target(phydev, event, rq->perout.start.sec,3237			       rq->perout.start.nsec);3238	lan8814_ptp_set_reload(phydev, event, rq->perout.period.sec,3239			       rq->perout.period.nsec);3240	lan8814_ptp_perout_on(phydev, pin);3241	mutex_unlock(&shared->shared_lock);3242 3243	return 0;3244}3245 3246static void lan8814_ptp_extts_on(struct phy_device *phydev, int pin, u32 flags)3247{3248	u16 tmp;3249 3250	/* Set as gpio input */3251	tmp = lanphy_read_page_reg(phydev, 4, LAN8814_GPIO_DIR_ADDR(pin));3252	tmp &= ~LAN8814_GPIO_DIR_BIT(pin);3253	lanphy_write_page_reg(phydev, 4, LAN8814_GPIO_DIR_ADDR(pin), tmp);3254 3255	/* Map the pin to ltc pin 0 of the capture map registers */3256	tmp = lanphy_read_page_reg(phydev, 4, PTP_GPIO_CAP_MAP_LO);3257	tmp |= pin;3258	lanphy_write_page_reg(phydev, 4, PTP_GPIO_CAP_MAP_LO, tmp);3259 3260	/* Enable capture on the edges of the ltc pin */3261	tmp = lanphy_read_page_reg(phydev, 4, PTP_GPIO_CAP_EN);3262	if (flags & PTP_RISING_EDGE)3263		tmp |= PTP_GPIO_CAP_EN_GPIO_RE_CAPTURE_ENABLE(0);3264	if (flags & PTP_FALLING_EDGE)3265		tmp |= PTP_GPIO_CAP_EN_GPIO_FE_CAPTURE_ENABLE(0);3266	lanphy_write_page_reg(phydev, 4, PTP_GPIO_CAP_EN, tmp);3267 3268	/* Enable interrupt top interrupt */3269	tmp = lanphy_read_page_reg(phydev, 4, PTP_COMMON_INT_ENA);3270	tmp |= PTP_COMMON_INT_ENA_GPIO_CAP_EN;3271	lanphy_write_page_reg(phydev, 4, PTP_COMMON_INT_ENA, tmp);3272}3273 3274static void lan8814_ptp_extts_off(struct phy_device *phydev, int pin)3275{3276	u16 tmp;3277 3278	/* Set as gpio out */3279	tmp = lanphy_read_page_reg(phydev, 4, LAN8814_GPIO_DIR_ADDR(pin));3280	tmp |= LAN8814_GPIO_DIR_BIT(pin);3281	lanphy_write_page_reg(phydev, 4, LAN8814_GPIO_DIR_ADDR(pin), tmp);3282 3283	/* Enable alternate, 0:for alternate function, 1:gpio */3284	tmp = lanphy_read_page_reg(phydev, 4, LAN8814_GPIO_EN_ADDR(pin));3285	tmp &= ~LAN8814_GPIO_EN_BIT(pin);3286	lanphy_write_page_reg(phydev, 4, LAN8814_GPIO_EN_ADDR(pin), tmp);3287 3288	/* Clear the mapping of pin to registers 0 of the capture registers */3289	tmp = lanphy_read_page_reg(phydev, 4, PTP_GPIO_CAP_MAP_LO);3290	tmp &= ~GENMASK(3, 0);3291	lanphy_write_page_reg(phydev, 4, PTP_GPIO_CAP_MAP_LO, tmp);3292 3293	/* Disable capture on both of the edges */3294	tmp = lanphy_read_page_reg(phydev, 4, PTP_GPIO_CAP_EN);3295	tmp &= ~PTP_GPIO_CAP_EN_GPIO_RE_CAPTURE_ENABLE(pin);3296	tmp &= ~PTP_GPIO_CAP_EN_GPIO_FE_CAPTURE_ENABLE(pin);3297	lanphy_write_page_reg(phydev, 4, PTP_GPIO_CAP_EN, tmp);3298 3299	/* Disable interrupt top interrupt */3300	tmp = lanphy_read_page_reg(phydev, 4, PTP_COMMON_INT_ENA);3301	tmp &= ~PTP_COMMON_INT_ENA_GPIO_CAP_EN;3302	lanphy_write_page_reg(phydev, 4, PTP_COMMON_INT_ENA, tmp);3303}3304 3305static int lan8814_ptp_extts(struct ptp_clock_info *ptpci,3306			     struct ptp_clock_request *rq, int on)3307{3308	struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv,3309							  ptp_clock_info);3310	struct phy_device *phydev = shared->phydev;3311	int pin;3312 3313	if (rq->extts.flags & ~(PTP_ENABLE_FEATURE |3314				PTP_EXTTS_EDGES |3315				PTP_STRICT_FLAGS))3316		return -EOPNOTSUPP;3317 3318	pin = ptp_find_pin(shared->ptp_clock, PTP_PF_EXTTS,3319			   rq->extts.index);3320	if (pin == -1 || pin != LAN8814_PTP_EXTTS_NUM)3321		return -EINVAL;3322 3323	mutex_lock(&shared->shared_lock);3324	if (on)3325		lan8814_ptp_extts_on(phydev, pin, rq->extts.flags);3326	else3327		lan8814_ptp_extts_off(phydev, pin);3328 3329	mutex_unlock(&shared->shared_lock);3330 3331	return 0;3332}3333 3334static int lan8814_ptpci_enable(struct ptp_clock_info *ptpci,3335				struct ptp_clock_request *rq, int on)3336{3337	switch (rq->type) {3338	case PTP_CLK_REQ_PEROUT:3339		return lan8814_ptp_perout(ptpci, rq, on);3340	case PTP_CLK_REQ_EXTTS:3341		return lan8814_ptp_extts(ptpci, rq, on);3342	default:3343		return -EINVAL;3344	}3345}3346 3347static int lan8814_ptpci_verify(struct ptp_clock_info *ptp, unsigned int pin,3348				enum ptp_pin_function func, unsigned int chan)3349{3350	switch (func) {3351	case PTP_PF_NONE:3352	case PTP_PF_PEROUT:3353		/* Only pins 0 and 1 can generate perout signals. And for pin 03354		 * there is only chan 0 (event A) and for pin 1 there is only3355		 * chan 1 (event B)3356		 */3357		if (pin >= LAN8814_PTP_PEROUT_NUM || pin != chan)3358			return -1;3359		break;3360	case PTP_PF_EXTTS:3361		if (pin != LAN8814_PTP_EXTTS_NUM)3362			return -1;3363		break;3364	default:3365		return -1;3366	}3367 3368	return 0;3369}3370 3371static bool lan8814_get_sig_tx(struct sk_buff *skb, u16 *sig)3372{3373	struct ptp_header *ptp_header;3374	u32 type;3375 3376	type = ptp_classify_raw(skb);3377	ptp_header = ptp_parse_header(skb, type);3378 3379	if (!ptp_header)3380		return false;3381 3382	*sig = (__force u16)(ntohs(ptp_header->sequence_id));3383	return true;3384}3385 3386static void lan8814_match_tx_skb(struct kszphy_ptp_priv *ptp_priv,3387				 u32 seconds, u32 nsec, u16 seq_id)3388{3389	struct skb_shared_hwtstamps shhwtstamps;3390	struct sk_buff *skb, *skb_tmp;3391	unsigned long flags;3392	bool ret = false;3393	u16 skb_sig;3394 3395	spin_lock_irqsave(&ptp_priv->tx_queue.lock, flags);3396	skb_queue_walk_safe(&ptp_priv->tx_queue, skb, skb_tmp) {3397		if (!lan8814_get_sig_tx(skb, &skb_sig))3398			continue;3399 3400		if (memcmp(&skb_sig, &seq_id, sizeof(seq_id)))3401			continue;3402 3403		__skb_unlink(skb, &ptp_priv->tx_queue);3404		ret = true;3405		break;3406	}3407	spin_unlock_irqrestore(&ptp_priv->tx_queue.lock, flags);3408 3409	if (ret) {3410		memset(&shhwtstamps, 0, sizeof(shhwtstamps));3411		shhwtstamps.hwtstamp = ktime_set(seconds, nsec);3412		skb_complete_tx_timestamp(skb, &shhwtstamps);3413	}3414}3415 3416static void lan8814_dequeue_tx_skb(struct kszphy_ptp_priv *ptp_priv)3417{3418	struct phy_device *phydev = ptp_priv->phydev;3419	u32 seconds, nsec;3420	u16 seq_id;3421 3422	lan8814_ptp_tx_ts_get(phydev, &seconds, &nsec, &seq_id);3423	lan8814_match_tx_skb(ptp_priv, seconds, nsec, seq_id);3424}3425 3426static void lan8814_get_tx_ts(struct kszphy_ptp_priv *ptp_priv)3427{3428	struct phy_device *phydev = ptp_priv->phydev;3429	u32 reg;3430 3431	do {3432		lan8814_dequeue_tx_skb(ptp_priv);3433 3434		/* If other timestamps are available in the FIFO,3435		 * process them.3436		 */3437		reg = lanphy_read_page_reg(phydev, 5, PTP_CAP_INFO);3438	} while (PTP_CAP_INFO_TX_TS_CNT_GET_(reg) > 0);3439}3440 3441static bool lan8814_match_skb(struct kszphy_ptp_priv *ptp_priv,3442			      struct lan8814_ptp_rx_ts *rx_ts)3443{3444	struct skb_shared_hwtstamps *shhwtstamps;3445	struct sk_buff *skb, *skb_tmp;3446	unsigned long flags;3447	bool ret = false;3448	u16 skb_sig;3449 3450	spin_lock_irqsave(&ptp_priv->rx_queue.lock, flags);3451	skb_queue_walk_safe(&ptp_priv->rx_queue, skb, skb_tmp) {3452		if (!lan8814_get_sig_rx(skb, &skb_sig))3453			continue;3454 3455		if (memcmp(&skb_sig, &rx_ts->seq_id, sizeof(rx_ts->seq_id)))3456			continue;3457 3458		__skb_unlink(skb, &ptp_priv->rx_queue);3459 3460		ret = true;3461		break;3462	}3463	spin_unlock_irqrestore(&ptp_priv->rx_queue.lock, flags);3464 3465	if (ret) {3466		shhwtstamps = skb_hwtstamps(skb);3467		memset(shhwtstamps, 0, sizeof(*shhwtstamps));3468		shhwtstamps->hwtstamp = ktime_set(rx_ts->seconds, rx_ts->nsec);3469		netif_rx(skb);3470	}3471 3472	return ret;3473}3474 3475static void lan8814_match_rx_ts(struct kszphy_ptp_priv *ptp_priv,3476				struct lan8814_ptp_rx_ts *rx_ts)3477{3478	unsigned long flags;3479 3480	/* If we failed to match the skb add it to the queue for when3481	 * the frame will come3482	 */3483	if (!lan8814_match_skb(ptp_priv, rx_ts)) {3484		spin_lock_irqsave(&ptp_priv->rx_ts_lock, flags);3485		list_add(&rx_ts->list, &ptp_priv->rx_ts_list);3486		spin_unlock_irqrestore(&ptp_priv->rx_ts_lock, flags);3487	} else {3488		kfree(rx_ts);3489	}3490}3491 3492static void lan8814_get_rx_ts(struct kszphy_ptp_priv *ptp_priv)3493{3494	struct phy_device *phydev = ptp_priv->phydev;3495	struct lan8814_ptp_rx_ts *rx_ts;3496	u32 reg;3497 3498	do {3499		rx_ts = kzalloc(sizeof(*rx_ts), GFP_KERNEL);3500		if (!rx_ts)3501			return;3502 3503		lan8814_ptp_rx_ts_get(phydev, &rx_ts->seconds, &rx_ts->nsec,3504				      &rx_ts->seq_id);3505		lan8814_match_rx_ts(ptp_priv, rx_ts);3506 3507		/* If other timestamps are available in the FIFO,3508		 * process them.3509		 */3510		reg = lanphy_read_page_reg(phydev, 5, PTP_CAP_INFO);3511	} while (PTP_CAP_INFO_RX_TS_CNT_GET_(reg) > 0);3512}3513 3514static void lan8814_handle_ptp_interrupt(struct phy_device *phydev, u16 status)3515{3516	struct kszphy_priv *priv = phydev->priv;3517	struct kszphy_ptp_priv *ptp_priv = &priv->ptp_priv;3518 3519	if (status & PTP_TSU_INT_STS_PTP_TX_TS_EN_)3520		lan8814_get_tx_ts(ptp_priv);3521 3522	if (status & PTP_TSU_INT_STS_PTP_RX_TS_EN_)3523		lan8814_get_rx_ts(ptp_priv);3524 3525	if (status & PTP_TSU_INT_STS_PTP_TX_TS_OVRFL_INT_) {3526		lan8814_flush_fifo(phydev, true);3527		skb_queue_purge(&ptp_priv->tx_queue);3528	}3529 3530	if (status & PTP_TSU_INT_STS_PTP_RX_TS_OVRFL_INT_) {3531		lan8814_flush_fifo(phydev, false);3532		skb_queue_purge(&ptp_priv->rx_queue);3533	}3534}3535 3536static int lan8814_gpio_process_cap(struct lan8814_shared_priv *shared)3537{3538	struct phy_device *phydev = shared->phydev;3539	struct ptp_clock_event ptp_event = {0};3540	unsigned long nsec;3541	s64 sec;3542	u16 tmp;3543 3544	/* This is 0 because whatever was the input pin it was mapped it to3545	 * ltc gpio pin 03546	 */3547	tmp = lanphy_read_page_reg(phydev, 4, PTP_GPIO_SEL);3548	tmp |= PTP_GPIO_SEL_GPIO_SEL(0);3549	lanphy_write_page_reg(phydev, 4, PTP_GPIO_SEL, tmp);3550 3551	tmp = lanphy_read_page_reg(phydev, 4, PTP_GPIO_CAP_STS);3552	if (!(tmp & PTP_GPIO_CAP_STS_PTP_GPIO_RE_STS(0)) &&3553	    !(tmp & PTP_GPIO_CAP_STS_PTP_GPIO_FE_STS(0)))3554		return -1;3555 3556	if (tmp & BIT(0)) {3557		sec = lanphy_read_page_reg(phydev, 4, PTP_GPIO_RE_LTC_SEC_HI_CAP);3558		sec <<= 16;3559		sec |= lanphy_read_page_reg(phydev, 4, PTP_GPIO_RE_LTC_SEC_LO_CAP);3560 3561		nsec = lanphy_read_page_reg(phydev, 4, PTP_GPIO_RE_LTC_NS_HI_CAP) & 0x3fff;3562		nsec <<= 16;3563		nsec |= lanphy_read_page_reg(phydev, 4, PTP_GPIO_RE_LTC_NS_LO_CAP);3564	} else {3565		sec = lanphy_read_page_reg(phydev, 4, PTP_GPIO_FE_LTC_SEC_HI_CAP);3566		sec <<= 16;3567		sec |= lanphy_read_page_reg(phydev, 4, PTP_GPIO_FE_LTC_SEC_LO_CAP);3568 3569		nsec = lanphy_read_page_reg(phydev, 4, PTP_GPIO_FE_LTC_NS_HI_CAP) & 0x3fff;3570		nsec <<= 16;3571		nsec |= lanphy_read_page_reg(phydev, 4, PTP_GPIO_RE_LTC_NS_LO_CAP);3572	}3573 3574	ptp_event.index = 0;3575	ptp_event.timestamp = ktime_set(sec, nsec);3576	ptp_event.type = PTP_CLOCK_EXTTS;3577	ptp_clock_event(shared->ptp_clock, &ptp_event);3578 3579	return 0;3580}3581 3582static int lan8814_handle_gpio_interrupt(struct phy_device *phydev, u16 status)3583{3584	struct lan8814_shared_priv *shared = phydev->shared->priv;3585	int ret;3586 3587	mutex_lock(&shared->shared_lock);3588	ret = lan8814_gpio_process_cap(shared);3589	mutex_unlock(&shared->shared_lock);3590 3591	return ret;3592}3593 3594static int lan8804_config_init(struct phy_device *phydev)3595{3596	int val;3597 3598	/* MDI-X setting for swap A,B transmit */3599	val = lanphy_read_page_reg(phydev, 2, LAN8804_ALIGN_SWAP);3600	val &= ~LAN8804_ALIGN_TX_A_B_SWAP_MASK;3601	val |= LAN8804_ALIGN_TX_A_B_SWAP;3602	lanphy_write_page_reg(phydev, 2, LAN8804_ALIGN_SWAP, val);3603 3604	/* Make sure that the PHY will not stop generating the clock when the3605	 * link partner goes down3606	 */3607	lanphy_write_page_reg(phydev, 31, LAN8814_CLOCK_MANAGEMENT, 0x27e);3608	lanphy_read_page_reg(phydev, 1, LAN8814_LINK_QUALITY);3609 3610	return 0;3611}3612 3613static irqreturn_t lan8804_handle_interrupt(struct phy_device *phydev)3614{3615	int status;3616 3617	status = phy_read(phydev, LAN8814_INTS);3618	if (status < 0) {3619		phy_error(phydev);3620		return IRQ_NONE;3621	}3622 3623	if (status > 0)3624		phy_trigger_machine(phydev);3625 3626	return IRQ_HANDLED;3627}3628 3629#define LAN8804_OUTPUT_CONTROL			253630#define LAN8804_OUTPUT_CONTROL_INTR_BUFFER	BIT(14)3631#define LAN8804_CONTROL				313632#define LAN8804_CONTROL_INTR_POLARITY		BIT(14)3633 3634static int lan8804_config_intr(struct phy_device *phydev)3635{3636	int err;3637 3638	/* This is an internal PHY of lan966x and is not possible to change the3639	 * polarity on the GIC found in lan966x, therefore change the polarity3640	 * of the interrupt in the PHY from being active low instead of active3641	 * high.3642	 */3643	phy_write(phydev, LAN8804_CONTROL, LAN8804_CONTROL_INTR_POLARITY);3644 3645	/* By default interrupt buffer is open-drain in which case the interrupt3646	 * can be active only low. Therefore change the interrupt buffer to be3647	 * push-pull to be able to change interrupt polarity3648	 */3649	phy_write(phydev, LAN8804_OUTPUT_CONTROL,3650		  LAN8804_OUTPUT_CONTROL_INTR_BUFFER);3651 3652	if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {3653		err = phy_read(phydev, LAN8814_INTS);3654		if (err < 0)3655			return err;3656 3657		err = phy_write(phydev, LAN8814_INTC, LAN8814_INT_LINK);3658		if (err)3659			return err;3660	} else {3661		err = phy_write(phydev, LAN8814_INTC, 0);3662		if (err)3663			return err;3664 3665		err = phy_read(phydev, LAN8814_INTS);3666		if (err < 0)3667			return err;3668	}3669 3670	return 0;3671}3672 3673static irqreturn_t lan8814_handle_interrupt(struct phy_device *phydev)3674{3675	int ret = IRQ_NONE;3676	int irq_status;3677 3678	irq_status = phy_read(phydev, LAN8814_INTS);3679	if (irq_status < 0) {3680		phy_error(phydev);3681		return IRQ_NONE;3682	}3683 3684	if (irq_status & LAN8814_INT_LINK) {3685		phy_trigger_machine(phydev);3686		ret = IRQ_HANDLED;3687	}3688 3689	while (true) {3690		irq_status = lanphy_read_page_reg(phydev, 5, PTP_TSU_INT_STS);3691		if (!irq_status)3692			break;3693 3694		lan8814_handle_ptp_interrupt(phydev, irq_status);3695		ret = IRQ_HANDLED;3696	}3697 3698	if (!lan8814_handle_gpio_interrupt(phydev, irq_status))3699		ret = IRQ_HANDLED;3700 3701	return ret;3702}3703 3704static int lan8814_ack_interrupt(struct phy_device *phydev)3705{3706	/* bit[12..0] int status, which is a read and clear register. */3707	int rc;3708 3709	rc = phy_read(phydev, LAN8814_INTS);3710 3711	return (rc < 0) ? rc : 0;3712}3713 3714static int lan8814_config_intr(struct phy_device *phydev)3715{3716	int err;3717 3718	lanphy_write_page_reg(phydev, 4, LAN8814_INTR_CTRL_REG,3719			      LAN8814_INTR_CTRL_REG_POLARITY |3720			      LAN8814_INTR_CTRL_REG_INTR_ENABLE);3721 3722	/* enable / disable interrupts */3723	if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {3724		err = lan8814_ack_interrupt(phydev);3725		if (err)3726			return err;3727 3728		err = phy_write(phydev, LAN8814_INTC, LAN8814_INT_LINK);3729	} else {3730		err = phy_write(phydev, LAN8814_INTC, 0);3731		if (err)3732			return err;3733 3734		err = lan8814_ack_interrupt(phydev);3735	}3736 3737	return err;3738}3739 3740static void lan8814_ptp_init(struct phy_device *phydev)3741{3742	struct kszphy_priv *priv = phydev->priv;3743	struct kszphy_ptp_priv *ptp_priv = &priv->ptp_priv;3744	u32 temp;3745 3746	if (!IS_ENABLED(CONFIG_PTP_1588_CLOCK) ||3747	    !IS_ENABLED(CONFIG_NETWORK_PHY_TIMESTAMPING))3748		return;3749 3750	lanphy_write_page_reg(phydev, 5, TSU_HARD_RESET, TSU_HARD_RESET_);3751 3752	temp = lanphy_read_page_reg(phydev, 5, PTP_TX_MOD);3753	temp |= PTP_TX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_;3754	lanphy_write_page_reg(phydev, 5, PTP_TX_MOD, temp);3755 3756	temp = lanphy_read_page_reg(phydev, 5, PTP_RX_MOD);3757	temp |= PTP_RX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_;3758	lanphy_write_page_reg(phydev, 5, PTP_RX_MOD, temp);3759 3760	lanphy_write_page_reg(phydev, 5, PTP_RX_PARSE_CONFIG, 0);3761	lanphy_write_page_reg(phydev, 5, PTP_TX_PARSE_CONFIG, 0);3762 3763	/* Removing default registers configs related to L2 and IP */3764	lanphy_write_page_reg(phydev, 5, PTP_TX_PARSE_L2_ADDR_EN, 0);3765	lanphy_write_page_reg(phydev, 5, PTP_RX_PARSE_L2_ADDR_EN, 0);3766	lanphy_write_page_reg(phydev, 5, PTP_TX_PARSE_IP_ADDR_EN, 0);3767	lanphy_write_page_reg(phydev, 5, PTP_RX_PARSE_IP_ADDR_EN, 0);3768 3769	/* Disable checking for minorVersionPTP field */3770	lanphy_write_page_reg(phydev, 5, PTP_RX_VERSION,3771			      PTP_MAX_VERSION(0xff) | PTP_MIN_VERSION(0x0));3772	lanphy_write_page_reg(phydev, 5, PTP_TX_VERSION,3773			      PTP_MAX_VERSION(0xff) | PTP_MIN_VERSION(0x0));3774 3775	skb_queue_head_init(&ptp_priv->tx_queue);3776	skb_queue_head_init(&ptp_priv->rx_queue);3777	INIT_LIST_HEAD(&ptp_priv->rx_ts_list);3778	spin_lock_init(&ptp_priv->rx_ts_lock);3779 3780	ptp_priv->phydev = phydev;3781 3782	ptp_priv->mii_ts.rxtstamp = lan8814_rxtstamp;3783	ptp_priv->mii_ts.txtstamp = lan8814_txtstamp;3784	ptp_priv->mii_ts.hwtstamp = lan8814_hwtstamp;3785	ptp_priv->mii_ts.ts_info  = lan8814_ts_info;3786 3787	phydev->mii_ts = &ptp_priv->mii_ts;3788 3789	/* Timestamp selected by default to keep legacy API */3790	phydev->default_timestamp = true;3791}3792 3793static int lan8814_ptp_probe_once(struct phy_device *phydev)3794{3795	struct lan8814_shared_priv *shared = phydev->shared->priv;3796 3797	/* Initialise shared lock for clock*/3798	mutex_init(&shared->shared_lock);3799 3800	shared->pin_config = devm_kmalloc_array(&phydev->mdio.dev,3801						LAN8814_PTP_GPIO_NUM,3802						sizeof(*shared->pin_config),3803						GFP_KERNEL);3804	if (!shared->pin_config)3805		return -ENOMEM;3806 3807	for (int i = 0; i < LAN8814_PTP_GPIO_NUM; i++) {3808		struct ptp_pin_desc *ptp_pin = &shared->pin_config[i];3809 3810		memset(ptp_pin, 0, sizeof(*ptp_pin));3811		snprintf(ptp_pin->name,3812			 sizeof(ptp_pin->name), "lan8814_ptp_pin_%02d", i);3813		ptp_pin->index = i;3814		ptp_pin->func =  PTP_PF_NONE;3815	}3816 3817	shared->ptp_clock_info.owner = THIS_MODULE;3818	snprintf(shared->ptp_clock_info.name, 30, "%s", phydev->drv->name);3819	shared->ptp_clock_info.max_adj = 31249999;3820	shared->ptp_clock_info.n_alarm = 0;3821	shared->ptp_clock_info.n_ext_ts = LAN8814_PTP_EXTTS_NUM;3822	shared->ptp_clock_info.n_pins = LAN8814_PTP_GPIO_NUM;3823	shared->ptp_clock_info.pps = 0;3824	shared->ptp_clock_info.pin_config = shared->pin_config;3825	shared->ptp_clock_info.n_per_out = LAN8814_PTP_PEROUT_NUM;3826	shared->ptp_clock_info.adjfine = lan8814_ptpci_adjfine;3827	shared->ptp_clock_info.adjtime = lan8814_ptpci_adjtime;3828	shared->ptp_clock_info.gettime64 = lan8814_ptpci_gettime64;3829	shared->ptp_clock_info.settime64 = lan8814_ptpci_settime64;3830	shared->ptp_clock_info.getcrosststamp = NULL;3831	shared->ptp_clock_info.enable = lan8814_ptpci_enable;3832	shared->ptp_clock_info.verify = lan8814_ptpci_verify;3833 3834	shared->ptp_clock = ptp_clock_register(&shared->ptp_clock_info,3835					       &phydev->mdio.dev);3836	if (IS_ERR(shared->ptp_clock)) {3837		phydev_err(phydev, "ptp_clock_register failed %lu\n",3838			   PTR_ERR(shared->ptp_clock));3839		return -EINVAL;3840	}3841 3842	/* Check if PHC support is missing at the configuration level */3843	if (!shared->ptp_clock)3844		return 0;3845 3846	phydev_dbg(phydev, "successfully registered ptp clock\n");3847 3848	shared->phydev = phydev;3849 3850	/* The EP.4 is shared between all the PHYs in the package and also it3851	 * can be accessed by any of the PHYs3852	 */3853	lanphy_write_page_reg(phydev, 4, LTC_HARD_RESET, LTC_HARD_RESET_);3854	lanphy_write_page_reg(phydev, 4, PTP_OPERATING_MODE,3855			      PTP_OPERATING_MODE_STANDALONE_);3856 3857	/* Enable ptp to run LTC clock for ptp and gpio 1PPS operation */3858	lanphy_write_page_reg(phydev, 4, PTP_CMD_CTL, PTP_CMD_CTL_PTP_ENABLE_);3859 3860	return 0;3861}3862 3863static void lan8814_setup_led(struct phy_device *phydev, int val)3864{3865	int temp;3866 3867	temp = lanphy_read_page_reg(phydev, 5, LAN8814_LED_CTRL_1);3868 3869	if (val)3870		temp |= LAN8814_LED_CTRL_1_KSZ9031_LED_MODE_;3871	else3872		temp &= ~LAN8814_LED_CTRL_1_KSZ9031_LED_MODE_;3873 3874	lanphy_write_page_reg(phydev, 5, LAN8814_LED_CTRL_1, temp);3875}3876 3877static int lan8814_config_init(struct phy_device *phydev)3878{3879	struct kszphy_priv *lan8814 = phydev->priv;3880	int val;3881 3882	/* Reset the PHY */3883	val = lanphy_read_page_reg(phydev, 4, LAN8814_QSGMII_SOFT_RESET);3884	val |= LAN8814_QSGMII_SOFT_RESET_BIT;3885	lanphy_write_page_reg(phydev, 4, LAN8814_QSGMII_SOFT_RESET, val);3886 3887	/* Disable ANEG with QSGMII PCS Host side */3888	val = lanphy_read_page_reg(phydev, 5, LAN8814_QSGMII_PCS1G_ANEG_CONFIG);3889	val &= ~LAN8814_QSGMII_PCS1G_ANEG_CONFIG_ANEG_ENA;3890	lanphy_write_page_reg(phydev, 5, LAN8814_QSGMII_PCS1G_ANEG_CONFIG, val);3891 3892	/* MDI-X setting for swap A,B transmit */3893	val = lanphy_read_page_reg(phydev, 2, LAN8814_ALIGN_SWAP);3894	val &= ~LAN8814_ALIGN_TX_A_B_SWAP_MASK;3895	val |= LAN8814_ALIGN_TX_A_B_SWAP;3896	lanphy_write_page_reg(phydev, 2, LAN8814_ALIGN_SWAP, val);3897 3898	if (lan8814->led_mode >= 0)3899		lan8814_setup_led(phydev, lan8814->led_mode);3900 3901	return 0;3902}3903 3904/* It is expected that there will not be any 'lan8814_take_coma_mode'3905 * function called in suspend. Because the GPIO line can be shared, so if one of3906 * the phys goes back in coma mode, then all the other PHYs will go, which is3907 * wrong.3908 */3909static int lan8814_release_coma_mode(struct phy_device *phydev)3910{3911	struct gpio_desc *gpiod;3912 3913	gpiod = devm_gpiod_get_optional(&phydev->mdio.dev, "coma-mode",3914					GPIOD_OUT_HIGH_OPEN_DRAIN |3915					GPIOD_FLAGS_BIT_NONEXCLUSIVE);3916	if (IS_ERR(gpiod))3917		return PTR_ERR(gpiod);3918 3919	gpiod_set_consumer_name(gpiod, "LAN8814 coma mode");3920	gpiod_set_value_cansleep(gpiod, 0);3921 3922	return 0;3923}3924 3925static void lan8814_clear_2psp_bit(struct phy_device *phydev)3926{3927	u16 val;3928 3929	/* It was noticed that when traffic is passing through the PHY and the3930	 * cable is removed then the LED was still one even though there is no3931	 * link3932	 */3933	val = lanphy_read_page_reg(phydev, 2, LAN8814_EEE_STATE);3934	val &= ~LAN8814_EEE_STATE_MASK2P5P;3935	lanphy_write_page_reg(phydev, 2, LAN8814_EEE_STATE, val);3936}3937 3938static void lan8814_update_meas_time(struct phy_device *phydev)3939{3940	u16 val;3941 3942	/* By setting the measure time to a value of 0xb this will allow cables3943	 * longer than 100m to be used. This configuration can be used3944	 * regardless of the mode of operation of the PHY3945	 */3946	val = lanphy_read_page_reg(phydev, 1, LAN8814_PD_CONTROLS);3947	val &= ~LAN8814_PD_CONTROLS_PD_MEAS_TIME_MASK;3948	val |= LAN8814_PD_CONTROLS_PD_MEAS_TIME_VAL;3949	lanphy_write_page_reg(phydev, 1, LAN8814_PD_CONTROLS, val);3950}3951 3952static int lan8814_probe(struct phy_device *phydev)3953{3954	const struct kszphy_type *type = phydev->drv->driver_data;3955	struct kszphy_priv *priv;3956	u16 addr;3957	int err;3958 3959	priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);3960	if (!priv)3961		return -ENOMEM;3962 3963	phydev->priv = priv;3964 3965	priv->type = type;3966 3967	kszphy_parse_led_mode(phydev);3968 3969	/* Strap-in value for PHY address, below register read gives starting3970	 * phy address value3971	 */3972	addr = lanphy_read_page_reg(phydev, 4, 0) & 0x1F;3973	devm_phy_package_join(&phydev->mdio.dev, phydev,3974			      addr, sizeof(struct lan8814_shared_priv));3975 3976	if (phy_package_init_once(phydev)) {3977		err = lan8814_release_coma_mode(phydev);3978		if (err)3979			return err;3980 3981		err = lan8814_ptp_probe_once(phydev);3982		if (err)3983			return err;3984	}3985 3986	lan8814_ptp_init(phydev);3987 3988	/* Errata workarounds */3989	lan8814_clear_2psp_bit(phydev);3990	lan8814_update_meas_time(phydev);3991 3992	return 0;3993}3994 3995#define LAN8841_MMD_TIMER_REG			03996#define LAN8841_MMD0_REGISTER_17		173997#define LAN8841_MMD0_REGISTER_17_DROP_OPT(x)	((x) & 0x3)3998#define LAN8841_MMD0_REGISTER_17_XMIT_TOG_TX_DIS	BIT(3)3999#define LAN8841_OPERATION_MODE_STRAP_OVERRIDE_LOW_REG	24000#define LAN8841_OPERATION_MODE_STRAP_OVERRIDE_LOW_REG_MAGJACK	BIT(14)4001#define LAN8841_MMD_ANALOG_REG			284002#define LAN8841_ANALOG_CONTROL_1		14003#define LAN8841_ANALOG_CONTROL_1_PLL_TRIM(x)	(((x) & 0x3) << 5)4004#define LAN8841_ANALOG_CONTROL_10		134005#define LAN8841_ANALOG_CONTROL_10_PLL_DIV(x)	((x) & 0x3)4006#define LAN8841_ANALOG_CONTROL_11		144007#define LAN8841_ANALOG_CONTROL_11_LDO_REF(x)	(((x) & 0x7) << 12)4008#define LAN8841_TX_LOW_I_CH_C_D_POWER_MANAGMENT	694009#define LAN8841_TX_LOW_I_CH_C_D_POWER_MANAGMENT_VAL 0xbffc4010#define LAN8841_BTRX_POWER_DOWN			704011#define LAN8841_BTRX_POWER_DOWN_QBIAS_CH_A	BIT(0)4012#define LAN8841_BTRX_POWER_DOWN_BTRX_CH_A	BIT(1)4013#define LAN8841_BTRX_POWER_DOWN_QBIAS_CH_B	BIT(2)4014#define LAN8841_BTRX_POWER_DOWN_BTRX_CH_B	BIT(3)4015#define LAN8841_BTRX_POWER_DOWN_BTRX_CH_C	BIT(5)4016#define LAN8841_BTRX_POWER_DOWN_BTRX_CH_D	BIT(7)4017#define LAN8841_ADC_CHANNEL_MASK		1984018#define LAN8841_PTP_RX_PARSE_L2_ADDR_EN		3704019#define LAN8841_PTP_RX_PARSE_IP_ADDR_EN		3714020#define LAN8841_PTP_RX_VERSION			3744021#define LAN8841_PTP_TX_PARSE_L2_ADDR_EN		4344022#define LAN8841_PTP_TX_PARSE_IP_ADDR_EN		4354023#define LAN8841_PTP_TX_VERSION			4384024#define LAN8841_PTP_CMD_CTL			2564025#define LAN8841_PTP_CMD_CTL_PTP_ENABLE		BIT(2)4026#define LAN8841_PTP_CMD_CTL_PTP_DISABLE		BIT(1)4027#define LAN8841_PTP_CMD_CTL_PTP_RESET		BIT(0)4028#define LAN8841_PTP_RX_PARSE_CONFIG		3684029#define LAN8841_PTP_TX_PARSE_CONFIG		4324030#define LAN8841_PTP_RX_MODE			3814031#define LAN8841_PTP_INSERT_TS_EN		BIT(0)4032#define LAN8841_PTP_INSERT_TS_32BIT		BIT(1)4033 4034static int lan8841_config_init(struct phy_device *phydev)4035{4036	int ret;4037 4038	ret = ksz9131_config_init(phydev);4039	if (ret)4040		return ret;4041 4042	/* Initialize the HW by resetting everything */4043	phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,4044		       LAN8841_PTP_CMD_CTL,4045		       LAN8841_PTP_CMD_CTL_PTP_RESET,4046		       LAN8841_PTP_CMD_CTL_PTP_RESET);4047 4048	phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,4049		       LAN8841_PTP_CMD_CTL,4050		       LAN8841_PTP_CMD_CTL_PTP_ENABLE,4051		       LAN8841_PTP_CMD_CTL_PTP_ENABLE);4052 4053	/* Don't process any frames */4054	phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,4055		      LAN8841_PTP_RX_PARSE_CONFIG, 0);4056	phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,4057		      LAN8841_PTP_TX_PARSE_CONFIG, 0);4058	phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,4059		      LAN8841_PTP_TX_PARSE_L2_ADDR_EN, 0);4060	phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,4061		      LAN8841_PTP_RX_PARSE_L2_ADDR_EN, 0);4062	phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,4063		      LAN8841_PTP_TX_PARSE_IP_ADDR_EN, 0);4064	phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,4065		      LAN8841_PTP_RX_PARSE_IP_ADDR_EN, 0);4066 4067	/* Disable checking for minorVersionPTP field */4068	phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,4069		      LAN8841_PTP_RX_VERSION, 0xff00);4070	phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,4071		      LAN8841_PTP_TX_VERSION, 0xff00);4072 4073	/* 100BT Clause 40 improvenent errata */4074	phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,4075		      LAN8841_ANALOG_CONTROL_1,4076		      LAN8841_ANALOG_CONTROL_1_PLL_TRIM(0x2));4077	phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,4078		      LAN8841_ANALOG_CONTROL_10,4079		      LAN8841_ANALOG_CONTROL_10_PLL_DIV(0x1));4080 4081	/* 10M/100M Ethernet Signal Tuning Errata for Shorted-Center Tap4082	 * Magnetics4083	 */4084	ret = phy_read_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,4085			   LAN8841_OPERATION_MODE_STRAP_OVERRIDE_LOW_REG);4086	if (ret & LAN8841_OPERATION_MODE_STRAP_OVERRIDE_LOW_REG_MAGJACK) {4087		phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,4088			      LAN8841_TX_LOW_I_CH_C_D_POWER_MANAGMENT,4089			      LAN8841_TX_LOW_I_CH_C_D_POWER_MANAGMENT_VAL);4090		phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,4091			      LAN8841_BTRX_POWER_DOWN,4092			      LAN8841_BTRX_POWER_DOWN_QBIAS_CH_A |4093			      LAN8841_BTRX_POWER_DOWN_BTRX_CH_A |4094			      LAN8841_BTRX_POWER_DOWN_QBIAS_CH_B |4095			      LAN8841_BTRX_POWER_DOWN_BTRX_CH_B |4096			      LAN8841_BTRX_POWER_DOWN_BTRX_CH_C |4097			      LAN8841_BTRX_POWER_DOWN_BTRX_CH_D);4098	}4099 4100	/* LDO Adjustment errata */4101	phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,4102		      LAN8841_ANALOG_CONTROL_11,4103		      LAN8841_ANALOG_CONTROL_11_LDO_REF(1));4104 4105	/* 100BT RGMII latency tuning errata */4106	phy_write_mmd(phydev, MDIO_MMD_PMAPMD,4107		      LAN8841_ADC_CHANNEL_MASK, 0x0);4108	phy_write_mmd(phydev, LAN8841_MMD_TIMER_REG,4109		      LAN8841_MMD0_REGISTER_17,4110		      LAN8841_MMD0_REGISTER_17_DROP_OPT(2) |4111		      LAN8841_MMD0_REGISTER_17_XMIT_TOG_TX_DIS);4112 4113	return 0;4114}4115 4116#define LAN8841_OUTPUT_CTRL			254117#define LAN8841_OUTPUT_CTRL_INT_BUFFER		BIT(14)4118#define LAN8841_INT_PTP				BIT(9)4119 4120static int lan8841_config_intr(struct phy_device *phydev)4121{4122	int err;4123 4124	phy_modify(phydev, LAN8841_OUTPUT_CTRL,4125		   LAN8841_OUTPUT_CTRL_INT_BUFFER, 0);4126 4127	if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {4128		err = phy_read(phydev, LAN8814_INTS);4129		if (err < 0)4130			return err;4131 4132		/* Enable / disable interrupts. It is OK to enable PTP interrupt4133		 * even if it PTP is not enabled. Because the underneath blocks4134		 * will not enable the PTP so we will never get the PTP4135		 * interrupt.4136		 */4137		err = phy_write(phydev, LAN8814_INTC,4138				LAN8814_INT_LINK | LAN8841_INT_PTP);4139	} else {4140		err = phy_write(phydev, LAN8814_INTC, 0);4141		if (err)4142			return err;4143 4144		err = phy_read(phydev, LAN8814_INTS);4145		if (err < 0)4146			return err;4147 4148		/* Getting a positive value doesn't mean that is an error, it4149		 * just indicates what was the status. Therefore make sure to4150		 * clear the value and say that there is no error.4151		 */4152		err = 0;4153	}4154 4155	return err;4156}4157 4158#define LAN8841_PTP_TX_EGRESS_SEC_LO			4534159#define LAN8841_PTP_TX_EGRESS_SEC_HI			4524160#define LAN8841_PTP_TX_EGRESS_NS_LO			4514161#define LAN8841_PTP_TX_EGRESS_NS_HI			4504162#define LAN8841_PTP_TX_EGRESS_NSEC_HI_VALID		BIT(15)4163#define LAN8841_PTP_TX_MSG_HEADER2			4554164 4165static bool lan8841_ptp_get_tx_ts(struct kszphy_ptp_priv *ptp_priv,4166				  u32 *sec, u32 *nsec, u16 *seq)4167{4168	struct phy_device *phydev = ptp_priv->phydev;4169 4170	*nsec = phy_read_mmd(phydev, 2, LAN8841_PTP_TX_EGRESS_NS_HI);4171	if (!(*nsec & LAN8841_PTP_TX_EGRESS_NSEC_HI_VALID))4172		return false;4173 4174	*nsec = ((*nsec & 0x3fff) << 16);4175	*nsec = *nsec | phy_read_mmd(phydev, 2, LAN8841_PTP_TX_EGRESS_NS_LO);4176 4177	*sec = phy_read_mmd(phydev, 2, LAN8841_PTP_TX_EGRESS_SEC_HI);4178	*sec = *sec << 16;4179	*sec = *sec | phy_read_mmd(phydev, 2, LAN8841_PTP_TX_EGRESS_SEC_LO);4180 4181	*seq = phy_read_mmd(phydev, 2, LAN8841_PTP_TX_MSG_HEADER2);4182 4183	return true;4184}4185 4186static void lan8841_ptp_process_tx_ts(struct kszphy_ptp_priv *ptp_priv)4187{4188	u32 sec, nsec;4189	u16 seq;4190 4191	while (lan8841_ptp_get_tx_ts(ptp_priv, &sec, &nsec, &seq))4192		lan8814_match_tx_skb(ptp_priv, sec, nsec, seq);4193}4194 4195#define LAN8841_PTP_INT_STS			2594196#define LAN8841_PTP_INT_STS_PTP_TX_TS_OVRFL_INT	BIT(13)4197#define LAN8841_PTP_INT_STS_PTP_TX_TS_INT	BIT(12)4198#define LAN8841_PTP_INT_STS_PTP_GPIO_CAP_INT	BIT(2)4199 4200static void lan8841_ptp_flush_fifo(struct kszphy_ptp_priv *ptp_priv)4201{4202	struct phy_device *phydev = ptp_priv->phydev;4203	int i;4204 4205	for (i = 0; i < FIFO_SIZE; ++i)4206		phy_read_mmd(phydev, 2, LAN8841_PTP_TX_MSG_HEADER2);4207 4208	phy_read_mmd(phydev, 2, LAN8841_PTP_INT_STS);4209}4210 4211#define LAN8841_PTP_GPIO_CAP_STS			5064212#define LAN8841_PTP_GPIO_SEL				3274213#define LAN8841_PTP_GPIO_SEL_GPIO_SEL(gpio)		((gpio) << 8)4214#define LAN8841_PTP_GPIO_RE_LTC_SEC_HI_CAP		4984215#define LAN8841_PTP_GPIO_RE_LTC_SEC_LO_CAP		4994216#define LAN8841_PTP_GPIO_RE_LTC_NS_HI_CAP		5004217#define LAN8841_PTP_GPIO_RE_LTC_NS_LO_CAP		5014218#define LAN8841_PTP_GPIO_FE_LTC_SEC_HI_CAP		5024219#define LAN8841_PTP_GPIO_FE_LTC_SEC_LO_CAP		5034220#define LAN8841_PTP_GPIO_FE_LTC_NS_HI_CAP		5044221#define LAN8841_PTP_GPIO_FE_LTC_NS_LO_CAP		5054222 4223static void lan8841_gpio_process_cap(struct kszphy_ptp_priv *ptp_priv)4224{4225	struct phy_device *phydev = ptp_priv->phydev;4226	struct ptp_clock_event ptp_event = {0};4227	int pin, ret, tmp;4228	s32 sec, nsec;4229 4230	pin = ptp_find_pin_unlocked(ptp_priv->ptp_clock, PTP_PF_EXTTS, 0);4231	if (pin == -1)4232		return;4233 4234	tmp = phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_CAP_STS);4235	if (tmp < 0)4236		return;4237 4238	ret = phy_write_mmd(phydev, 2, LAN8841_PTP_GPIO_SEL,4239			    LAN8841_PTP_GPIO_SEL_GPIO_SEL(pin));4240	if (ret)4241		return;4242 4243	mutex_lock(&ptp_priv->ptp_lock);4244	if (tmp & BIT(pin)) {4245		sec = phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_RE_LTC_SEC_HI_CAP);4246		sec <<= 16;4247		sec |= phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_RE_LTC_SEC_LO_CAP);4248 4249		nsec = phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_RE_LTC_NS_HI_CAP) & 0x3fff;4250		nsec <<= 16;4251		nsec |= phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_RE_LTC_NS_LO_CAP);4252	} else {4253		sec = phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_FE_LTC_SEC_HI_CAP);4254		sec <<= 16;4255		sec |= phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_FE_LTC_SEC_LO_CAP);4256 4257		nsec = phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_FE_LTC_NS_HI_CAP) & 0x3fff;4258		nsec <<= 16;4259		nsec |= phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_FE_LTC_NS_LO_CAP);4260	}4261	mutex_unlock(&ptp_priv->ptp_lock);4262	ret = phy_write_mmd(phydev, 2, LAN8841_PTP_GPIO_SEL, 0);4263	if (ret)4264		return;4265 4266	ptp_event.index = 0;4267	ptp_event.timestamp = ktime_set(sec, nsec);4268	ptp_event.type = PTP_CLOCK_EXTTS;4269	ptp_clock_event(ptp_priv->ptp_clock, &ptp_event);4270}4271 4272static void lan8841_handle_ptp_interrupt(struct phy_device *phydev)4273{4274	struct kszphy_priv *priv = phydev->priv;4275	struct kszphy_ptp_priv *ptp_priv = &priv->ptp_priv;4276	u16 status;4277 4278	do {4279		status = phy_read_mmd(phydev, 2, LAN8841_PTP_INT_STS);4280 4281		if (status & LAN8841_PTP_INT_STS_PTP_TX_TS_INT)4282			lan8841_ptp_process_tx_ts(ptp_priv);4283 4284		if (status & LAN8841_PTP_INT_STS_PTP_GPIO_CAP_INT)4285			lan8841_gpio_process_cap(ptp_priv);4286 4287		if (status & LAN8841_PTP_INT_STS_PTP_TX_TS_OVRFL_INT) {4288			lan8841_ptp_flush_fifo(ptp_priv);4289			skb_queue_purge(&ptp_priv->tx_queue);4290		}4291 4292	} while (status & (LAN8841_PTP_INT_STS_PTP_TX_TS_INT |4293			   LAN8841_PTP_INT_STS_PTP_GPIO_CAP_INT |4294			   LAN8841_PTP_INT_STS_PTP_TX_TS_OVRFL_INT));4295}4296 4297#define LAN8841_INTS_PTP		BIT(9)4298 4299static irqreturn_t lan8841_handle_interrupt(struct phy_device *phydev)4300{4301	irqreturn_t ret = IRQ_NONE;4302	int irq_status;4303 4304	irq_status = phy_read(phydev, LAN8814_INTS);4305	if (irq_status < 0) {4306		phy_error(phydev);4307		return IRQ_NONE;4308	}4309 4310	if (irq_status & LAN8814_INT_LINK) {4311		phy_trigger_machine(phydev);4312		ret = IRQ_HANDLED;4313	}4314 4315	if (irq_status & LAN8841_INTS_PTP) {4316		lan8841_handle_ptp_interrupt(phydev);4317		ret = IRQ_HANDLED;4318	}4319 4320	return ret;4321}4322 4323static int lan8841_ts_info(struct mii_timestamper *mii_ts,4324			   struct kernel_ethtool_ts_info *info)4325{4326	struct kszphy_ptp_priv *ptp_priv;4327 4328	ptp_priv = container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);4329 4330	info->phc_index = ptp_priv->ptp_clock ?4331				ptp_clock_index(ptp_priv->ptp_clock) : -1;4332	if (info->phc_index == -1)4333		return 0;4334 4335	info->so_timestamping = SOF_TIMESTAMPING_TX_HARDWARE |4336				SOF_TIMESTAMPING_RX_HARDWARE |4337				SOF_TIMESTAMPING_RAW_HARDWARE;4338 4339	info->tx_types = (1 << HWTSTAMP_TX_OFF) |4340			 (1 << HWTSTAMP_TX_ON) |4341			 (1 << HWTSTAMP_TX_ONESTEP_SYNC);4342 4343	info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |4344			   (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |4345			   (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |4346			   (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);4347 4348	return 0;4349}4350 4351#define LAN8841_PTP_INT_EN			2604352#define LAN8841_PTP_INT_EN_PTP_TX_TS_OVRFL_EN	BIT(13)4353#define LAN8841_PTP_INT_EN_PTP_TX_TS_EN		BIT(12)4354 4355static void lan8841_ptp_enable_processing(struct kszphy_ptp_priv *ptp_priv,4356					  bool enable)4357{4358	struct phy_device *phydev = ptp_priv->phydev;4359 4360	if (enable) {4361		/* Enable interrupts on the TX side */4362		phy_modify_mmd(phydev, 2, LAN8841_PTP_INT_EN,4363			       LAN8841_PTP_INT_EN_PTP_TX_TS_OVRFL_EN |4364			       LAN8841_PTP_INT_EN_PTP_TX_TS_EN,4365			       LAN8841_PTP_INT_EN_PTP_TX_TS_OVRFL_EN |4366			       LAN8841_PTP_INT_EN_PTP_TX_TS_EN);4367 4368		/* Enable the modification of the frame on RX side,4369		 * this will add the ns and 2 bits of sec in the reserved field4370		 * of the PTP header4371		 */4372		phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,4373			       LAN8841_PTP_RX_MODE,4374			       LAN8841_PTP_INSERT_TS_EN |4375			       LAN8841_PTP_INSERT_TS_32BIT,4376			       LAN8841_PTP_INSERT_TS_EN |4377			       LAN8841_PTP_INSERT_TS_32BIT);4378 4379		ptp_schedule_worker(ptp_priv->ptp_clock, 0);4380	} else {4381		/* Disable interrupts on the TX side */4382		phy_modify_mmd(phydev, 2, LAN8841_PTP_INT_EN,4383			       LAN8841_PTP_INT_EN_PTP_TX_TS_OVRFL_EN |4384			       LAN8841_PTP_INT_EN_PTP_TX_TS_EN, 0);4385 4386		/* Disable modification of the RX frames */4387		phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,4388			       LAN8841_PTP_RX_MODE,4389			       LAN8841_PTP_INSERT_TS_EN |4390			       LAN8841_PTP_INSERT_TS_32BIT, 0);4391 4392		ptp_cancel_worker_sync(ptp_priv->ptp_clock);4393	}4394}4395 4396#define LAN8841_PTP_RX_TIMESTAMP_EN		3794397#define LAN8841_PTP_TX_TIMESTAMP_EN		4434398#define LAN8841_PTP_TX_MOD			4454399 4400static int lan8841_hwtstamp(struct mii_timestamper *mii_ts,4401			    struct kernel_hwtstamp_config *config,4402			    struct netlink_ext_ack *extack)4403{4404	struct kszphy_ptp_priv *ptp_priv = container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);4405	struct phy_device *phydev = ptp_priv->phydev;4406	int txcfg = 0, rxcfg = 0;4407	int pkt_ts_enable;4408 4409	ptp_priv->hwts_tx_type = config->tx_type;4410	ptp_priv->rx_filter = config->rx_filter;4411 4412	switch (config->rx_filter) {4413	case HWTSTAMP_FILTER_NONE:4414		ptp_priv->layer = 0;4415		ptp_priv->version = 0;4416		break;4417	case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:4418	case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:4419	case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:4420		ptp_priv->layer = PTP_CLASS_L4;4421		ptp_priv->version = PTP_CLASS_V2;4422		break;4423	case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:4424	case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:4425	case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:4426		ptp_priv->layer = PTP_CLASS_L2;4427		ptp_priv->version = PTP_CLASS_V2;4428		break;4429	case HWTSTAMP_FILTER_PTP_V2_EVENT:4430	case HWTSTAMP_FILTER_PTP_V2_SYNC:4431	case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:4432		ptp_priv->layer = PTP_CLASS_L4 | PTP_CLASS_L2;4433		ptp_priv->version = PTP_CLASS_V2;4434		break;4435	default:4436		return -ERANGE;4437	}4438 4439	/* Setup parsing of the frames and enable the timestamping for ptp4440	 * frames4441	 */4442	if (ptp_priv->layer & PTP_CLASS_L2) {4443		rxcfg |= PTP_RX_PARSE_CONFIG_LAYER2_EN_;4444		txcfg |= PTP_TX_PARSE_CONFIG_LAYER2_EN_;4445	} else if (ptp_priv->layer & PTP_CLASS_L4) {4446		rxcfg |= PTP_RX_PARSE_CONFIG_IPV4_EN_ | PTP_RX_PARSE_CONFIG_IPV6_EN_;4447		txcfg |= PTP_TX_PARSE_CONFIG_IPV4_EN_ | PTP_TX_PARSE_CONFIG_IPV6_EN_;4448	}4449 4450	phy_write_mmd(phydev, 2, LAN8841_PTP_RX_PARSE_CONFIG, rxcfg);4451	phy_write_mmd(phydev, 2, LAN8841_PTP_TX_PARSE_CONFIG, txcfg);4452 4453	pkt_ts_enable = PTP_TIMESTAMP_EN_SYNC_ | PTP_TIMESTAMP_EN_DREQ_ |4454			PTP_TIMESTAMP_EN_PDREQ_ | PTP_TIMESTAMP_EN_PDRES_;4455	phy_write_mmd(phydev, 2, LAN8841_PTP_RX_TIMESTAMP_EN, pkt_ts_enable);4456	phy_write_mmd(phydev, 2, LAN8841_PTP_TX_TIMESTAMP_EN, pkt_ts_enable);4457 4458	/* Enable / disable of the TX timestamp in the SYNC frames */4459	phy_modify_mmd(phydev, 2, LAN8841_PTP_TX_MOD,4460		       PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_,4461		       ptp_priv->hwts_tx_type == HWTSTAMP_TX_ONESTEP_SYNC ?4462				PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_ : 0);4463 4464	/* Now enable/disable the timestamping */4465	lan8841_ptp_enable_processing(ptp_priv,4466				      config->rx_filter != HWTSTAMP_FILTER_NONE);4467 4468	skb_queue_purge(&ptp_priv->tx_queue);4469 4470	lan8841_ptp_flush_fifo(ptp_priv);4471 4472	return 0;4473}4474 4475static bool lan8841_rxtstamp(struct mii_timestamper *mii_ts,4476			     struct sk_buff *skb, int type)4477{4478	struct kszphy_ptp_priv *ptp_priv =4479			container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);4480	struct ptp_header *header = ptp_parse_header(skb, type);4481	struct skb_shared_hwtstamps *shhwtstamps;4482	struct timespec64 ts;4483	unsigned long flags;4484	u32 ts_header;4485 4486	if (!header)4487		return false;4488 4489	if (ptp_priv->rx_filter == HWTSTAMP_FILTER_NONE ||4490	    type == PTP_CLASS_NONE)4491		return false;4492 4493	if ((type & ptp_priv->version) == 0 || (type & ptp_priv->layer) == 0)4494		return false;4495 4496	spin_lock_irqsave(&ptp_priv->seconds_lock, flags);4497	ts.tv_sec = ptp_priv->seconds;4498	spin_unlock_irqrestore(&ptp_priv->seconds_lock, flags);4499	ts_header = __be32_to_cpu(header->reserved2);4500 4501	shhwtstamps = skb_hwtstamps(skb);4502	memset(shhwtstamps, 0, sizeof(*shhwtstamps));4503 4504	/* Check for any wrap arounds for the second part */4505	if ((ts.tv_sec & GENMASK(1, 0)) == 0 && (ts_header >> 30) == 3)4506		ts.tv_sec -= GENMASK(1, 0) + 1;4507	else if ((ts.tv_sec & GENMASK(1, 0)) == 3 && (ts_header >> 30) == 0)4508		ts.tv_sec += 1;4509 4510	shhwtstamps->hwtstamp =4511		ktime_set((ts.tv_sec & ~(GENMASK(1, 0))) | ts_header >> 30,4512			  ts_header & GENMASK(29, 0));4513	header->reserved2 = 0;4514 4515	netif_rx(skb);4516 4517	return true;4518}4519 4520#define LAN8841_EVENT_A		04521#define LAN8841_EVENT_B		14522#define LAN8841_PTP_LTC_TARGET_SEC_HI(event)	((event) == LAN8841_EVENT_A ? 278 : 288)4523#define LAN8841_PTP_LTC_TARGET_SEC_LO(event)	((event) == LAN8841_EVENT_A ? 279 : 289)4524#define LAN8841_PTP_LTC_TARGET_NS_HI(event)	((event) == LAN8841_EVENT_A ? 280 : 290)4525#define LAN8841_PTP_LTC_TARGET_NS_LO(event)	((event) == LAN8841_EVENT_A ? 281 : 291)4526 4527static int lan8841_ptp_set_target(struct kszphy_ptp_priv *ptp_priv, u8 event,4528				  s64 sec, u32 nsec)4529{4530	struct phy_device *phydev = ptp_priv->phydev;4531	int ret;4532 4533	ret = phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_SEC_HI(event),4534			    upper_16_bits(sec));4535	if (ret)4536		return ret;4537 4538	ret = phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_SEC_LO(event),4539			    lower_16_bits(sec));4540	if (ret)4541		return ret;4542 4543	ret = phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_NS_HI(event) & 0x3fff,4544			    upper_16_bits(nsec));4545	if (ret)4546		return ret;4547 4548	return phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_NS_LO(event),4549			    lower_16_bits(nsec));4550}4551 4552#define LAN8841_BUFFER_TIME	24553 4554static int lan8841_ptp_update_target(struct kszphy_ptp_priv *ptp_priv,4555				     const struct timespec64 *ts)4556{4557	return lan8841_ptp_set_target(ptp_priv, LAN8841_EVENT_A,4558				      ts->tv_sec + LAN8841_BUFFER_TIME, 0);4559}4560 4561#define LAN8841_PTP_LTC_TARGET_RELOAD_SEC_HI(event)	((event) == LAN8841_EVENT_A ? 282 : 292)4562#define LAN8841_PTP_LTC_TARGET_RELOAD_SEC_LO(event)	((event) == LAN8841_EVENT_A ? 283 : 293)4563#define LAN8841_PTP_LTC_TARGET_RELOAD_NS_HI(event)	((event) == LAN8841_EVENT_A ? 284 : 294)4564#define LAN8841_PTP_LTC_TARGET_RELOAD_NS_LO(event)	((event) == LAN8841_EVENT_A ? 285 : 295)4565 4566static int lan8841_ptp_set_reload(struct kszphy_ptp_priv *ptp_priv, u8 event,4567				  s64 sec, u32 nsec)4568{4569	struct phy_device *phydev = ptp_priv->phydev;4570	int ret;4571 4572	ret = phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_RELOAD_SEC_HI(event),4573			    upper_16_bits(sec));4574	if (ret)4575		return ret;4576 4577	ret = phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_RELOAD_SEC_LO(event),4578			    lower_16_bits(sec));4579	if (ret)4580		return ret;4581 4582	ret = phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_RELOAD_NS_HI(event) & 0x3fff,4583			    upper_16_bits(nsec));4584	if (ret)4585		return ret;4586 4587	return phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_RELOAD_NS_LO(event),4588			     lower_16_bits(nsec));4589}4590 4591#define LAN8841_PTP_LTC_SET_SEC_HI	2624592#define LAN8841_PTP_LTC_SET_SEC_MID	2634593#define LAN8841_PTP_LTC_SET_SEC_LO	2644594#define LAN8841_PTP_LTC_SET_NS_HI	2654595#define LAN8841_PTP_LTC_SET_NS_LO	2664596#define LAN8841_PTP_CMD_CTL_PTP_LTC_LOAD	BIT(4)4597 4598static int lan8841_ptp_settime64(struct ptp_clock_info *ptp,4599				 const struct timespec64 *ts)4600{4601	struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,4602							ptp_clock_info);4603	struct phy_device *phydev = ptp_priv->phydev;4604	unsigned long flags;4605	int ret;4606 4607	/* Set the value to be stored */4608	mutex_lock(&ptp_priv->ptp_lock);4609	phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_SET_SEC_LO, lower_16_bits(ts->tv_sec));4610	phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_SET_SEC_MID, upper_16_bits(ts->tv_sec));4611	phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_SET_SEC_HI, upper_32_bits(ts->tv_sec) & 0xffff);4612	phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_SET_NS_LO, lower_16_bits(ts->tv_nsec));4613	phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_SET_NS_HI, upper_16_bits(ts->tv_nsec) & 0x3fff);4614 4615	/* Set the command to load the LTC */4616	phy_write_mmd(phydev, 2, LAN8841_PTP_CMD_CTL,4617		      LAN8841_PTP_CMD_CTL_PTP_LTC_LOAD);4618	ret = lan8841_ptp_update_target(ptp_priv, ts);4619	mutex_unlock(&ptp_priv->ptp_lock);4620 4621	spin_lock_irqsave(&ptp_priv->seconds_lock, flags);4622	ptp_priv->seconds = ts->tv_sec;4623	spin_unlock_irqrestore(&ptp_priv->seconds_lock, flags);4624 4625	return ret;4626}4627 4628#define LAN8841_PTP_LTC_RD_SEC_HI	3584629#define LAN8841_PTP_LTC_RD_SEC_MID	3594630#define LAN8841_PTP_LTC_RD_SEC_LO	3604631#define LAN8841_PTP_LTC_RD_NS_HI	3614632#define LAN8841_PTP_LTC_RD_NS_LO	3624633#define LAN8841_PTP_CMD_CTL_PTP_LTC_READ	BIT(3)4634 4635static int lan8841_ptp_gettime64(struct ptp_clock_info *ptp,4636				 struct timespec64 *ts)4637{4638	struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,4639							ptp_clock_info);4640	struct phy_device *phydev = ptp_priv->phydev;4641	time64_t s;4642	s64 ns;4643 4644	mutex_lock(&ptp_priv->ptp_lock);4645	/* Issue the command to read the LTC */4646	phy_write_mmd(phydev, 2, LAN8841_PTP_CMD_CTL,4647		      LAN8841_PTP_CMD_CTL_PTP_LTC_READ);4648 4649	/* Read the LTC */4650	s = phy_read_mmd(phydev, 2, LAN8841_PTP_LTC_RD_SEC_HI);4651	s <<= 16;4652	s |= phy_read_mmd(phydev, 2, LAN8841_PTP_LTC_RD_SEC_MID);4653	s <<= 16;4654	s |= phy_read_mmd(phydev, 2, LAN8841_PTP_LTC_RD_SEC_LO);4655 4656	ns = phy_read_mmd(phydev, 2, LAN8841_PTP_LTC_RD_NS_HI) & 0x3fff;4657	ns <<= 16;4658	ns |= phy_read_mmd(phydev, 2, LAN8841_PTP_LTC_RD_NS_LO);4659	mutex_unlock(&ptp_priv->ptp_lock);4660 4661	set_normalized_timespec64(ts, s, ns);4662	return 0;4663}4664 4665static void lan8841_ptp_getseconds(struct ptp_clock_info *ptp,4666				   struct timespec64 *ts)4667{4668	struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,4669							ptp_clock_info);4670	struct phy_device *phydev = ptp_priv->phydev;4671	time64_t s;4672 4673	mutex_lock(&ptp_priv->ptp_lock);4674	/* Issue the command to read the LTC */4675	phy_write_mmd(phydev, 2, LAN8841_PTP_CMD_CTL,4676		      LAN8841_PTP_CMD_CTL_PTP_LTC_READ);4677 4678	/* Read the LTC */4679	s = phy_read_mmd(phydev, 2, LAN8841_PTP_LTC_RD_SEC_HI);4680	s <<= 16;4681	s |= phy_read_mmd(phydev, 2, LAN8841_PTP_LTC_RD_SEC_MID);4682	s <<= 16;4683	s |= phy_read_mmd(phydev, 2, LAN8841_PTP_LTC_RD_SEC_LO);4684	mutex_unlock(&ptp_priv->ptp_lock);4685 4686	set_normalized_timespec64(ts, s, 0);4687}4688 4689#define LAN8841_PTP_LTC_STEP_ADJ_LO			2764690#define LAN8841_PTP_LTC_STEP_ADJ_HI			2754691#define LAN8841_PTP_LTC_STEP_ADJ_DIR			BIT(15)4692#define LAN8841_PTP_CMD_CTL_PTP_LTC_STEP_SECONDS	BIT(5)4693#define LAN8841_PTP_CMD_CTL_PTP_LTC_STEP_NANOSECONDS	BIT(6)4694 4695static int lan8841_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)4696{4697	struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,4698							ptp_clock_info);4699	struct phy_device *phydev = ptp_priv->phydev;4700	struct timespec64 ts;4701	bool add = true;4702	u32 nsec;4703	s32 sec;4704	int ret;4705 4706	/* The HW allows up to 15 sec to adjust the time, but here we limit to4707	 * 10 sec the adjustment. The reason is, in case the adjustment is 144708	 * sec and 999999999 nsec, then we add 8ns to compansate the actual4709	 * increment so the value can be bigger than 15 sec. Therefore limit the4710	 * possible adjustments so we will not have these corner cases4711	 */4712	if (delta > 10000000000LL || delta < -10000000000LL) {4713		/* The timeadjustment is too big, so fall back using set time */4714		u64 now;4715 4716		ptp->gettime64(ptp, &ts);4717 4718		now = ktime_to_ns(timespec64_to_ktime(ts));4719		ts = ns_to_timespec64(now + delta);4720 4721		ptp->settime64(ptp, &ts);4722		return 0;4723	}4724 4725	sec = div_u64_rem(delta < 0 ? -delta : delta, NSEC_PER_SEC, &nsec);4726	if (delta < 0 && nsec != 0) {4727		/* It is not allowed to adjust low the nsec part, therefore4728		 * subtract more from second part and add to nanosecond such4729		 * that would roll over, so the second part will increase4730		 */4731		sec--;4732		nsec = NSEC_PER_SEC - nsec;4733	}4734 4735	/* Calculate the adjustments and the direction */4736	if (delta < 0)4737		add = false;4738 4739	if (nsec > 0)4740		/* add 8 ns to cover the likely normal increment */4741		nsec += 8;4742 4743	if (nsec >= NSEC_PER_SEC) {4744		/* carry into seconds */4745		sec++;4746		nsec -= NSEC_PER_SEC;4747	}4748 4749	mutex_lock(&ptp_priv->ptp_lock);4750	if (sec) {4751		phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_STEP_ADJ_LO, sec);4752		phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_STEP_ADJ_HI,4753			      add ? LAN8841_PTP_LTC_STEP_ADJ_DIR : 0);4754		phy_write_mmd(phydev, 2, LAN8841_PTP_CMD_CTL,4755			      LAN8841_PTP_CMD_CTL_PTP_LTC_STEP_SECONDS);4756	}4757 4758	if (nsec) {4759		phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_STEP_ADJ_LO,4760			      nsec & 0xffff);4761		phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_STEP_ADJ_HI,4762			      (nsec >> 16) & 0x3fff);4763		phy_write_mmd(phydev, 2, LAN8841_PTP_CMD_CTL,4764			      LAN8841_PTP_CMD_CTL_PTP_LTC_STEP_NANOSECONDS);4765	}4766	mutex_unlock(&ptp_priv->ptp_lock);4767 4768	/* Update the target clock */4769	ptp->gettime64(ptp, &ts);4770	mutex_lock(&ptp_priv->ptp_lock);4771	ret = lan8841_ptp_update_target(ptp_priv, &ts);4772	mutex_unlock(&ptp_priv->ptp_lock);4773 4774	return ret;4775}4776 4777#define LAN8841_PTP_LTC_RATE_ADJ_HI		2694778#define LAN8841_PTP_LTC_RATE_ADJ_HI_DIR		BIT(15)4779#define LAN8841_PTP_LTC_RATE_ADJ_LO		2704780 4781static int lan8841_ptp_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)4782{4783	struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,4784							ptp_clock_info);4785	struct phy_device *phydev = ptp_priv->phydev;4786	bool faster = true;4787	u32 rate;4788 4789	if (!scaled_ppm)4790		return 0;4791 4792	if (scaled_ppm < 0) {4793		scaled_ppm = -scaled_ppm;4794		faster = false;4795	}4796 4797	rate = LAN8841_1PPM_FORMAT * (upper_16_bits(scaled_ppm));4798	rate += (LAN8841_1PPM_FORMAT * (lower_16_bits(scaled_ppm))) >> 16;4799 4800	mutex_lock(&ptp_priv->ptp_lock);4801	phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_RATE_ADJ_HI,4802		      faster ? LAN8841_PTP_LTC_RATE_ADJ_HI_DIR | (upper_16_bits(rate) & 0x3fff)4803			     : upper_16_bits(rate) & 0x3fff);4804	phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_RATE_ADJ_LO, lower_16_bits(rate));4805	mutex_unlock(&ptp_priv->ptp_lock);4806 4807	return 0;4808}4809 4810static int lan8841_ptp_verify(struct ptp_clock_info *ptp, unsigned int pin,4811			      enum ptp_pin_function func, unsigned int chan)4812{4813	switch (func) {4814	case PTP_PF_NONE:4815	case PTP_PF_PEROUT:4816	case PTP_PF_EXTTS:4817		break;4818	default:4819		return -1;4820	}4821 4822	return 0;4823}4824 4825#define LAN8841_PTP_GPIO_NUM	104826#define LAN8841_GPIO_EN		1284827#define LAN8841_GPIO_DIR	1294828#define LAN8841_GPIO_BUF	1304829 4830static int lan8841_ptp_perout_off(struct kszphy_ptp_priv *ptp_priv, int pin)4831{4832	struct phy_device *phydev = ptp_priv->phydev;4833	int ret;4834 4835	ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_EN, BIT(pin));4836	if (ret)4837		return ret;4838 4839	ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_DIR, BIT(pin));4840	if (ret)4841		return ret;4842 4843	return phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_BUF, BIT(pin));4844}4845 4846static int lan8841_ptp_perout_on(struct kszphy_ptp_priv *ptp_priv, int pin)4847{4848	struct phy_device *phydev = ptp_priv->phydev;4849	int ret;4850 4851	ret = phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_EN, BIT(pin));4852	if (ret)4853		return ret;4854 4855	ret = phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_DIR, BIT(pin));4856	if (ret)4857		return ret;4858 4859	return phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_BUF, BIT(pin));4860}4861 4862#define LAN8841_GPIO_DATA_SEL1				1314863#define LAN8841_GPIO_DATA_SEL2				1324864#define LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_MASK	GENMASK(2, 0)4865#define LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_A	14866#define LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_B	24867#define LAN8841_PTP_GENERAL_CONFIG			2574868#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_A	BIT(1)4869#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_B	BIT(3)4870#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_A_MASK	GENMASK(7, 4)4871#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_B_MASK	GENMASK(11, 8)4872#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_A		44873#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_B		74874 4875static int lan8841_ptp_remove_event(struct kszphy_ptp_priv *ptp_priv, int pin,4876				    u8 event)4877{4878	struct phy_device *phydev = ptp_priv->phydev;4879	u16 tmp;4880	int ret;4881 4882	/* Now remove pin from the event. GPIO_DATA_SEL1 contains the GPIO4883	 * pins 0-4 while GPIO_DATA_SEL2 contains GPIO pins 5-9, therefore4884	 * depending on the pin, it requires to read a different register4885	 */4886	if (pin < 5) {4887		tmp = LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_MASK << (3 * pin);4888		ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_DATA_SEL1, tmp);4889	} else {4890		tmp = LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_MASK << (3 * (pin - 5));4891		ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_DATA_SEL2, tmp);4892	}4893	if (ret)4894		return ret;4895 4896	/* Disable the event */4897	if (event == LAN8841_EVENT_A)4898		tmp = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_A |4899		      LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_A_MASK;4900	else4901		tmp = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_B |4902		      LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_B_MASK;4903	return phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_EN, tmp);4904}4905 4906static int lan8841_ptp_enable_event(struct kszphy_ptp_priv *ptp_priv, int pin,4907				    u8 event, int pulse_width)4908{4909	struct phy_device *phydev = ptp_priv->phydev;4910	u16 tmp;4911	int ret;4912 4913	/* Enable the event */4914	if (event == LAN8841_EVENT_A)4915		ret = phy_modify_mmd(phydev, 2, LAN8841_PTP_GENERAL_CONFIG,4916				     LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_A |4917				     LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_A_MASK,4918				     LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_A |4919				     pulse_width << LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_A);4920	else4921		ret = phy_modify_mmd(phydev, 2, LAN8841_PTP_GENERAL_CONFIG,4922				     LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_B |4923				     LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_B_MASK,4924				     LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_B |4925				     pulse_width << LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_B);4926	if (ret)4927		return ret;4928 4929	/* Now connect the pin to the event. GPIO_DATA_SEL1 contains the GPIO4930	 * pins 0-4 while GPIO_DATA_SEL2 contains GPIO pins 5-9, therefore4931	 * depending on the pin, it requires to read a different register4932	 */4933	if (event == LAN8841_EVENT_A)4934		tmp = LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_A;4935	else4936		tmp = LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_B;4937 4938	if (pin < 5)4939		ret = phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_DATA_SEL1,4940				       tmp << (3 * pin));4941	else4942		ret = phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_DATA_SEL2,4943				       tmp << (3 * (pin - 5)));4944 4945	return ret;4946}4947 4948#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_200MS	134949#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100MS	124950#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_50MS	114951#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_10MS	104952#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_5MS	94953#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_1MS	84954#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_500US	74955#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100US	64956#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_50US	54957#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_10US	44958#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_5US	34959#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_1US	24960#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_500NS	14961#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100NS	04962 4963static int lan8841_ptp_perout(struct ptp_clock_info *ptp,4964			      struct ptp_clock_request *rq, int on)4965{4966	struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,4967							ptp_clock_info);4968	struct phy_device *phydev = ptp_priv->phydev;4969	struct timespec64 ts_on, ts_period;4970	s64 on_nsec, period_nsec;4971	int pulse_width;4972	int pin;4973	int ret;4974 4975	if (rq->perout.flags & ~PTP_PEROUT_DUTY_CYCLE)4976		return -EOPNOTSUPP;4977 4978	pin = ptp_find_pin(ptp_priv->ptp_clock, PTP_PF_PEROUT, rq->perout.index);4979	if (pin == -1 || pin >= LAN8841_PTP_GPIO_NUM)4980		return -EINVAL;4981 4982	if (!on) {4983		ret = lan8841_ptp_perout_off(ptp_priv, pin);4984		if (ret)4985			return ret;4986 4987		return lan8841_ptp_remove_event(ptp_priv, LAN8841_EVENT_A, pin);4988	}4989 4990	ts_on.tv_sec = rq->perout.on.sec;4991	ts_on.tv_nsec = rq->perout.on.nsec;4992	on_nsec = timespec64_to_ns(&ts_on);4993 4994	ts_period.tv_sec = rq->perout.period.sec;4995	ts_period.tv_nsec = rq->perout.period.nsec;4996	period_nsec = timespec64_to_ns(&ts_period);4997 4998	if (period_nsec < 200) {4999		pr_warn_ratelimited("%s: perout period too small, minimum is 200 nsec\n",5000				    phydev_name(phydev));5001		return -EOPNOTSUPP;5002	}5003 5004	if (on_nsec >= period_nsec) {5005		pr_warn_ratelimited("%s: pulse width must be smaller than period\n",5006				    phydev_name(phydev));5007		return -EINVAL;5008	}5009 5010	switch (on_nsec) {5011	case 200000000:5012		pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_200MS;5013		break;5014	case 100000000:5015		pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100MS;5016		break;5017	case 50000000:5018		pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_50MS;5019		break;5020	case 10000000:5021		pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_10MS;5022		break;5023	case 5000000:5024		pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_5MS;5025		break;5026	case 1000000:5027		pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_1MS;5028		break;5029	case 500000:5030		pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_500US;5031		break;5032	case 100000:5033		pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100US;5034		break;5035	case 50000:5036		pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_50US;5037		break;5038	case 10000:5039		pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_10US;5040		break;5041	case 5000:5042		pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_5US;5043		break;5044	case 1000:5045		pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_1US;5046		break;5047	case 500:5048		pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_500NS;5049		break;5050	case 100:5051		pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100NS;5052		break;5053	default:5054		pr_warn_ratelimited("%s: Use default duty cycle of 100ns\n",5055				    phydev_name(phydev));5056		pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100NS;5057		break;5058	}5059 5060	mutex_lock(&ptp_priv->ptp_lock);5061	ret = lan8841_ptp_set_target(ptp_priv, LAN8841_EVENT_A, rq->perout.start.sec,5062				     rq->perout.start.nsec);5063	mutex_unlock(&ptp_priv->ptp_lock);5064	if (ret)5065		return ret;5066 5067	ret = lan8841_ptp_set_reload(ptp_priv, LAN8841_EVENT_A, rq->perout.period.sec,5068				     rq->perout.period.nsec);5069	if (ret)5070		return ret;5071 5072	ret = lan8841_ptp_enable_event(ptp_priv, pin, LAN8841_EVENT_A,5073				       pulse_width);5074	if (ret)5075		return ret;5076 5077	ret = lan8841_ptp_perout_on(ptp_priv, pin);5078	if (ret)5079		lan8841_ptp_remove_event(ptp_priv, pin, LAN8841_EVENT_A);5080 5081	return ret;5082}5083 5084#define LAN8841_PTP_GPIO_CAP_EN			4965085#define LAN8841_PTP_GPIO_CAP_EN_GPIO_RE_CAPTURE_ENABLE(gpio)	(BIT(gpio))5086#define LAN8841_PTP_GPIO_CAP_EN_GPIO_FE_CAPTURE_ENABLE(gpio)	(BIT(gpio) << 8)5087#define LAN8841_PTP_INT_EN_PTP_GPIO_CAP_EN	BIT(2)5088 5089static int lan8841_ptp_extts_on(struct kszphy_ptp_priv *ptp_priv, int pin,5090				u32 flags)5091{5092	struct phy_device *phydev = ptp_priv->phydev;5093	u16 tmp = 0;5094	int ret;5095 5096	/* Set GPIO to be intput */5097	ret = phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_EN, BIT(pin));5098	if (ret)5099		return ret;5100 5101	ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_BUF, BIT(pin));5102	if (ret)5103		return ret;5104 5105	/* Enable capture on the edges of the pin */5106	if (flags & PTP_RISING_EDGE)5107		tmp |= LAN8841_PTP_GPIO_CAP_EN_GPIO_RE_CAPTURE_ENABLE(pin);5108	if (flags & PTP_FALLING_EDGE)5109		tmp |= LAN8841_PTP_GPIO_CAP_EN_GPIO_FE_CAPTURE_ENABLE(pin);5110	ret = phy_write_mmd(phydev, 2, LAN8841_PTP_GPIO_CAP_EN, tmp);5111	if (ret)5112		return ret;5113 5114	/* Enable interrupt */5115	return phy_modify_mmd(phydev, 2, LAN8841_PTP_INT_EN,5116			      LAN8841_PTP_INT_EN_PTP_GPIO_CAP_EN,5117			      LAN8841_PTP_INT_EN_PTP_GPIO_CAP_EN);5118}5119 5120static int lan8841_ptp_extts_off(struct kszphy_ptp_priv *ptp_priv, int pin)5121{5122	struct phy_device *phydev = ptp_priv->phydev;5123	int ret;5124 5125	/* Set GPIO to be output */5126	ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_EN, BIT(pin));5127	if (ret)5128		return ret;5129 5130	ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_BUF, BIT(pin));5131	if (ret)5132		return ret;5133 5134	/* Disable capture on both of the edges */5135	ret = phy_modify_mmd(phydev, 2, LAN8841_PTP_GPIO_CAP_EN,5136			     LAN8841_PTP_GPIO_CAP_EN_GPIO_RE_CAPTURE_ENABLE(pin) |5137			     LAN8841_PTP_GPIO_CAP_EN_GPIO_FE_CAPTURE_ENABLE(pin),5138			     0);5139	if (ret)5140		return ret;5141 5142	/* Disable interrupt */5143	return phy_modify_mmd(phydev, 2, LAN8841_PTP_INT_EN,5144			      LAN8841_PTP_INT_EN_PTP_GPIO_CAP_EN,5145			      0);5146}5147 5148static int lan8841_ptp_extts(struct ptp_clock_info *ptp,5149			     struct ptp_clock_request *rq, int on)5150{5151	struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,5152							ptp_clock_info);5153	int pin;5154	int ret;5155 5156	/* Reject requests with unsupported flags */5157	if (rq->extts.flags & ~(PTP_ENABLE_FEATURE |5158				PTP_EXTTS_EDGES |5159				PTP_STRICT_FLAGS))5160		return -EOPNOTSUPP;5161 5162	pin = ptp_find_pin(ptp_priv->ptp_clock, PTP_PF_EXTTS, rq->extts.index);5163	if (pin == -1 || pin >= LAN8841_PTP_GPIO_NUM)5164		return -EINVAL;5165 5166	mutex_lock(&ptp_priv->ptp_lock);5167	if (on)5168		ret = lan8841_ptp_extts_on(ptp_priv, pin, rq->extts.flags);5169	else5170		ret = lan8841_ptp_extts_off(ptp_priv, pin);5171	mutex_unlock(&ptp_priv->ptp_lock);5172 5173	return ret;5174}5175 5176static int lan8841_ptp_enable(struct ptp_clock_info *ptp,5177			      struct ptp_clock_request *rq, int on)5178{5179	switch (rq->type) {5180	case PTP_CLK_REQ_EXTTS:5181		return lan8841_ptp_extts(ptp, rq, on);5182	case PTP_CLK_REQ_PEROUT:5183		return lan8841_ptp_perout(ptp, rq, on);5184	default:5185		return -EOPNOTSUPP;5186	}5187 5188	return 0;5189}5190 5191static long lan8841_ptp_do_aux_work(struct ptp_clock_info *ptp)5192{5193	struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,5194							ptp_clock_info);5195	struct timespec64 ts;5196	unsigned long flags;5197 5198	lan8841_ptp_getseconds(&ptp_priv->ptp_clock_info, &ts);5199 5200	spin_lock_irqsave(&ptp_priv->seconds_lock, flags);5201	ptp_priv->seconds = ts.tv_sec;5202	spin_unlock_irqrestore(&ptp_priv->seconds_lock, flags);5203 5204	return nsecs_to_jiffies(LAN8841_GET_SEC_LTC_DELAY);5205}5206 5207static struct ptp_clock_info lan8841_ptp_clock_info = {5208	.owner		= THIS_MODULE,5209	.name		= "lan8841 ptp",5210	.max_adj	= 31249999,5211	.gettime64	= lan8841_ptp_gettime64,5212	.settime64	= lan8841_ptp_settime64,5213	.adjtime	= lan8841_ptp_adjtime,5214	.adjfine	= lan8841_ptp_adjfine,5215	.verify         = lan8841_ptp_verify,5216	.enable         = lan8841_ptp_enable,5217	.do_aux_work	= lan8841_ptp_do_aux_work,5218	.n_per_out      = LAN8841_PTP_GPIO_NUM,5219	.n_ext_ts       = LAN8841_PTP_GPIO_NUM,5220	.n_pins         = LAN8841_PTP_GPIO_NUM,5221};5222 5223#define LAN8841_OPERATION_MODE_STRAP_LOW_REGISTER 35224#define LAN8841_OPERATION_MODE_STRAP_LOW_REGISTER_STRAP_RGMII_EN BIT(0)5225 5226static int lan8841_probe(struct phy_device *phydev)5227{5228	struct kszphy_ptp_priv *ptp_priv;5229	struct kszphy_priv *priv;5230	int err;5231 5232	err = kszphy_probe(phydev);5233	if (err)5234		return err;5235 5236	if (phy_read_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,5237			 LAN8841_OPERATION_MODE_STRAP_LOW_REGISTER) &5238	    LAN8841_OPERATION_MODE_STRAP_LOW_REGISTER_STRAP_RGMII_EN)5239		phydev->interface = PHY_INTERFACE_MODE_RGMII_RXID;5240 5241	/* Register the clock */5242	if (!IS_ENABLED(CONFIG_NETWORK_PHY_TIMESTAMPING))5243		return 0;5244 5245	priv = phydev->priv;5246	ptp_priv = &priv->ptp_priv;5247 5248	ptp_priv->pin_config = devm_kcalloc(&phydev->mdio.dev,5249					    LAN8841_PTP_GPIO_NUM,5250					    sizeof(*ptp_priv->pin_config),5251					    GFP_KERNEL);5252	if (!ptp_priv->pin_config)5253		return -ENOMEM;5254 5255	for (int i = 0; i < LAN8841_PTP_GPIO_NUM; ++i) {5256		struct ptp_pin_desc *p = &ptp_priv->pin_config[i];5257 5258		snprintf(p->name, sizeof(p->name), "pin%d", i);5259		p->index = i;5260		p->func = PTP_PF_NONE;5261	}5262 5263	ptp_priv->ptp_clock_info = lan8841_ptp_clock_info;5264	ptp_priv->ptp_clock_info.pin_config = ptp_priv->pin_config;5265	ptp_priv->ptp_clock = ptp_clock_register(&ptp_priv->ptp_clock_info,5266						 &phydev->mdio.dev);5267	if (IS_ERR(ptp_priv->ptp_clock)) {5268		phydev_err(phydev, "ptp_clock_register failed: %lu\n",5269			   PTR_ERR(ptp_priv->ptp_clock));5270		return -EINVAL;5271	}5272 5273	if (!ptp_priv->ptp_clock)5274		return 0;5275 5276	/* Initialize the SW */5277	skb_queue_head_init(&ptp_priv->tx_queue);5278	ptp_priv->phydev = phydev;5279	mutex_init(&ptp_priv->ptp_lock);5280	spin_lock_init(&ptp_priv->seconds_lock);5281 5282	ptp_priv->mii_ts.rxtstamp = lan8841_rxtstamp;5283	ptp_priv->mii_ts.txtstamp = lan8814_txtstamp;5284	ptp_priv->mii_ts.hwtstamp = lan8841_hwtstamp;5285	ptp_priv->mii_ts.ts_info = lan8841_ts_info;5286 5287	phydev->mii_ts = &ptp_priv->mii_ts;5288 5289	/* Timestamp selected by default to keep legacy API */5290	phydev->default_timestamp = true;5291 5292	return 0;5293}5294 5295static int lan8841_suspend(struct phy_device *phydev)5296{5297	struct kszphy_priv *priv = phydev->priv;5298	struct kszphy_ptp_priv *ptp_priv = &priv->ptp_priv;5299 5300	if (ptp_priv->ptp_clock)5301		ptp_cancel_worker_sync(ptp_priv->ptp_clock);5302 5303	return genphy_suspend(phydev);5304}5305 5306static struct phy_driver ksphy_driver[] = {5307{5308	.phy_id		= PHY_ID_KS8737,5309	.phy_id_mask	= MICREL_PHY_ID_MASK,5310	.name		= "Micrel KS8737",5311	/* PHY_BASIC_FEATURES */5312	.driver_data	= &ks8737_type,5313	.probe		= kszphy_probe,5314	.config_init	= kszphy_config_init,5315	.config_intr	= kszphy_config_intr,5316	.handle_interrupt = kszphy_handle_interrupt,5317	.suspend	= kszphy_suspend,5318	.resume		= kszphy_resume,5319}, {5320	.phy_id		= PHY_ID_KSZ8021,5321	.phy_id_mask	= 0x00ffffff,5322	.name		= "Micrel KSZ8021 or KSZ8031",5323	/* PHY_BASIC_FEATURES */5324	.driver_data	= &ksz8021_type,5325	.probe		= kszphy_probe,5326	.config_init	= kszphy_config_init,5327	.config_intr	= kszphy_config_intr,5328	.handle_interrupt = kszphy_handle_interrupt,5329	.get_sset_count = kszphy_get_sset_count,5330	.get_strings	= kszphy_get_strings,5331	.get_stats	= kszphy_get_stats,5332	.suspend	= kszphy_suspend,5333	.resume		= kszphy_resume,5334}, {5335	.phy_id		= PHY_ID_KSZ8031,5336	.phy_id_mask	= 0x00ffffff,5337	.name		= "Micrel KSZ8031",5338	/* PHY_BASIC_FEATURES */5339	.driver_data	= &ksz8021_type,5340	.probe		= kszphy_probe,5341	.config_init	= kszphy_config_init,5342	.config_intr	= kszphy_config_intr,5343	.handle_interrupt = kszphy_handle_interrupt,5344	.get_sset_count = kszphy_get_sset_count,5345	.get_strings	= kszphy_get_strings,5346	.get_stats	= kszphy_get_stats,5347	.suspend	= kszphy_suspend,5348	.resume		= kszphy_resume,5349}, {5350	.phy_id		= PHY_ID_KSZ8041,5351	.phy_id_mask	= MICREL_PHY_ID_MASK,5352	.name		= "Micrel KSZ8041",5353	/* PHY_BASIC_FEATURES */5354	.driver_data	= &ksz8041_type,5355	.probe		= kszphy_probe,5356	.config_init	= ksz8041_config_init,5357	.config_aneg	= ksz8041_config_aneg,5358	.config_intr	= kszphy_config_intr,5359	.handle_interrupt = kszphy_handle_interrupt,5360	.get_sset_count = kszphy_get_sset_count,5361	.get_strings	= kszphy_get_strings,5362	.get_stats	= kszphy_get_stats,5363	/* No suspend/resume callbacks because of errata DS80000700A,5364	 * receiver error following software power down.5365	 */5366}, {5367	.phy_id		= PHY_ID_KSZ8041RNLI,5368	.phy_id_mask	= MICREL_PHY_ID_MASK,5369	.name		= "Micrel KSZ8041RNLI",5370	/* PHY_BASIC_FEATURES */5371	.driver_data	= &ksz8041_type,5372	.probe		= kszphy_probe,5373	.config_init	= kszphy_config_init,5374	.config_intr	= kszphy_config_intr,5375	.handle_interrupt = kszphy_handle_interrupt,5376	.get_sset_count = kszphy_get_sset_count,5377	.get_strings	= kszphy_get_strings,5378	.get_stats	= kszphy_get_stats,5379	.suspend	= kszphy_suspend,5380	.resume		= kszphy_resume,5381}, {5382	.name		= "Micrel KSZ8051",5383	/* PHY_BASIC_FEATURES */5384	.driver_data	= &ksz8051_type,5385	.probe		= kszphy_probe,5386	.config_init	= kszphy_config_init,5387	.config_intr	= kszphy_config_intr,5388	.handle_interrupt = kszphy_handle_interrupt,5389	.get_sset_count = kszphy_get_sset_count,5390	.get_strings	= kszphy_get_strings,5391	.get_stats	= kszphy_get_stats,5392	.match_phy_device = ksz8051_match_phy_device,5393	.suspend	= kszphy_suspend,5394	.resume		= kszphy_resume,5395}, {5396	.phy_id		= PHY_ID_KSZ8001,5397	.name		= "Micrel KSZ8001 or KS8721",5398	.phy_id_mask	= 0x00fffffc,5399	/* PHY_BASIC_FEATURES */5400	.driver_data	= &ksz8041_type,5401	.probe		= kszphy_probe,5402	.config_init	= kszphy_config_init,5403	.config_intr	= kszphy_config_intr,5404	.handle_interrupt = kszphy_handle_interrupt,5405	.get_sset_count = kszphy_get_sset_count,5406	.get_strings	= kszphy_get_strings,5407	.get_stats	= kszphy_get_stats,5408	.suspend	= kszphy_suspend,5409	.resume		= kszphy_resume,5410}, {5411	.phy_id		= PHY_ID_KSZ8081,5412	.name		= "Micrel KSZ8081 or KSZ8091",5413	.phy_id_mask	= MICREL_PHY_ID_MASK,5414	.flags		= PHY_POLL_CABLE_TEST,5415	/* PHY_BASIC_FEATURES */5416	.driver_data	= &ksz8081_type,5417	.probe		= kszphy_probe,5418	.config_init	= ksz8081_config_init,5419	.soft_reset	= genphy_soft_reset,5420	.config_aneg	= ksz8081_config_aneg,5421	.read_status	= ksz8081_read_status,5422	.config_intr	= kszphy_config_intr,5423	.handle_interrupt = kszphy_handle_interrupt,5424	.get_sset_count = kszphy_get_sset_count,5425	.get_strings	= kszphy_get_strings,5426	.get_stats	= kszphy_get_stats,5427	.suspend	= kszphy_suspend,5428	.resume		= kszphy_resume,5429	.cable_test_start	= ksz886x_cable_test_start,5430	.cable_test_get_status	= ksz886x_cable_test_get_status,5431}, {5432	.phy_id		= PHY_ID_KSZ8061,5433	.name		= "Micrel KSZ8061",5434	.phy_id_mask	= MICREL_PHY_ID_MASK,5435	/* PHY_BASIC_FEATURES */5436	.probe		= kszphy_probe,5437	.config_init	= ksz8061_config_init,5438	.soft_reset	= genphy_soft_reset,5439	.config_intr	= kszphy_config_intr,5440	.handle_interrupt = kszphy_handle_interrupt,5441	.suspend	= kszphy_suspend,5442	.resume		= ksz8061_resume,5443}, {5444	.phy_id		= PHY_ID_KSZ9021,5445	.phy_id_mask	= 0x000ffffe,5446	.name		= "Micrel KSZ9021 Gigabit PHY",5447	/* PHY_GBIT_FEATURES */5448	.driver_data	= &ksz9021_type,5449	.probe		= kszphy_probe,5450	.get_features	= ksz9031_get_features,5451	.config_init	= ksz9021_config_init,5452	.config_intr	= kszphy_config_intr,5453	.handle_interrupt = kszphy_handle_interrupt,5454	.get_sset_count = kszphy_get_sset_count,5455	.get_strings	= kszphy_get_strings,5456	.get_stats	= kszphy_get_stats,5457	.suspend	= kszphy_suspend,5458	.resume		= kszphy_resume,5459	.read_mmd	= genphy_read_mmd_unsupported,5460	.write_mmd	= genphy_write_mmd_unsupported,5461}, {5462	.phy_id		= PHY_ID_KSZ9031,5463	.phy_id_mask	= MICREL_PHY_ID_MASK,5464	.name		= "Micrel KSZ9031 Gigabit PHY",5465	.flags		= PHY_POLL_CABLE_TEST,5466	.driver_data	= &ksz9021_type,5467	.probe		= kszphy_probe,5468	.get_features	= ksz9031_get_features,5469	.config_init	= ksz9031_config_init,5470	.soft_reset	= genphy_soft_reset,5471	.read_status	= ksz9031_read_status,5472	.config_intr	= kszphy_config_intr,5473	.handle_interrupt = kszphy_handle_interrupt,5474	.get_sset_count = kszphy_get_sset_count,5475	.get_strings	= kszphy_get_strings,5476	.get_stats	= kszphy_get_stats,5477	.suspend	= kszphy_suspend,5478	.resume		= kszphy_resume,5479	.cable_test_start	= ksz9x31_cable_test_start,5480	.cable_test_get_status	= ksz9x31_cable_test_get_status,5481}, {5482	.phy_id		= PHY_ID_LAN8814,5483	.phy_id_mask	= MICREL_PHY_ID_MASK,5484	.name		= "Microchip INDY Gigabit Quad PHY",5485	.flags          = PHY_POLL_CABLE_TEST,5486	.config_init	= lan8814_config_init,5487	.driver_data	= &lan8814_type,5488	.probe		= lan8814_probe,5489	.soft_reset	= genphy_soft_reset,5490	.read_status	= ksz9031_read_status,5491	.get_sset_count	= kszphy_get_sset_count,5492	.get_strings	= kszphy_get_strings,5493	.get_stats	= kszphy_get_stats,5494	.suspend	= genphy_suspend,5495	.resume		= kszphy_resume,5496	.config_intr	= lan8814_config_intr,5497	.handle_interrupt = lan8814_handle_interrupt,5498	.cable_test_start	= lan8814_cable_test_start,5499	.cable_test_get_status	= ksz886x_cable_test_get_status,5500}, {5501	.phy_id		= PHY_ID_LAN8804,5502	.phy_id_mask	= MICREL_PHY_ID_MASK,5503	.name		= "Microchip LAN966X Gigabit PHY",5504	.config_init	= lan8804_config_init,5505	.driver_data	= &ksz9021_type,5506	.probe		= kszphy_probe,5507	.soft_reset	= genphy_soft_reset,5508	.read_status	= ksz9031_read_status,5509	.get_sset_count	= kszphy_get_sset_count,5510	.get_strings	= kszphy_get_strings,5511	.get_stats	= kszphy_get_stats,5512	.suspend	= genphy_suspend,5513	.resume		= kszphy_resume,5514	.config_intr	= lan8804_config_intr,5515	.handle_interrupt = lan8804_handle_interrupt,5516}, {5517	.phy_id		= PHY_ID_LAN8841,5518	.phy_id_mask	= MICREL_PHY_ID_MASK,5519	.name		= "Microchip LAN8841 Gigabit PHY",5520	.flags		= PHY_POLL_CABLE_TEST,5521	.driver_data	= &lan8841_type,5522	.config_init	= lan8841_config_init,5523	.probe		= lan8841_probe,5524	.soft_reset	= genphy_soft_reset,5525	.config_intr	= lan8841_config_intr,5526	.handle_interrupt = lan8841_handle_interrupt,5527	.get_sset_count = kszphy_get_sset_count,5528	.get_strings	= kszphy_get_strings,5529	.get_stats	= kszphy_get_stats,5530	.suspend	= lan8841_suspend,5531	.resume		= genphy_resume,5532	.cable_test_start	= lan8814_cable_test_start,5533	.cable_test_get_status	= ksz886x_cable_test_get_status,5534}, {5535	.phy_id		= PHY_ID_KSZ9131,5536	.phy_id_mask	= MICREL_PHY_ID_MASK,5537	.name		= "Microchip KSZ9131 Gigabit PHY",5538	/* PHY_GBIT_FEATURES */5539	.flags		= PHY_POLL_CABLE_TEST,5540	.driver_data	= &ksz9131_type,5541	.probe		= kszphy_probe,5542	.soft_reset	= genphy_soft_reset,5543	.config_init	= ksz9131_config_init,5544	.config_intr	= kszphy_config_intr,5545	.config_aneg	= ksz9131_config_aneg,5546	.read_status	= ksz9131_read_status,5547	.handle_interrupt = kszphy_handle_interrupt,5548	.get_sset_count = kszphy_get_sset_count,5549	.get_strings	= kszphy_get_strings,5550	.get_stats	= kszphy_get_stats,5551	.suspend	= kszphy_suspend,5552	.resume		= kszphy_resume,5553	.cable_test_start	= ksz9x31_cable_test_start,5554	.cable_test_get_status	= ksz9x31_cable_test_get_status,5555	.get_features	= ksz9477_get_features,5556}, {5557	.phy_id		= PHY_ID_KSZ8873MLL,5558	.phy_id_mask	= MICREL_PHY_ID_MASK,5559	.name		= "Micrel KSZ8873MLL Switch",5560	/* PHY_BASIC_FEATURES */5561	.config_init	= kszphy_config_init,5562	.config_aneg	= ksz8873mll_config_aneg,5563	.read_status	= ksz8873mll_read_status,5564	.suspend	= genphy_suspend,5565	.resume		= genphy_resume,5566}, {5567	.phy_id		= PHY_ID_KSZ886X,5568	.phy_id_mask	= MICREL_PHY_ID_MASK,5569	.name		= "Micrel KSZ8851 Ethernet MAC or KSZ886X Switch",5570	.driver_data	= &ksz886x_type,5571	/* PHY_BASIC_FEATURES */5572	.flags		= PHY_POLL_CABLE_TEST,5573	.config_init	= kszphy_config_init,5574	.config_aneg	= ksz886x_config_aneg,5575	.read_status	= ksz886x_read_status,5576	.suspend	= genphy_suspend,5577	.resume		= genphy_resume,5578	.cable_test_start	= ksz886x_cable_test_start,5579	.cable_test_get_status	= ksz886x_cable_test_get_status,5580}, {5581	.name		= "Micrel KSZ87XX Switch",5582	/* PHY_BASIC_FEATURES */5583	.config_init	= kszphy_config_init,5584	.match_phy_device = ksz8795_match_phy_device,5585	.suspend	= genphy_suspend,5586	.resume		= genphy_resume,5587}, {5588	.phy_id		= PHY_ID_KSZ9477,5589	.phy_id_mask	= MICREL_PHY_ID_MASK,5590	.name		= "Microchip KSZ9477",5591	/* PHY_GBIT_FEATURES */5592	.config_init	= ksz9477_config_init,5593	.config_intr	= kszphy_config_intr,5594	.handle_interrupt = kszphy_handle_interrupt,5595	.suspend	= genphy_suspend,5596	.resume		= ksz9477_resume,5597	.get_features	= ksz9477_get_features,5598} };5599 5600module_phy_driver(ksphy_driver);5601 5602MODULE_DESCRIPTION("Micrel PHY driver");5603MODULE_AUTHOR("David J. Choi");5604MODULE_LICENSE("GPL");5605 5606static struct mdio_device_id __maybe_unused micrel_tbl[] = {5607	{ PHY_ID_KSZ9021, 0x000ffffe },5608	{ PHY_ID_KSZ9031, MICREL_PHY_ID_MASK },5609	{ PHY_ID_KSZ9131, MICREL_PHY_ID_MASK },5610	{ PHY_ID_KSZ8001, 0x00fffffc },5611	{ PHY_ID_KS8737, MICREL_PHY_ID_MASK },5612	{ PHY_ID_KSZ8021, 0x00ffffff },5613	{ PHY_ID_KSZ8031, 0x00ffffff },5614	{ PHY_ID_KSZ8041, MICREL_PHY_ID_MASK },5615	{ PHY_ID_KSZ8051, MICREL_PHY_ID_MASK },5616	{ PHY_ID_KSZ8061, MICREL_PHY_ID_MASK },5617	{ PHY_ID_KSZ8081, MICREL_PHY_ID_MASK },5618	{ PHY_ID_KSZ8873MLL, MICREL_PHY_ID_MASK },5619	{ PHY_ID_KSZ886X, MICREL_PHY_ID_MASK },5620	{ PHY_ID_KSZ9477, MICREL_PHY_ID_MASK },5621	{ PHY_ID_LAN8814, MICREL_PHY_ID_MASK },5622	{ PHY_ID_LAN8804, MICREL_PHY_ID_MASK },5623	{ PHY_ID_LAN8841, MICREL_PHY_ID_MASK },5624	{ }5625};5626 5627MODULE_DEVICE_TABLE(mdio, micrel_tbl);5628