1901 lines · c
1// SPDX-License-Identifier: GPL-2.02// Copyright (C) 2018 Microchip Technology3 4#include <linux/kernel.h>5#include <linux/module.h>6#include <linux/delay.h>7#include <linux/mii.h>8#include <linux/phy.h>9#include <linux/ethtool.h>10#include <linux/ethtool_netlink.h>11#include <linux/bitfield.h>12 13#define PHY_ID_LAN87XX 0x0007c15014#define PHY_ID_LAN937X 0x0007c18015#define PHY_ID_LAN887X 0x0007c1f016 17/* External Register Control Register */18#define LAN87XX_EXT_REG_CTL (0x14)19#define LAN87XX_EXT_REG_CTL_RD_CTL (0x1000)20#define LAN87XX_EXT_REG_CTL_WR_CTL (0x0800)21#define LAN87XX_REG_BANK_SEL_MASK GENMASK(10, 8)22#define LAN87XX_REG_ADDR_MASK GENMASK(7, 0)23 24/* External Register Read Data Register */25#define LAN87XX_EXT_REG_RD_DATA (0x15)26 27/* External Register Write Data Register */28#define LAN87XX_EXT_REG_WR_DATA (0x16)29 30/* Interrupt Source Register */31#define LAN87XX_INTERRUPT_SOURCE (0x18)32#define LAN87XX_INTERRUPT_SOURCE_2 (0x08)33 34/* Interrupt Mask Register */35#define LAN87XX_INTERRUPT_MASK (0x19)36#define LAN87XX_MASK_LINK_UP (0x0004)37#define LAN87XX_MASK_LINK_DOWN (0x0002)38 39#define LAN87XX_INTERRUPT_MASK_2 (0x09)40#define LAN87XX_MASK_COMM_RDY BIT(10)41 42/* MISC Control 1 Register */43#define LAN87XX_CTRL_1 (0x11)44#define LAN87XX_MASK_RGMII_TXC_DLY_EN (0x4000)45#define LAN87XX_MASK_RGMII_RXC_DLY_EN (0x2000)46 47/* phyaccess nested types */48#define PHYACC_ATTR_MODE_READ 049#define PHYACC_ATTR_MODE_WRITE 150#define PHYACC_ATTR_MODE_MODIFY 251#define PHYACC_ATTR_MODE_POLL 352 53#define PHYACC_ATTR_BANK_SMI 054#define PHYACC_ATTR_BANK_MISC 155#define PHYACC_ATTR_BANK_PCS 256#define PHYACC_ATTR_BANK_AFE 357#define PHYACC_ATTR_BANK_DSP 458#define PHYACC_ATTR_BANK_MAX 759 60/* measurement defines */61#define LAN87XX_CABLE_TEST_OK 062#define LAN87XX_CABLE_TEST_OPEN 163#define LAN87XX_CABLE_TEST_SAME_SHORT 264 65/* T1 Registers */66#define T1_AFE_PORT_CFG1_REG 0x0B67#define T1_POWER_DOWN_CONTROL_REG 0x1A68#define T1_SLV_FD_MULT_CFG_REG 0x1869#define T1_CDR_CFG_PRE_LOCK_REG 0x0570#define T1_CDR_CFG_POST_LOCK_REG 0x0671#define T1_LCK_STG2_MUFACT_CFG_REG 0x1A72#define T1_LCK_STG3_MUFACT_CFG_REG 0x1B73#define T1_POST_LCK_MUFACT_CFG_REG 0x1C74#define T1_TX_RX_FIFO_CFG_REG 0x0275#define T1_TX_LPF_FIR_CFG_REG 0x5576#define T1_COEF_CLK_PWR_DN_CFG 0x0477#define T1_COEF_RW_CTL_CFG 0x0D78#define T1_SQI_CONFIG_REG 0x2E79#define T1_SQI_CONFIG2_REG 0x4A80#define T1_DCQ_SQI_REG 0xC381#define T1_DCQ_SQI_MSK GENMASK(3, 1)82#define T1_MDIO_CONTROL2_REG 0x1083#define T1_INTERRUPT_SOURCE_REG 0x1884#define T1_INTERRUPT2_SOURCE_REG 0x0885#define T1_EQ_FD_STG1_FRZ_CFG 0x6986#define T1_EQ_FD_STG2_FRZ_CFG 0x6A87#define T1_EQ_FD_STG3_FRZ_CFG 0x6B88#define T1_EQ_FD_STG4_FRZ_CFG 0x6C89#define T1_EQ_WT_FD_LCK_FRZ_CFG 0x6D90#define T1_PST_EQ_LCK_STG1_FRZ_CFG 0x6E91 92#define T1_MODE_STAT_REG 0x1193#define T1_LINK_UP_MSK BIT(0)94 95/* SQI defines */96#define LAN87XX_MAX_SQI 0x0797 98/* Chiptop registers */99#define LAN887X_PMA_EXT_ABILITY_2 0x12100#define LAN887X_PMA_EXT_ABILITY_2_1000T1 BIT(1)101#define LAN887X_PMA_EXT_ABILITY_2_100T1 BIT(0)102 103/* DSP 100M registers */104#define LAN887x_CDR_CONFIG1_100 0x0405105#define LAN887x_LOCK1_EQLSR_CONFIG_100 0x0411106#define LAN887x_SLV_HD_MUFAC_CONFIG_100 0x0417107#define LAN887x_PLOCK_MUFAC_CONFIG_100 0x041c108#define LAN887x_PROT_DISABLE_100 0x0425109#define LAN887x_KF_LOOP_SAT_CONFIG_100 0x0454110 111/* DSP 1000M registers */112#define LAN887X_LOCK1_EQLSR_CONFIG 0x0811113#define LAN887X_LOCK3_EQLSR_CONFIG 0x0813114#define LAN887X_PROT_DISABLE 0x0825115#define LAN887X_FFE_GAIN6 0x0843116#define LAN887X_FFE_GAIN7 0x0844117#define LAN887X_FFE_GAIN8 0x0845118#define LAN887X_FFE_GAIN9 0x0846119#define LAN887X_ECHO_DELAY_CONFIG 0x08ec120#define LAN887X_FFE_MAX_CONFIG 0x08ee121 122/* PCS 1000M registers */123#define LAN887X_SCR_CONFIG_3 0x8043124#define LAN887X_INFO_FLD_CONFIG_5 0x8048125 126/* T1 afe registers */127#define LAN887X_ZQCAL_CONTROL_1 0x8080128#define LAN887X_AFE_PORT_TESTBUS_CTRL2 0x8089129#define LAN887X_AFE_PORT_TESTBUS_CTRL4 0x808b130#define LAN887X_AFE_PORT_TESTBUS_CTRL6 0x808d131#define LAN887X_TX_AMPLT_1000T1_REG 0x80b0132#define LAN887X_INIT_COEFF_DFE1_100 0x0422133 134/* PMA registers */135#define LAN887X_DSP_PMA_CONTROL 0x810e136#define LAN887X_DSP_PMA_CONTROL_LNK_SYNC BIT(4)137 138/* PCS 100M registers */139#define LAN887X_IDLE_ERR_TIMER_WIN 0x8204140#define LAN887X_IDLE_ERR_CNT_THRESH 0x8213141 142/* Misc registers */143#define LAN887X_REG_REG26 0x001a144#define LAN887X_REG_REG26_HW_INIT_SEQ_EN BIT(8)145 146/* Mis registers */147#define LAN887X_MIS_CFG_REG0 0xa00148#define LAN887X_MIS_CFG_REG0_RCLKOUT_DIS BIT(5)149#define LAN887X_MIS_CFG_REG0_MAC_MODE_SEL GENMASK(1, 0)150 151#define LAN887X_MAC_MODE_RGMII 0x01152#define LAN887X_MAC_MODE_SGMII 0x03153 154#define LAN887X_MIS_DLL_CFG_REG0 0xa01155#define LAN887X_MIS_DLL_CFG_REG1 0xa02156 157#define LAN887X_MIS_DLL_DELAY_EN BIT(15)158#define LAN887X_MIS_DLL_EN BIT(0)159#define LAN887X_MIS_DLL_CONF (LAN887X_MIS_DLL_DELAY_EN |\160 LAN887X_MIS_DLL_EN)161 162#define LAN887X_MIS_CFG_REG2 0xa03163#define LAN887X_MIS_CFG_REG2_FE_LPBK_EN BIT(2)164 165#define LAN887X_MIS_PKT_STAT_REG0 0xa06166#define LAN887X_MIS_PKT_STAT_REG1 0xa07167#define LAN887X_MIS_PKT_STAT_REG3 0xa09168#define LAN887X_MIS_PKT_STAT_REG4 0xa0a169#define LAN887X_MIS_PKT_STAT_REG5 0xa0b170#define LAN887X_MIS_PKT_STAT_REG6 0xa0c171 172/* Chiptop common registers */173#define LAN887X_COMMON_LED3_LED2 0xc05174#define LAN887X_COMMON_LED2_MODE_SEL_MASK GENMASK(4, 0)175#define LAN887X_LED_LINK_ACT_ANY_SPEED 0x0176 177/* MX chip top registers */178#define LAN887X_CHIP_HARD_RST 0xf03e179#define LAN887X_CHIP_HARD_RST_RESET BIT(0)180 181#define LAN887X_CHIP_SOFT_RST 0xf03f182#define LAN887X_CHIP_SOFT_RST_RESET BIT(0)183 184#define LAN887X_SGMII_CTL 0xf01a185#define LAN887X_SGMII_CTL_SGMII_MUX_EN BIT(0)186 187#define LAN887X_SGMII_PCS_CFG 0xf034188#define LAN887X_SGMII_PCS_CFG_PCS_ENA BIT(9)189 190#define LAN887X_EFUSE_READ_DAT9 0xf209191#define LAN887X_EFUSE_READ_DAT9_SGMII_DIS BIT(9)192#define LAN887X_EFUSE_READ_DAT9_MAC_MODE GENMASK(1, 0)193 194#define LAN887X_CALIB_CONFIG_100 0x437195#define LAN887X_CALIB_CONFIG_100_CBL_DIAG_USE_LOCAL_SMPL BIT(5)196#define LAN887X_CALIB_CONFIG_100_CBL_DIAG_STB_SYNC_MODE BIT(4)197#define LAN887X_CALIB_CONFIG_100_CBL_DIAG_CLK_ALGN_MODE BIT(3)198#define LAN887X_CALIB_CONFIG_100_VAL \199 (LAN887X_CALIB_CONFIG_100_CBL_DIAG_CLK_ALGN_MODE |\200 LAN887X_CALIB_CONFIG_100_CBL_DIAG_STB_SYNC_MODE |\201 LAN887X_CALIB_CONFIG_100_CBL_DIAG_USE_LOCAL_SMPL)202 203#define LAN887X_MAX_PGA_GAIN_100 0x44f204#define LAN887X_MIN_PGA_GAIN_100 0x450205#define LAN887X_START_CBL_DIAG_100 0x45a206#define LAN887X_CBL_DIAG_DONE BIT(1)207#define LAN887X_CBL_DIAG_START BIT(0)208#define LAN887X_CBL_DIAG_STOP 0x0209 210#define LAN887X_CBL_DIAG_TDR_THRESH_100 0x45b211#define LAN887X_CBL_DIAG_AGC_THRESH_100 0x45c212#define LAN887X_CBL_DIAG_MIN_WAIT_CONFIG_100 0x45d213#define LAN887X_CBL_DIAG_MAX_WAIT_CONFIG_100 0x45e214#define LAN887X_CBL_DIAG_CYC_CONFIG_100 0x45f215#define LAN887X_CBL_DIAG_TX_PULSE_CONFIG_100 0x460216#define LAN887X_CBL_DIAG_MIN_PGA_GAIN_100 0x462217#define LAN887X_CBL_DIAG_AGC_GAIN_100 0x497218#define LAN887X_CBL_DIAG_POS_PEAK_VALUE_100 0x499219#define LAN887X_CBL_DIAG_NEG_PEAK_VALUE_100 0x49a220#define LAN887X_CBL_DIAG_POS_PEAK_TIME_100 0x49c221#define LAN887X_CBL_DIAG_NEG_PEAK_TIME_100 0x49d222 223#define MICROCHIP_CABLE_NOISE_MARGIN 20224#define MICROCHIP_CABLE_TIME_MARGIN 89225#define MICROCHIP_CABLE_MIN_TIME_DIFF 96226#define MICROCHIP_CABLE_MAX_TIME_DIFF \227 (MICROCHIP_CABLE_MIN_TIME_DIFF + MICROCHIP_CABLE_TIME_MARGIN)228 229#define DRIVER_AUTHOR "Nisar Sayed <nisar.sayed@microchip.com>"230#define DRIVER_DESC "Microchip LAN87XX/LAN937x/LAN887x T1 PHY driver"231 232/* TEST_MODE_NORMAL: Non-hybrid results to calculate cable status(open/short/ok)233 * TEST_MODE_HYBRID: Hybrid results to calculate distance to fault234 */235enum cable_diag_mode {236 TEST_MODE_NORMAL,237 TEST_MODE_HYBRID238};239 240/* CD_TEST_INIT: Cable test is initated241 * CD_TEST_DONE: Cable test is done242 */243enum cable_diag_state {244 CD_TEST_INIT,245 CD_TEST_DONE246};247 248struct access_ereg_val {249 u8 mode;250 u8 bank;251 u8 offset;252 u16 val;253 u16 mask;254};255 256struct lan887x_hw_stat {257 const char *string;258 u8 mmd;259 u16 reg;260 u8 bits;261};262 263static const struct lan887x_hw_stat lan887x_hw_stats[] = {264 { "TX Good Count", MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG0, 14},265 { "RX Good Count", MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG1, 14},266 { "RX ERR Count detected by PCS", MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG3, 16},267 { "TX CRC ERR Count", MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG4, 8},268 { "RX CRC ERR Count", MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG5, 8},269 { "RX ERR Count for SGMII MII2GMII", MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG6, 8},270};271 272struct lan887x_regwr_map {273 u8 mmd;274 u16 reg;275 u16 val;276};277 278struct lan887x_priv {279 u64 stats[ARRAY_SIZE(lan887x_hw_stats)];280};281 282static int lan937x_dsp_workaround(struct phy_device *phydev, u16 ereg, u8 bank)283{284 u8 prev_bank;285 int rc = 0;286 u16 val;287 288 mutex_lock(&phydev->lock);289 /* Read previous selected bank */290 rc = phy_read(phydev, LAN87XX_EXT_REG_CTL);291 if (rc < 0)292 goto out_unlock;293 294 /* store the prev_bank */295 prev_bank = FIELD_GET(LAN87XX_REG_BANK_SEL_MASK, rc);296 297 if (bank != prev_bank && bank == PHYACC_ATTR_BANK_DSP) {298 val = ereg & ~LAN87XX_REG_ADDR_MASK;299 300 val &= ~LAN87XX_EXT_REG_CTL_WR_CTL;301 val |= LAN87XX_EXT_REG_CTL_RD_CTL;302 303 /* access twice for DSP bank change,dummy access */304 rc = phy_write(phydev, LAN87XX_EXT_REG_CTL, val);305 }306 307out_unlock:308 mutex_unlock(&phydev->lock);309 310 return rc;311}312 313static int access_ereg(struct phy_device *phydev, u8 mode, u8 bank,314 u8 offset, u16 val)315{316 u16 ereg = 0;317 int rc = 0;318 319 if (mode > PHYACC_ATTR_MODE_WRITE || bank > PHYACC_ATTR_BANK_MAX)320 return -EINVAL;321 322 if (bank == PHYACC_ATTR_BANK_SMI) {323 if (mode == PHYACC_ATTR_MODE_WRITE)324 rc = phy_write(phydev, offset, val);325 else326 rc = phy_read(phydev, offset);327 return rc;328 }329 330 if (mode == PHYACC_ATTR_MODE_WRITE) {331 ereg = LAN87XX_EXT_REG_CTL_WR_CTL;332 rc = phy_write(phydev, LAN87XX_EXT_REG_WR_DATA, val);333 if (rc < 0)334 return rc;335 } else {336 ereg = LAN87XX_EXT_REG_CTL_RD_CTL;337 }338 339 ereg |= (bank << 8) | offset;340 341 /* DSP bank access workaround for lan937x */342 if (phydev->phy_id == PHY_ID_LAN937X) {343 rc = lan937x_dsp_workaround(phydev, ereg, bank);344 if (rc < 0)345 return rc;346 }347 348 rc = phy_write(phydev, LAN87XX_EXT_REG_CTL, ereg);349 if (rc < 0)350 return rc;351 352 if (mode == PHYACC_ATTR_MODE_READ)353 rc = phy_read(phydev, LAN87XX_EXT_REG_RD_DATA);354 355 return rc;356}357 358static int access_ereg_modify_changed(struct phy_device *phydev,359 u8 bank, u8 offset, u16 val, u16 mask)360{361 int new = 0, rc = 0;362 363 if (bank > PHYACC_ATTR_BANK_MAX)364 return -EINVAL;365 366 rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ, bank, offset, val);367 if (rc < 0)368 return rc;369 370 new = val | (rc & (mask ^ 0xFFFF));371 rc = access_ereg(phydev, PHYACC_ATTR_MODE_WRITE, bank, offset, new);372 373 return rc;374}375 376static int access_smi_poll_timeout(struct phy_device *phydev,377 u8 offset, u16 mask, u16 clr)378{379 int val;380 381 return phy_read_poll_timeout(phydev, offset, val, (val & mask) == clr,382 150, 30000, true);383}384 385static int lan87xx_config_rgmii_delay(struct phy_device *phydev)386{387 int rc;388 389 if (!phy_interface_is_rgmii(phydev))390 return 0;391 392 rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ,393 PHYACC_ATTR_BANK_MISC, LAN87XX_CTRL_1, 0);394 if (rc < 0)395 return rc;396 397 switch (phydev->interface) {398 case PHY_INTERFACE_MODE_RGMII:399 rc &= ~LAN87XX_MASK_RGMII_TXC_DLY_EN;400 rc &= ~LAN87XX_MASK_RGMII_RXC_DLY_EN;401 break;402 case PHY_INTERFACE_MODE_RGMII_ID:403 rc |= LAN87XX_MASK_RGMII_TXC_DLY_EN;404 rc |= LAN87XX_MASK_RGMII_RXC_DLY_EN;405 break;406 case PHY_INTERFACE_MODE_RGMII_RXID:407 rc &= ~LAN87XX_MASK_RGMII_TXC_DLY_EN;408 rc |= LAN87XX_MASK_RGMII_RXC_DLY_EN;409 break;410 case PHY_INTERFACE_MODE_RGMII_TXID:411 rc |= LAN87XX_MASK_RGMII_TXC_DLY_EN;412 rc &= ~LAN87XX_MASK_RGMII_RXC_DLY_EN;413 break;414 default:415 return 0;416 }417 418 return access_ereg(phydev, PHYACC_ATTR_MODE_WRITE,419 PHYACC_ATTR_BANK_MISC, LAN87XX_CTRL_1, rc);420}421 422static int lan87xx_phy_init_cmd(struct phy_device *phydev,423 const struct access_ereg_val *cmd_seq, int cnt)424{425 int ret, i;426 427 for (i = 0; i < cnt; i++) {428 if (cmd_seq[i].mode == PHYACC_ATTR_MODE_POLL &&429 cmd_seq[i].bank == PHYACC_ATTR_BANK_SMI) {430 ret = access_smi_poll_timeout(phydev,431 cmd_seq[i].offset,432 cmd_seq[i].val,433 cmd_seq[i].mask);434 } else {435 ret = access_ereg(phydev, cmd_seq[i].mode,436 cmd_seq[i].bank, cmd_seq[i].offset,437 cmd_seq[i].val);438 }439 if (ret < 0)440 return ret;441 }442 443 return ret;444}445 446static int lan87xx_phy_init(struct phy_device *phydev)447{448 static const struct access_ereg_val hw_init[] = {449 /* TXPD/TXAMP6 Configs */450 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_AFE,451 T1_AFE_PORT_CFG1_REG, 0x002D, 0 },452 /* HW_Init Hi and Force_ED */453 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_SMI,454 T1_POWER_DOWN_CONTROL_REG, 0x0308, 0 },455 };456 457 static const struct access_ereg_val slave_init[] = {458 /* Equalizer Full Duplex Freeze - T1 Slave */459 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,460 T1_EQ_FD_STG1_FRZ_CFG, 0x0002, 0 },461 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,462 T1_EQ_FD_STG2_FRZ_CFG, 0x0002, 0 },463 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,464 T1_EQ_FD_STG3_FRZ_CFG, 0x0002, 0 },465 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,466 T1_EQ_FD_STG4_FRZ_CFG, 0x0002, 0 },467 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,468 T1_EQ_WT_FD_LCK_FRZ_CFG, 0x0002, 0 },469 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,470 T1_PST_EQ_LCK_STG1_FRZ_CFG, 0x0002, 0 },471 };472 473 static const struct access_ereg_val phy_init[] = {474 /* Slave Full Duplex Multi Configs */475 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,476 T1_SLV_FD_MULT_CFG_REG, 0x0D53, 0 },477 /* CDR Pre and Post Lock Configs */478 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,479 T1_CDR_CFG_PRE_LOCK_REG, 0x0AB2, 0 },480 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,481 T1_CDR_CFG_POST_LOCK_REG, 0x0AB3, 0 },482 /* Lock Stage 2-3 Multi Factor Config */483 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,484 T1_LCK_STG2_MUFACT_CFG_REG, 0x0AEA, 0 },485 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,486 T1_LCK_STG3_MUFACT_CFG_REG, 0x0AEB, 0 },487 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,488 T1_POST_LCK_MUFACT_CFG_REG, 0x0AEB, 0 },489 /* Pointer delay */490 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,491 T1_TX_RX_FIFO_CFG_REG, 0x1C00, 0 },492 /* Tx iir edits */493 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,494 T1_TX_LPF_FIR_CFG_REG, 0x1000, 0 },495 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,496 T1_TX_LPF_FIR_CFG_REG, 0x1861, 0 },497 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,498 T1_TX_LPF_FIR_CFG_REG, 0x1061, 0 },499 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,500 T1_TX_LPF_FIR_CFG_REG, 0x1922, 0 },501 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,502 T1_TX_LPF_FIR_CFG_REG, 0x1122, 0 },503 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,504 T1_TX_LPF_FIR_CFG_REG, 0x1983, 0 },505 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,506 T1_TX_LPF_FIR_CFG_REG, 0x1183, 0 },507 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,508 T1_TX_LPF_FIR_CFG_REG, 0x1944, 0 },509 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,510 T1_TX_LPF_FIR_CFG_REG, 0x1144, 0 },511 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,512 T1_TX_LPF_FIR_CFG_REG, 0x18c5, 0 },513 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,514 T1_TX_LPF_FIR_CFG_REG, 0x10c5, 0 },515 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,516 T1_TX_LPF_FIR_CFG_REG, 0x1846, 0 },517 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,518 T1_TX_LPF_FIR_CFG_REG, 0x1046, 0 },519 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,520 T1_TX_LPF_FIR_CFG_REG, 0x1807, 0 },521 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,522 T1_TX_LPF_FIR_CFG_REG, 0x1007, 0 },523 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,524 T1_TX_LPF_FIR_CFG_REG, 0x1808, 0 },525 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,526 T1_TX_LPF_FIR_CFG_REG, 0x1008, 0 },527 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,528 T1_TX_LPF_FIR_CFG_REG, 0x1809, 0 },529 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,530 T1_TX_LPF_FIR_CFG_REG, 0x1009, 0 },531 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,532 T1_TX_LPF_FIR_CFG_REG, 0x180A, 0 },533 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,534 T1_TX_LPF_FIR_CFG_REG, 0x100A, 0 },535 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,536 T1_TX_LPF_FIR_CFG_REG, 0x180B, 0 },537 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,538 T1_TX_LPF_FIR_CFG_REG, 0x100B, 0 },539 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,540 T1_TX_LPF_FIR_CFG_REG, 0x180C, 0 },541 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,542 T1_TX_LPF_FIR_CFG_REG, 0x100C, 0 },543 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,544 T1_TX_LPF_FIR_CFG_REG, 0x180D, 0 },545 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,546 T1_TX_LPF_FIR_CFG_REG, 0x100D, 0 },547 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,548 T1_TX_LPF_FIR_CFG_REG, 0x180E, 0 },549 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,550 T1_TX_LPF_FIR_CFG_REG, 0x100E, 0 },551 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,552 T1_TX_LPF_FIR_CFG_REG, 0x180F, 0 },553 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,554 T1_TX_LPF_FIR_CFG_REG, 0x100F, 0 },555 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,556 T1_TX_LPF_FIR_CFG_REG, 0x1810, 0 },557 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,558 T1_TX_LPF_FIR_CFG_REG, 0x1010, 0 },559 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,560 T1_TX_LPF_FIR_CFG_REG, 0x1811, 0 },561 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,562 T1_TX_LPF_FIR_CFG_REG, 0x1011, 0 },563 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,564 T1_TX_LPF_FIR_CFG_REG, 0x1000, 0 },565 /* Setup SQI measurement */566 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,567 T1_COEF_CLK_PWR_DN_CFG, 0x16d6, 0 },568 /* SQI enable */569 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,570 T1_SQI_CONFIG_REG, 0x9572, 0 },571 /* SQI select mode 5 */572 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,573 T1_SQI_CONFIG2_REG, 0x0001, 0 },574 /* Throws the first SQI reading */575 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,576 T1_COEF_RW_CTL_CFG, 0x0301, 0 },577 { PHYACC_ATTR_MODE_READ, PHYACC_ATTR_BANK_DSP,578 T1_DCQ_SQI_REG, 0, 0 },579 /* Flag LPS and WUR as idle errors */580 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_SMI,581 T1_MDIO_CONTROL2_REG, 0x0014, 0 },582 /* HW_Init toggle, undo force ED, TXPD off */583 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_SMI,584 T1_POWER_DOWN_CONTROL_REG, 0x0200, 0 },585 /* Reset PCS to trigger hardware initialization */586 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_SMI,587 T1_MDIO_CONTROL2_REG, 0x0094, 0 },588 /* Poll till Hardware is initialized */589 { PHYACC_ATTR_MODE_POLL, PHYACC_ATTR_BANK_SMI,590 T1_MDIO_CONTROL2_REG, 0x0080, 0 },591 /* Tx AMP - 0x06 */592 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_AFE,593 T1_AFE_PORT_CFG1_REG, 0x000C, 0 },594 /* Read INTERRUPT_SOURCE Register */595 { PHYACC_ATTR_MODE_READ, PHYACC_ATTR_BANK_SMI,596 T1_INTERRUPT_SOURCE_REG, 0, 0 },597 /* Read INTERRUPT_SOURCE Register */598 { PHYACC_ATTR_MODE_READ, PHYACC_ATTR_BANK_MISC,599 T1_INTERRUPT2_SOURCE_REG, 0, 0 },600 /* HW_Init Hi */601 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_SMI,602 T1_POWER_DOWN_CONTROL_REG, 0x0300, 0 },603 };604 int rc;605 606 /* phy Soft reset */607 rc = genphy_soft_reset(phydev);608 if (rc < 0)609 return rc;610 611 /* PHY Initialization */612 rc = lan87xx_phy_init_cmd(phydev, hw_init, ARRAY_SIZE(hw_init));613 if (rc < 0)614 return rc;615 616 rc = genphy_read_master_slave(phydev);617 if (rc)618 return rc;619 620 /* The following squence needs to run only if phydev is in621 * slave mode.622 */623 if (phydev->master_slave_state == MASTER_SLAVE_STATE_SLAVE) {624 rc = lan87xx_phy_init_cmd(phydev, slave_init,625 ARRAY_SIZE(slave_init));626 if (rc < 0)627 return rc;628 }629 630 rc = lan87xx_phy_init_cmd(phydev, phy_init, ARRAY_SIZE(phy_init));631 if (rc < 0)632 return rc;633 634 return lan87xx_config_rgmii_delay(phydev);635}636 637static int lan87xx_phy_config_intr(struct phy_device *phydev)638{639 int rc, val = 0;640 641 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {642 /* clear all interrupt */643 rc = phy_write(phydev, LAN87XX_INTERRUPT_MASK, val);644 if (rc < 0)645 return rc;646 647 rc = phy_read(phydev, LAN87XX_INTERRUPT_SOURCE);648 if (rc < 0)649 return rc;650 651 rc = access_ereg(phydev, PHYACC_ATTR_MODE_WRITE,652 PHYACC_ATTR_BANK_MISC,653 LAN87XX_INTERRUPT_MASK_2, val);654 if (rc < 0)655 return rc;656 657 rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ,658 PHYACC_ATTR_BANK_MISC,659 LAN87XX_INTERRUPT_SOURCE_2, 0);660 if (rc < 0)661 return rc;662 663 /* enable link down and comm ready interrupt */664 val = LAN87XX_MASK_LINK_DOWN;665 rc = phy_write(phydev, LAN87XX_INTERRUPT_MASK, val);666 if (rc < 0)667 return rc;668 669 val = LAN87XX_MASK_COMM_RDY;670 rc = access_ereg(phydev, PHYACC_ATTR_MODE_WRITE,671 PHYACC_ATTR_BANK_MISC,672 LAN87XX_INTERRUPT_MASK_2, val);673 } else {674 rc = phy_write(phydev, LAN87XX_INTERRUPT_MASK, val);675 if (rc < 0)676 return rc;677 678 rc = phy_read(phydev, LAN87XX_INTERRUPT_SOURCE);679 if (rc < 0)680 return rc;681 682 rc = access_ereg(phydev, PHYACC_ATTR_MODE_WRITE,683 PHYACC_ATTR_BANK_MISC,684 LAN87XX_INTERRUPT_MASK_2, val);685 if (rc < 0)686 return rc;687 688 rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ,689 PHYACC_ATTR_BANK_MISC,690 LAN87XX_INTERRUPT_SOURCE_2, 0);691 }692 693 return rc < 0 ? rc : 0;694}695 696static irqreturn_t lan87xx_handle_interrupt(struct phy_device *phydev)697{698 int irq_status;699 700 irq_status = access_ereg(phydev, PHYACC_ATTR_MODE_READ,701 PHYACC_ATTR_BANK_MISC,702 LAN87XX_INTERRUPT_SOURCE_2, 0);703 if (irq_status < 0) {704 phy_error(phydev);705 return IRQ_NONE;706 }707 708 irq_status = phy_read(phydev, LAN87XX_INTERRUPT_SOURCE);709 if (irq_status < 0) {710 phy_error(phydev);711 return IRQ_NONE;712 }713 714 if (irq_status == 0)715 return IRQ_NONE;716 717 phy_trigger_machine(phydev);718 719 return IRQ_HANDLED;720}721 722static int lan87xx_config_init(struct phy_device *phydev)723{724 int rc = lan87xx_phy_init(phydev);725 726 return rc < 0 ? rc : 0;727}728 729static int microchip_cable_test_start_common(struct phy_device *phydev)730{731 int bmcr, bmsr, ret;732 733 /* If auto-negotiation is enabled, but not complete, the cable734 * test never completes. So disable auto-neg.735 */736 bmcr = phy_read(phydev, MII_BMCR);737 if (bmcr < 0)738 return bmcr;739 740 bmsr = phy_read(phydev, MII_BMSR);741 742 if (bmsr < 0)743 return bmsr;744 745 if (bmcr & BMCR_ANENABLE) {746 ret = phy_modify(phydev, MII_BMCR, BMCR_ANENABLE, 0);747 if (ret < 0)748 return ret;749 ret = genphy_soft_reset(phydev);750 if (ret < 0)751 return ret;752 }753 754 /* If the link is up, allow it some time to go down */755 if (bmsr & BMSR_LSTATUS)756 msleep(1500);757 758 return 0;759}760 761static int lan87xx_cable_test_start(struct phy_device *phydev)762{763 static const struct access_ereg_val cable_test[] = {764 /* min wait */765 {PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 93,766 0, 0},767 /* max wait */768 {PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 94,769 10, 0},770 /* pulse cycle */771 {PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 95,772 90, 0},773 /* cable diag thresh */774 {PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 92,775 60, 0},776 /* max gain */777 {PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 79,778 31, 0},779 /* clock align for each iteration */780 {PHYACC_ATTR_MODE_MODIFY, PHYACC_ATTR_BANK_DSP, 55,781 0, 0x0038},782 /* max cycle wait config */783 {PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 94,784 70, 0},785 /* start cable diag*/786 {PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 90,787 1, 0},788 };789 int rc, i;790 791 rc = microchip_cable_test_start_common(phydev);792 if (rc < 0)793 return rc;794 795 /* start cable diag */796 /* check if part is alive - if not, return diagnostic error */797 rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ, PHYACC_ATTR_BANK_SMI,798 0x00, 0);799 if (rc < 0)800 return rc;801 802 /* master/slave specific configs */803 rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ, PHYACC_ATTR_BANK_SMI,804 0x0A, 0);805 if (rc < 0)806 return rc;807 808 if ((rc & 0x4000) != 0x4000) {809 /* DUT is Slave */810 rc = access_ereg_modify_changed(phydev, PHYACC_ATTR_BANK_AFE,811 0x0E, 0x5, 0x7);812 if (rc < 0)813 return rc;814 rc = access_ereg_modify_changed(phydev, PHYACC_ATTR_BANK_SMI,815 0x1A, 0x8, 0x8);816 if (rc < 0)817 return rc;818 } else {819 /* DUT is Master */820 rc = access_ereg_modify_changed(phydev, PHYACC_ATTR_BANK_SMI,821 0x10, 0x8, 0x40);822 if (rc < 0)823 return rc;824 }825 826 for (i = 0; i < ARRAY_SIZE(cable_test); i++) {827 if (cable_test[i].mode == PHYACC_ATTR_MODE_MODIFY) {828 rc = access_ereg_modify_changed(phydev,829 cable_test[i].bank,830 cable_test[i].offset,831 cable_test[i].val,832 cable_test[i].mask);833 /* wait 50ms */834 msleep(50);835 } else {836 rc = access_ereg(phydev, cable_test[i].mode,837 cable_test[i].bank,838 cable_test[i].offset,839 cable_test[i].val);840 }841 if (rc < 0)842 return rc;843 }844 /* cable diag started */845 846 return 0;847}848 849static int lan87xx_cable_test_report_trans(u32 result)850{851 switch (result) {852 case LAN87XX_CABLE_TEST_OK:853 return ETHTOOL_A_CABLE_RESULT_CODE_OK;854 case LAN87XX_CABLE_TEST_OPEN:855 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;856 case LAN87XX_CABLE_TEST_SAME_SHORT:857 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;858 default:859 /* DIAGNOSTIC_ERROR */860 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;861 }862}863 864static int lan87xx_cable_test_report(struct phy_device *phydev)865{866 int pos_peak_cycle = 0, pos_peak_in_phases = 0, pos_peak_phase = 0;867 int neg_peak_cycle = 0, neg_peak_in_phases = 0, neg_peak_phase = 0;868 int noise_margin = 20, time_margin = 89, jitter_var = 30;869 int min_time_diff = 96, max_time_diff = 96 + time_margin;870 bool fault = false, check_a = false, check_b = false;871 int gain_idx = 0, pos_peak = 0, neg_peak = 0;872 int pos_peak_time = 0, neg_peak_time = 0;873 int pos_peak_in_phases_hybrid = 0;874 int detect = -1;875 876 gain_idx = access_ereg(phydev, PHYACC_ATTR_MODE_READ,877 PHYACC_ATTR_BANK_DSP, 151, 0);878 /* read non-hybrid results */879 pos_peak = access_ereg(phydev, PHYACC_ATTR_MODE_READ,880 PHYACC_ATTR_BANK_DSP, 153, 0);881 neg_peak = access_ereg(phydev, PHYACC_ATTR_MODE_READ,882 PHYACC_ATTR_BANK_DSP, 154, 0);883 pos_peak_time = access_ereg(phydev, PHYACC_ATTR_MODE_READ,884 PHYACC_ATTR_BANK_DSP, 156, 0);885 neg_peak_time = access_ereg(phydev, PHYACC_ATTR_MODE_READ,886 PHYACC_ATTR_BANK_DSP, 157, 0);887 888 pos_peak_cycle = (pos_peak_time >> 7) & 0x7F;889 /* calculate non-hybrid values */890 pos_peak_phase = pos_peak_time & 0x7F;891 pos_peak_in_phases = (pos_peak_cycle * 96) + pos_peak_phase;892 neg_peak_cycle = (neg_peak_time >> 7) & 0x7F;893 neg_peak_phase = neg_peak_time & 0x7F;894 neg_peak_in_phases = (neg_peak_cycle * 96) + neg_peak_phase;895 896 /* process values */897 check_a =898 ((pos_peak_in_phases - neg_peak_in_phases) >= min_time_diff) &&899 ((pos_peak_in_phases - neg_peak_in_phases) < max_time_diff) &&900 pos_peak_in_phases_hybrid < pos_peak_in_phases &&901 (pos_peak_in_phases_hybrid < (neg_peak_in_phases + jitter_var));902 check_b =903 ((neg_peak_in_phases - pos_peak_in_phases) >= min_time_diff) &&904 ((neg_peak_in_phases - pos_peak_in_phases) < max_time_diff) &&905 pos_peak_in_phases_hybrid < neg_peak_in_phases &&906 (pos_peak_in_phases_hybrid < (pos_peak_in_phases + jitter_var));907 908 if (pos_peak_in_phases > neg_peak_in_phases && check_a)909 detect = 2;910 else if ((neg_peak_in_phases > pos_peak_in_phases) && check_b)911 detect = 1;912 913 if (pos_peak > noise_margin && neg_peak > noise_margin &&914 gain_idx >= 0) {915 if (detect == 1 || detect == 2)916 fault = true;917 }918 919 if (!fault)920 detect = 0;921 922 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A,923 lan87xx_cable_test_report_trans(detect));924 925 return phy_init_hw(phydev);926}927 928static int lan87xx_cable_test_get_status(struct phy_device *phydev,929 bool *finished)930{931 int rc = 0;932 933 *finished = false;934 935 /* check if cable diag was finished */936 rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ, PHYACC_ATTR_BANK_DSP,937 90, 0);938 if (rc < 0)939 return rc;940 941 if ((rc & 2) == 2) {942 /* stop cable diag*/943 rc = access_ereg(phydev, PHYACC_ATTR_MODE_WRITE,944 PHYACC_ATTR_BANK_DSP,945 90, 0);946 if (rc < 0)947 return rc;948 949 *finished = true;950 951 return lan87xx_cable_test_report(phydev);952 }953 954 return 0;955}956 957static int lan87xx_read_status(struct phy_device *phydev)958{959 int rc = 0;960 961 rc = phy_read(phydev, T1_MODE_STAT_REG);962 if (rc < 0)963 return rc;964 965 if (rc & T1_LINK_UP_MSK)966 phydev->link = 1;967 else968 phydev->link = 0;969 970 phydev->speed = SPEED_UNKNOWN;971 phydev->duplex = DUPLEX_UNKNOWN;972 phydev->pause = 0;973 phydev->asym_pause = 0;974 975 rc = genphy_read_master_slave(phydev);976 if (rc < 0)977 return rc;978 979 rc = genphy_read_status_fixed(phydev);980 if (rc < 0)981 return rc;982 983 return rc;984}985 986static int lan87xx_config_aneg(struct phy_device *phydev)987{988 u16 ctl = 0;989 int ret;990 991 switch (phydev->master_slave_set) {992 case MASTER_SLAVE_CFG_MASTER_FORCE:993 ctl |= CTL1000_AS_MASTER;994 break;995 case MASTER_SLAVE_CFG_SLAVE_FORCE:996 break;997 case MASTER_SLAVE_CFG_UNKNOWN:998 case MASTER_SLAVE_CFG_UNSUPPORTED:999 return 0;1000 default:1001 phydev_warn(phydev, "Unsupported Master/Slave mode\n");1002 return -EOPNOTSUPP;1003 }1004 1005 ret = phy_modify_changed(phydev, MII_CTRL1000, CTL1000_AS_MASTER, ctl);1006 if (ret == 1)1007 return phy_init_hw(phydev);1008 1009 return ret;1010}1011 1012static int lan87xx_get_sqi(struct phy_device *phydev)1013{1014 u8 sqi_value = 0;1015 int rc;1016 1017 rc = access_ereg(phydev, PHYACC_ATTR_MODE_WRITE,1018 PHYACC_ATTR_BANK_DSP, T1_COEF_RW_CTL_CFG, 0x0301);1019 if (rc < 0)1020 return rc;1021 1022 rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ,1023 PHYACC_ATTR_BANK_DSP, T1_DCQ_SQI_REG, 0x0);1024 if (rc < 0)1025 return rc;1026 1027 sqi_value = FIELD_GET(T1_DCQ_SQI_MSK, rc);1028 1029 return sqi_value;1030}1031 1032static int lan87xx_get_sqi_max(struct phy_device *phydev)1033{1034 return LAN87XX_MAX_SQI;1035}1036 1037static int lan887x_rgmii_init(struct phy_device *phydev)1038{1039 int ret;1040 1041 /* SGMII mux disable */1042 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,1043 LAN887X_SGMII_CTL,1044 LAN887X_SGMII_CTL_SGMII_MUX_EN);1045 if (ret < 0)1046 return ret;1047 1048 /* Select MAC_MODE as RGMII */1049 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, LAN887X_MIS_CFG_REG0,1050 LAN887X_MIS_CFG_REG0_MAC_MODE_SEL,1051 LAN887X_MAC_MODE_RGMII);1052 if (ret < 0)1053 return ret;1054 1055 /* Disable PCS */1056 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,1057 LAN887X_SGMII_PCS_CFG,1058 LAN887X_SGMII_PCS_CFG_PCS_ENA);1059 if (ret < 0)1060 return ret;1061 1062 /* LAN887x Errata: RGMII rx clock active in SGMII mode1063 * Disabled it for SGMII mode1064 * Re-enabling it for RGMII mode1065 */1066 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,1067 LAN887X_MIS_CFG_REG0,1068 LAN887X_MIS_CFG_REG0_RCLKOUT_DIS);1069}1070 1071static int lan887x_sgmii_init(struct phy_device *phydev)1072{1073 int ret;1074 1075 /* SGMII mux enable */1076 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,1077 LAN887X_SGMII_CTL,1078 LAN887X_SGMII_CTL_SGMII_MUX_EN);1079 if (ret < 0)1080 return ret;1081 1082 /* Select MAC_MODE as SGMII */1083 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, LAN887X_MIS_CFG_REG0,1084 LAN887X_MIS_CFG_REG0_MAC_MODE_SEL,1085 LAN887X_MAC_MODE_SGMII);1086 if (ret < 0)1087 return ret;1088 1089 /* LAN887x Errata: RGMII rx clock active in SGMII mode.1090 * So disabling it for SGMII mode1091 */1092 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, LAN887X_MIS_CFG_REG0,1093 LAN887X_MIS_CFG_REG0_RCLKOUT_DIS);1094 if (ret < 0)1095 return ret;1096 1097 /* Enable PCS */1098 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, LAN887X_SGMII_PCS_CFG,1099 LAN887X_SGMII_PCS_CFG_PCS_ENA);1100}1101 1102static int lan887x_config_rgmii_en(struct phy_device *phydev)1103{1104 int txc;1105 int rxc;1106 int ret;1107 1108 ret = lan887x_rgmii_init(phydev);1109 if (ret < 0)1110 return ret;1111 1112 /* Control bit to enable/disable TX DLL delay line in signal path */1113 txc = phy_read_mmd(phydev, MDIO_MMD_VEND1, LAN887X_MIS_DLL_CFG_REG0);1114 if (txc < 0)1115 return txc;1116 1117 /* Control bit to enable/disable RX DLL delay line in signal path */1118 rxc = phy_read_mmd(phydev, MDIO_MMD_VEND1, LAN887X_MIS_DLL_CFG_REG1);1119 if (rxc < 0)1120 return rxc;1121 1122 /* Configures the phy to enable RX/TX delay1123 * RGMII - TX & RX delays are either added by MAC or not needed,1124 * phy should not add1125 * RGMII_ID - Configures phy to enable TX & RX delays, MAC shouldn't add1126 * RGMII_RX_ID - Configures the PHY to enable the RX delay.1127 * The MAC shouldn't add the RX delay1128 * RGMII_TX_ID - Configures the PHY to enable the TX delay.1129 * The MAC shouldn't add the TX delay in this case1130 */1131 switch (phydev->interface) {1132 case PHY_INTERFACE_MODE_RGMII:1133 txc &= ~LAN887X_MIS_DLL_CONF;1134 rxc &= ~LAN887X_MIS_DLL_CONF;1135 break;1136 case PHY_INTERFACE_MODE_RGMII_ID:1137 txc |= LAN887X_MIS_DLL_CONF;1138 rxc |= LAN887X_MIS_DLL_CONF;1139 break;1140 case PHY_INTERFACE_MODE_RGMII_RXID:1141 txc &= ~LAN887X_MIS_DLL_CONF;1142 rxc |= LAN887X_MIS_DLL_CONF;1143 break;1144 case PHY_INTERFACE_MODE_RGMII_TXID:1145 txc |= LAN887X_MIS_DLL_CONF;1146 rxc &= ~LAN887X_MIS_DLL_CONF;1147 break;1148 default:1149 WARN_ONCE(1, "Invalid phydev interface %d\n", phydev->interface);1150 return 0;1151 }1152 1153 /* Configures the PHY to enable/disable RX delay in signal path */1154 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, LAN887X_MIS_DLL_CFG_REG1,1155 LAN887X_MIS_DLL_CONF, rxc);1156 if (ret < 0)1157 return ret;1158 1159 /* Configures the PHY to enable/disable the TX delay in signal path */1160 return phy_modify_mmd(phydev, MDIO_MMD_VEND1, LAN887X_MIS_DLL_CFG_REG0,1161 LAN887X_MIS_DLL_CONF, txc);1162}1163 1164static int lan887x_config_phy_interface(struct phy_device *phydev)1165{1166 int interface_mode;1167 int sgmii_dis;1168 int ret;1169 1170 /* Read sku efuse data for interfaces supported by sku */1171 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, LAN887X_EFUSE_READ_DAT9);1172 if (ret < 0)1173 return ret;1174 1175 /* If interface_mode is 1 then efuse sets RGMII operations.1176 * If interface mode is 3 then efuse sets SGMII operations.1177 */1178 interface_mode = ret & LAN887X_EFUSE_READ_DAT9_MAC_MODE;1179 /* SGMII disable is set for RGMII operations */1180 sgmii_dis = ret & LAN887X_EFUSE_READ_DAT9_SGMII_DIS;1181 1182 switch (phydev->interface) {1183 case PHY_INTERFACE_MODE_RGMII:1184 case PHY_INTERFACE_MODE_RGMII_ID:1185 case PHY_INTERFACE_MODE_RGMII_RXID:1186 case PHY_INTERFACE_MODE_RGMII_TXID:1187 /* Reject RGMII settings for SGMII only sku */1188 ret = -EOPNOTSUPP;1189 1190 if (!((interface_mode & LAN887X_MAC_MODE_SGMII) ==1191 LAN887X_MAC_MODE_SGMII))1192 ret = lan887x_config_rgmii_en(phydev);1193 break;1194 case PHY_INTERFACE_MODE_SGMII:1195 /* Reject SGMII setting for RGMII only sku */1196 ret = -EOPNOTSUPP;1197 1198 if (!sgmii_dis)1199 ret = lan887x_sgmii_init(phydev);1200 break;1201 default:1202 /* Reject setting for unsupported interfaces */1203 ret = -EOPNOTSUPP;1204 }1205 1206 return ret;1207}1208 1209static int lan887x_get_features(struct phy_device *phydev)1210{1211 int ret;1212 1213 ret = genphy_c45_pma_read_abilities(phydev);1214 if (ret < 0)1215 return ret;1216 1217 /* Enable twisted pair */1218 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, phydev->supported);1219 1220 /* First patch only supports 100Mbps and 1000Mbps force-mode.1221 * T1 Auto-Negotiation (Clause 98 of IEEE 802.3) will be added later.1222 */1223 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported);1224 1225 return 0;1226}1227 1228static int lan887x_phy_init(struct phy_device *phydev)1229{1230 int ret;1231 1232 /* Clear loopback */1233 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,1234 LAN887X_MIS_CFG_REG2,1235 LAN887X_MIS_CFG_REG2_FE_LPBK_EN);1236 if (ret < 0)1237 return ret;1238 1239 /* Configure default behavior of led to link and activity for any1240 * speed1241 */1242 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1,1243 LAN887X_COMMON_LED3_LED2,1244 LAN887X_COMMON_LED2_MODE_SEL_MASK,1245 LAN887X_LED_LINK_ACT_ANY_SPEED);1246 if (ret < 0)1247 return ret;1248 1249 /* PHY interface setup */1250 return lan887x_config_phy_interface(phydev);1251}1252 1253static int lan887x_phy_config(struct phy_device *phydev,1254 const struct lan887x_regwr_map *reg_map, int cnt)1255{1256 int ret;1257 1258 for (int i = 0; i < cnt; i++) {1259 ret = phy_write_mmd(phydev, reg_map[i].mmd,1260 reg_map[i].reg, reg_map[i].val);1261 if (ret < 0)1262 return ret;1263 }1264 1265 return 0;1266}1267 1268static int lan887x_phy_setup(struct phy_device *phydev)1269{1270 static const struct lan887x_regwr_map phy_cfg[] = {1271 /* PORT_AFE writes */1272 {MDIO_MMD_PMAPMD, LAN887X_ZQCAL_CONTROL_1, 0x4008},1273 {MDIO_MMD_PMAPMD, LAN887X_AFE_PORT_TESTBUS_CTRL2, 0x0000},1274 {MDIO_MMD_PMAPMD, LAN887X_AFE_PORT_TESTBUS_CTRL6, 0x0040},1275 /* 100T1_PCS_VENDOR writes */1276 {MDIO_MMD_PCS, LAN887X_IDLE_ERR_CNT_THRESH, 0x0008},1277 {MDIO_MMD_PCS, LAN887X_IDLE_ERR_TIMER_WIN, 0x800d},1278 /* 100T1 DSP writes */1279 {MDIO_MMD_VEND1, LAN887x_CDR_CONFIG1_100, 0x0ab1},1280 {MDIO_MMD_VEND1, LAN887x_LOCK1_EQLSR_CONFIG_100, 0x5274},1281 {MDIO_MMD_VEND1, LAN887x_SLV_HD_MUFAC_CONFIG_100, 0x0d74},1282 {MDIO_MMD_VEND1, LAN887x_PLOCK_MUFAC_CONFIG_100, 0x0aea},1283 {MDIO_MMD_VEND1, LAN887x_PROT_DISABLE_100, 0x0360},1284 {MDIO_MMD_VEND1, LAN887x_KF_LOOP_SAT_CONFIG_100, 0x0c30},1285 /* 1000T1 DSP writes */1286 {MDIO_MMD_VEND1, LAN887X_LOCK1_EQLSR_CONFIG, 0x2a78},1287 {MDIO_MMD_VEND1, LAN887X_LOCK3_EQLSR_CONFIG, 0x1368},1288 {MDIO_MMD_VEND1, LAN887X_PROT_DISABLE, 0x1354},1289 {MDIO_MMD_VEND1, LAN887X_FFE_GAIN6, 0x3C84},1290 {MDIO_MMD_VEND1, LAN887X_FFE_GAIN7, 0x3ca5},1291 {MDIO_MMD_VEND1, LAN887X_FFE_GAIN8, 0x3ca5},1292 {MDIO_MMD_VEND1, LAN887X_FFE_GAIN9, 0x3ca5},1293 {MDIO_MMD_VEND1, LAN887X_ECHO_DELAY_CONFIG, 0x0024},1294 {MDIO_MMD_VEND1, LAN887X_FFE_MAX_CONFIG, 0x227f},1295 /* 1000T1 PCS writes */1296 {MDIO_MMD_PCS, LAN887X_SCR_CONFIG_3, 0x1e00},1297 {MDIO_MMD_PCS, LAN887X_INFO_FLD_CONFIG_5, 0x0fa1},1298 };1299 1300 return lan887x_phy_config(phydev, phy_cfg, ARRAY_SIZE(phy_cfg));1301}1302 1303static int lan887x_100M_setup(struct phy_device *phydev)1304{1305 int ret;1306 1307 /* (Re)configure the speed/mode dependent T1 settings */1308 if (phydev->master_slave_set == MASTER_SLAVE_CFG_MASTER_FORCE ||1309 phydev->master_slave_set == MASTER_SLAVE_CFG_MASTER_PREFERRED){1310 static const struct lan887x_regwr_map phy_cfg[] = {1311 {MDIO_MMD_PMAPMD, LAN887X_AFE_PORT_TESTBUS_CTRL4, 0x00b8},1312 {MDIO_MMD_PMAPMD, LAN887X_TX_AMPLT_1000T1_REG, 0x0038},1313 {MDIO_MMD_VEND1, LAN887X_INIT_COEFF_DFE1_100, 0x000f},1314 };1315 1316 ret = lan887x_phy_config(phydev, phy_cfg, ARRAY_SIZE(phy_cfg));1317 } else {1318 static const struct lan887x_regwr_map phy_cfg[] = {1319 {MDIO_MMD_PMAPMD, LAN887X_AFE_PORT_TESTBUS_CTRL4, 0x0038},1320 {MDIO_MMD_VEND1, LAN887X_INIT_COEFF_DFE1_100, 0x0014},1321 };1322 1323 ret = lan887x_phy_config(phydev, phy_cfg, ARRAY_SIZE(phy_cfg));1324 }1325 if (ret < 0)1326 return ret;1327 1328 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, LAN887X_REG_REG26,1329 LAN887X_REG_REG26_HW_INIT_SEQ_EN);1330}1331 1332static int lan887x_1000M_setup(struct phy_device *phydev)1333{1334 static const struct lan887x_regwr_map phy_cfg[] = {1335 {MDIO_MMD_PMAPMD, LAN887X_TX_AMPLT_1000T1_REG, 0x003f},1336 {MDIO_MMD_PMAPMD, LAN887X_AFE_PORT_TESTBUS_CTRL4, 0x00b8},1337 };1338 int ret;1339 1340 /* (Re)configure the speed/mode dependent T1 settings */1341 ret = lan887x_phy_config(phydev, phy_cfg, ARRAY_SIZE(phy_cfg));1342 if (ret < 0)1343 return ret;1344 1345 return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, LAN887X_DSP_PMA_CONTROL,1346 LAN887X_DSP_PMA_CONTROL_LNK_SYNC);1347}1348 1349static int lan887x_link_setup(struct phy_device *phydev)1350{1351 int ret = -EINVAL;1352 1353 if (phydev->speed == SPEED_1000)1354 ret = lan887x_1000M_setup(phydev);1355 else if (phydev->speed == SPEED_100)1356 ret = lan887x_100M_setup(phydev);1357 1358 return ret;1359}1360 1361/* LAN887x Errata: speed configuration changes require soft reset1362 * and chip soft reset1363 */1364static int lan887x_phy_reset(struct phy_device *phydev)1365{1366 int ret, val;1367 1368 /* Clear 1000M link sync */1369 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, LAN887X_DSP_PMA_CONTROL,1370 LAN887X_DSP_PMA_CONTROL_LNK_SYNC);1371 if (ret < 0)1372 return ret;1373 1374 /* Clear 100M link sync */1375 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, LAN887X_REG_REG26,1376 LAN887X_REG_REG26_HW_INIT_SEQ_EN);1377 if (ret < 0)1378 return ret;1379 1380 /* Chiptop soft-reset to allow the speed/mode change */1381 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, LAN887X_CHIP_SOFT_RST,1382 LAN887X_CHIP_SOFT_RST_RESET);1383 if (ret < 0)1384 return ret;1385 1386 /* CL22 soft-reset to let the link re-train */1387 ret = phy_modify(phydev, MII_BMCR, BMCR_RESET, BMCR_RESET);1388 if (ret < 0)1389 return ret;1390 1391 /* Wait for reset complete or timeout if > 10ms */1392 return phy_read_poll_timeout(phydev, MII_BMCR, val, !(val & BMCR_RESET),1393 5000, 10000, true);1394}1395 1396static int lan887x_phy_reconfig(struct phy_device *phydev)1397{1398 int ret;1399 1400 linkmode_zero(phydev->advertising);1401 1402 ret = genphy_c45_pma_setup_forced(phydev);1403 if (ret < 0)1404 return ret;1405 1406 return lan887x_link_setup(phydev);1407}1408 1409static int lan887x_config_aneg(struct phy_device *phydev)1410{1411 int ret;1412 1413 /* LAN887x Errata: speed configuration changes require soft reset1414 * and chip soft reset1415 */1416 ret = lan887x_phy_reset(phydev);1417 if (ret < 0)1418 return ret;1419 1420 return lan887x_phy_reconfig(phydev);1421}1422 1423static int lan887x_probe(struct phy_device *phydev)1424{1425 struct lan887x_priv *priv;1426 1427 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);1428 if (!priv)1429 return -ENOMEM;1430 1431 phydev->priv = priv;1432 1433 return lan887x_phy_setup(phydev);1434}1435 1436static u64 lan887x_get_stat(struct phy_device *phydev, int i)1437{1438 struct lan887x_hw_stat stat = lan887x_hw_stats[i];1439 struct lan887x_priv *priv = phydev->priv;1440 int val;1441 u64 ret;1442 1443 if (stat.mmd)1444 val = phy_read_mmd(phydev, stat.mmd, stat.reg);1445 else1446 val = phy_read(phydev, stat.reg);1447 1448 if (val < 0) {1449 ret = U64_MAX;1450 } else {1451 val = val & ((1 << stat.bits) - 1);1452 priv->stats[i] += val;1453 ret = priv->stats[i];1454 }1455 1456 return ret;1457}1458 1459static void lan887x_get_stats(struct phy_device *phydev,1460 struct ethtool_stats *stats, u64 *data)1461{1462 for (int i = 0; i < ARRAY_SIZE(lan887x_hw_stats); i++)1463 data[i] = lan887x_get_stat(phydev, i);1464}1465 1466static int lan887x_get_sset_count(struct phy_device *phydev)1467{1468 return ARRAY_SIZE(lan887x_hw_stats);1469}1470 1471static void lan887x_get_strings(struct phy_device *phydev, u8 *data)1472{1473 for (int i = 0; i < ARRAY_SIZE(lan887x_hw_stats); i++)1474 ethtool_puts(&data, lan887x_hw_stats[i].string);1475}1476 1477static int lan887x_cd_reset(struct phy_device *phydev,1478 enum cable_diag_state cd_done)1479{1480 u16 val;1481 int rc;1482 1483 /* Chip hard-reset */1484 rc = phy_write_mmd(phydev, MDIO_MMD_VEND1, LAN887X_CHIP_HARD_RST,1485 LAN887X_CHIP_HARD_RST_RESET);1486 if (rc < 0)1487 return rc;1488 1489 /* Wait for reset to complete */1490 rc = phy_read_poll_timeout(phydev, MII_PHYSID2, val,1491 ((val & GENMASK(15, 4)) ==1492 (PHY_ID_LAN887X & GENMASK(15, 4))),1493 5000, 50000, true);1494 if (rc < 0)1495 return rc;1496 1497 if (cd_done == CD_TEST_DONE) {1498 /* Cable diagnostics complete. Restore PHY. */1499 rc = lan887x_phy_setup(phydev);1500 if (rc < 0)1501 return rc;1502 1503 rc = lan887x_phy_init(phydev);1504 if (rc < 0)1505 return rc;1506 1507 rc = lan887x_phy_reconfig(phydev);1508 if (rc < 0)1509 return rc;1510 }1511 1512 return 0;1513}1514 1515static int lan887x_cable_test_prep(struct phy_device *phydev,1516 enum cable_diag_mode mode)1517{1518 static const struct lan887x_regwr_map values[] = {1519 {MDIO_MMD_VEND1, LAN887X_MAX_PGA_GAIN_100, 0x1f},1520 {MDIO_MMD_VEND1, LAN887X_MIN_PGA_GAIN_100, 0x0},1521 {MDIO_MMD_VEND1, LAN887X_CBL_DIAG_TDR_THRESH_100, 0x1},1522 {MDIO_MMD_VEND1, LAN887X_CBL_DIAG_AGC_THRESH_100, 0x3c},1523 {MDIO_MMD_VEND1, LAN887X_CBL_DIAG_MIN_WAIT_CONFIG_100, 0x0},1524 {MDIO_MMD_VEND1, LAN887X_CBL_DIAG_MAX_WAIT_CONFIG_100, 0x46},1525 {MDIO_MMD_VEND1, LAN887X_CBL_DIAG_CYC_CONFIG_100, 0x5a},1526 {MDIO_MMD_VEND1, LAN887X_CBL_DIAG_TX_PULSE_CONFIG_100, 0x44d5},1527 {MDIO_MMD_VEND1, LAN887X_CBL_DIAG_MIN_PGA_GAIN_100, 0x0},1528 1529 };1530 int rc;1531 1532 rc = lan887x_cd_reset(phydev, CD_TEST_INIT);1533 if (rc < 0)1534 return rc;1535 1536 /* Forcing DUT to master mode, as we don't care about1537 * mode during diagnostics1538 */1539 rc = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1_CTRL,1540 MDIO_PMA_PMD_BT1_CTRL_CFG_MST);1541 if (rc < 0)1542 return rc;1543 1544 rc = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, 0x80b0, 0x0038);1545 if (rc < 0)1546 return rc;1547 1548 rc = phy_modify_mmd(phydev, MDIO_MMD_VEND1,1549 LAN887X_CALIB_CONFIG_100, 0,1550 LAN887X_CALIB_CONFIG_100_VAL);1551 if (rc < 0)1552 return rc;1553 1554 for (int i = 0; i < ARRAY_SIZE(values); i++) {1555 rc = phy_write_mmd(phydev, values[i].mmd, values[i].reg,1556 values[i].val);1557 if (rc < 0)1558 return rc;1559 1560 if (mode &&1561 values[i].reg == LAN887X_CBL_DIAG_MAX_WAIT_CONFIG_100) {1562 rc = phy_write_mmd(phydev, values[i].mmd,1563 values[i].reg, 0xa);1564 if (rc < 0)1565 return rc;1566 }1567 }1568 1569 if (mode == TEST_MODE_HYBRID) {1570 rc = phy_modify_mmd(phydev, MDIO_MMD_PMAPMD,1571 LAN887X_AFE_PORT_TESTBUS_CTRL4,1572 BIT(0), BIT(0));1573 if (rc < 0)1574 return rc;1575 }1576 1577 /* HW_INIT 100T1, Get DUT running in 100T1 mode */1578 rc = phy_modify_mmd(phydev, MDIO_MMD_VEND1, LAN887X_REG_REG26,1579 LAN887X_REG_REG26_HW_INIT_SEQ_EN,1580 LAN887X_REG_REG26_HW_INIT_SEQ_EN);1581 if (rc < 0)1582 return rc;1583 1584 /* Cable diag requires hard reset and is sensitive regarding the delays.1585 * Hard reset is expected into and out of cable diag.1586 * Wait for 50ms1587 */1588 msleep(50);1589 1590 /* Start cable diag */1591 return phy_write_mmd(phydev, MDIO_MMD_VEND1,1592 LAN887X_START_CBL_DIAG_100,1593 LAN887X_CBL_DIAG_START);1594}1595 1596static int lan887x_cable_test_chk(struct phy_device *phydev,1597 enum cable_diag_mode mode)1598{1599 int val;1600 int rc;1601 1602 if (mode == TEST_MODE_HYBRID) {1603 /* Cable diag requires hard reset and is sensitive regarding the delays.1604 * Hard reset is expected into and out of cable diag.1605 * Wait for cable diag to complete.1606 * Minimum wait time is 50ms if the condition is not a match.1607 */1608 rc = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,1609 LAN887X_START_CBL_DIAG_100, val,1610 ((val & LAN887X_CBL_DIAG_DONE) ==1611 LAN887X_CBL_DIAG_DONE),1612 50000, 500000, false);1613 if (rc < 0)1614 return rc;1615 } else {1616 rc = phy_read_mmd(phydev, MDIO_MMD_VEND1,1617 LAN887X_START_CBL_DIAG_100);1618 if (rc < 0)1619 return rc;1620 1621 if ((rc & LAN887X_CBL_DIAG_DONE) != LAN887X_CBL_DIAG_DONE)1622 return -EAGAIN;1623 }1624 1625 /* Stop cable diag */1626 return phy_write_mmd(phydev, MDIO_MMD_VEND1,1627 LAN887X_START_CBL_DIAG_100,1628 LAN887X_CBL_DIAG_STOP);1629}1630 1631static int lan887x_cable_test_start(struct phy_device *phydev)1632{1633 int rc, ret;1634 1635 rc = lan887x_cable_test_prep(phydev, TEST_MODE_NORMAL);1636 if (rc < 0) {1637 ret = lan887x_cd_reset(phydev, CD_TEST_DONE);1638 if (ret < 0)1639 return ret;1640 1641 return rc;1642 }1643 1644 return 0;1645}1646 1647static int lan887x_cable_test_report(struct phy_device *phydev)1648{1649 int pos_peak_cycle, pos_peak_cycle_hybrid, pos_peak_in_phases;1650 int pos_peak_time, pos_peak_time_hybrid, neg_peak_time;1651 int neg_peak_cycle, neg_peak_in_phases;1652 int pos_peak_in_phases_hybrid;1653 int gain_idx, gain_idx_hybrid;1654 int pos_peak_phase_hybrid;1655 int pos_peak, neg_peak;1656 int distance;1657 int detect;1658 int length;1659 int ret;1660 int rc;1661 1662 /* Read non-hybrid results */1663 gain_idx = phy_read_mmd(phydev, MDIO_MMD_VEND1,1664 LAN887X_CBL_DIAG_AGC_GAIN_100);1665 if (gain_idx < 0) {1666 rc = gain_idx;1667 goto error;1668 }1669 1670 pos_peak = phy_read_mmd(phydev, MDIO_MMD_VEND1,1671 LAN887X_CBL_DIAG_POS_PEAK_VALUE_100);1672 if (pos_peak < 0) {1673 rc = pos_peak;1674 goto error;1675 }1676 1677 neg_peak = phy_read_mmd(phydev, MDIO_MMD_VEND1,1678 LAN887X_CBL_DIAG_NEG_PEAK_VALUE_100);1679 if (neg_peak < 0) {1680 rc = neg_peak;1681 goto error;1682 }1683 1684 pos_peak_time = phy_read_mmd(phydev, MDIO_MMD_VEND1,1685 LAN887X_CBL_DIAG_POS_PEAK_TIME_100);1686 if (pos_peak_time < 0) {1687 rc = pos_peak_time;1688 goto error;1689 }1690 1691 neg_peak_time = phy_read_mmd(phydev, MDIO_MMD_VEND1,1692 LAN887X_CBL_DIAG_NEG_PEAK_TIME_100);1693 if (neg_peak_time < 0) {1694 rc = neg_peak_time;1695 goto error;1696 }1697 1698 /* Calculate non-hybrid values */1699 pos_peak_cycle = (pos_peak_time >> 7) & 0x7f;1700 pos_peak_in_phases = (pos_peak_cycle * 96) + (pos_peak_time & 0x7f);1701 neg_peak_cycle = (neg_peak_time >> 7) & 0x7f;1702 neg_peak_in_phases = (neg_peak_cycle * 96) + (neg_peak_time & 0x7f);1703 1704 /* Deriving the status of cable */1705 if (pos_peak > MICROCHIP_CABLE_NOISE_MARGIN &&1706 neg_peak > MICROCHIP_CABLE_NOISE_MARGIN && gain_idx >= 0) {1707 if (pos_peak_in_phases > neg_peak_in_phases &&1708 ((pos_peak_in_phases - neg_peak_in_phases) >=1709 MICROCHIP_CABLE_MIN_TIME_DIFF) &&1710 ((pos_peak_in_phases - neg_peak_in_phases) <1711 MICROCHIP_CABLE_MAX_TIME_DIFF) &&1712 pos_peak_in_phases > 0) {1713 detect = LAN87XX_CABLE_TEST_SAME_SHORT;1714 } else if (neg_peak_in_phases > pos_peak_in_phases &&1715 ((neg_peak_in_phases - pos_peak_in_phases) >=1716 MICROCHIP_CABLE_MIN_TIME_DIFF) &&1717 ((neg_peak_in_phases - pos_peak_in_phases) <1718 MICROCHIP_CABLE_MAX_TIME_DIFF) &&1719 neg_peak_in_phases > 0) {1720 detect = LAN87XX_CABLE_TEST_OPEN;1721 } else {1722 detect = LAN87XX_CABLE_TEST_OK;1723 }1724 } else {1725 detect = LAN87XX_CABLE_TEST_OK;1726 }1727 1728 if (detect == LAN87XX_CABLE_TEST_OK) {1729 distance = 0;1730 goto get_len;1731 }1732 1733 /* Re-initialize PHY and start cable diag test */1734 rc = lan887x_cable_test_prep(phydev, TEST_MODE_HYBRID);1735 if (rc < 0)1736 goto cd_stop;1737 1738 /* Wait for cable diag test completion */1739 rc = lan887x_cable_test_chk(phydev, TEST_MODE_HYBRID);1740 if (rc < 0)1741 goto cd_stop;1742 1743 /* Read hybrid results */1744 gain_idx_hybrid = phy_read_mmd(phydev, MDIO_MMD_VEND1,1745 LAN887X_CBL_DIAG_AGC_GAIN_100);1746 if (gain_idx_hybrid < 0) {1747 rc = gain_idx_hybrid;1748 goto error;1749 }1750 1751 pos_peak_time_hybrid = phy_read_mmd(phydev, MDIO_MMD_VEND1,1752 LAN887X_CBL_DIAG_POS_PEAK_TIME_100);1753 if (pos_peak_time_hybrid < 0) {1754 rc = pos_peak_time_hybrid;1755 goto error;1756 }1757 1758 /* Calculate hybrid values to derive cable length to fault */1759 pos_peak_cycle_hybrid = (pos_peak_time_hybrid >> 7) & 0x7f;1760 pos_peak_phase_hybrid = pos_peak_time_hybrid & 0x7f;1761 pos_peak_in_phases_hybrid = pos_peak_cycle_hybrid * 96 +1762 pos_peak_phase_hybrid;1763 1764 /* Distance to fault calculation.1765 * distance = (peak_in_phases - peak_in_phases_hybrid) *1766 * propagationconstant.1767 * constant to convert number of phases to meters1768 * propagationconstant = 0.0159531769 * (0.6811 * 2.9979 * 156.2499 * 0.0001 * 0.5)1770 * Applying constant 1.5953 as ethtool further devides by 100 to1771 * convert to meters.1772 */1773 if (detect == LAN87XX_CABLE_TEST_OPEN) {1774 distance = (((pos_peak_in_phases - pos_peak_in_phases_hybrid)1775 * 15953) / 10000);1776 } else if (detect == LAN87XX_CABLE_TEST_SAME_SHORT) {1777 distance = (((neg_peak_in_phases - pos_peak_in_phases_hybrid)1778 * 15953) / 10000);1779 } else {1780 distance = 0;1781 }1782 1783get_len:1784 rc = lan887x_cd_reset(phydev, CD_TEST_DONE);1785 if (rc < 0)1786 return rc;1787 1788 length = ((u32)distance & GENMASK(15, 0));1789 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A,1790 lan87xx_cable_test_report_trans(detect));1791 ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_A, length);1792 1793 return 0;1794 1795cd_stop:1796 /* Stop cable diag */1797 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1,1798 LAN887X_START_CBL_DIAG_100,1799 LAN887X_CBL_DIAG_STOP);1800 if (ret < 0)1801 return ret;1802 1803error:1804 /* Cable diag test failed */1805 ret = lan887x_cd_reset(phydev, CD_TEST_DONE);1806 if (ret < 0)1807 return ret;1808 1809 /* Return error in failure case */1810 return rc;1811}1812 1813static int lan887x_cable_test_get_status(struct phy_device *phydev,1814 bool *finished)1815{1816 int rc;1817 1818 rc = lan887x_cable_test_chk(phydev, TEST_MODE_NORMAL);1819 if (rc < 0) {1820 /* Let PHY statemachine poll again */1821 if (rc == -EAGAIN)1822 return 0;1823 return rc;1824 }1825 1826 /* Cable diag test complete */1827 *finished = true;1828 1829 /* Retrieve test status and cable length to fault */1830 return lan887x_cable_test_report(phydev);1831}1832 1833static struct phy_driver microchip_t1_phy_driver[] = {1834 {1835 PHY_ID_MATCH_MODEL(PHY_ID_LAN87XX),1836 .name = "Microchip LAN87xx T1",1837 .flags = PHY_POLL_CABLE_TEST,1838 .features = PHY_BASIC_T1_FEATURES,1839 .config_init = lan87xx_config_init,1840 .config_intr = lan87xx_phy_config_intr,1841 .handle_interrupt = lan87xx_handle_interrupt,1842 .suspend = genphy_suspend,1843 .resume = genphy_resume,1844 .config_aneg = lan87xx_config_aneg,1845 .read_status = lan87xx_read_status,1846 .get_sqi = lan87xx_get_sqi,1847 .get_sqi_max = lan87xx_get_sqi_max,1848 .cable_test_start = lan87xx_cable_test_start,1849 .cable_test_get_status = lan87xx_cable_test_get_status,1850 },1851 {1852 PHY_ID_MATCH_MODEL(PHY_ID_LAN937X),1853 .name = "Microchip LAN937x T1",1854 .flags = PHY_POLL_CABLE_TEST,1855 .features = PHY_BASIC_T1_FEATURES,1856 .config_init = lan87xx_config_init,1857 .config_intr = lan87xx_phy_config_intr,1858 .handle_interrupt = lan87xx_handle_interrupt,1859 .suspend = genphy_suspend,1860 .resume = genphy_resume,1861 .config_aneg = lan87xx_config_aneg,1862 .read_status = lan87xx_read_status,1863 .get_sqi = lan87xx_get_sqi,1864 .get_sqi_max = lan87xx_get_sqi_max,1865 .cable_test_start = lan87xx_cable_test_start,1866 .cable_test_get_status = lan87xx_cable_test_get_status,1867 },1868 {1869 PHY_ID_MATCH_MODEL(PHY_ID_LAN887X),1870 .name = "Microchip LAN887x T1 PHY",1871 .flags = PHY_POLL_CABLE_TEST,1872 .probe = lan887x_probe,1873 .get_features = lan887x_get_features,1874 .config_init = lan887x_phy_init,1875 .config_aneg = lan887x_config_aneg,1876 .get_stats = lan887x_get_stats,1877 .get_sset_count = lan887x_get_sset_count,1878 .get_strings = lan887x_get_strings,1879 .suspend = genphy_suspend,1880 .resume = genphy_resume,1881 .read_status = genphy_c45_read_status,1882 .cable_test_start = lan887x_cable_test_start,1883 .cable_test_get_status = lan887x_cable_test_get_status,1884 }1885};1886 1887module_phy_driver(microchip_t1_phy_driver);1888 1889static struct mdio_device_id __maybe_unused microchip_t1_tbl[] = {1890 { PHY_ID_MATCH_MODEL(PHY_ID_LAN87XX) },1891 { PHY_ID_MATCH_MODEL(PHY_ID_LAN937X) },1892 { PHY_ID_MATCH_MODEL(PHY_ID_LAN887X) },1893 { }1894};1895 1896MODULE_DEVICE_TABLE(mdio, microchip_t1_tbl);1897 1898MODULE_AUTHOR(DRIVER_AUTHOR);1899MODULE_DESCRIPTION(DRIVER_DESC);1900MODULE_LICENSE("GPL");1901