501 lines · c
1/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */2/*3 * Driver for Microsemi VSC85xx PHYs4 *5 * Copyright (c) 2016 Microsemi Corporation6 */7 8#ifndef _MSCC_PHY_H_9#define _MSCC_PHY_H_10 11#if IS_ENABLED(CONFIG_MACSEC)12#include "mscc_macsec.h"13#endif14 15enum rgmii_clock_delay {16 RGMII_CLK_DELAY_0_2_NS = 0,17 RGMII_CLK_DELAY_0_8_NS = 1,18 RGMII_CLK_DELAY_1_1_NS = 2,19 RGMII_CLK_DELAY_1_7_NS = 3,20 RGMII_CLK_DELAY_2_0_NS = 4,21 RGMII_CLK_DELAY_2_3_NS = 5,22 RGMII_CLK_DELAY_2_6_NS = 6,23 RGMII_CLK_DELAY_3_4_NS = 724};25 26/* Microsemi VSC85xx PHY registers */27/* IEEE 802. Std Registers */28#define MSCC_PHY_BYPASS_CONTROL 1829#define DISABLE_HP_AUTO_MDIX_MASK 0x008030#define DISABLE_PAIR_SWAP_CORR_MASK 0x002031#define DISABLE_POLARITY_CORR_MASK 0x001032#define PARALLEL_DET_IGNORE_ADVERTISED 0x000833 34#define MSCC_PHY_EXT_CNTL_STATUS 2235#define SMI_BROADCAST_WR_EN 0x000136 37#define MSCC_PHY_ERR_RX_CNT 1938#define MSCC_PHY_ERR_FALSE_CARRIER_CNT 2039#define MSCC_PHY_ERR_LINK_DISCONNECT_CNT 2140#define ERR_CNT_MASK GENMASK(7, 0)41 42#define MSCC_PHY_EXT_PHY_CNTL_1 2343#define MAC_IF_SELECTION_MASK 0x180044#define MAC_IF_SELECTION_GMII 045#define MAC_IF_SELECTION_RMII 146#define MAC_IF_SELECTION_RGMII 247#define MAC_IF_SELECTION_POS 1148#define VSC8584_MAC_IF_SELECTION_MASK 0x100049#define VSC8584_MAC_IF_SELECTION_SGMII 050#define VSC8584_MAC_IF_SELECTION_1000BASEX 151#define VSC8584_MAC_IF_SELECTION_POS 1252#define FAR_END_LOOPBACK_MODE_MASK 0x000853#define MEDIA_OP_MODE_MASK 0x070054#define MEDIA_OP_MODE_COPPER 055#define MEDIA_OP_MODE_SERDES 156#define MEDIA_OP_MODE_1000BASEX 257#define MEDIA_OP_MODE_100BASEFX 358#define MEDIA_OP_MODE_AMS_COPPER_SERDES 559#define MEDIA_OP_MODE_AMS_COPPER_1000BASEX 660#define MEDIA_OP_MODE_AMS_COPPER_100BASEFX 761#define MEDIA_OP_MODE_POS 862 63#define MSCC_PHY_EXT_PHY_CNTL_2 2464 65#define MII_VSC85XX_INT_MASK 2566#define MII_VSC85XX_INT_MASK_MDINT BIT(15)67#define MII_VSC85XX_INT_MASK_LINK_CHG BIT(13)68#define MII_VSC85XX_INT_MASK_WOL BIT(6)69#define MII_VSC85XX_INT_MASK_EXT BIT(5)70#define MII_VSC85XX_INT_STATUS 2671 72#define MII_VSC85XX_INT_MASK_MASK (MII_VSC85XX_INT_MASK_MDINT | \73 MII_VSC85XX_INT_MASK_LINK_CHG | \74 MII_VSC85XX_INT_MASK_EXT)75 76#define MSCC_PHY_WOL_MAC_CONTROL 2777#define EDGE_RATE_CNTL_POS 578#define EDGE_RATE_CNTL_MASK 0x00E079 80#define MSCC_PHY_DEV_AUX_CNTL 2881#define HP_AUTO_MDIX_X_OVER_IND_MASK 0x200082 83#define MSCC_PHY_LED_MODE_SEL 2984#define LED_MODE_SEL_POS(x) ((x) * 4)85#define LED_MODE_SEL_MASK(x) (GENMASK(3, 0) << LED_MODE_SEL_POS(x))86#define LED_MODE_SEL(x, mode) (((mode) << LED_MODE_SEL_POS(x)) & LED_MODE_SEL_MASK(x))87 88#define MSCC_EXT_PAGE_CSR_CNTL_17 1789#define MSCC_EXT_PAGE_CSR_CNTL_18 1890 91#define MSCC_EXT_PAGE_CSR_CNTL_19 1992#define MSCC_PHY_CSR_CNTL_19_REG_ADDR(x) (x)93#define MSCC_PHY_CSR_CNTL_19_TARGET(x) ((x) << 12)94#define MSCC_PHY_CSR_CNTL_19_READ BIT(14)95#define MSCC_PHY_CSR_CNTL_19_CMD BIT(15)96 97#define MSCC_EXT_PAGE_CSR_CNTL_20 2098#define MSCC_PHY_CSR_CNTL_20_TARGET(x) (x)99 100#define PHY_MCB_TARGET 0x07101#define PHY_MCB_S6G_WRITE BIT(31)102#define PHY_MCB_S6G_READ BIT(30)103 104#define PHY_S6G_PLL5G_CFG0 0x06105#define PHY_S6G_PLL5G_CFG2 0x08106#define PHY_S6G_LCPLL_CFG 0x11107#define PHY_S6G_PLL_CFG 0x2b108#define PHY_S6G_COMMON_CFG 0x2c109#define PHY_S6G_GPC_CFG 0x2e110#define PHY_S6G_MISC_CFG 0x3b111#define PHY_MCB_S6G_CFG 0x3f112#define PHY_S6G_DFT_CFG2 0x3e113#define PHY_S6G_PLL_STATUS 0x31114#define PHY_S6G_IB_STATUS0 0x2f115 116#define PHY_S6G_SYS_RST_POS 31117#define PHY_S6G_ENA_LANE_POS 18118#define PHY_S6G_ENA_LOOP_POS 8119#define PHY_S6G_QRATE_POS 6120#define PHY_S6G_IF_MODE_POS 4121#define PHY_S6G_PLL_ENA_OFFS_POS 21122#define PHY_S6G_PLL_FSM_CTRL_DATA_POS 8123#define PHY_S6G_PLL_FSM_ENA_POS 7124 125#define PHY_S6G_CFG2_FSM_DIS 1126#define PHY_S6G_CFG2_FSM_CLK_BP 23127 128#define MSCC_EXT_PAGE_ACCESS 31129#define MSCC_PHY_PAGE_STANDARD 0x0000 /* Standard registers */130#define MSCC_PHY_PAGE_EXTENDED 0x0001 /* Extended registers */131#define MSCC_PHY_PAGE_EXTENDED_2 0x0002 /* Extended reg - page 2 */132#define MSCC_PHY_PAGE_EXTENDED_3 0x0003 /* Extended reg - page 3 */133#define MSCC_PHY_PAGE_EXTENDED_4 0x0004 /* Extended reg - page 4 */134#define MSCC_PHY_PAGE_CSR_CNTL MSCC_PHY_PAGE_EXTENDED_4135#define MSCC_PHY_PAGE_MACSEC MSCC_PHY_PAGE_EXTENDED_4136/* Extended reg - GPIO; this is a bank of registers that are shared for all PHYs137 * in the same package.138 */139#define MSCC_PHY_PAGE_EXTENDED_GPIO 0x0010 /* Extended reg - GPIO */140#define MSCC_PHY_PAGE_1588 0x1588 /* PTP (1588) */141#define MSCC_PHY_PAGE_TEST 0x2a30 /* Test reg */142#define MSCC_PHY_PAGE_TR 0x52b5 /* Token ring registers */143#define MSCC_PHY_GPIO_CONTROL_2 14144 145#define MSCC_PHY_COMA_MODE 0x2000 /* input(1) / output(0) */146#define MSCC_PHY_COMA_OUTPUT 0x1000 /* value to output */147 148/* Extended Page 1 Registers */149#define MSCC_PHY_CU_MEDIA_CRC_VALID_CNT 18150#define VALID_CRC_CNT_CRC_MASK GENMASK(13, 0)151 152#define MSCC_PHY_EXT_MODE_CNTL 19153#define FORCE_MDI_CROSSOVER_MASK 0x000C154#define FORCE_MDI_CROSSOVER_MDIX 0x000C155#define FORCE_MDI_CROSSOVER_MDI 0x0008156 157#define MSCC_PHY_ACTIPHY_CNTL 20158#define PHY_ADDR_REVERSED 0x0200159#define DOWNSHIFT_CNTL_MASK 0x001C160#define DOWNSHIFT_EN 0x0010161#define DOWNSHIFT_CNTL_POS 2162 163#define MSCC_PHY_EXT_PHY_CNTL_4 23164#define PHY_CNTL_4_ADDR_POS 11165 166#define MSCC_PHY_VERIPHY_CNTL_2 25167 168#define MSCC_PHY_VERIPHY_CNTL_3 26169 170/* Extended Page 2 Registers */171#define MSCC_PHY_CU_PMD_TX_CNTL 16172 173/* RGMII setting controls at address 18E2, for VSC8572 and similar */174#define VSC8572_RGMII_CNTL 18175#define VSC8572_RGMII_RX_DELAY_MASK 0x000E176#define VSC8572_RGMII_TX_DELAY_MASK 0x0070177 178/* RGMII controls at address 20E2, for VSC8502 and similar */179#define VSC8502_RGMII_CNTL 20180#define VSC8502_RGMII_RX_DELAY_MASK 0x0070181#define VSC8502_RGMII_TX_DELAY_MASK 0x0007182#define VSC8502_RGMII_RX_CLK_DISABLE 0x0800183 184#define MSCC_PHY_WOL_LOWER_MAC_ADDR 21185#define MSCC_PHY_WOL_MID_MAC_ADDR 22186#define MSCC_PHY_WOL_UPPER_MAC_ADDR 23187#define MSCC_PHY_WOL_LOWER_PASSWD 24188#define MSCC_PHY_WOL_MID_PASSWD 25189#define MSCC_PHY_WOL_UPPER_PASSWD 26190 191#define MSCC_PHY_WOL_MAC_CONTROL 27192#define SECURE_ON_ENABLE 0x8000193#define SECURE_ON_PASSWD_LEN_4 0x4000194 195#define MSCC_PHY_EXTENDED_INT 28196#define MSCC_PHY_EXTENDED_INT_MS_EGR BIT(9)197 198/* Extended Page 3 Registers */199#define MSCC_PHY_SERDES_TX_VALID_CNT 21200#define MSCC_PHY_SERDES_TX_CRC_ERR_CNT 22201#define MSCC_PHY_SERDES_RX_VALID_CNT 28202#define MSCC_PHY_SERDES_RX_CRC_ERR_CNT 29203 204/* Extended page GPIO Registers */205#define MSCC_DW8051_CNTL_STATUS 0206#define MICRO_NSOFT_RESET 0x8000207#define RUN_FROM_INT_ROM 0x4000208#define AUTOINC_ADDR 0x2000209#define PATCH_RAM_CLK 0x1000210#define MICRO_PATCH_EN 0x0080211#define DW8051_CLK_EN 0x0010212#define MICRO_CLK_EN 0x0008213#define MICRO_CLK_DIVIDE(x) ((x) >> 1)214#define MSCC_DW8051_VLD_MASK 0xf1ff215 216/* x Address in range 1-4 */217#define MSCC_TRAP_ROM_ADDR(x) ((x) * 2 + 1)218#define MSCC_PATCH_RAM_ADDR(x) (((x) + 1) * 2)219#define MSCC_INT_MEM_ADDR 11220 221#define MSCC_INT_MEM_CNTL 12222#define READ_SFR 0x6000223#define READ_PRAM 0x4000224#define READ_ROM 0x2000225#define READ_RAM 0x0000226#define INT_MEM_WRITE_EN 0x1000227#define EN_PATCH_RAM_TRAP_ADDR(x) (0x0100 << ((x) - 1))228#define INT_MEM_DATA_M 0x00ff229#define INT_MEM_DATA(x) (INT_MEM_DATA_M & (x))230 231#define MSCC_PHY_PROC_CMD 18232#define PROC_CMD_NCOMPLETED 0x8000233#define PROC_CMD_FAILED 0x4000234#define PROC_CMD_SGMII_PORT(x) ((x) << 8)235#define PROC_CMD_FIBER_PORT(x) (0x0100 << (x) % 4)236#define PROC_CMD_QSGMII_PORT 0x0c00237#define PROC_CMD_RST_CONF_PORT 0x0080238#define PROC_CMD_RECONF_PORT 0x0000239#define PROC_CMD_READ_MOD_WRITE_PORT 0x0040240#define PROC_CMD_WRITE 0x0040241#define PROC_CMD_READ 0x0000242#define PROC_CMD_FIBER_DISABLE 0x0020243#define PROC_CMD_FIBER_100BASE_FX 0x0010244#define PROC_CMD_FIBER_1000BASE_X 0x0000245#define PROC_CMD_SGMII_MAC 0x0030246#define PROC_CMD_QSGMII_MAC 0x0020247#define PROC_CMD_NO_MAC_CONF 0x0000248#define PROC_CMD_1588_DEFAULT_INIT 0x0010249#define PROC_CMD_NOP 0x000f250#define PROC_CMD_PHY_INIT 0x000a251#define PROC_CMD_CRC16 0x0008252#define PROC_CMD_FIBER_MEDIA_CONF 0x0001253#define PROC_CMD_MCB_ACCESS_MAC_CONF 0x0000254#define PROC_CMD_NCOMPLETED_TIMEOUT_MS 500255 256#define MSCC_PHY_MAC_CFG_FASTLINK 19257#define MAC_CFG_MASK 0xc000258#define MAC_CFG_SGMII 0x0000259#define MAC_CFG_QSGMII 0x4000260#define MAC_CFG_RGMII 0x8000261 262/* Test page Registers */263#define MSCC_PHY_TEST_PAGE_5 5264#define MSCC_PHY_TEST_PAGE_8 8265#define TR_CLK_DISABLE 0x8000266#define MSCC_PHY_TEST_PAGE_9 9267#define MSCC_PHY_TEST_PAGE_20 20268#define MSCC_PHY_TEST_PAGE_24 24269 270/* Token ring page Registers */271#define MSCC_PHY_TR_CNTL 16272#define TR_WRITE 0x8000273#define TR_ADDR(x) (0x7fff & (x))274#define MSCC_PHY_TR_LSB 17275#define MSCC_PHY_TR_MSB 18276 277/* Microsemi PHY ID's278 * Code assumes lowest nibble is 0279 */280#define PHY_ID_VSC8501 0x00070530281#define PHY_ID_VSC8502 0x00070630282#define PHY_ID_VSC8504 0x000704c0283#define PHY_ID_VSC8514 0x00070670284#define PHY_ID_VSC8530 0x00070560285#define PHY_ID_VSC8531 0x00070570286#define PHY_ID_VSC8540 0x00070760287#define PHY_ID_VSC8541 0x00070770288#define PHY_ID_VSC8552 0x000704e0289#define PHY_ID_VSC856X 0x000707e0290#define PHY_ID_VSC8572 0x000704d0291#define PHY_ID_VSC8574 0x000704a0292#define PHY_ID_VSC8575 0x000707d0293#define PHY_ID_VSC8582 0x000707b0294#define PHY_ID_VSC8584 0x000707c0295#define PHY_VENDOR_MSCC 0x00070400296 297#define MSCC_VDDMAC_1500 1500298#define MSCC_VDDMAC_1800 1800299#define MSCC_VDDMAC_2500 2500300#define MSCC_VDDMAC_3300 3300301 302#define DOWNSHIFT_COUNT_MAX 5303 304#define MAX_LEDS 4305 306#define VSC8584_SUPP_LED_MODES (BIT(VSC8531_LINK_ACTIVITY) | \307 BIT(VSC8531_LINK_1000_ACTIVITY) | \308 BIT(VSC8531_LINK_100_ACTIVITY) | \309 BIT(VSC8531_LINK_10_ACTIVITY) | \310 BIT(VSC8531_LINK_100_1000_ACTIVITY) | \311 BIT(VSC8531_LINK_10_1000_ACTIVITY) | \312 BIT(VSC8531_LINK_10_100_ACTIVITY) | \313 BIT(VSC8584_LINK_100FX_1000X_ACTIVITY) | \314 BIT(VSC8531_DUPLEX_COLLISION) | \315 BIT(VSC8531_COLLISION) | \316 BIT(VSC8531_ACTIVITY) | \317 BIT(VSC8584_100FX_1000X_ACTIVITY) | \318 BIT(VSC8531_AUTONEG_FAULT) | \319 BIT(VSC8531_SERIAL_MODE) | \320 BIT(VSC8531_FORCE_LED_OFF) | \321 BIT(VSC8531_FORCE_LED_ON))322 323#define VSC85XX_SUPP_LED_MODES (BIT(VSC8531_LINK_ACTIVITY) | \324 BIT(VSC8531_LINK_1000_ACTIVITY) | \325 BIT(VSC8531_LINK_100_ACTIVITY) | \326 BIT(VSC8531_LINK_10_ACTIVITY) | \327 BIT(VSC8531_LINK_100_1000_ACTIVITY) | \328 BIT(VSC8531_LINK_10_1000_ACTIVITY) | \329 BIT(VSC8531_LINK_10_100_ACTIVITY) | \330 BIT(VSC8531_DUPLEX_COLLISION) | \331 BIT(VSC8531_COLLISION) | \332 BIT(VSC8531_ACTIVITY) | \333 BIT(VSC8531_AUTONEG_FAULT) | \334 BIT(VSC8531_SERIAL_MODE) | \335 BIT(VSC8531_FORCE_LED_OFF) | \336 BIT(VSC8531_FORCE_LED_ON))337 338#define MSCC_VSC8584_REVB_INT8051_FW "microchip/mscc_vsc8584_revb_int8051_fb48.bin"339#define MSCC_VSC8584_REVB_INT8051_FW_START_ADDR 0xe800340#define MSCC_VSC8584_REVB_INT8051_FW_CRC 0xfb48341 342#define MSCC_VSC8574_REVB_INT8051_FW "microchip/mscc_vsc8574_revb_int8051_29e8.bin"343#define MSCC_VSC8574_REVB_INT8051_FW_START_ADDR 0x4000344#define MSCC_VSC8574_REVB_INT8051_FW_CRC 0x29e8345 346#define VSC8584_REVB 0x0001347#define MSCC_DEV_REV_MASK GENMASK(3, 0)348 349#define MSCC_ROM_TRAP_SERDES_6G_CFG 0x1E48350#define MSCC_RAM_TRAP_SERDES_6G_CFG 0x1E4F351#define PATCH_VEC_ZERO_EN 0x0100352 353struct reg_val {354 u16 reg;355 u32 val;356};357 358struct vsc85xx_hw_stat {359 const char *string;360 u8 reg;361 u16 page;362 u16 mask;363};364 365struct vsc8531_private {366 int rate_magic;367 u16 supp_led_modes;368 u32 leds_mode[MAX_LEDS];369 u8 nleds;370 const struct vsc85xx_hw_stat *hw_stats;371 u64 *stats;372 int nstats;373 /* PHY address within the package. */374 u8 addr;375 /* For multiple port PHYs; the MDIO address of the base PHY in the376 * package.377 */378 unsigned int base_addr;379 380#if IS_ENABLED(CONFIG_MACSEC)381 /* MACsec fields:382 * - One SecY per device (enforced at the s/w implementation level)383 * - macsec_flows: list of h/w flows384 * - ingr_flows: bitmap of ingress flows385 * - egr_flows: bitmap of egress flows386 */387 struct macsec_secy *secy;388 struct list_head macsec_flows;389 unsigned long ingr_flows;390 unsigned long egr_flows;391#endif392 393 struct mii_timestamper mii_ts;394 395 bool input_clk_init;396 struct vsc85xx_ptp *ptp;397 /* LOAD/SAVE GPIO pin, used for retrieving or setting time to the PHC. */398 struct gpio_desc *load_save;399 400 /* For multiple port PHYs; the MDIO address of the base PHY in the401 * pair of two PHYs that share a 1588 engine. PHY0 and PHY2 are coupled.402 * PHY1 and PHY3 as well. PHY0 and PHY1 are base PHYs for their403 * respective pair.404 */405 unsigned int ts_base_addr;406 u8 ts_base_phy;407 408 /* ts_lock: used for per-PHY timestamping operations.409 * phc_lock: used for per-PHY PHC opertations.410 */411 struct mutex ts_lock;412 struct mutex phc_lock;413};414 415/* Shared structure between the PHYs of the same package.416 * gpio_lock: used for PHC operations. Common for all PHYs as the load/save GPIO417 * is shared.418 */419 420enum vsc85xx_global_phy {421 VSC88XX_BASE_ADDR = 0,422};423 424struct vsc85xx_shared_private {425 struct mutex gpio_lock;426};427 428#if IS_ENABLED(CONFIG_OF_MDIO)429struct vsc8531_edge_rate_table {430 u32 vddmac;431 u32 slowdown[8];432};433#endif /* CONFIG_OF_MDIO */434 435enum csr_target {436 MACRO_CTRL = 0x07,437};438 439u32 vsc85xx_csr_read(struct phy_device *phydev,440 enum csr_target target, u32 reg);441 442int vsc85xx_csr_write(struct phy_device *phydev,443 enum csr_target target, u32 reg, u32 val);444 445int phy_base_write(struct phy_device *phydev, u32 regnum, u16 val);446int phy_base_read(struct phy_device *phydev, u32 regnum);447int phy_update_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb);448int phy_commit_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb);449int vsc8584_cmd(struct phy_device *phydev, u16 val);450 451#if IS_ENABLED(CONFIG_MACSEC)452int vsc8584_macsec_init(struct phy_device *phydev);453void vsc8584_handle_macsec_interrupt(struct phy_device *phydev);454void vsc8584_config_macsec_intr(struct phy_device *phydev);455#else456static inline int vsc8584_macsec_init(struct phy_device *phydev)457{458 return 0;459}460static inline void vsc8584_handle_macsec_interrupt(struct phy_device *phydev)461{462}463static inline void vsc8584_config_macsec_intr(struct phy_device *phydev)464{465}466#endif467 468#if IS_ENABLED(CONFIG_NETWORK_PHY_TIMESTAMPING)469void vsc85xx_link_change_notify(struct phy_device *phydev);470void vsc8584_config_ts_intr(struct phy_device *phydev);471int vsc8584_ptp_init(struct phy_device *phydev);472int vsc8584_ptp_probe_once(struct phy_device *phydev);473int vsc8584_ptp_probe(struct phy_device *phydev);474irqreturn_t vsc8584_handle_ts_interrupt(struct phy_device *phydev);475#else476static inline void vsc85xx_link_change_notify(struct phy_device *phydev)477{478}479static inline void vsc8584_config_ts_intr(struct phy_device *phydev)480{481}482static inline int vsc8584_ptp_init(struct phy_device *phydev)483{484 return 0;485}486static inline int vsc8584_ptp_probe_once(struct phy_device *phydev)487{488 return 0;489}490static inline int vsc8584_ptp_probe(struct phy_device *phydev)491{492 return 0;493}494static inline irqreturn_t vsc8584_handle_ts_interrupt(struct phy_device *phydev)495{496 return IRQ_NONE;497}498#endif499 500#endif /* _MSCC_PHY_H_ */501