160 lines · c
1/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */2/*3 * Driver for Microsemi VSC85xx PHYs4 *5 * Copyright (c) 2020 Microsemi Corporation6 */7 8#ifndef _MSCC_PHY_LINE_MAC_H_9#define _MSCC_PHY_LINE_MAC_H_10 11#define MSCC_MAC_CFG_ENA_CFG 0x0012#define MSCC_MAC_CFG_MODE_CFG 0x0113#define MSCC_MAC_CFG_MAXLEN_CFG 0x0214#define MSCC_MAC_CFG_NUM_TAGS_CFG 0x0315#define MSCC_MAC_CFG_TAGS_CFG 0x0416#define MSCC_MAC_CFG_ADV_CHK_CFG 0x0717#define MSCC_MAC_CFG_LFS_CFG 0x0818#define MSCC_MAC_CFG_LB_CFG 0x0919#define MSCC_MAC_CFG_PKTINF_CFG 0x0a20#define MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL 0x0b21#define MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_2 0x0c22#define MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL 0x0d23#define MSCC_MAC_PAUSE_CFG_STATE 0x0e24#define MSCC_MAC_PAUSE_CFG_MAC_ADDRESS_LSB 0x0f25#define MSCC_MAC_PAUSE_CFG_MAC_ADDRESS_MSB 0x1026#define MSCC_MAC_STATUS_RX_LANE_STICKY_0 0x1127#define MSCC_MAC_STATUS_RX_LANE_STICKY_1 0x1228#define MSCC_MAC_STATUS_TX_MONITOR_STICKY 0x1329#define MSCC_MAC_STATUS_TX_MONITOR_STICKY_MASK 0x1430#define MSCC_MAC_STATUS_STICKY 0x1531#define MSCC_MAC_STATUS_STICKY_MASK 0x1632#define MSCC_MAC_STATS_32BIT_RX_HIH_CKSM_ERR_CNT 0x1733#define MSCC_MAC_STATS_32BIT_RX_XGMII_PROT_ERR_CNT 0x1834#define MSCC_MAC_STATS_32BIT_RX_SYMBOL_ERR_CNT 0x1935#define MSCC_MAC_STATS_32BIT_RX_PAUSE_CNT 0x1a36#define MSCC_MAC_STATS_32BIT_RX_UNSUP_OPCODE_CNT 0x1b37#define MSCC_MAC_STATS_32BIT_RX_UC_CNT 0x1c38#define MSCC_MAC_STATS_32BIT_RX_MC_CNT 0x1d39#define MSCC_MAC_STATS_32BIT_RX_BC_CNT 0x1e40#define MSCC_MAC_STATS_32BIT_RX_CRC_ERR_CNT 0x1f41#define MSCC_MAC_STATS_32BIT_RX_UNDERSIZE_CNT 0x2042#define MSCC_MAC_STATS_32BIT_RX_FRAGMENTS_CNT 0x2143#define MSCC_MAC_STATS_32BIT_RX_IN_RANGE_LEN_ERR_CNT 0x2244#define MSCC_MAC_STATS_32BIT_RX_OUT_OF_RANGE_LEN_ERR_CNT 0x2345#define MSCC_MAC_STATS_32BIT_RX_OVERSIZE_CNT 0x2446#define MSCC_MAC_STATS_32BIT_RX_JABBERS_CNT 0x2547#define MSCC_MAC_STATS_32BIT_RX_SIZE64_CNT 0x2648#define MSCC_MAC_STATS_32BIT_RX_SIZE65TO127_CNT 0x2749#define MSCC_MAC_STATS_32BIT_RX_SIZE128TO255_CNT 0x2850#define MSCC_MAC_STATS_32BIT_RX_SIZE256TO511_CNT 0x2951#define MSCC_MAC_STATS_32BIT_RX_SIZE512TO1023_CNT 0x2a52#define MSCC_MAC_STATS_32BIT_RX_SIZE1024TO1518_CNT 0x2b53#define MSCC_MAC_STATS_32BIT_RX_SIZE1519TOMAX_CNT 0x2c54#define MSCC_MAC_STATS_32BIT_RX_IPG_SHRINK_CNT 0x2d55#define MSCC_MAC_STATS_32BIT_TX_PAUSE_CNT 0x2e56#define MSCC_MAC_STATS_32BIT_TX_UC_CNT 0x2f57#define MSCC_MAC_STATS_32BIT_TX_MC_CNT 0x3058#define MSCC_MAC_STATS_32BIT_TX_BC_CNT 0x3159#define MSCC_MAC_STATS_32BIT_TX_SIZE64_CNT 0x3260#define MSCC_MAC_STATS_32BIT_TX_SIZE65TO127_CNT 0x3361#define MSCC_MAC_STATS_32BIT_TX_SIZE128TO255_CNT 0x3462#define MSCC_MAC_STATS_32BIT_TX_SIZE256TO511_CNT 0x3563#define MSCC_MAC_STATS_32BIT_TX_SIZE512TO1023_CNT 0x3664#define MSCC_MAC_STATS_32BIT_TX_SIZE1024TO1518_CNT 0x3765#define MSCC_MAC_STATS_32BIT_TX_SIZE1519TOMAX_CNT 0x3866#define MSCC_MAC_STATS_40BIT_RX_BAD_BYTES_CNT 0x3967#define MSCC_MAC_STATS_40BIT_RX_BAD_BYTES_MSB_CNT 0x3a68#define MSCC_MAC_STATS_40BIT_RX_OK_BYTES_CNT 0x3b69#define MSCC_MAC_STATS_40BIT_RX_OK_BYTES_MSB_CNT 0x3c70#define MSCC_MAC_STATS_40BIT_RX_IN_BYTES_CNT 0x3d71#define MSCC_MAC_STATS_40BIT_RX_IN_BYTES_MSB_CNT 0x3e72#define MSCC_MAC_STATS_40BIT_TX_OK_BYTES_CNT 0x3f73#define MSCC_MAC_STATS_40BIT_TX_OK_BYTES_MSB_CNT 0x4074#define MSCC_MAC_STATS_40BIT_TX_OUT_BYTES_CNT 0x4175#define MSCC_MAC_STATS_40BIT_TX_OUT_BYTES_MSB_CNT 0x4276 77#define MSCC_MAC_CFG_ENA_CFG_RX_CLK_ENA BIT(0)78#define MSCC_MAC_CFG_ENA_CFG_TX_CLK_ENA BIT(4)79#define MSCC_MAC_CFG_ENA_CFG_RX_SW_RST BIT(8)80#define MSCC_MAC_CFG_ENA_CFG_TX_SW_RST BIT(12)81#define MSCC_MAC_CFG_ENA_CFG_RX_ENA BIT(16)82#define MSCC_MAC_CFG_ENA_CFG_TX_ENA BIT(20)83 84#define MSCC_MAC_CFG_MODE_CFG_FORCE_CW_UPDATE_INTERVAL(x) ((x) << 20)85#define MSCC_MAC_CFG_MODE_CFG_FORCE_CW_UPDATE_INTERVAL_M GENMASK(29, 20)86#define MSCC_MAC_CFG_MODE_CFG_FORCE_CW_UPDATE BIT(16)87#define MSCC_MAC_CFG_MODE_CFG_TUNNEL_PAUSE_FRAMES BIT(14)88#define MSCC_MAC_CFG_MODE_CFG_MAC_PREAMBLE_CFG(x) ((x) << 10)89#define MSCC_MAC_CFG_MODE_CFG_MAC_PREAMBLE_CFG_M GENMASK(12, 10)90#define MSCC_MAC_CFG_MODE_CFG_MAC_IPG_CFG BIT(6)91#define MSCC_MAC_CFG_MODE_CFG_XGMII_GEN_MODE_ENA BIT(4)92#define MSCC_MAC_CFG_MODE_CFG_HIH_CRC_CHECK BIT(2)93#define MSCC_MAC_CFG_MODE_CFG_UNDERSIZED_FRAME_DROP_DIS BIT(1)94#define MSCC_MAC_CFG_MODE_CFG_DISABLE_DIC BIT(0)95 96#define MSCC_MAC_CFG_MAXLEN_CFG_MAX_LEN_TAG_CHK BIT(16)97#define MSCC_MAC_CFG_MAXLEN_CFG_MAX_LEN(x) (x)98#define MSCC_MAC_CFG_MAXLEN_CFG_MAX_LEN_M GENMASK(15, 0)99 100#define MSCC_MAC_CFG_TAGS_CFG_RSZ 0x4101#define MSCC_MAC_CFG_TAGS_CFG_TAG_ID(x) ((x) << 16)102#define MSCC_MAC_CFG_TAGS_CFG_TAG_ID_M GENMASK(31, 16)103#define MSCC_MAC_CFG_TAGS_CFG_TAG_ENA BIT(4)104 105#define MSCC_MAC_CFG_ADV_CHK_CFG_EXT_EOP_CHK_ENA BIT(24)106#define MSCC_MAC_CFG_ADV_CHK_CFG_EXT_SOP_CHK_ENA BIT(20)107#define MSCC_MAC_CFG_ADV_CHK_CFG_SFD_CHK_ENA BIT(16)108#define MSCC_MAC_CFG_ADV_CHK_CFG_PRM_SHK_CHK_DIS BIT(12)109#define MSCC_MAC_CFG_ADV_CHK_CFG_PRM_CHK_ENA BIT(8)110#define MSCC_MAC_CFG_ADV_CHK_CFG_OOR_ERR_ENA BIT(4)111#define MSCC_MAC_CFG_ADV_CHK_CFG_INR_ERR_ENA BIT(0)112 113#define MSCC_MAC_CFG_LFS_CFG_LFS_INH_TX BIT(8)114#define MSCC_MAC_CFG_LFS_CFG_LFS_DIS_TX BIT(4)115#define MSCC_MAC_CFG_LFS_CFG_LFS_UNIDIR_ENA BIT(3)116#define MSCC_MAC_CFG_LFS_CFG_USE_LEADING_EDGE_DETECT BIT(2)117#define MSCC_MAC_CFG_LFS_CFG_SPURIOUS_Q_DIS BIT(1)118#define MSCC_MAC_CFG_LFS_CFG_LFS_MODE_ENA BIT(0)119 120#define MSCC_MAC_CFG_LB_CFG_XGMII_HOST_LB_ENA BIT(4)121#define MSCC_MAC_CFG_LB_CFG_XGMII_PHY_LB_ENA BIT(0)122 123#define MSCC_MAC_CFG_PKTINF_CFG_STRIP_FCS_ENA BIT(0)124#define MSCC_MAC_CFG_PKTINF_CFG_INSERT_FCS_ENA BIT(4)125#define MSCC_MAC_CFG_PKTINF_CFG_STRIP_PREAMBLE_ENA BIT(8)126#define MSCC_MAC_CFG_PKTINF_CFG_INSERT_PREAMBLE_ENA BIT(12)127#define MSCC_MAC_CFG_PKTINF_CFG_LPI_RELAY_ENA BIT(16)128#define MSCC_MAC_CFG_PKTINF_CFG_LF_RELAY_ENA BIT(20)129#define MSCC_MAC_CFG_PKTINF_CFG_RF_RELAY_ENA BIT(24)130#define MSCC_MAC_CFG_PKTINF_CFG_ENABLE_TX_PADDING BIT(25)131#define MSCC_MAC_CFG_PKTINF_CFG_ENABLE_RX_PADDING BIT(26)132#define MSCC_MAC_CFG_PKTINF_CFG_ENABLE_4BYTE_PREAMBLE BIT(27)133#define MSCC_MAC_CFG_PKTINF_CFG_MACSEC_BYPASS_NUM_PTP_STALL_CLKS(x) ((x) << 28)134#define MSCC_MAC_CFG_PKTINF_CFG_MACSEC_BYPASS_NUM_PTP_STALL_CLKS_M GENMASK(30, 28)135 136#define MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_PAUSE_VALUE(x) ((x) << 16)137#define MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_PAUSE_VALUE_M GENMASK(31, 16)138#define MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_WAIT_FOR_LPI_LOW BIT(12)139#define MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_USE_PAUSE_STALL_ENA BIT(8)140#define MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_PAUSE_REPL_MODE BIT(4)141#define MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_PAUSE_FRC_FRAME BIT(2)142#define MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_PAUSE_MODE(x) (x)143#define MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_PAUSE_MODE_M GENMASK(1, 0)144 145#define MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL_EARLY_PAUSE_DETECT_ENA BIT(16)146#define MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL_PRE_CRC_MODE BIT(20)147#define MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL_PAUSE_TIMER_ENA BIT(12)148#define MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL_PAUSE_REACT_ENA BIT(8)149#define MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL_PAUSE_FRAME_DROP_ENA BIT(4)150#define MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL_PAUSE_MODE BIT(0)151 152#define MSCC_MAC_PAUSE_CFG_STATE_PAUSE_STATE BIT(0)153#define MSCC_MAC_PAUSE_CFG_STATE_MAC_TX_PAUSE_GEN BIT(4)154 155#define MSCC_PROC_IP_1588_TOP_CFG_STAT_MODE_CTL 0x2156#define MSCC_PROC_IP_1588_TOP_CFG_STAT_MODE_CTL_PROTOCOL_MODE(x) (x)157#define MSCC_PROC_IP_1588_TOP_CFG_STAT_MODE_CTL_PROTOCOL_MODE_M GENMASK(2, 0)158 159#endif /* _MSCC_PHY_LINE_MAC_H_ */160