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1/* SPDX-License-Identifier: GPL-2.0-or-later */2/* Aquantia Corp. Aquantia AQtion USB to 5GbE Controller3 * Copyright (C) 2003-2005 David Hollis <dhollis@davehollis.com>4 * Copyright (C) 2005 Phil Chang <pchang23@sbcglobal.net>5 * Copyright (C) 2002-2003 TiVo Inc.6 * Copyright (C) 2017-2018 ASIX7 * Copyright (C) 2018 Aquantia Corp.8 */9 10#ifndef __LINUX_USBNET_AQC111_H11#define __LINUX_USBNET_AQC111_H12 13#define URB_SIZE (1024 * 62)14 15#define AQ_MCAST_FILTER_SIZE 816#define AQ_MAX_MCAST 6417 18#define AQ_ACCESS_MAC 0x0119#define AQ_FLASH_PARAMETERS 0x2020#define AQ_PHY_POWER 0x3121#define AQ_WOL_CFG 0x6022#define AQ_PHY_OPS 0x6123 24#define AQ_USB_PHY_SET_TIMEOUT 1000025#define AQ_USB_SET_TIMEOUT 400026 27/* Feature. ********************************************/28#define AQ_SUPPORT_FEATURE (NETIF_F_SG | NETIF_F_IP_CSUM |\29 NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM |\30 NETIF_F_TSO | NETIF_F_HW_VLAN_CTAG_TX |\31 NETIF_F_HW_VLAN_CTAG_RX)32 33#define AQ_SUPPORT_HW_FEATURE (NETIF_F_SG | NETIF_F_IP_CSUM |\34 NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM |\35 NETIF_F_TSO | NETIF_F_HW_VLAN_CTAG_FILTER)36 37#define AQ_SUPPORT_VLAN_FEATURE (NETIF_F_SG | NETIF_F_IP_CSUM |\38 NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM |\39 NETIF_F_TSO)40 41/* SFR Reg. ********************************************/42 43#define SFR_GENERAL_STATUS 0x0344#define SFR_CHIP_STATUS 0x0545#define SFR_RX_CTL 0x0B46 #define SFR_RX_CTL_TXPADCRC 0x040047 #define SFR_RX_CTL_IPE 0x020048 #define SFR_RX_CTL_DROPCRCERR 0x010049 #define SFR_RX_CTL_START 0x008050 #define SFR_RX_CTL_RF_WAK 0x004051 #define SFR_RX_CTL_AP 0x002052 #define SFR_RX_CTL_AM 0x001053 #define SFR_RX_CTL_AB 0x000854 #define SFR_RX_CTL_AMALL 0x000255 #define SFR_RX_CTL_PRO 0x000156 #define SFR_RX_CTL_STOP 0x000057#define SFR_INTER_PACKET_GAP_0 0x0D58#define SFR_NODE_ID 0x1059#define SFR_MULTI_FILTER_ARRY 0x1660#define SFR_MEDIUM_STATUS_MODE 0x2261 #define SFR_MEDIUM_XGMIIMODE 0x000162 #define SFR_MEDIUM_FULL_DUPLEX 0x000263 #define SFR_MEDIUM_RXFLOW_CTRLEN 0x001064 #define SFR_MEDIUM_TXFLOW_CTRLEN 0x002065 #define SFR_MEDIUM_JUMBO_EN 0x004066 #define SFR_MEDIUM_RECEIVE_EN 0x010067#define SFR_MONITOR_MODE 0x2468 #define SFR_MONITOR_MODE_EPHYRW 0x0169 #define SFR_MONITOR_MODE_RWLC 0x0270 #define SFR_MONITOR_MODE_RWMP 0x0471 #define SFR_MONITOR_MODE_RWWF 0x0872 #define SFR_MONITOR_MODE_RW_FLAG 0x1073 #define SFR_MONITOR_MODE_PMEPOL 0x2074 #define SFR_MONITOR_MODE_PMETYPE 0x4075#define SFR_PHYPWR_RSTCTL 0x2676 #define SFR_PHYPWR_RSTCTL_BZ 0x001077 #define SFR_PHYPWR_RSTCTL_IPRL 0x002078#define SFR_VLAN_ID_ADDRESS 0x2A79#define SFR_VLAN_ID_CONTROL 0x2B80 #define SFR_VLAN_CONTROL_WE 0x000181 #define SFR_VLAN_CONTROL_RD 0x000282 #define SFR_VLAN_CONTROL_VSO 0x001083 #define SFR_VLAN_CONTROL_VFE 0x002084#define SFR_VLAN_ID_DATA0 0x2C85#define SFR_VLAN_ID_DATA1 0x2D86#define SFR_RX_BULKIN_QCTRL 0x2E87 #define SFR_RX_BULKIN_QCTRL_TIME 0x0188 #define SFR_RX_BULKIN_QCTRL_IFG 0x0289 #define SFR_RX_BULKIN_QCTRL_SIZE 0x0490#define SFR_RX_BULKIN_QTIMR_LOW 0x2F91#define SFR_RX_BULKIN_QTIMR_HIGH 0x3092#define SFR_RX_BULKIN_QSIZE 0x3193#define SFR_RX_BULKIN_QIFG 0x3294#define SFR_RXCOE_CTL 0x3495 #define SFR_RXCOE_IP 0x0196 #define SFR_RXCOE_TCP 0x0297 #define SFR_RXCOE_UDP 0x0498 #define SFR_RXCOE_ICMP 0x0899 #define SFR_RXCOE_IGMP 0x10100 #define SFR_RXCOE_TCPV6 0x20101 #define SFR_RXCOE_UDPV6 0x40102 #define SFR_RXCOE_ICMV6 0x80103#define SFR_TXCOE_CTL 0x35104 #define SFR_TXCOE_IP 0x01105 #define SFR_TXCOE_TCP 0x02106 #define SFR_TXCOE_UDP 0x04107 #define SFR_TXCOE_ICMP 0x08108 #define SFR_TXCOE_IGMP 0x10109 #define SFR_TXCOE_TCPV6 0x20110 #define SFR_TXCOE_UDPV6 0x40111 #define SFR_TXCOE_ICMV6 0x80112#define SFR_BM_INT_MASK 0x41113#define SFR_BMRX_DMA_CONTROL 0x43114 #define SFR_BMRX_DMA_EN 0x80115#define SFR_BMTX_DMA_CONTROL 0x46116#define SFR_PAUSE_WATERLVL_LOW 0x54117#define SFR_PAUSE_WATERLVL_HIGH 0x55118#define SFR_ARC_CTRL 0x9E119#define SFR_SWP_CTRL 0xB1120#define SFR_TX_PAUSE_RESEND_T 0xB2121#define SFR_ETH_MAC_PATH 0xB7122 #define SFR_RX_PATH_READY 0x01123#define SFR_BULK_OUT_CTRL 0xB9124 #define SFR_BULK_OUT_FLUSH_EN 0x01125 #define SFR_BULK_OUT_EFF_EN 0x02126 127#define AQ_FW_VER_MAJOR 0xDA128#define AQ_FW_VER_MINOR 0xDB129#define AQ_FW_VER_REV 0xDC130 131/*PHY_OPS**********************************************************************/132 133#define AQ_ADV_100M BIT(0)134#define AQ_ADV_1G BIT(1)135#define AQ_ADV_2G5 BIT(2)136#define AQ_ADV_5G BIT(3)137#define AQ_ADV_MASK 0x0F138 139#define AQ_PAUSE BIT(16)140#define AQ_ASYM_PAUSE BIT(17)141#define AQ_LOW_POWER BIT(18)142#define AQ_PHY_POWER_EN BIT(19)143#define AQ_WOL BIT(20)144#define AQ_DOWNSHIFT BIT(21)145 146#define AQ_DSH_RETRIES_SHIFT 0x18147#define AQ_DSH_RETRIES_MASK 0xF000000148 149#define AQ_WOL_FLAG_MP 0x2150 151/******************************************************************************/152 153struct aqc111_wol_cfg {154 u8 hw_addr[6];155 u8 flags;156 u8 rsvd[283];157} __packed;158 159#define WOL_CFG_SIZE sizeof(struct aqc111_wol_cfg)160 161struct aqc111_data {162 u16 rxctl;163 u8 rx_checksum;164 u8 link_speed;165 u8 link;166 u8 autoneg;167 u32 advertised_speed;168 struct {169 u8 major;170 u8 minor;171 u8 rev;172 } fw_ver;173 u32 phy_cfg;174 u8 wol_flags;175};176 177#define AQ_LS_MASK 0x8000178#define AQ_SPEED_MASK 0x7F00179#define AQ_SPEED_SHIFT 0x0008180#define AQ_INT_SPEED_5G 0x000F181#define AQ_INT_SPEED_2_5G 0x0010182#define AQ_INT_SPEED_1G 0x0011183#define AQ_INT_SPEED_100M 0x0013184 185/* TX Descriptor */186#define AQ_TX_DESC_LEN_MASK 0x1FFFFF187#define AQ_TX_DESC_DROP_PADD BIT(28)188#define AQ_TX_DESC_VLAN BIT(29)189#define AQ_TX_DESC_MSS_MASK 0x7FFF190#define AQ_TX_DESC_MSS_SHIFT 0x20191#define AQ_TX_DESC_VLAN_MASK 0xFFFF192#define AQ_TX_DESC_VLAN_SHIFT 0x30193 194#define AQ_RX_HW_PAD 0x02195 196/* RX Packet Descriptor */197#define AQ_RX_PD_L4_ERR BIT(0)198#define AQ_RX_PD_L3_ERR BIT(1)199#define AQ_RX_PD_L4_TYPE_MASK 0x1C200#define AQ_RX_PD_L4_UDP 0x04201#define AQ_RX_PD_L4_TCP 0x10202#define AQ_RX_PD_L3_TYPE_MASK 0x60203#define AQ_RX_PD_L3_IP 0x20204#define AQ_RX_PD_L3_IP6 0x40205 206#define AQ_RX_PD_VLAN BIT(10)207#define AQ_RX_PD_RX_OK BIT(11)208#define AQ_RX_PD_DROP BIT(31)209#define AQ_RX_PD_LEN_MASK 0x7FFF0000210#define AQ_RX_PD_LEN_SHIFT 0x10211#define AQ_RX_PD_VLAN_SHIFT 0x20212 213/* RX Descriptor header */214#define AQ_RX_DH_PKT_CNT_MASK 0x1FFF215#define AQ_RX_DH_DESC_OFFSET_MASK 0xFFFFE000216#define AQ_RX_DH_DESC_OFFSET_SHIFT 0x0D217 218static struct {219 unsigned char ctrl;220 unsigned char timer_l;221 unsigned char timer_h;222 unsigned char size;223 unsigned char ifg;224} AQC111_BULKIN_SIZE[] = {225 /* xHCI & EHCI & OHCI */226 {7, 0x00, 0x01, 0x1E, 0xFF},/* 10G, 5G, 2.5G, 1G */227 {7, 0xA0, 0x00, 0x14, 0x00},/* 100M */228 /* Jumbo packet */229 {7, 0x00, 0x01, 0x18, 0xFF},230};231 232#endif /* __LINUX_USBNET_AQC111_H */233