brintos / linux-shallow public Read only

1// SPDX-License-Identifier: GPL-2.0-only2/*3 *  Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.4 */5 6#include <linux/signal.h>7#include <linux/slab.h>8#include <linux/module.h>9#include <linux/netdevice.h>10#include <linux/etherdevice.h>11#include <linux/mii.h>12#include <linux/ethtool.h>13#include <linux/phy.h>14#include <linux/usb.h>15#include <linux/crc32.h>16#include <linux/if_vlan.h>17#include <linux/uaccess.h>18#include <linux/list.h>19#include <linux/ip.h>20#include <linux/ipv6.h>21#include <net/ip6_checksum.h>22#include <uapi/linux/mdio.h>23#include <linux/mdio.h>24#include <linux/usb/cdc.h>25#include <linux/suspend.h>26#include <linux/atomic.h>27#include <linux/acpi.h>28#include <linux/firmware.h>29#include <crypto/hash.h>30#include <linux/usb/r8152.h>31#include <net/gso.h>32 33/* Information for net-next */34#define NETNEXT_VERSION		"12"35 36/* Information for net */37#define NET_VERSION		"13"38 39#define DRIVER_VERSION		"v1." NETNEXT_VERSION "." NET_VERSION40#define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"41#define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"42#define MODULENAME "r8152"43 44#define R8152_PHY_ID		3245 46#define PLA_IDR			0xc00047#define PLA_RCR			0xc01048#define PLA_RCR1		0xc01249#define PLA_RMS			0xc01650#define PLA_RXFIFO_CTRL0	0xc0a051#define PLA_RXFIFO_FULL		0xc0a252#define PLA_RXFIFO_CTRL1	0xc0a453#define PLA_RX_FIFO_FULL	0xc0a654#define PLA_RXFIFO_CTRL2	0xc0a855#define PLA_RX_FIFO_EMPTY	0xc0aa56#define PLA_DMY_REG0		0xc0b057#define PLA_FMC			0xc0b458#define PLA_CFG_WOL		0xc0b659#define PLA_TEREDO_CFG		0xc0bc60#define PLA_TEREDO_WAKE_BASE	0xc0c461#define PLA_MAR			0xcd0062#define PLA_BACKUP		0xd00063#define PLA_BDC_CR		0xd1a064#define PLA_TEREDO_TIMER	0xd2cc65#define PLA_REALWOW_TIMER	0xd2e866#define PLA_UPHY_TIMER		0xd38867#define PLA_SUSPEND_FLAG	0xd38a68#define PLA_INDICATE_FALG	0xd38c69#define PLA_MACDBG_PRE		0xd38c	/* RTL_VER_04 only */70#define PLA_MACDBG_POST		0xd38e	/* RTL_VER_04 only */71#define PLA_EXTRA_STATUS	0xd39872#define PLA_GPHY_CTRL		0xd3ae73#define PLA_POL_GPIO_CTRL	0xdc6a74#define PLA_EFUSE_DATA		0xdd0075#define PLA_EFUSE_CMD		0xdd0276#define PLA_LEDSEL		0xdd9077#define PLA_LED_FEATURE		0xdd9278#define PLA_PHYAR		0xde0079#define PLA_BOOT_CTRL		0xe00480#define PLA_LWAKE_CTRL_REG	0xe00781#define PLA_GPHY_INTR_IMR	0xe02282#define PLA_EEE_CR		0xe04083#define PLA_EEE_TXTWSYS		0xe04c84#define PLA_EEE_TXTWSYS_2P5G	0xe05885#define PLA_EEEP_CR		0xe08086#define PLA_MAC_PWR_CTRL	0xe0c087#define PLA_MAC_PWR_CTRL2	0xe0ca88#define PLA_MAC_PWR_CTRL3	0xe0cc89#define PLA_MAC_PWR_CTRL4	0xe0ce90#define PLA_WDT6_CTRL		0xe42891#define PLA_TCR0		0xe61092#define PLA_TCR1		0xe61293#define PLA_MTPS		0xe61594#define PLA_TXFIFO_CTRL		0xe61895#define PLA_TXFIFO_FULL		0xe61a96#define PLA_RSTTALLY		0xe80097#define PLA_CR			0xe81398#define PLA_CRWECR		0xe81c99#define PLA_CONFIG12		0xe81e	/* CONFIG1, CONFIG2 */100#define PLA_CONFIG34		0xe820	/* CONFIG3, CONFIG4 */101#define PLA_CONFIG5		0xe822102#define PLA_PHY_PWR		0xe84c103#define PLA_OOB_CTRL		0xe84f104#define PLA_CPCR		0xe854105#define PLA_MISC_0		0xe858106#define PLA_MISC_1		0xe85a107#define PLA_OCP_GPHY_BASE	0xe86c108#define PLA_TALLYCNT		0xe890109#define PLA_SFF_STS_7		0xe8de110#define PLA_PHYSTATUS		0xe908111#define PLA_CONFIG6		0xe90a /* CONFIG6 */112#define PLA_USB_CFG		0xe952113#define PLA_BP_BA		0xfc26114#define PLA_BP_0		0xfc28115#define PLA_BP_1		0xfc2a116#define PLA_BP_2		0xfc2c117#define PLA_BP_3		0xfc2e118#define PLA_BP_4		0xfc30119#define PLA_BP_5		0xfc32120#define PLA_BP_6		0xfc34121#define PLA_BP_7		0xfc36122#define PLA_BP_EN		0xfc38123 124#define USB_USB2PHY		0xb41e125#define USB_SSPHYLINK1		0xb426126#define USB_SSPHYLINK2		0xb428127#define USB_L1_CTRL		0xb45e128#define USB_U2P3_CTRL		0xb460129#define USB_CSR_DUMMY1		0xb464130#define USB_CSR_DUMMY2		0xb466131#define USB_DEV_STAT		0xb808132#define USB_CONNECT_TIMER	0xcbf8133#define USB_MSC_TIMER		0xcbfc134#define USB_BURST_SIZE		0xcfc0135#define USB_FW_FIX_EN0		0xcfca136#define USB_FW_FIX_EN1		0xcfcc137#define USB_LPM_CONFIG		0xcfd8138#define USB_ECM_OPTION		0xcfee139#define USB_CSTMR		0xcfef	/* RTL8153A */140#define USB_MISC_2		0xcfff141#define USB_ECM_OP		0xd26b142#define USB_GPHY_CTRL		0xd284143#define USB_SPEED_OPTION	0xd32a144#define USB_FW_CTRL		0xd334	/* RTL8153B */145#define USB_FC_TIMER		0xd340146#define USB_USB_CTRL		0xd406147#define USB_PHY_CTRL		0xd408148#define USB_TX_AGG		0xd40a149#define USB_RX_BUF_TH		0xd40c150#define USB_USB_TIMER		0xd428151#define USB_RX_EARLY_TIMEOUT	0xd42c152#define USB_RX_EARLY_SIZE	0xd42e153#define USB_PM_CTRL_STATUS	0xd432	/* RTL8153A */154#define USB_RX_EXTRA_AGGR_TMR	0xd432	/* RTL8153B */155#define USB_TX_DMA		0xd434156#define USB_UPT_RXDMA_OWN	0xd437157#define USB_UPHY3_MDCMDIO	0xd480158#define USB_TOLERANCE		0xd490159#define USB_LPM_CTRL		0xd41a160#define USB_BMU_RESET		0xd4b0161#define USB_BMU_CONFIG		0xd4b4162#define USB_U1U2_TIMER		0xd4da163#define USB_FW_TASK		0xd4e8	/* RTL8153B */164#define USB_RX_AGGR_NUM		0xd4ee165#define USB_UPS_CTRL		0xd800166#define USB_POWER_CUT		0xd80a167#define USB_MISC_0		0xd81a168#define USB_MISC_1		0xd81f169#define USB_AFE_CTRL2		0xd824170#define USB_UPHY_XTAL		0xd826171#define USB_UPS_CFG		0xd842172#define USB_UPS_FLAGS		0xd848173#define USB_WDT1_CTRL		0xe404174#define USB_WDT11_CTRL		0xe43c175#define USB_BP_BA		PLA_BP_BA176#define USB_BP_0		PLA_BP_0177#define USB_BP_1		PLA_BP_1178#define USB_BP_2		PLA_BP_2179#define USB_BP_3		PLA_BP_3180#define USB_BP_4		PLA_BP_4181#define USB_BP_5		PLA_BP_5182#define USB_BP_6		PLA_BP_6183#define USB_BP_7		PLA_BP_7184#define USB_BP_EN		PLA_BP_EN	/* RTL8153A */185#define USB_BP_8		0xfc38		/* RTL8153B */186#define USB_BP_9		0xfc3a187#define USB_BP_10		0xfc3c188#define USB_BP_11		0xfc3e189#define USB_BP_12		0xfc40190#define USB_BP_13		0xfc42191#define USB_BP_14		0xfc44192#define USB_BP_15		0xfc46193#define USB_BP2_EN		0xfc48194 195/* OCP Registers */196#define OCP_ALDPS_CONFIG	0x2010197#define OCP_EEE_CONFIG1		0x2080198#define OCP_EEE_CONFIG2		0x2092199#define OCP_EEE_CONFIG3		0x2094200#define OCP_BASE_MII		0xa400201#define OCP_EEE_AR		0xa41a202#define OCP_EEE_DATA		0xa41c203#define OCP_PHY_STATUS		0xa420204#define OCP_INTR_EN		0xa424205#define OCP_NCTL_CFG		0xa42c206#define OCP_POWER_CFG		0xa430207#define OCP_EEE_CFG		0xa432208#define OCP_SRAM_ADDR		0xa436209#define OCP_SRAM_DATA		0xa438210#define OCP_DOWN_SPEED		0xa442211#define OCP_EEE_ABLE		0xa5c4212#define OCP_EEE_ADV		0xa5d0213#define OCP_EEE_LPABLE		0xa5d2214#define OCP_10GBT_CTRL		0xa5d4215#define OCP_10GBT_STAT		0xa5d6216#define OCP_EEE_ADV2		0xa6d4217#define OCP_PHY_STATE		0xa708		/* nway state for 8153 */218#define OCP_PHY_PATCH_STAT	0xb800219#define OCP_PHY_PATCH_CMD	0xb820220#define OCP_PHY_LOCK		0xb82e221#define OCP_ADC_IOFFSET		0xbcfc222#define OCP_ADC_CFG		0xbc06223#define OCP_SYSCLK_CFG		0xc416224 225/* SRAM Register */226#define SRAM_GREEN_CFG		0x8011227#define SRAM_LPF_CFG		0x8012228#define SRAM_GPHY_FW_VER	0x801e229#define SRAM_10M_AMP1		0x8080230#define SRAM_10M_AMP2		0x8082231#define SRAM_IMPEDANCE		0x8084232#define SRAM_PHY_LOCK		0xb82e233 234/* PLA_RCR */235#define RCR_AAP			0x00000001236#define RCR_APM			0x00000002237#define RCR_AM			0x00000004238#define RCR_AB			0x00000008239#define RCR_ACPT_ALL		(RCR_AAP | RCR_APM | RCR_AM | RCR_AB)240#define SLOT_EN			BIT(11)241 242/* PLA_RCR1 */243#define OUTER_VLAN		BIT(7)244#define INNER_VLAN		BIT(6)245 246/* PLA_RXFIFO_CTRL0 */247#define RXFIFO_THR1_NORMAL	0x00080002248#define RXFIFO_THR1_OOB		0x01800003249 250/* PLA_RXFIFO_FULL */251#define RXFIFO_FULL_MASK	0xfff252 253/* PLA_RXFIFO_CTRL1 */254#define RXFIFO_THR2_FULL	0x00000060255#define RXFIFO_THR2_HIGH	0x00000038256#define RXFIFO_THR2_OOB		0x0000004a257#define RXFIFO_THR2_NORMAL	0x00a0258 259/* PLA_RXFIFO_CTRL2 */260#define RXFIFO_THR3_FULL	0x00000078261#define RXFIFO_THR3_HIGH	0x00000048262#define RXFIFO_THR3_OOB		0x0000005a263#define RXFIFO_THR3_NORMAL	0x0110264 265/* PLA_TXFIFO_CTRL */266#define TXFIFO_THR_NORMAL	0x00400008267#define TXFIFO_THR_NORMAL2	0x01000008268 269/* PLA_DMY_REG0 */270#define ECM_ALDPS		0x0002271 272/* PLA_FMC */273#define FMC_FCR_MCU_EN		0x0001274 275/* PLA_EEEP_CR */276#define EEEP_CR_EEEP_TX		0x0002277 278/* PLA_WDT6_CTRL */279#define WDT6_SET_MODE		0x0010280 281/* PLA_TCR0 */282#define TCR0_TX_EMPTY		0x0800283#define TCR0_AUTO_FIFO		0x0080284 285/* PLA_TCR1 */286#define VERSION_MASK		0x7cf0287#define IFG_MASK		(BIT(3) | BIT(9) | BIT(8))288#define IFG_144NS		BIT(9)289#define IFG_96NS		(BIT(9) | BIT(8))290 291/* PLA_MTPS */292#define MTPS_JUMBO		(12 * 1024 / 64)293#define MTPS_DEFAULT		(6 * 1024 / 64)294 295/* PLA_RSTTALLY */296#define TALLY_RESET		0x0001297 298/* PLA_CR */299#define CR_RST			0x10300#define CR_RE			0x08301#define CR_TE			0x04302 303/* PLA_CRWECR */304#define CRWECR_NORAML		0x00305#define CRWECR_CONFIG		0xc0306 307/* PLA_OOB_CTRL */308#define NOW_IS_OOB		0x80309#define TXFIFO_EMPTY		0x20310#define RXFIFO_EMPTY		0x10311#define LINK_LIST_READY		0x02312#define DIS_MCU_CLROOB		0x01313#define FIFO_EMPTY		(TXFIFO_EMPTY | RXFIFO_EMPTY)314 315/* PLA_MISC_1 */316#define RXDY_GATED_EN		0x0008317 318/* PLA_SFF_STS_7 */319#define RE_INIT_LL		0x8000320#define MCU_BORW_EN		0x4000321 322/* PLA_CPCR */323#define FLOW_CTRL_EN		BIT(0)324#define CPCR_RX_VLAN		0x0040325 326/* PLA_CFG_WOL */327#define MAGIC_EN		0x0001328 329/* PLA_TEREDO_CFG */330#define TEREDO_SEL		0x8000331#define TEREDO_WAKE_MASK	0x7f00332#define TEREDO_RS_EVENT_MASK	0x00fe333#define OOB_TEREDO_EN		0x0001334 335/* PLA_BDC_CR */336#define ALDPS_PROXY_MODE	0x0001337 338/* PLA_EFUSE_CMD */339#define EFUSE_READ_CMD		BIT(15)340#define EFUSE_DATA_BIT16	BIT(7)341 342/* PLA_CONFIG34 */343#define LINK_ON_WAKE_EN		0x0010344#define LINK_OFF_WAKE_EN	0x0008345 346/* PLA_CONFIG6 */347#define LANWAKE_CLR_EN		BIT(0)348 349/* PLA_USB_CFG */350#define EN_XG_LIP		BIT(1)351#define EN_G_LIP		BIT(2)352 353/* PLA_CONFIG5 */354#define BWF_EN			0x0040355#define MWF_EN			0x0020356#define UWF_EN			0x0010357#define LAN_WAKE_EN		0x0002358 359/* PLA_LED_FEATURE */360#define LED_MODE_MASK		0x0700361 362/* PLA_PHY_PWR */363#define TX_10M_IDLE_EN		0x0080364#define PFM_PWM_SWITCH		0x0040365#define TEST_IO_OFF		BIT(4)366 367/* PLA_MAC_PWR_CTRL */368#define D3_CLK_GATED_EN		0x00004000369#define MCU_CLK_RATIO		0x07010f07370#define MCU_CLK_RATIO_MASK	0x0f0f0f0f371#define ALDPS_SPDWN_RATIO	0x0f87372 373/* PLA_MAC_PWR_CTRL2 */374#define EEE_SPDWN_RATIO		0x8007375#define MAC_CLK_SPDWN_EN	BIT(15)376#define EEE_SPDWN_RATIO_MASK	0xff377 378/* PLA_MAC_PWR_CTRL3 */379#define PLA_MCU_SPDWN_EN	BIT(14)380#define PKT_AVAIL_SPDWN_EN	0x0100381#define SUSPEND_SPDWN_EN	0x0004382#define U1U2_SPDWN_EN		0x0002383#define L1_SPDWN_EN		0x0001384 385/* PLA_MAC_PWR_CTRL4 */386#define PWRSAVE_SPDWN_EN	0x1000387#define RXDV_SPDWN_EN		0x0800388#define TX10MIDLE_EN		0x0100389#define IDLE_SPDWN_EN		BIT(6)390#define TP100_SPDWN_EN		0x0020391#define TP500_SPDWN_EN		0x0010392#define TP1000_SPDWN_EN		0x0008393#define EEE_SPDWN_EN		0x0001394 395/* PLA_GPHY_INTR_IMR */396#define GPHY_STS_MSK		0x0001397#define SPEED_DOWN_MSK		0x0002398#define SPDWN_RXDV_MSK		0x0004399#define SPDWN_LINKCHG_MSK	0x0008400 401/* PLA_PHYAR */402#define PHYAR_FLAG		0x80000000403 404/* PLA_EEE_CR */405#define EEE_RX_EN		0x0001406#define EEE_TX_EN		0x0002407 408/* PLA_BOOT_CTRL */409#define AUTOLOAD_DONE		0x0002410 411/* PLA_LWAKE_CTRL_REG */412#define LANWAKE_PIN		BIT(7)413 414/* PLA_SUSPEND_FLAG */415#define LINK_CHG_EVENT		BIT(0)416 417/* PLA_INDICATE_FALG */418#define UPCOMING_RUNTIME_D3	BIT(0)419 420/* PLA_MACDBG_PRE and PLA_MACDBG_POST */421#define DEBUG_OE		BIT(0)422#define DEBUG_LTSSM		0x0082423 424/* PLA_EXTRA_STATUS */425#define CUR_LINK_OK		BIT(15)426#define U3P3_CHECK_EN		BIT(7)	/* RTL_VER_05 only */427#define LINK_CHANGE_FLAG	BIT(8)428#define POLL_LINK_CHG		BIT(0)429 430/* PLA_GPHY_CTRL */431#define GPHY_FLASH		BIT(1)432 433/* PLA_POL_GPIO_CTRL */434#define DACK_DET_EN		BIT(15)435#define POL_GPHY_PATCH		BIT(4)436 437/* USB_USB2PHY */438#define USB2PHY_SUSPEND		0x0001439#define USB2PHY_L1		0x0002440 441/* USB_SSPHYLINK1 */442#define DELAY_PHY_PWR_CHG	BIT(1)443 444/* USB_SSPHYLINK2 */445#define pwd_dn_scale_mask	0x3ffe446#define pwd_dn_scale(x)		((x) << 1)447 448/* USB_CSR_DUMMY1 */449#define DYNAMIC_BURST		0x0001450 451/* USB_CSR_DUMMY2 */452#define EP4_FULL_FC		0x0001453 454/* USB_DEV_STAT */455#define STAT_SPEED_MASK		0x0006456#define STAT_SPEED_HIGH		0x0000457#define STAT_SPEED_FULL		0x0002458 459/* USB_FW_FIX_EN0 */460#define FW_FIX_SUSPEND		BIT(14)461 462/* USB_FW_FIX_EN1 */463#define FW_IP_RESET_EN		BIT(9)464 465/* USB_LPM_CONFIG */466#define LPM_U1U2_EN		BIT(0)467 468/* USB_TX_AGG */469#define TX_AGG_MAX_THRESHOLD	0x03470 471/* USB_RX_BUF_TH */472#define RX_THR_SUPPER		0x0c350180473#define RX_THR_HIGH		0x7a120180474#define RX_THR_SLOW		0xffff0180475#define RX_THR_B		0x00010001476 477/* USB_TX_DMA */478#define TEST_MODE_DISABLE	0x00000001479#define TX_SIZE_ADJUST1		0x00000100480 481/* USB_BMU_RESET */482#define BMU_RESET_EP_IN		0x01483#define BMU_RESET_EP_OUT	0x02484 485/* USB_BMU_CONFIG */486#define ACT_ODMA		BIT(1)487 488/* USB_UPT_RXDMA_OWN */489#define OWN_UPDATE		BIT(0)490#define OWN_CLEAR		BIT(1)491 492/* USB_FW_TASK */493#define FC_PATCH_TASK		BIT(1)494 495/* USB_RX_AGGR_NUM */496#define RX_AGGR_NUM_MASK	0x1ff497 498/* USB_UPS_CTRL */499#define POWER_CUT		0x0100500 501/* USB_PM_CTRL_STATUS */502#define RESUME_INDICATE		0x0001503 504/* USB_ECM_OPTION */505#define BYPASS_MAC_RESET	BIT(5)506 507/* USB_CSTMR */508#define FORCE_SUPER		BIT(0)509 510/* USB_MISC_2 */511#define UPS_FORCE_PWR_DOWN	BIT(0)512 513/* USB_ECM_OP */514#define	EN_ALL_SPEED		BIT(0)515 516/* USB_GPHY_CTRL */517#define GPHY_PATCH_DONE		BIT(2)518#define BYPASS_FLASH		BIT(5)519#define BACKUP_RESTRORE		BIT(6)520 521/* USB_SPEED_OPTION */522#define RG_PWRDN_EN		BIT(8)523#define ALL_SPEED_OFF		BIT(9)524 525/* USB_FW_CTRL */526#define FLOW_CTRL_PATCH_OPT	BIT(1)527#define AUTO_SPEEDUP		BIT(3)528#define FLOW_CTRL_PATCH_2	BIT(8)529 530/* USB_FC_TIMER */531#define CTRL_TIMER_EN		BIT(15)532 533/* USB_USB_CTRL */534#define CDC_ECM_EN		BIT(3)535#define RX_AGG_DISABLE		0x0010536#define RX_ZERO_EN		0x0080537 538/* USB_U2P3_CTRL */539#define U2P3_ENABLE		0x0001540#define RX_DETECT8		BIT(3)541 542/* USB_POWER_CUT */543#define PWR_EN			0x0001544#define PHASE2_EN		0x0008545#define UPS_EN			BIT(4)546#define USP_PREWAKE		BIT(5)547 548/* USB_MISC_0 */549#define PCUT_STATUS		0x0001550 551/* USB_RX_EARLY_TIMEOUT */552#define COALESCE_SUPER		 85000U553#define COALESCE_HIGH		250000U554#define COALESCE_SLOW		524280U555 556/* USB_WDT1_CTRL */557#define WTD1_EN			BIT(0)558 559/* USB_WDT11_CTRL */560#define TIMER11_EN		0x0001561 562/* USB_LPM_CTRL */563/* bit 4 ~ 5: fifo empty boundary */564#define FIFO_EMPTY_1FB		0x30	/* 0x1fb * 64 = 32448 bytes */565/* bit 2 ~ 3: LMP timer */566#define LPM_TIMER_MASK		0x0c567#define LPM_TIMER_500MS		0x04	/* 500 ms */568#define LPM_TIMER_500US		0x0c	/* 500 us */569#define ROK_EXIT_LPM		0x02570 571/* USB_AFE_CTRL2 */572#define SEN_VAL_MASK		0xf800573#define SEN_VAL_NORMAL		0xa000574#define SEL_RXIDLE		0x0100575 576/* USB_UPHY_XTAL */577#define OOBS_POLLING		BIT(8)578 579/* USB_UPS_CFG */580#define SAW_CNT_1MS_MASK	0x0fff581#define MID_REVERSE		BIT(5)	/* RTL8156A */582 583/* USB_UPS_FLAGS */584#define UPS_FLAGS_R_TUNE		BIT(0)585#define UPS_FLAGS_EN_10M_CKDIV		BIT(1)586#define UPS_FLAGS_250M_CKDIV		BIT(2)587#define UPS_FLAGS_EN_ALDPS		BIT(3)588#define UPS_FLAGS_CTAP_SHORT_DIS	BIT(4)589#define UPS_FLAGS_SPEED_MASK		(0xf << 16)590#define ups_flags_speed(x)		((x) << 16)591#define UPS_FLAGS_EN_EEE		BIT(20)592#define UPS_FLAGS_EN_500M_EEE		BIT(21)593#define UPS_FLAGS_EN_EEE_CKDIV		BIT(22)594#define UPS_FLAGS_EEE_PLLOFF_100	BIT(23)595#define UPS_FLAGS_EEE_PLLOFF_GIGA	BIT(24)596#define UPS_FLAGS_EEE_CMOD_LV_EN	BIT(25)597#define UPS_FLAGS_EN_GREEN		BIT(26)598#define UPS_FLAGS_EN_FLOW_CTR		BIT(27)599 600enum spd_duplex {601	NWAY_10M_HALF,602	NWAY_10M_FULL,603	NWAY_100M_HALF,604	NWAY_100M_FULL,605	NWAY_1000M_FULL,606	FORCE_10M_HALF,607	FORCE_10M_FULL,608	FORCE_100M_HALF,609	FORCE_100M_FULL,610	FORCE_1000M_FULL,611	NWAY_2500M_FULL,612};613 614/* OCP_ALDPS_CONFIG */615#define ENPWRSAVE		0x8000616#define ENPDNPS			0x0200617#define LINKENA			0x0100618#define DIS_SDSAVE		0x0010619 620/* OCP_PHY_STATUS */621#define PHY_STAT_MASK		0x0007622#define PHY_STAT_EXT_INIT	2623#define PHY_STAT_LAN_ON		3624#define PHY_STAT_PWRDN		5625 626/* OCP_INTR_EN */627#define INTR_SPEED_FORCE	BIT(3)628 629/* OCP_NCTL_CFG */630#define PGA_RETURN_EN		BIT(1)631 632/* OCP_POWER_CFG */633#define EEE_CLKDIV_EN		0x8000634#define EN_ALDPS		0x0004635#define EN_10M_PLLOFF		0x0001636 637/* OCP_EEE_CONFIG1 */638#define RG_TXLPI_MSK_HFDUP	0x8000639#define RG_MATCLR_EN		0x4000640#define EEE_10_CAP		0x2000641#define EEE_NWAY_EN		0x1000642#define TX_QUIET_EN		0x0200643#define RX_QUIET_EN		0x0100644#define sd_rise_time_mask	0x0070645#define sd_rise_time(x)		(min(x, 7) << 4)	/* bit 4 ~ 6 */646#define RG_RXLPI_MSK_HFDUP	0x0008647#define SDFALLTIME		0x0007	/* bit 0 ~ 2 */648 649/* OCP_EEE_CONFIG2 */650#define RG_LPIHYS_NUM		0x7000	/* bit 12 ~ 15 */651#define RG_DACQUIET_EN		0x0400652#define RG_LDVQUIET_EN		0x0200653#define RG_CKRSEL		0x0020654#define RG_EEEPRG_EN		0x0010655 656/* OCP_EEE_CONFIG3 */657#define fast_snr_mask		0xff80658#define fast_snr(x)		(min(x, 0x1ff) << 7)	/* bit 7 ~ 15 */659#define RG_LFS_SEL		0x0060	/* bit 6 ~ 5 */660#define MSK_PH			0x0006	/* bit 0 ~ 3 */661 662/* OCP_EEE_AR */663/* bit[15:14] function */664#define FUN_ADDR		0x0000665#define FUN_DATA		0x4000666/* bit[4:0] device addr */667 668/* OCP_EEE_CFG */669#define CTAP_SHORT_EN		0x0040670#define EEE10_EN		0x0010671 672/* OCP_DOWN_SPEED */673#define EN_EEE_CMODE		BIT(14)674#define EN_EEE_1000		BIT(13)675#define EN_EEE_100		BIT(12)676#define EN_10M_CLKDIV		BIT(11)677#define EN_10M_BGOFF		0x0080678 679/* OCP_10GBT_CTRL */680#define RTL_ADV2_5G_F_R		BIT(5)	/* Advertise 2.5GBASE-T fast-retrain */681 682/* OCP_PHY_STATE */683#define TXDIS_STATE		0x01684#define ABD_STATE		0x02685 686/* OCP_PHY_PATCH_STAT */687#define PATCH_READY		BIT(6)688 689/* OCP_PHY_PATCH_CMD */690#define PATCH_REQUEST		BIT(4)691 692/* OCP_PHY_LOCK */693#define PATCH_LOCK		BIT(0)694 695/* OCP_ADC_CFG */696#define CKADSEL_L		0x0100697#define ADC_EN			0x0080698#define EN_EMI_L		0x0040699 700/* OCP_SYSCLK_CFG */701#define sysclk_div_expo(x)	(min(x, 5) << 8)702#define clk_div_expo(x)		(min(x, 5) << 4)703 704/* SRAM_GREEN_CFG */705#define GREEN_ETH_EN		BIT(15)706#define R_TUNE_EN		BIT(11)707 708/* SRAM_LPF_CFG */709#define LPF_AUTO_TUNE		0x8000710 711/* SRAM_10M_AMP1 */712#define GDAC_IB_UPALL		0x0008713 714/* SRAM_10M_AMP2 */715#define AMP_DN			0x0200716 717/* SRAM_IMPEDANCE */718#define RX_DRIVING_MASK		0x6000719 720/* SRAM_PHY_LOCK */721#define PHY_PATCH_LOCK		0x0001722 723/* MAC PASSTHRU */724#define AD_MASK			0xfee0725#define BND_MASK		0x0004726#define BD_MASK			0x0001727#define EFUSE			0xcfdb728#define PASS_THRU_MASK		0x1729 730#define BP4_SUPER_ONLY		0x1578	/* RTL_VER_04 only */731 732enum rtl_register_content {733	_2500bps	= BIT(10),734	_1250bps	= BIT(9),735	_500bps		= BIT(8),736	_tx_flow	= BIT(6),737	_rx_flow	= BIT(5),738	_1000bps	= 0x10,739	_100bps		= 0x08,740	_10bps		= 0x04,741	LINK_STATUS	= 0x02,742	FULL_DUP	= 0x01,743};744 745#define is_speed_2500(_speed)	(((_speed) & (_2500bps | LINK_STATUS)) == (_2500bps | LINK_STATUS))746#define is_flow_control(_speed)	(((_speed) & (_tx_flow | _rx_flow)) == (_tx_flow | _rx_flow))747 748#define RTL8152_MAX_TX		4749#define RTL8152_MAX_RX		10750#define INTBUFSIZE		2751#define TX_ALIGN		4752#define RX_ALIGN		8753 754#define RTL8152_RX_MAX_PENDING	4096755#define RTL8152_RXFG_HEADSZ	256756 757#define INTR_LINK		0x0004758 759#define RTL8152_RMS		(VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)760#define RTL8153_RMS		RTL8153_MAX_PACKET761#define RTL8152_TX_TIMEOUT	(5 * HZ)762#define mtu_to_size(m)		((m) + VLAN_ETH_HLEN + ETH_FCS_LEN)763#define size_to_mtu(s)		((s) - VLAN_ETH_HLEN - ETH_FCS_LEN)764#define rx_reserved_size(x)	(mtu_to_size(x) + sizeof(struct rx_desc) + RX_ALIGN)765 766/* rtl8152 flags */767enum rtl8152_flags {768	RTL8152_INACCESSIBLE = 0,769	RTL8152_SET_RX_MODE,770	WORK_ENABLE,771	RTL8152_LINK_CHG,772	SELECTIVE_SUSPEND,773	PHY_RESET,774	SCHEDULE_TASKLET,775	GREEN_ETHERNET,776	RX_EPROTO,777	IN_PRE_RESET,778	PROBED_WITH_NO_ERRORS,779	PROBE_SHOULD_RETRY,780};781 782#define DEVICE_ID_LENOVO_USB_C_TRAVEL_HUB		0x721e783#define DEVICE_ID_THINKPAD_ONELINK_PLUS_DOCK		0x3054784#define DEVICE_ID_THINKPAD_THUNDERBOLT3_DOCK_GEN2	0x3082785#define DEVICE_ID_THINKPAD_USB_C_DONGLE			0x720c786#define DEVICE_ID_THINKPAD_USB_C_DOCK_GEN2		0xa387787#define DEVICE_ID_THINKPAD_USB_C_DOCK_GEN3		0x3062788 789struct tally_counter {790	__le64	tx_packets;791	__le64	rx_packets;792	__le64	tx_errors;793	__le32	rx_errors;794	__le16	rx_missed;795	__le16	align_errors;796	__le32	tx_one_collision;797	__le32	tx_multi_collision;798	__le64	rx_unicast;799	__le64	rx_broadcast;800	__le32	rx_multicast;801	__le16	tx_aborted;802	__le16	tx_underrun;803};804 805struct rx_desc {806	__le32 opts1;807#define RX_LEN_MASK			0x7fff808 809	__le32 opts2;810#define RD_UDP_CS			BIT(23)811#define RD_TCP_CS			BIT(22)812#define RD_IPV6_CS			BIT(20)813#define RD_IPV4_CS			BIT(19)814 815	__le32 opts3;816#define IPF				BIT(23) /* IP checksum fail */817#define UDPF				BIT(22) /* UDP checksum fail */818#define TCPF				BIT(21) /* TCP checksum fail */819#define RX_VLAN_TAG			BIT(16)820 821	__le32 opts4;822	__le32 opts5;823	__le32 opts6;824};825 826struct tx_desc {827	__le32 opts1;828#define TX_FS			BIT(31) /* First segment of a packet */829#define TX_LS			BIT(30) /* Final segment of a packet */830#define GTSENDV4		BIT(28)831#define GTSENDV6		BIT(27)832#define GTTCPHO_SHIFT		18833#define GTTCPHO_MAX		0x7fU834#define TX_LEN_MAX		0x3ffffU835 836	__le32 opts2;837#define UDP_CS			BIT(31) /* Calculate UDP/IP checksum */838#define TCP_CS			BIT(30) /* Calculate TCP/IP checksum */839#define IPV4_CS			BIT(29) /* Calculate IPv4 checksum */840#define IPV6_CS			BIT(28) /* Calculate IPv6 checksum */841#define MSS_SHIFT		17842#define MSS_MAX			0x7ffU843#define TCPHO_SHIFT		17844#define TCPHO_MAX		0x7ffU845#define TX_VLAN_TAG		BIT(16)846};847 848struct r8152;849 850struct rx_agg {851	struct list_head list, info_list;852	struct urb *urb;853	struct r8152 *context;854	struct page *page;855	void *buffer;856};857 858struct tx_agg {859	struct list_head list;860	struct urb *urb;861	struct r8152 *context;862	void *buffer;863	void *head;864	u32 skb_num;865	u32 skb_len;866};867 868struct r8152 {869	unsigned long flags;870	struct usb_device *udev;871	struct napi_struct napi;872	struct usb_interface *intf;873	struct net_device *netdev;874	struct urb *intr_urb;875	struct tx_agg tx_info[RTL8152_MAX_TX];876	struct list_head rx_info, rx_used;877	struct list_head rx_done, tx_free;878	struct sk_buff_head tx_queue, rx_queue;879	spinlock_t rx_lock, tx_lock;880	struct delayed_work schedule, hw_phy_work;881	struct mii_if_info mii;882	struct mutex control;	/* use for hw setting */883#ifdef CONFIG_PM_SLEEP884	struct notifier_block pm_notifier;885#endif886	struct tasklet_struct tx_tl;887 888	struct rtl_ops {889		void (*init)(struct r8152 *tp);890		int (*enable)(struct r8152 *tp);891		void (*disable)(struct r8152 *tp);892		void (*up)(struct r8152 *tp);893		void (*down)(struct r8152 *tp);894		void (*unload)(struct r8152 *tp);895		int (*eee_get)(struct r8152 *tp, struct ethtool_keee *eee);896		int (*eee_set)(struct r8152 *tp, struct ethtool_keee *eee);897		bool (*in_nway)(struct r8152 *tp);898		void (*hw_phy_cfg)(struct r8152 *tp);899		void (*autosuspend_en)(struct r8152 *tp, bool enable);900		void (*change_mtu)(struct r8152 *tp);901	} rtl_ops;902 903	struct ups_info {904		u32 r_tune:1;905		u32 _10m_ckdiv:1;906		u32 _250m_ckdiv:1;907		u32 aldps:1;908		u32 lite_mode:2;909		u32 speed_duplex:4;910		u32 eee:1;911		u32 eee_lite:1;912		u32 eee_ckdiv:1;913		u32 eee_plloff_100:1;914		u32 eee_plloff_giga:1;915		u32 eee_cmod_lv:1;916		u32 green:1;917		u32 flow_control:1;918		u32 ctap_short_off:1;919	} ups_info;920 921#define RTL_VER_SIZE		32922 923	struct rtl_fw {924		const char *fw_name;925		const struct firmware *fw;926 927		char version[RTL_VER_SIZE];928		int (*pre_fw)(struct r8152 *tp);929		int (*post_fw)(struct r8152 *tp);930 931		bool retry;932	} rtl_fw;933 934	atomic_t rx_count;935 936	bool eee_en;937	int intr_interval;938	u32 saved_wolopts;939	u32 msg_enable;940	u32 tx_qlen;941	u32 coalesce;942	u32 advertising;943	u32 rx_buf_sz;944	u32 rx_copybreak;945	u32 rx_pending;946	u32 fc_pause_on, fc_pause_off;947 948	unsigned int pipe_in, pipe_out, pipe_intr, pipe_ctrl_in, pipe_ctrl_out;949 950	u32 support_2500full:1;951	u32 lenovo_macpassthru:1;952	u32 dell_tb_rx_agg_bug:1;953	u16 ocp_base;954	u16 speed;955	u16 eee_adv;956	u8 *intr_buff;957	u8 version;958	u8 duplex;959	u8 autoneg;960 961	unsigned int reg_access_reset_count;962};963 964/**965 * struct fw_block - block type and total length966 * @type: type of the current block, such as RTL_FW_END, RTL_FW_PLA,967 *	RTL_FW_USB and so on.968 * @length: total length of the current block.969 */970struct fw_block {971	__le32 type;972	__le32 length;973} __packed;974 975/**976 * struct fw_header - header of the firmware file977 * @checksum: checksum of sha256 which is calculated from the whole file978 *	except the checksum field of the file. That is, calculate sha256979 *	from the version field to the end of the file.980 * @version: version of this firmware.981 * @blocks: the first firmware block of the file982 */983struct fw_header {984	u8 checksum[32];985	char version[RTL_VER_SIZE];986	struct fw_block blocks[];987} __packed;988 989enum rtl8152_fw_flags {990	FW_FLAGS_USB = 0,991	FW_FLAGS_PLA,992	FW_FLAGS_START,993	FW_FLAGS_STOP,994	FW_FLAGS_NC,995	FW_FLAGS_NC1,996	FW_FLAGS_NC2,997	FW_FLAGS_UC2,998	FW_FLAGS_UC,999	FW_FLAGS_SPEED_UP,1000	FW_FLAGS_VER,1001};1002 1003enum rtl8152_fw_fixup_cmd {1004	FW_FIXUP_AND = 0,1005	FW_FIXUP_OR,1006	FW_FIXUP_NOT,1007	FW_FIXUP_XOR,1008};1009 1010struct fw_phy_set {1011	__le16 addr;1012	__le16 data;1013} __packed;1014 1015struct fw_phy_speed_up {1016	struct fw_block blk_hdr;1017	__le16 fw_offset;1018	__le16 version;1019	__le16 fw_reg;1020	__le16 reserved;1021	char info[];1022} __packed;1023 1024struct fw_phy_ver {1025	struct fw_block blk_hdr;1026	struct fw_phy_set ver;1027	__le32 reserved;1028} __packed;1029 1030struct fw_phy_fixup {1031	struct fw_block blk_hdr;1032	struct fw_phy_set setting;1033	__le16 bit_cmd;1034	__le16 reserved;1035} __packed;1036 1037struct fw_phy_union {1038	struct fw_block blk_hdr;1039	__le16 fw_offset;1040	__le16 fw_reg;1041	struct fw_phy_set pre_set[2];1042	struct fw_phy_set bp[8];1043	struct fw_phy_set bp_en;1044	u8 pre_num;1045	u8 bp_num;1046	char info[];1047} __packed;1048 1049/**1050 * struct fw_mac - a firmware block used by RTL_FW_PLA and RTL_FW_USB.1051 *	The layout of the firmware block is:1052 *	<struct fw_mac> + <info> + <firmware data>.1053 * @blk_hdr: firmware descriptor (type, length)1054 * @fw_offset: offset of the firmware binary data. The start address of1055 *	the data would be the address of struct fw_mac + @fw_offset.1056 * @fw_reg: the register to load the firmware. Depends on chip.1057 * @bp_ba_addr: the register to write break point base address. Depends on1058 *	chip.1059 * @bp_ba_value: break point base address. Depends on chip.1060 * @bp_en_addr: the register to write break point enabled mask. Depends1061 *	on chip.1062 * @bp_en_value: break point enabled mask. Depends on the firmware.1063 * @bp_start: the start register of break points. Depends on chip.1064 * @bp_num: the break point number which needs to be set for this firmware.1065 *	Depends on the firmware.1066 * @bp: break points. Depends on firmware.1067 * @reserved: reserved space (unused)1068 * @fw_ver_reg: the register to store the fw version.1069 * @fw_ver_data: the firmware version of the current type.1070 * @info: additional information for debugging, and is followed by the1071 *	binary data of firmware.1072 */1073struct fw_mac {1074	struct fw_block blk_hdr;1075	__le16 fw_offset;1076	__le16 fw_reg;1077	__le16 bp_ba_addr;1078	__le16 bp_ba_value;1079	__le16 bp_en_addr;1080	__le16 bp_en_value;1081	__le16 bp_start;1082	__le16 bp_num;1083	__le16 bp[16]; /* any value determined by firmware */1084	__le32 reserved;1085	__le16 fw_ver_reg;1086	u8 fw_ver_data;1087	char info[];1088} __packed;1089 1090/**1091 * struct fw_phy_patch_key - a firmware block used by RTL_FW_PHY_START.1092 *	This is used to set patch key when loading the firmware of PHY.1093 * @blk_hdr: firmware descriptor (type, length)1094 * @key_reg: the register to write the patch key.1095 * @key_data: patch key.1096 * @reserved: reserved space (unused)1097 */1098struct fw_phy_patch_key {1099	struct fw_block blk_hdr;1100	__le16 key_reg;1101	__le16 key_data;1102	__le32 reserved;1103} __packed;1104 1105/**1106 * struct fw_phy_nc - a firmware block used by RTL_FW_PHY_NC.1107 *	The layout of the firmware block is:1108 *	<struct fw_phy_nc> + <info> + <firmware data>.1109 * @blk_hdr: firmware descriptor (type, length)1110 * @fw_offset: offset of the firmware binary data. The start address of1111 *	the data would be the address of struct fw_phy_nc + @fw_offset.1112 * @fw_reg: the register to load the firmware. Depends on chip.1113 * @ba_reg: the register to write the base address. Depends on chip.1114 * @ba_data: base address. Depends on chip.1115 * @patch_en_addr: the register of enabling patch mode. Depends on chip.1116 * @patch_en_value: patch mode enabled mask. Depends on the firmware.1117 * @mode_reg: the regitster of switching the mode.1118 * @mode_pre: the mode needing to be set before loading the firmware.1119 * @mode_post: the mode to be set when finishing to load the firmware.1120 * @reserved: reserved space (unused)1121 * @bp_start: the start register of break points. Depends on chip.1122 * @bp_num: the break point number which needs to be set for this firmware.1123 *	Depends on the firmware.1124 * @bp: break points. Depends on firmware.1125 * @info: additional information for debugging, and is followed by the1126 *	binary data of firmware.1127 */1128struct fw_phy_nc {1129	struct fw_block blk_hdr;1130	__le16 fw_offset;1131	__le16 fw_reg;1132	__le16 ba_reg;1133	__le16 ba_data;1134	__le16 patch_en_addr;1135	__le16 patch_en_value;1136	__le16 mode_reg;1137	__le16 mode_pre;1138	__le16 mode_post;1139	__le16 reserved;1140	__le16 bp_start;1141	__le16 bp_num;1142	__le16 bp[4];1143	char info[];1144} __packed;1145 1146enum rtl_fw_type {1147	RTL_FW_END = 0,1148	RTL_FW_PLA,1149	RTL_FW_USB,1150	RTL_FW_PHY_START,1151	RTL_FW_PHY_STOP,1152	RTL_FW_PHY_NC,1153	RTL_FW_PHY_FIXUP,1154	RTL_FW_PHY_UNION_NC,1155	RTL_FW_PHY_UNION_NC1,1156	RTL_FW_PHY_UNION_NC2,1157	RTL_FW_PHY_UNION_UC2,1158	RTL_FW_PHY_UNION_UC,1159	RTL_FW_PHY_UNION_MISC,1160	RTL_FW_PHY_SPEED_UP,1161	RTL_FW_PHY_VER,1162};1163 1164enum rtl_version {1165	RTL_VER_UNKNOWN = 0,1166	RTL_VER_01,1167	RTL_VER_02,1168	RTL_VER_03,1169	RTL_VER_04,1170	RTL_VER_05,1171	RTL_VER_06,1172	RTL_VER_07,1173	RTL_VER_08,1174	RTL_VER_09,1175 1176	RTL_TEST_01,1177	RTL_VER_10,1178	RTL_VER_11,1179	RTL_VER_12,1180	RTL_VER_13,1181	RTL_VER_14,1182	RTL_VER_15,1183 1184	RTL_VER_MAX1185};1186 1187enum tx_csum_stat {1188	TX_CSUM_SUCCESS = 0,1189	TX_CSUM_TSO,1190	TX_CSUM_NONE1191};1192 1193#define RTL_ADVERTISED_10_HALF			BIT(0)1194#define RTL_ADVERTISED_10_FULL			BIT(1)1195#define RTL_ADVERTISED_100_HALF			BIT(2)1196#define RTL_ADVERTISED_100_FULL			BIT(3)1197#define RTL_ADVERTISED_1000_HALF		BIT(4)1198#define RTL_ADVERTISED_1000_FULL		BIT(5)1199#define RTL_ADVERTISED_2500_FULL		BIT(6)1200 1201/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).1202 * The RTL chips use a 64 element hash table based on the Ethernet CRC.1203 */1204static const int multicast_filter_limit = 32;1205static unsigned int agg_buf_sz = 16384;1206 1207#define RTL_LIMITED_TSO_SIZE	(size_to_mtu(agg_buf_sz) - sizeof(struct tx_desc))1208 1209/* If register access fails then we block access and issue a reset. If this1210 * happens too many times in a row without a successful access then we stop1211 * trying to reset and just leave access blocked.1212 */1213#define REGISTER_ACCESS_MAX_RESETS	31214 1215static void rtl_set_inaccessible(struct r8152 *tp)1216{1217	set_bit(RTL8152_INACCESSIBLE, &tp->flags);1218	smp_mb__after_atomic();1219}1220 1221static void rtl_set_accessible(struct r8152 *tp)1222{1223	clear_bit(RTL8152_INACCESSIBLE, &tp->flags);1224	smp_mb__after_atomic();1225}1226 1227static1228int r8152_control_msg(struct r8152 *tp, unsigned int pipe, __u8 request,1229		      __u8 requesttype, __u16 value, __u16 index, void *data,1230		      __u16 size, const char *msg_tag)1231{1232	struct usb_device *udev = tp->udev;1233	int ret;1234 1235	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))1236		return -ENODEV;1237 1238	ret = usb_control_msg(udev, pipe, request, requesttype,1239			      value, index, data, size,1240			      USB_CTRL_GET_TIMEOUT);1241 1242	/* No need to issue a reset to report an error if the USB device got1243	 * unplugged; just return immediately.1244	 */1245	if (ret == -ENODEV)1246		return ret;1247 1248	/* If the write was successful then we're done */1249	if (ret >= 0) {1250		tp->reg_access_reset_count = 0;1251		return ret;1252	}1253 1254	dev_err(&udev->dev,1255		"Failed to %s %d bytes at %#06x/%#06x (%d)\n",1256		msg_tag, size, value, index, ret);1257 1258	/* Block all future register access until we reset. Much of the code1259	 * in the driver doesn't check for errors. Notably, many parts of the1260	 * driver do a read/modify/write of a register value without1261	 * confirming that the read succeeded. Writing back modified garbage1262	 * like this can fully wedge the adapter, requiring a power cycle.1263	 */1264	rtl_set_inaccessible(tp);1265 1266	/* If probe hasn't yet finished, then we'll request a retry of the1267	 * whole probe routine if we get any control transfer errors. We1268	 * never have to clear this bit since we free/reallocate the whole "tp"1269	 * structure if we retry probe.1270	 */1271	if (!test_bit(PROBED_WITH_NO_ERRORS, &tp->flags)) {1272		set_bit(PROBE_SHOULD_RETRY, &tp->flags);1273		return ret;1274	}1275 1276	/* Failing to access registers in pre-reset is not surprising since we1277	 * wouldn't be resetting if things were behaving normally. The register1278	 * access we do in pre-reset isn't truly mandatory--we're just reusing1279	 * the disable() function and trying to be nice by powering the1280	 * adapter down before resetting it. Thus, if we're in pre-reset,1281	 * we'll return right away and not try to queue up yet another reset.1282	 * We know the post-reset is already coming.1283	 */1284	if (test_bit(IN_PRE_RESET, &tp->flags))1285		return ret;1286 1287	if (tp->reg_access_reset_count < REGISTER_ACCESS_MAX_RESETS) {1288		usb_queue_reset_device(tp->intf);1289		tp->reg_access_reset_count++;1290	} else if (tp->reg_access_reset_count == REGISTER_ACCESS_MAX_RESETS) {1291		dev_err(&udev->dev,1292			"Tried to reset %d times; giving up.\n",1293			REGISTER_ACCESS_MAX_RESETS);1294	}1295 1296	return ret;1297}1298 1299static1300int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)1301{1302	int ret;1303	void *tmp;1304 1305	tmp = kmalloc(size, GFP_KERNEL);1306	if (!tmp)1307		return -ENOMEM;1308 1309	ret = r8152_control_msg(tp, tp->pipe_ctrl_in,1310				RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,1311				value, index, tmp, size, "read");1312 1313	if (ret < 0)1314		memset(data, 0xff, size);1315	else1316		memcpy(data, tmp, size);1317 1318	kfree(tmp);1319 1320	return ret;1321}1322 1323static1324int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)1325{1326	int ret;1327	void *tmp;1328 1329	tmp = kmemdup(data, size, GFP_KERNEL);1330	if (!tmp)1331		return -ENOMEM;1332 1333	ret = r8152_control_msg(tp, tp->pipe_ctrl_out,1334				RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,1335				value, index, tmp, size, "write");1336 1337	kfree(tmp);1338 1339	return ret;1340}1341 1342static void rtl_set_unplug(struct r8152 *tp)1343{1344	if (tp->udev->state == USB_STATE_NOTATTACHED)1345		rtl_set_inaccessible(tp);1346}1347 1348static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,1349			    void *data, u16 type)1350{1351	u16 limit = 64;1352	int ret = 0;1353 1354	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))1355		return -ENODEV;1356 1357	/* both size and indix must be 4 bytes align */1358	if ((size & 3) || !size || (index & 3) || !data)1359		return -EPERM;1360 1361	if ((u32)index + (u32)size > 0xffff)1362		return -EPERM;1363 1364	while (size) {1365		if (size > limit) {1366			ret = get_registers(tp, index, type, limit, data);1367			if (ret < 0)1368				break;1369 1370			index += limit;1371			data += limit;1372			size -= limit;1373		} else {1374			ret = get_registers(tp, index, type, size, data);1375			if (ret < 0)1376				break;1377 1378			index += size;1379			data += size;1380			size = 0;1381			break;1382		}1383	}1384 1385	if (ret == -ENODEV)1386		rtl_set_unplug(tp);1387 1388	return ret;1389}1390 1391static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,1392			     u16 size, void *data, u16 type)1393{1394	int ret;1395	u16 byteen_start, byteen_end, byen;1396	u16 limit = 512;1397 1398	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))1399		return -ENODEV;1400 1401	/* both size and indix must be 4 bytes align */1402	if ((size & 3) || !size || (index & 3) || !data)1403		return -EPERM;1404 1405	if ((u32)index + (u32)size > 0xffff)1406		return -EPERM;1407 1408	byteen_start = byteen & BYTE_EN_START_MASK;1409	byteen_end = byteen & BYTE_EN_END_MASK;1410 1411	byen = byteen_start | (byteen_start << 4);1412 1413	/* Split the first DWORD if the byte_en is not 0xff */1414	if (byen != BYTE_EN_DWORD) {1415		ret = set_registers(tp, index, type | byen, 4, data);1416		if (ret < 0)1417			goto error1;1418 1419		index += 4;1420		data += 4;1421		size -= 4;1422	}1423 1424	if (size) {1425		byen = byteen_end | (byteen_end >> 4);1426 1427		/* Split the last DWORD if the byte_en is not 0xff */1428		if (byen != BYTE_EN_DWORD)1429			size -= 4;1430 1431		while (size) {1432			if (size > limit) {1433				ret = set_registers(tp, index,1434						    type | BYTE_EN_DWORD,1435						    limit, data);1436				if (ret < 0)1437					goto error1;1438 1439				index += limit;1440				data += limit;1441				size -= limit;1442			} else {1443				ret = set_registers(tp, index,1444						    type | BYTE_EN_DWORD,1445						    size, data);1446				if (ret < 0)1447					goto error1;1448 1449				index += size;1450				data += size;1451				size = 0;1452				break;1453			}1454		}1455 1456		/* Set the last DWORD */1457		if (byen != BYTE_EN_DWORD)1458			ret = set_registers(tp, index, type | byen, 4, data);1459	}1460 1461error1:1462	if (ret == -ENODEV)1463		rtl_set_unplug(tp);1464 1465	return ret;1466}1467 1468static inline1469int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)1470{1471	return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);1472}1473 1474static inline1475int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)1476{1477	return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);1478}1479 1480static inline1481int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)1482{1483	return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);1484}1485 1486static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)1487{1488	__le32 data;1489 1490	generic_ocp_read(tp, index, sizeof(data), &data, type);1491 1492	return __le32_to_cpu(data);1493}1494 1495static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)1496{1497	__le32 tmp = __cpu_to_le32(data);1498 1499	generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);1500}1501 1502static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)1503{1504	u32 data;1505	__le32 tmp;1506	u16 byen = BYTE_EN_WORD;1507	u8 shift = index & 2;1508 1509	index &= ~3;1510	byen <<= shift;1511 1512	generic_ocp_read(tp, index, sizeof(tmp), &tmp, type | byen);1513 1514	data = __le32_to_cpu(tmp);1515	data >>= (shift * 8);1516	data &= 0xffff;1517 1518	return (u16)data;1519}1520 1521static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)1522{1523	u32 mask = 0xffff;1524	__le32 tmp;1525	u16 byen = BYTE_EN_WORD;1526	u8 shift = index & 2;1527 1528	data &= mask;1529 1530	if (index & 2) {1531		byen <<= shift;1532		mask <<= (shift * 8);1533		data <<= (shift * 8);1534		index &= ~3;1535	}1536 1537	tmp = __cpu_to_le32(data);1538 1539	generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);1540}1541 1542static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)1543{1544	u32 data;1545	__le32 tmp;1546	u8 shift = index & 3;1547 1548	index &= ~3;1549 1550	generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);1551 1552	data = __le32_to_cpu(tmp);1553	data >>= (shift * 8);1554	data &= 0xff;1555 1556	return (u8)data;1557}1558 1559static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)1560{1561	u32 mask = 0xff;1562	__le32 tmp;1563	u16 byen = BYTE_EN_BYTE;1564	u8 shift = index & 3;1565 1566	data &= mask;1567 1568	if (index & 3) {1569		byen <<= shift;1570		mask <<= (shift * 8);1571		data <<= (shift * 8);1572		index &= ~3;1573	}1574 1575	tmp = __cpu_to_le32(data);1576 1577	generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);1578}1579 1580static u16 ocp_reg_read(struct r8152 *tp, u16 addr)1581{1582	u16 ocp_base, ocp_index;1583 1584	ocp_base = addr & 0xf000;1585	if (ocp_base != tp->ocp_base) {1586		ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);1587		tp->ocp_base = ocp_base;1588	}1589 1590	ocp_index = (addr & 0x0fff) | 0xb000;1591	return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);1592}1593 1594static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)1595{1596	u16 ocp_base, ocp_index;1597 1598	ocp_base = addr & 0xf000;1599	if (ocp_base != tp->ocp_base) {1600		ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);1601		tp->ocp_base = ocp_base;1602	}1603 1604	ocp_index = (addr & 0x0fff) | 0xb000;1605	ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);1606}1607 1608static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)1609{1610	ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);1611}1612 1613static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)1614{1615	return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);1616}1617 1618static void sram_write(struct r8152 *tp, u16 addr, u16 data)1619{1620	ocp_reg_write(tp, OCP_SRAM_ADDR, addr);1621	ocp_reg_write(tp, OCP_SRAM_DATA, data);1622}1623 1624static u16 sram_read(struct r8152 *tp, u16 addr)1625{1626	ocp_reg_write(tp, OCP_SRAM_ADDR, addr);1627	return ocp_reg_read(tp, OCP_SRAM_DATA);1628}1629 1630static int read_mii_word(struct net_device *netdev, int phy_id, int reg)1631{1632	struct r8152 *tp = netdev_priv(netdev);1633	int ret;1634 1635	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))1636		return -ENODEV;1637 1638	if (phy_id != R8152_PHY_ID)1639		return -EINVAL;1640 1641	ret = r8152_mdio_read(tp, reg);1642 1643	return ret;1644}1645 1646static1647void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)1648{1649	struct r8152 *tp = netdev_priv(netdev);1650 1651	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))1652		return;1653 1654	if (phy_id != R8152_PHY_ID)1655		return;1656 1657	r8152_mdio_write(tp, reg, val);1658}1659 1660static int1661r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);1662 1663static int1664rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u32 speed, u8 duplex,1665		  u32 advertising);1666 1667static int __rtl8152_set_mac_address(struct net_device *netdev, void *p,1668				     bool in_resume)1669{1670	struct r8152 *tp = netdev_priv(netdev);1671	struct sockaddr *addr = p;1672	int ret = -EADDRNOTAVAIL;1673 1674	if (!is_valid_ether_addr(addr->sa_data))1675		goto out1;1676 1677	if (!in_resume) {1678		ret = usb_autopm_get_interface(tp->intf);1679		if (ret < 0)1680			goto out1;1681	}1682 1683	mutex_lock(&tp->control);1684 1685	eth_hw_addr_set(netdev, addr->sa_data);1686 1687	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);1688	pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);1689	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);1690 1691	mutex_unlock(&tp->control);1692 1693	if (!in_resume)1694		usb_autopm_put_interface(tp->intf);1695out1:1696	return ret;1697}1698 1699static int rtl8152_set_mac_address(struct net_device *netdev, void *p)1700{1701	return __rtl8152_set_mac_address(netdev, p, false);1702}1703 1704/* Devices containing proper chips can support a persistent1705 * host system provided MAC address.1706 * Examples of this are Dell TB15 and Dell WD15 docks1707 */1708static int vendor_mac_passthru_addr_read(struct r8152 *tp, struct sockaddr *sa)1709{1710	acpi_status status;1711	struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };1712	union acpi_object *obj;1713	int ret = -EINVAL;1714	u32 ocp_data;1715	unsigned char buf[6];1716	char *mac_obj_name;1717	acpi_object_type mac_obj_type;1718	int mac_strlen;1719 1720	if (tp->lenovo_macpassthru) {1721		mac_obj_name = "\\MACA";1722		mac_obj_type = ACPI_TYPE_STRING;1723		mac_strlen = 0x16;1724	} else {1725		/* test for -AD variant of RTL8153 */1726		ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);1727		if ((ocp_data & AD_MASK) == 0x1000) {1728			/* test for MAC address pass-through bit */1729			ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, EFUSE);1730			if ((ocp_data & PASS_THRU_MASK) != 1) {1731				netif_dbg(tp, probe, tp->netdev,1732						"No efuse for RTL8153-AD MAC pass through\n");1733				return -ENODEV;1734			}1735		} else {1736			/* test for RTL8153-BND and RTL8153-BD */1737			ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1);1738			if ((ocp_data & BND_MASK) == 0 && (ocp_data & BD_MASK) == 0) {1739				netif_dbg(tp, probe, tp->netdev,1740						"Invalid variant for MAC pass through\n");1741				return -ENODEV;1742			}1743		}1744 1745		mac_obj_name = "\\_SB.AMAC";1746		mac_obj_type = ACPI_TYPE_BUFFER;1747		mac_strlen = 0x17;1748	}1749 1750	/* returns _AUXMAC_#AABBCCDDEEFF# */1751	status = acpi_evaluate_object(NULL, mac_obj_name, NULL, &buffer);1752	obj = (union acpi_object *)buffer.pointer;1753	if (!ACPI_SUCCESS(status))1754		return -ENODEV;1755	if (obj->type != mac_obj_type || obj->string.length != mac_strlen) {1756		netif_warn(tp, probe, tp->netdev,1757			   "Invalid buffer for pass-thru MAC addr: (%d, %d)\n",1758			   obj->type, obj->string.length);1759		goto amacout;1760	}1761 1762	if (strncmp(obj->string.pointer, "_AUXMAC_#", 9) != 0 ||1763	    strncmp(obj->string.pointer + 0x15, "#", 1) != 0) {1764		netif_warn(tp, probe, tp->netdev,1765			   "Invalid header when reading pass-thru MAC addr\n");1766		goto amacout;1767	}1768	ret = hex2bin(buf, obj->string.pointer + 9, 6);1769	if (!(ret == 0 && is_valid_ether_addr(buf))) {1770		netif_warn(tp, probe, tp->netdev,1771			   "Invalid MAC for pass-thru MAC addr: %d, %pM\n",1772			   ret, buf);1773		ret = -EINVAL;1774		goto amacout;1775	}1776	memcpy(sa->sa_data, buf, 6);1777	tp->netdev->addr_assign_type = NET_ADDR_STOLEN;1778	netif_info(tp, probe, tp->netdev,1779		   "Using pass-thru MAC addr %pM\n", sa->sa_data);1780 1781amacout:1782	kfree(obj);1783	return ret;1784}1785 1786static int determine_ethernet_addr(struct r8152 *tp, struct sockaddr *sa)1787{1788	struct net_device *dev = tp->netdev;1789	int ret;1790 1791	sa->sa_family = dev->type;1792 1793	ret = eth_platform_get_mac_address(&tp->udev->dev, sa->sa_data);1794	if (ret < 0) {1795		if (tp->version == RTL_VER_01) {1796			ret = pla_ocp_read(tp, PLA_IDR, 8, sa->sa_data);1797		} else {1798			/* if device doesn't support MAC pass through this will1799			 * be expected to be non-zero1800			 */1801			ret = vendor_mac_passthru_addr_read(tp, sa);1802			if (ret < 0)1803				ret = pla_ocp_read(tp, PLA_BACKUP, 8,1804						   sa->sa_data);1805		}1806	}1807 1808	if (ret < 0) {1809		netif_err(tp, probe, dev, "Get ether addr fail\n");1810	} else if (!is_valid_ether_addr(sa->sa_data)) {1811		netif_err(tp, probe, dev, "Invalid ether addr %pM\n",1812			  sa->sa_data);1813		eth_hw_addr_random(dev);1814		ether_addr_copy(sa->sa_data, dev->dev_addr);1815		netif_info(tp, probe, dev, "Random ether addr %pM\n",1816			   sa->sa_data);1817		return 0;1818	}1819 1820	return ret;1821}1822 1823static int set_ethernet_addr(struct r8152 *tp, bool in_resume)1824{1825	struct net_device *dev = tp->netdev;1826	struct sockaddr sa;1827	int ret;1828 1829	ret = determine_ethernet_addr(tp, &sa);1830	if (ret < 0)1831		return ret;1832 1833	if (tp->version == RTL_VER_01)1834		eth_hw_addr_set(dev, sa.sa_data);1835	else1836		ret = __rtl8152_set_mac_address(dev, &sa, in_resume);1837 1838	return ret;1839}1840 1841static void read_bulk_callback(struct urb *urb)1842{1843	struct net_device *netdev;1844	int status = urb->status;1845	struct rx_agg *agg;1846	struct r8152 *tp;1847	unsigned long flags;1848 1849	agg = urb->context;1850	if (!agg)1851		return;1852 1853	tp = agg->context;1854	if (!tp)1855		return;1856 1857	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))1858		return;1859 1860	if (!test_bit(WORK_ENABLE, &tp->flags))1861		return;1862 1863	netdev = tp->netdev;1864 1865	/* When link down, the driver would cancel all bulks. */1866	/* This avoid the re-submitting bulk */1867	if (!netif_carrier_ok(netdev))1868		return;1869 1870	usb_mark_last_busy(tp->udev);1871 1872	switch (status) {1873	case 0:1874		if (urb->actual_length < ETH_ZLEN)1875			break;1876 1877		spin_lock_irqsave(&tp->rx_lock, flags);1878		list_add_tail(&agg->list, &tp->rx_done);1879		spin_unlock_irqrestore(&tp->rx_lock, flags);1880		napi_schedule(&tp->napi);1881		return;1882	case -ESHUTDOWN:1883		rtl_set_unplug(tp);1884		netif_device_detach(tp->netdev);1885		return;1886	case -EPROTO:1887		urb->actual_length = 0;1888		spin_lock_irqsave(&tp->rx_lock, flags);1889		list_add_tail(&agg->list, &tp->rx_done);1890		spin_unlock_irqrestore(&tp->rx_lock, flags);1891		set_bit(RX_EPROTO, &tp->flags);1892		schedule_delayed_work(&tp->schedule, 1);1893		return;1894	case -ENOENT:1895		return;	/* the urb is in unlink state */1896	case -ETIME:1897		if (net_ratelimit())1898			netdev_warn(netdev, "maybe reset is needed?\n");1899		break;1900	default:1901		if (net_ratelimit())1902			netdev_warn(netdev, "Rx status %d\n", status);1903		break;1904	}1905 1906	r8152_submit_rx(tp, agg, GFP_ATOMIC);1907}1908 1909static void write_bulk_callback(struct urb *urb)1910{1911	struct net_device_stats *stats;1912	struct net_device *netdev;1913	struct tx_agg *agg;1914	struct r8152 *tp;1915	unsigned long flags;1916	int status = urb->status;1917 1918	agg = urb->context;1919	if (!agg)1920		return;1921 1922	tp = agg->context;1923	if (!tp)1924		return;1925 1926	netdev = tp->netdev;1927	stats = &netdev->stats;1928	if (status) {1929		if (net_ratelimit())1930			netdev_warn(netdev, "Tx status %d\n", status);1931		stats->tx_errors += agg->skb_num;1932	} else {1933		stats->tx_packets += agg->skb_num;1934		stats->tx_bytes += agg->skb_len;1935	}1936 1937	spin_lock_irqsave(&tp->tx_lock, flags);1938	list_add_tail(&agg->list, &tp->tx_free);1939	spin_unlock_irqrestore(&tp->tx_lock, flags);1940 1941	usb_autopm_put_interface_async(tp->intf);1942 1943	if (!netif_carrier_ok(netdev))1944		return;1945 1946	if (!test_bit(WORK_ENABLE, &tp->flags))1947		return;1948 1949	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))1950		return;1951 1952	if (!skb_queue_empty(&tp->tx_queue))1953		tasklet_schedule(&tp->tx_tl);1954}1955 1956static void intr_callback(struct urb *urb)1957{1958	struct r8152 *tp;1959	__le16 *d;1960	int status = urb->status;1961	int res;1962 1963	tp = urb->context;1964	if (!tp)1965		return;1966 1967	if (!test_bit(WORK_ENABLE, &tp->flags))1968		return;1969 1970	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))1971		return;1972 1973	switch (status) {1974	case 0:			/* success */1975		break;1976	case -ECONNRESET:	/* unlink */1977	case -ESHUTDOWN:1978		netif_device_detach(tp->netdev);1979		fallthrough;1980	case -ENOENT:1981	case -EPROTO:1982		netif_info(tp, intr, tp->netdev,1983			   "Stop submitting intr, status %d\n", status);1984		return;1985	case -EOVERFLOW:1986		if (net_ratelimit())1987			netif_info(tp, intr, tp->netdev,1988				   "intr status -EOVERFLOW\n");1989		goto resubmit;1990	/* -EPIPE:  should clear the halt */1991	default:1992		netif_info(tp, intr, tp->netdev, "intr status %d\n", status);1993		goto resubmit;1994	}1995 1996	d = urb->transfer_buffer;1997	if (INTR_LINK & __le16_to_cpu(d[0])) {1998		if (!netif_carrier_ok(tp->netdev)) {1999			set_bit(RTL8152_LINK_CHG, &tp->flags);2000			schedule_delayed_work(&tp->schedule, 0);2001		}2002	} else {2003		if (netif_carrier_ok(tp->netdev)) {2004			netif_stop_queue(tp->netdev);2005			set_bit(RTL8152_LINK_CHG, &tp->flags);2006			schedule_delayed_work(&tp->schedule, 0);2007		}2008	}2009 2010resubmit:2011	res = usb_submit_urb(urb, GFP_ATOMIC);2012	if (res == -ENODEV) {2013		rtl_set_unplug(tp);2014		netif_device_detach(tp->netdev);2015	} else if (res) {2016		netif_err(tp, intr, tp->netdev,2017			  "can't resubmit intr, status %d\n", res);2018	}2019}2020 2021static inline void *rx_agg_align(void *data)2022{2023	return (void *)ALIGN((uintptr_t)data, RX_ALIGN);2024}2025 2026static inline void *tx_agg_align(void *data)2027{2028	return (void *)ALIGN((uintptr_t)data, TX_ALIGN);2029}2030 2031static void free_rx_agg(struct r8152 *tp, struct rx_agg *agg)2032{2033	list_del(&agg->info_list);2034 2035	usb_free_urb(agg->urb);2036	put_page(agg->page);2037	kfree(agg);2038 2039	atomic_dec(&tp->rx_count);2040}2041 2042static struct rx_agg *alloc_rx_agg(struct r8152 *tp, gfp_t mflags)2043{2044	struct net_device *netdev = tp->netdev;2045	int node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;2046	unsigned int order = get_order(tp->rx_buf_sz);2047	struct rx_agg *rx_agg;2048	unsigned long flags;2049 2050	rx_agg = kmalloc_node(sizeof(*rx_agg), mflags, node);2051	if (!rx_agg)2052		return NULL;2053 2054	rx_agg->page = alloc_pages(mflags | __GFP_COMP | __GFP_NOWARN, order);2055	if (!rx_agg->page)2056		goto free_rx;2057 2058	rx_agg->buffer = page_address(rx_agg->page);2059 2060	rx_agg->urb = usb_alloc_urb(0, mflags);2061	if (!rx_agg->urb)2062		goto free_buf;2063 2064	rx_agg->context = tp;2065 2066	INIT_LIST_HEAD(&rx_agg->list);2067	INIT_LIST_HEAD(&rx_agg->info_list);2068	spin_lock_irqsave(&tp->rx_lock, flags);2069	list_add_tail(&rx_agg->info_list, &tp->rx_info);2070	spin_unlock_irqrestore(&tp->rx_lock, flags);2071 2072	atomic_inc(&tp->rx_count);2073 2074	return rx_agg;2075 2076free_buf:2077	__free_pages(rx_agg->page, order);2078free_rx:2079	kfree(rx_agg);2080	return NULL;2081}2082 2083static void free_all_mem(struct r8152 *tp)2084{2085	struct rx_agg *agg, *agg_next;2086	unsigned long flags;2087	int i;2088 2089	spin_lock_irqsave(&tp->rx_lock, flags);2090 2091	list_for_each_entry_safe(agg, agg_next, &tp->rx_info, info_list)2092		free_rx_agg(tp, agg);2093 2094	spin_unlock_irqrestore(&tp->rx_lock, flags);2095 2096	WARN_ON(atomic_read(&tp->rx_count));2097 2098	for (i = 0; i < RTL8152_MAX_TX; i++) {2099		usb_free_urb(tp->tx_info[i].urb);2100		tp->tx_info[i].urb = NULL;2101 2102		kfree(tp->tx_info[i].buffer);2103		tp->tx_info[i].buffer = NULL;2104		tp->tx_info[i].head = NULL;2105	}2106 2107	usb_free_urb(tp->intr_urb);2108	tp->intr_urb = NULL;2109 2110	kfree(tp->intr_buff);2111	tp->intr_buff = NULL;2112}2113 2114static int alloc_all_mem(struct r8152 *tp)2115{2116	struct net_device *netdev = tp->netdev;2117	struct usb_interface *intf = tp->intf;2118	struct usb_host_interface *alt = intf->cur_altsetting;2119	struct usb_host_endpoint *ep_intr = alt->endpoint + 2;2120	int node, i;2121 2122	node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;2123 2124	spin_lock_init(&tp->rx_lock);2125	spin_lock_init(&tp->tx_lock);2126	INIT_LIST_HEAD(&tp->rx_info);2127	INIT_LIST_HEAD(&tp->tx_free);2128	INIT_LIST_HEAD(&tp->rx_done);2129	skb_queue_head_init(&tp->tx_queue);2130	skb_queue_head_init(&tp->rx_queue);2131	atomic_set(&tp->rx_count, 0);2132 2133	for (i = 0; i < RTL8152_MAX_RX; i++) {2134		if (!alloc_rx_agg(tp, GFP_KERNEL))2135			goto err1;2136	}2137 2138	for (i = 0; i < RTL8152_MAX_TX; i++) {2139		struct urb *urb;2140		u8 *buf;2141 2142		buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);2143		if (!buf)2144			goto err1;2145 2146		if (buf != tx_agg_align(buf)) {2147			kfree(buf);2148			buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL,2149					   node);2150			if (!buf)2151				goto err1;2152		}2153 2154		urb = usb_alloc_urb(0, GFP_KERNEL);2155		if (!urb) {2156			kfree(buf);2157			goto err1;2158		}2159 2160		INIT_LIST_HEAD(&tp->tx_info[i].list);2161		tp->tx_info[i].context = tp;2162		tp->tx_info[i].urb = urb;2163		tp->tx_info[i].buffer = buf;2164		tp->tx_info[i].head = tx_agg_align(buf);2165 2166		list_add_tail(&tp->tx_info[i].list, &tp->tx_free);2167	}2168 2169	tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);2170	if (!tp->intr_urb)2171		goto err1;2172 2173	tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);2174	if (!tp->intr_buff)2175		goto err1;2176 2177	tp->intr_interval = (int)ep_intr->desc.bInterval;2178	usb_fill_int_urb(tp->intr_urb, tp->udev, tp->pipe_intr,2179			 tp->intr_buff, INTBUFSIZE, intr_callback,2180			 tp, tp->intr_interval);2181 2182	return 0;2183 2184err1:2185	free_all_mem(tp);2186	return -ENOMEM;2187}2188 2189static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)2190{2191	struct tx_agg *agg = NULL;2192	unsigned long flags;2193 2194	if (list_empty(&tp->tx_free))2195		return NULL;2196 2197	spin_lock_irqsave(&tp->tx_lock, flags);2198	if (!list_empty(&tp->tx_free)) {2199		struct list_head *cursor;2200 2201		cursor = tp->tx_free.next;2202		list_del_init(cursor);2203		agg = list_entry(cursor, struct tx_agg, list);2204	}2205	spin_unlock_irqrestore(&tp->tx_lock, flags);2206 2207	return agg;2208}2209 2210/* r8152_csum_workaround()2211 * The hw limits the value of the transport offset. When the offset is out of2212 * range, calculate the checksum by sw.2213 */2214static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,2215				  struct sk_buff_head *list)2216{2217	if (skb_shinfo(skb)->gso_size) {2218		netdev_features_t features = tp->netdev->features;2219		struct sk_buff *segs, *seg, *next;2220		struct sk_buff_head seg_list;2221 2222		features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);2223		segs = skb_gso_segment(skb, features);2224		if (IS_ERR(segs) || !segs)2225			goto drop;2226 2227		__skb_queue_head_init(&seg_list);2228 2229		skb_list_walk_safe(segs, seg, next) {2230			skb_mark_not_on_list(seg);2231			__skb_queue_tail(&seg_list, seg);2232		}2233 2234		skb_queue_splice(&seg_list, list);2235		dev_kfree_skb(skb);2236	} else if (skb->ip_summed == CHECKSUM_PARTIAL) {2237		if (skb_checksum_help(skb) < 0)2238			goto drop;2239 2240		__skb_queue_head(list, skb);2241	} else {2242		struct net_device_stats *stats;2243 2244drop:2245		stats = &tp->netdev->stats;2246		stats->tx_dropped++;2247		dev_kfree_skb(skb);2248	}2249}2250 2251static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb)2252{2253	if (skb_vlan_tag_present(skb)) {2254		u32 opts2;2255 2256		opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb));2257		desc->opts2 |= cpu_to_le32(opts2);2258	}2259}2260 2261static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb)2262{2263	u32 opts2 = le32_to_cpu(desc->opts2);2264 2265	if (opts2 & RX_VLAN_TAG)2266		__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),2267				       swab16(opts2 & 0xffff));2268}2269 2270static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,2271			 struct sk_buff *skb, u32 len)2272{2273	u32 mss = skb_shinfo(skb)->gso_size;2274	u32 opts1, opts2 = 0;2275	int ret = TX_CSUM_SUCCESS;2276 2277	WARN_ON_ONCE(len > TX_LEN_MAX);2278 2279	opts1 = len | TX_FS | TX_LS;2280 2281	if (mss) {2282		u32 transport_offset = (u32)skb_transport_offset(skb);2283 2284		if (transport_offset > GTTCPHO_MAX) {2285			netif_warn(tp, tx_err, tp->netdev,2286				   "Invalid transport offset 0x%x for TSO\n",2287				   transport_offset);2288			ret = TX_CSUM_TSO;2289			goto unavailable;2290		}2291 2292		switch (vlan_get_protocol(skb)) {2293		case htons(ETH_P_IP):2294			opts1 |= GTSENDV4;2295			break;2296 2297		case htons(ETH_P_IPV6):2298			if (skb_cow_head(skb, 0)) {2299				ret = TX_CSUM_TSO;2300				goto unavailable;2301			}2302			tcp_v6_gso_csum_prep(skb);2303			opts1 |= GTSENDV6;2304			break;2305 2306		default:2307			WARN_ON_ONCE(1);2308			break;2309		}2310 2311		opts1 |= transport_offset << GTTCPHO_SHIFT;2312		opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;2313	} else if (skb->ip_summed == CHECKSUM_PARTIAL) {2314		u32 transport_offset = (u32)skb_transport_offset(skb);2315		u8 ip_protocol;2316 2317		if (transport_offset > TCPHO_MAX) {2318			netif_warn(tp, tx_err, tp->netdev,2319				   "Invalid transport offset 0x%x\n",2320				   transport_offset);2321			ret = TX_CSUM_NONE;2322			goto unavailable;2323		}2324 2325		switch (vlan_get_protocol(skb)) {2326		case htons(ETH_P_IP):2327			opts2 |= IPV4_CS;2328			ip_protocol = ip_hdr(skb)->protocol;2329			break;2330 2331		case htons(ETH_P_IPV6):2332			opts2 |= IPV6_CS;2333			ip_protocol = ipv6_hdr(skb)->nexthdr;2334			break;2335 2336		default:2337			ip_protocol = IPPROTO_RAW;2338			break;2339		}2340 2341		if (ip_protocol == IPPROTO_TCP)2342			opts2 |= TCP_CS;2343		else if (ip_protocol == IPPROTO_UDP)2344			opts2 |= UDP_CS;2345		else2346			WARN_ON_ONCE(1);2347 2348		opts2 |= transport_offset << TCPHO_SHIFT;2349	}2350 2351	desc->opts2 = cpu_to_le32(opts2);2352	desc->opts1 = cpu_to_le32(opts1);2353 2354unavailable:2355	return ret;2356}2357 2358static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)2359{2360	struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;2361	int remain, ret;2362	u8 *tx_data;2363 2364	__skb_queue_head_init(&skb_head);2365	spin_lock(&tx_queue->lock);2366	skb_queue_splice_init(tx_queue, &skb_head);2367	spin_unlock(&tx_queue->lock);2368 2369	tx_data = agg->head;2370	agg->skb_num = 0;2371	agg->skb_len = 0;2372	remain = agg_buf_sz;2373 2374	while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {2375		struct tx_desc *tx_desc;2376		struct sk_buff *skb;2377		unsigned int len;2378 2379		skb = __skb_dequeue(&skb_head);2380		if (!skb)2381			break;2382 2383		len = skb->len + sizeof(*tx_desc);2384 2385		if (len > remain) {2386			__skb_queue_head(&skb_head, skb);2387			break;2388		}2389 2390		tx_data = tx_agg_align(tx_data);2391		tx_desc = (struct tx_desc *)tx_data;2392 2393		if (r8152_tx_csum(tp, tx_desc, skb, skb->len)) {2394			r8152_csum_workaround(tp, skb, &skb_head);2395			continue;2396		}2397 2398		rtl_tx_vlan_tag(tx_desc, skb);2399 2400		tx_data += sizeof(*tx_desc);2401 2402		len = skb->len;2403		if (skb_copy_bits(skb, 0, tx_data, len) < 0) {2404			struct net_device_stats *stats = &tp->netdev->stats;2405 2406			stats->tx_dropped++;2407			dev_kfree_skb_any(skb);2408			tx_data -= sizeof(*tx_desc);2409			continue;2410		}2411 2412		tx_data += len;2413		agg->skb_len += len;2414		agg->skb_num += skb_shinfo(skb)->gso_segs ?: 1;2415 2416		dev_kfree_skb_any(skb);2417 2418		remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);2419 2420		if (tp->dell_tb_rx_agg_bug)2421			break;2422	}2423 2424	if (!skb_queue_empty(&skb_head)) {2425		spin_lock(&tx_queue->lock);2426		skb_queue_splice(&skb_head, tx_queue);2427		spin_unlock(&tx_queue->lock);2428	}2429 2430	netif_tx_lock(tp->netdev);2431 2432	if (netif_queue_stopped(tp->netdev) &&2433	    skb_queue_len(&tp->tx_queue) < tp->tx_qlen)2434		netif_wake_queue(tp->netdev);2435 2436	netif_tx_unlock(tp->netdev);2437 2438	ret = usb_autopm_get_interface_async(tp->intf);2439	if (ret < 0)2440		goto out_tx_fill;2441 2442	usb_fill_bulk_urb(agg->urb, tp->udev, tp->pipe_out,2443			  agg->head, (int)(tx_data - (u8 *)agg->head),2444			  (usb_complete_t)write_bulk_callback, agg);2445 2446	ret = usb_submit_urb(agg->urb, GFP_ATOMIC);2447	if (ret < 0)2448		usb_autopm_put_interface_async(tp->intf);2449 2450out_tx_fill:2451	return ret;2452}2453 2454static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)2455{2456	u8 checksum = CHECKSUM_NONE;2457	u32 opts2, opts3;2458 2459	if (!(tp->netdev->features & NETIF_F_RXCSUM))2460		goto return_result;2461 2462	opts2 = le32_to_cpu(rx_desc->opts2);2463	opts3 = le32_to_cpu(rx_desc->opts3);2464 2465	if (opts2 & RD_IPV4_CS) {2466		if (opts3 & IPF)2467			checksum = CHECKSUM_NONE;2468		else if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))2469			checksum = CHECKSUM_UNNECESSARY;2470		else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))2471			checksum = CHECKSUM_UNNECESSARY;2472	} else if (opts2 & RD_IPV6_CS) {2473		if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))2474			checksum = CHECKSUM_UNNECESSARY;2475		else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))2476			checksum = CHECKSUM_UNNECESSARY;2477	}2478 2479return_result:2480	return checksum;2481}2482 2483static inline bool rx_count_exceed(struct r8152 *tp)2484{2485	return atomic_read(&tp->rx_count) > RTL8152_MAX_RX;2486}2487 2488static inline int agg_offset(struct rx_agg *agg, void *addr)2489{2490	return (int)(addr - agg->buffer);2491}2492 2493static struct rx_agg *rtl_get_free_rx(struct r8152 *tp, gfp_t mflags)2494{2495	struct rx_agg *agg, *agg_next, *agg_free = NULL;2496	unsigned long flags;2497 2498	spin_lock_irqsave(&tp->rx_lock, flags);2499 2500	list_for_each_entry_safe(agg, agg_next, &tp->rx_used, list) {2501		if (page_count(agg->page) == 1) {2502			if (!agg_free) {2503				list_del_init(&agg->list);2504				agg_free = agg;2505				continue;2506			}2507			if (rx_count_exceed(tp)) {2508				list_del_init(&agg->list);2509				free_rx_agg(tp, agg);2510			}2511			break;2512		}2513	}2514 2515	spin_unlock_irqrestore(&tp->rx_lock, flags);2516 2517	if (!agg_free && atomic_read(&tp->rx_count) < tp->rx_pending)2518		agg_free = alloc_rx_agg(tp, mflags);2519 2520	return agg_free;2521}2522 2523static int rx_bottom(struct r8152 *tp, int budget)2524{2525	unsigned long flags;2526	struct list_head *cursor, *next, rx_queue;2527	int ret = 0, work_done = 0;2528	struct napi_struct *napi = &tp->napi;2529 2530	if (!skb_queue_empty(&tp->rx_queue)) {2531		while (work_done < budget) {2532			struct sk_buff *skb = __skb_dequeue(&tp->rx_queue);2533			struct net_device *netdev = tp->netdev;2534			struct net_device_stats *stats = &netdev->stats;2535			unsigned int pkt_len;2536 2537			if (!skb)2538				break;2539 2540			pkt_len = skb->len;2541			napi_gro_receive(napi, skb);2542			work_done++;2543			stats->rx_packets++;2544			stats->rx_bytes += pkt_len;2545		}2546	}2547 2548	if (list_empty(&tp->rx_done) || work_done >= budget)2549		goto out1;2550 2551	clear_bit(RX_EPROTO, &tp->flags);2552	INIT_LIST_HEAD(&rx_queue);2553	spin_lock_irqsave(&tp->rx_lock, flags);2554	list_splice_init(&tp->rx_done, &rx_queue);2555	spin_unlock_irqrestore(&tp->rx_lock, flags);2556 2557	list_for_each_safe(cursor, next, &rx_queue) {2558		struct rx_desc *rx_desc;2559		struct rx_agg *agg, *agg_free;2560		int len_used = 0;2561		struct urb *urb;2562		u8 *rx_data;2563 2564		/* A bulk transfer of USB may contain may packets, so the2565		 * total packets may more than the budget. Deal with all2566		 * packets in current bulk transfer, and stop to handle the2567		 * next bulk transfer until next schedule, if budget is2568		 * exhausted.2569		 */2570		if (work_done >= budget)2571			break;2572 2573		list_del_init(cursor);2574 2575		agg = list_entry(cursor, struct rx_agg, list);2576		urb = agg->urb;2577		if (urb->status != 0 || urb->actual_length < ETH_ZLEN)2578			goto submit;2579 2580		agg_free = rtl_get_free_rx(tp, GFP_ATOMIC);2581 2582		rx_desc = agg->buffer;2583		rx_data = agg->buffer;2584		len_used += sizeof(struct rx_desc);2585 2586		while (urb->actual_length > len_used) {2587			struct net_device *netdev = tp->netdev;2588			struct net_device_stats *stats = &netdev->stats;2589			unsigned int pkt_len, rx_frag_head_sz, len;2590			struct sk_buff *skb;2591			bool use_frags;2592 2593			WARN_ON_ONCE(skb_queue_len(&tp->rx_queue) >= 1000);2594 2595			pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;2596			if (pkt_len < ETH_ZLEN)2597				break;2598 2599			len_used += pkt_len;2600			if (urb->actual_length < len_used)2601				break;2602 2603			pkt_len -= ETH_FCS_LEN;2604			len = pkt_len;2605			rx_data += sizeof(struct rx_desc);2606 2607			if (!agg_free || tp->rx_copybreak > len)2608				use_frags = false;2609			else2610				use_frags = true;2611 2612			if (use_frags) {2613				/* If the budget is exhausted, the packet2614				 * would be queued in the driver. That is,2615				 * napi_gro_frags() wouldn't be called, so2616				 * we couldn't use napi_get_frags().2617				 */2618				if (work_done >= budget) {2619					rx_frag_head_sz = tp->rx_copybreak;2620					skb = napi_alloc_skb(napi,2621							     rx_frag_head_sz);2622				} else {2623					rx_frag_head_sz = 0;2624					skb = napi_get_frags(napi);2625				}2626			} else {2627				rx_frag_head_sz = 0;2628				skb = napi_alloc_skb(napi, len);2629			}2630 2631			if (!skb) {2632				stats->rx_dropped++;2633				goto find_next_rx;2634			}2635 2636			skb->ip_summed = r8152_rx_csum(tp, rx_desc);2637			rtl_rx_vlan_tag(rx_desc, skb);2638 2639			if (use_frags) {2640				if (rx_frag_head_sz) {2641					memcpy(skb->data, rx_data,2642					       rx_frag_head_sz);2643					skb_put(skb, rx_frag_head_sz);2644					len -= rx_frag_head_sz;2645					rx_data += rx_frag_head_sz;2646					skb->protocol = eth_type_trans(skb,2647								       netdev);2648				}2649 2650				skb_add_rx_frag(skb, 0, agg->page,2651						agg_offset(agg, rx_data),2652						len, SKB_DATA_ALIGN(len));2653				get_page(agg->page);2654			} else {2655				memcpy(skb->data, rx_data, len);2656				skb_put(skb, len);2657				skb->protocol = eth_type_trans(skb, netdev);2658			}2659 2660			if (work_done < budget) {2661				if (use_frags)2662					napi_gro_frags(napi);2663				else2664					napi_gro_receive(napi, skb);2665 2666				work_done++;2667				stats->rx_packets++;2668				stats->rx_bytes += pkt_len;2669			} else {2670				__skb_queue_tail(&tp->rx_queue, skb);2671			}2672 2673find_next_rx:2674			rx_data = rx_agg_align(rx_data + len + ETH_FCS_LEN);2675			rx_desc = (struct rx_desc *)rx_data;2676			len_used = agg_offset(agg, rx_data);2677			len_used += sizeof(struct rx_desc);2678		}2679 2680		WARN_ON(!agg_free && page_count(agg->page) > 1);2681 2682		if (agg_free) {2683			spin_lock_irqsave(&tp->rx_lock, flags);2684			if (page_count(agg->page) == 1) {2685				list_add(&agg_free->list, &tp->rx_used);2686			} else {2687				list_add_tail(&agg->list, &tp->rx_used);2688				agg = agg_free;2689				urb = agg->urb;2690			}2691			spin_unlock_irqrestore(&tp->rx_lock, flags);2692		}2693 2694submit:2695		if (!ret) {2696			ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);2697		} else {2698			urb->actual_length = 0;2699			list_add_tail(&agg->list, next);2700		}2701	}2702 2703	/* Splice the remained list back to rx_done for next schedule */2704	if (!list_empty(&rx_queue)) {2705		spin_lock_irqsave(&tp->rx_lock, flags);2706		list_splice(&rx_queue, &tp->rx_done);2707		spin_unlock_irqrestore(&tp->rx_lock, flags);2708	}2709 2710out1:2711	return work_done;2712}2713 2714static void tx_bottom(struct r8152 *tp)2715{2716	int res;2717 2718	do {2719		struct net_device *netdev = tp->netdev;2720		struct tx_agg *agg;2721 2722		if (skb_queue_empty(&tp->tx_queue))2723			break;2724 2725		agg = r8152_get_tx_agg(tp);2726		if (!agg)2727			break;2728 2729		res = r8152_tx_agg_fill(tp, agg);2730		if (!res)2731			continue;2732 2733		if (res == -ENODEV) {2734			rtl_set_unplug(tp);2735			netif_device_detach(netdev);2736		} else {2737			struct net_device_stats *stats = &netdev->stats;2738			unsigned long flags;2739 2740			netif_warn(tp, tx_err, netdev,2741				   "failed tx_urb %d\n", res);2742			stats->tx_dropped += agg->skb_num;2743 2744			spin_lock_irqsave(&tp->tx_lock, flags);2745			list_add_tail(&agg->list, &tp->tx_free);2746			spin_unlock_irqrestore(&tp->tx_lock, flags);2747		}2748	} while (res == 0);2749}2750 2751static void bottom_half(struct tasklet_struct *t)2752{2753	struct r8152 *tp = from_tasklet(tp, t, tx_tl);2754 2755	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))2756		return;2757 2758	if (!test_bit(WORK_ENABLE, &tp->flags))2759		return;2760 2761	/* When link down, the driver would cancel all bulks. */2762	/* This avoid the re-submitting bulk */2763	if (!netif_carrier_ok(tp->netdev))2764		return;2765 2766	clear_bit(SCHEDULE_TASKLET, &tp->flags);2767 2768	tx_bottom(tp);2769}2770 2771static int r8152_poll(struct napi_struct *napi, int budget)2772{2773	struct r8152 *tp = container_of(napi, struct r8152, napi);2774	int work_done;2775 2776	if (!budget)2777		return 0;2778 2779	work_done = rx_bottom(tp, budget);2780 2781	if (work_done < budget) {2782		if (!napi_complete_done(napi, work_done))2783			goto out;2784		if (!list_empty(&tp->rx_done))2785			napi_schedule(napi);2786	}2787 2788out:2789	return work_done;2790}2791 2792static2793int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)2794{2795	int ret;2796 2797	/* The rx would be stopped, so skip submitting */2798	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags) ||2799	    !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev))2800		return 0;2801 2802	usb_fill_bulk_urb(agg->urb, tp->udev, tp->pipe_in,2803			  agg->buffer, tp->rx_buf_sz,2804			  (usb_complete_t)read_bulk_callback, agg);2805 2806	ret = usb_submit_urb(agg->urb, mem_flags);2807	if (ret == -ENODEV) {2808		rtl_set_unplug(tp);2809		netif_device_detach(tp->netdev);2810	} else if (ret) {2811		struct urb *urb = agg->urb;2812		unsigned long flags;2813 2814		urb->actual_length = 0;2815		spin_lock_irqsave(&tp->rx_lock, flags);2816		list_add_tail(&agg->list, &tp->rx_done);2817		spin_unlock_irqrestore(&tp->rx_lock, flags);2818 2819		netif_err(tp, rx_err, tp->netdev,2820			  "Couldn't submit rx[%p], ret = %d\n", agg, ret);2821 2822		napi_schedule(&tp->napi);2823	}2824 2825	return ret;2826}2827 2828static void rtl_drop_queued_tx(struct r8152 *tp)2829{2830	struct net_device_stats *stats = &tp->netdev->stats;2831	struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;2832	struct sk_buff *skb;2833 2834	if (skb_queue_empty(tx_queue))2835		return;2836 2837	__skb_queue_head_init(&skb_head);2838	spin_lock_bh(&tx_queue->lock);2839	skb_queue_splice_init(tx_queue, &skb_head);2840	spin_unlock_bh(&tx_queue->lock);2841 2842	while ((skb = __skb_dequeue(&skb_head))) {2843		dev_kfree_skb(skb);2844		stats->tx_dropped++;2845	}2846}2847 2848static void rtl8152_tx_timeout(struct net_device *netdev, unsigned int txqueue)2849{2850	struct r8152 *tp = netdev_priv(netdev);2851 2852	netif_warn(tp, tx_err, netdev, "Tx timeout\n");2853 2854	usb_queue_reset_device(tp->intf);2855}2856 2857static void rtl8152_set_rx_mode(struct net_device *netdev)2858{2859	struct r8152 *tp = netdev_priv(netdev);2860 2861	if (netif_carrier_ok(netdev)) {2862		set_bit(RTL8152_SET_RX_MODE, &tp->flags);2863		schedule_delayed_work(&tp->schedule, 0);2864	}2865}2866 2867static void _rtl8152_set_rx_mode(struct net_device *netdev)2868{2869	struct r8152 *tp = netdev_priv(netdev);2870	u32 mc_filter[2];	/* Multicast hash filter */2871	__le32 tmp[2];2872	u32 ocp_data;2873 2874	netif_stop_queue(netdev);2875	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);2876	ocp_data &= ~RCR_ACPT_ALL;2877	ocp_data |= RCR_AB | RCR_APM;2878 2879	if (netdev->flags & IFF_PROMISC) {2880		/* Unconditionally log net taps. */2881		netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");2882		ocp_data |= RCR_AM | RCR_AAP;2883		mc_filter[1] = 0xffffffff;2884		mc_filter[0] = 0xffffffff;2885	} else if ((netdev->flags & IFF_MULTICAST &&2886				netdev_mc_count(netdev) > multicast_filter_limit) ||2887			   (netdev->flags & IFF_ALLMULTI)) {2888		/* Too many to filter perfectly -- accept all multicasts. */2889		ocp_data |= RCR_AM;2890		mc_filter[1] = 0xffffffff;2891		mc_filter[0] = 0xffffffff;2892	} else {2893		mc_filter[1] = 0;2894		mc_filter[0] = 0;2895 2896		if (netdev->flags & IFF_MULTICAST) {2897			struct netdev_hw_addr *ha;2898 2899			netdev_for_each_mc_addr(ha, netdev) {2900				int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;2901 2902				mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);2903				ocp_data |= RCR_AM;2904			}2905		}2906	}2907 2908	tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));2909	tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));2910 2911	pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);2912	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);2913	netif_wake_queue(netdev);2914}2915 2916static netdev_features_t2917rtl8152_features_check(struct sk_buff *skb, struct net_device *dev,2918		       netdev_features_t features)2919{2920	u32 mss = skb_shinfo(skb)->gso_size;2921	int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX;2922 2923	if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) &&2924	    skb_transport_offset(skb) > max_offset)2925		features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);2926	else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz)2927		features &= ~NETIF_F_GSO_MASK;2928 2929	return features;2930}2931 2932static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,2933				      struct net_device *netdev)2934{2935	struct r8152 *tp = netdev_priv(netdev);2936 2937	skb_tx_timestamp(skb);2938 2939	skb_queue_tail(&tp->tx_queue, skb);2940 2941	if (!list_empty(&tp->tx_free)) {2942		if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {2943			set_bit(SCHEDULE_TASKLET, &tp->flags);2944			schedule_delayed_work(&tp->schedule, 0);2945		} else {2946			usb_mark_last_busy(tp->udev);2947			tasklet_schedule(&tp->tx_tl);2948		}2949	} else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) {2950		netif_stop_queue(netdev);2951	}2952 2953	return NETDEV_TX_OK;2954}2955 2956static void r8152b_reset_packet_filter(struct r8152 *tp)2957{2958	u32 ocp_data;2959 2960	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);2961	ocp_data &= ~FMC_FCR_MCU_EN;2962	ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);2963	ocp_data |= FMC_FCR_MCU_EN;2964	ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);2965}2966 2967static void rtl8152_nic_reset(struct r8152 *tp)2968{2969	u32 ocp_data;2970	int i;2971 2972	switch (tp->version) {2973	case RTL_TEST_01:2974	case RTL_VER_10:2975	case RTL_VER_11:2976		ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);2977		ocp_data &= ~CR_TE;2978		ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);2979 2980		ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_RESET);2981		ocp_data &= ~BMU_RESET_EP_IN;2982		ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);2983 2984		ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);2985		ocp_data |= CDC_ECM_EN;2986		ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);2987 2988		ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);2989		ocp_data &= ~CR_RE;2990		ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);2991 2992		ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_RESET);2993		ocp_data |= BMU_RESET_EP_IN;2994		ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);2995 2996		ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);2997		ocp_data &= ~CDC_ECM_EN;2998		ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);2999		break;3000 3001	default:3002		ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);3003 3004		for (i = 0; i < 1000; i++) {3005			if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))3006				break;3007			if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))3008				break;3009			usleep_range(100, 400);3010		}3011		break;3012	}3013}3014 3015static void set_tx_qlen(struct r8152 *tp)3016{3017	tp->tx_qlen = agg_buf_sz / (mtu_to_size(tp->netdev->mtu) + sizeof(struct tx_desc));3018}3019 3020static inline u16 rtl8152_get_speed(struct r8152 *tp)3021{3022	return ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);3023}3024 3025static void rtl_eee_plus_en(struct r8152 *tp, bool enable)3026{3027	u32 ocp_data;3028 3029	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);3030	if (enable)3031		ocp_data |= EEEP_CR_EEEP_TX;3032	else3033		ocp_data &= ~EEEP_CR_EEEP_TX;3034	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);3035}3036 3037static void rtl_set_eee_plus(struct r8152 *tp)3038{3039	if (rtl8152_get_speed(tp) & _10bps)3040		rtl_eee_plus_en(tp, true);3041	else3042		rtl_eee_plus_en(tp, false);3043}3044 3045static void rxdy_gated_en(struct r8152 *tp, bool enable)3046{3047	u32 ocp_data;3048 3049	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);3050	if (enable)3051		ocp_data |= RXDY_GATED_EN;3052	else3053		ocp_data &= ~RXDY_GATED_EN;3054	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);3055}3056 3057static int rtl_start_rx(struct r8152 *tp)3058{3059	struct rx_agg *agg, *agg_next;3060	struct list_head tmp_list;3061	unsigned long flags;3062	int ret = 0, i = 0;3063 3064	INIT_LIST_HEAD(&tmp_list);3065 3066	spin_lock_irqsave(&tp->rx_lock, flags);3067 3068	INIT_LIST_HEAD(&tp->rx_done);3069	INIT_LIST_HEAD(&tp->rx_used);3070 3071	list_splice_init(&tp->rx_info, &tmp_list);3072 3073	spin_unlock_irqrestore(&tp->rx_lock, flags);3074 3075	list_for_each_entry_safe(agg, agg_next, &tmp_list, info_list) {3076		INIT_LIST_HEAD(&agg->list);3077 3078		/* Only RTL8152_MAX_RX rx_agg need to be submitted. */3079		if (++i > RTL8152_MAX_RX) {3080			spin_lock_irqsave(&tp->rx_lock, flags);3081			list_add_tail(&agg->list, &tp->rx_used);3082			spin_unlock_irqrestore(&tp->rx_lock, flags);3083		} else if (unlikely(ret < 0)) {3084			spin_lock_irqsave(&tp->rx_lock, flags);3085			list_add_tail(&agg->list, &tp->rx_done);3086			spin_unlock_irqrestore(&tp->rx_lock, flags);3087		} else {3088			ret = r8152_submit_rx(tp, agg, GFP_KERNEL);3089		}3090	}3091 3092	spin_lock_irqsave(&tp->rx_lock, flags);3093	WARN_ON(!list_empty(&tp->rx_info));3094	list_splice(&tmp_list, &tp->rx_info);3095	spin_unlock_irqrestore(&tp->rx_lock, flags);3096 3097	return ret;3098}3099 3100static int rtl_stop_rx(struct r8152 *tp)3101{3102	struct rx_agg *agg, *agg_next;3103	struct list_head tmp_list;3104	unsigned long flags;3105 3106	INIT_LIST_HEAD(&tmp_list);3107 3108	/* The usb_kill_urb() couldn't be used in atomic.3109	 * Therefore, move the list of rx_info to a tmp one.3110	 * Then, list_for_each_entry_safe could be used without3111	 * spin lock.3112	 */3113 3114	spin_lock_irqsave(&tp->rx_lock, flags);3115	list_splice_init(&tp->rx_info, &tmp_list);3116	spin_unlock_irqrestore(&tp->rx_lock, flags);3117 3118	list_for_each_entry_safe(agg, agg_next, &tmp_list, info_list) {3119		/* At least RTL8152_MAX_RX rx_agg have the page_count being3120		 * equal to 1, so the other ones could be freed safely.3121		 */3122		if (page_count(agg->page) > 1)3123			free_rx_agg(tp, agg);3124		else3125			usb_kill_urb(agg->urb);3126	}3127 3128	/* Move back the list of temp to the rx_info */3129	spin_lock_irqsave(&tp->rx_lock, flags);3130	WARN_ON(!list_empty(&tp->rx_info));3131	list_splice(&tmp_list, &tp->rx_info);3132	spin_unlock_irqrestore(&tp->rx_lock, flags);3133 3134	while (!skb_queue_empty(&tp->rx_queue))3135		dev_kfree_skb(__skb_dequeue(&tp->rx_queue));3136 3137	return 0;3138}3139 3140static void rtl_set_ifg(struct r8152 *tp, u16 speed)3141{3142	u32 ocp_data;3143 3144	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);3145	ocp_data &= ~IFG_MASK;3146	if ((speed & (_10bps | _100bps)) && !(speed & FULL_DUP)) {3147		ocp_data |= IFG_144NS;3148		ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR1, ocp_data);3149 3150		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);3151		ocp_data &= ~TX10MIDLE_EN;3152		ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);3153	} else {3154		ocp_data |= IFG_96NS;3155		ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR1, ocp_data);3156 3157		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);3158		ocp_data |= TX10MIDLE_EN;3159		ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);3160	}3161}3162 3163static inline void r8153b_rx_agg_chg_indicate(struct r8152 *tp)3164{3165	ocp_write_byte(tp, MCU_TYPE_USB, USB_UPT_RXDMA_OWN,3166		       OWN_UPDATE | OWN_CLEAR);3167}3168 3169static int rtl_enable(struct r8152 *tp)3170{3171	u32 ocp_data;3172 3173	r8152b_reset_packet_filter(tp);3174 3175	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);3176	ocp_data |= CR_RE | CR_TE;3177	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);3178 3179	switch (tp->version) {3180	case RTL_VER_01:3181	case RTL_VER_02:3182	case RTL_VER_03:3183	case RTL_VER_04:3184	case RTL_VER_05:3185	case RTL_VER_06:3186	case RTL_VER_07:3187		break;3188	default:3189		r8153b_rx_agg_chg_indicate(tp);3190		break;3191	}3192 3193	rxdy_gated_en(tp, false);3194 3195	return 0;3196}3197 3198static int rtl8152_enable(struct r8152 *tp)3199{3200	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))3201		return -ENODEV;3202 3203	set_tx_qlen(tp);3204	rtl_set_eee_plus(tp);3205 3206	return rtl_enable(tp);3207}3208 3209static void r8153_set_rx_early_timeout(struct r8152 *tp)3210{3211	u32 ocp_data = tp->coalesce / 8;3212 3213	switch (tp->version) {3214	case RTL_VER_03:3215	case RTL_VER_04:3216	case RTL_VER_05:3217	case RTL_VER_06:3218		ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,3219			       ocp_data);3220		break;3221 3222	case RTL_VER_08:3223	case RTL_VER_09:3224	case RTL_VER_14:3225		/* The RTL8153B uses USB_RX_EXTRA_AGGR_TMR for rx timeout3226		 * primarily. For USB_RX_EARLY_TIMEOUT, we fix it to 128ns.3227		 */3228		ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,3229			       128 / 8);3230		ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR,3231			       ocp_data);3232		break;3233 3234	case RTL_VER_10:3235	case RTL_VER_11:3236	case RTL_VER_12:3237	case RTL_VER_13:3238	case RTL_VER_15:3239		ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,3240			       640 / 8);3241		ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR,3242			       ocp_data);3243		break;3244 3245	default:3246		break;3247	}3248}3249 3250static void r8153_set_rx_early_size(struct r8152 *tp)3251{3252	u32 ocp_data = tp->rx_buf_sz - rx_reserved_size(tp->netdev->mtu);3253 3254	switch (tp->version) {3255	case RTL_VER_03:3256	case RTL_VER_04:3257	case RTL_VER_05:3258	case RTL_VER_06:3259		ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,3260			       ocp_data / 4);3261		break;3262	case RTL_VER_08:3263	case RTL_VER_09:3264	case RTL_VER_14:3265		ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,3266			       ocp_data / 8);3267		break;3268	case RTL_TEST_01:3269	case RTL_VER_10:3270	case RTL_VER_11:3271	case RTL_VER_12:3272	case RTL_VER_13:3273	case RTL_VER_15:3274		ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,3275			       ocp_data / 8);3276		break;3277	default:3278		WARN_ON_ONCE(1);3279		break;3280	}3281}3282 3283static int rtl8153_enable(struct r8152 *tp)3284{3285	u32 ocp_data;3286 3287	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))3288		return -ENODEV;3289 3290	set_tx_qlen(tp);3291	rtl_set_eee_plus(tp);3292	r8153_set_rx_early_timeout(tp);3293	r8153_set_rx_early_size(tp);3294 3295	rtl_set_ifg(tp, rtl8152_get_speed(tp));3296 3297	switch (tp->version) {3298	case RTL_VER_09:3299	case RTL_VER_14:3300		ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);3301		ocp_data &= ~FC_PATCH_TASK;3302		ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);3303		usleep_range(1000, 2000);3304		ocp_data |= FC_PATCH_TASK;3305		ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);3306		break;3307	default:3308		break;3309	}3310 3311	return rtl_enable(tp);3312}3313 3314static void rtl_disable(struct r8152 *tp)3315{3316	u32 ocp_data;3317	int i;3318 3319	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) {3320		rtl_drop_queued_tx(tp);3321		return;3322	}3323 3324	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);3325	ocp_data &= ~RCR_ACPT_ALL;3326	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);3327 3328	rtl_drop_queued_tx(tp);3329 3330	for (i = 0; i < RTL8152_MAX_TX; i++)3331		usb_kill_urb(tp->tx_info[i].urb);3332 3333	rxdy_gated_en(tp, true);3334 3335	for (i = 0; i < 1000; i++) {3336		if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))3337			break;3338		ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);3339		if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)3340			break;3341		usleep_range(1000, 2000);3342	}3343 3344	for (i = 0; i < 1000; i++) {3345		if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))3346			break;3347		if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)3348			break;3349		usleep_range(1000, 2000);3350	}3351 3352	rtl_stop_rx(tp);3353 3354	rtl8152_nic_reset(tp);3355}3356 3357static void r8152_power_cut_en(struct r8152 *tp, bool enable)3358{3359	u32 ocp_data;3360 3361	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);3362	if (enable)3363		ocp_data |= POWER_CUT;3364	else3365		ocp_data &= ~POWER_CUT;3366	ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);3367 3368	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);3369	ocp_data &= ~RESUME_INDICATE;3370	ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);3371}3372 3373static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)3374{3375	u32 ocp_data;3376 3377	switch (tp->version) {3378	case RTL_VER_01:3379	case RTL_VER_02:3380	case RTL_VER_03:3381	case RTL_VER_04:3382	case RTL_VER_05:3383	case RTL_VER_06:3384	case RTL_VER_07:3385	case RTL_VER_08:3386	case RTL_VER_09:3387	case RTL_VER_14:3388		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);3389		if (enable)3390			ocp_data |= CPCR_RX_VLAN;3391		else3392			ocp_data &= ~CPCR_RX_VLAN;3393		ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);3394		break;3395 3396	case RTL_TEST_01:3397	case RTL_VER_10:3398	case RTL_VER_11:3399	case RTL_VER_12:3400	case RTL_VER_13:3401	case RTL_VER_15:3402	default:3403		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RCR1);3404		if (enable)3405			ocp_data |= OUTER_VLAN | INNER_VLAN;3406		else3407			ocp_data &= ~(OUTER_VLAN | INNER_VLAN);3408		ocp_write_word(tp, MCU_TYPE_PLA, PLA_RCR1, ocp_data);3409		break;3410	}3411}3412 3413static int rtl8152_set_features(struct net_device *dev,3414				netdev_features_t features)3415{3416	netdev_features_t changed = features ^ dev->features;3417	struct r8152 *tp = netdev_priv(dev);3418	int ret;3419 3420	ret = usb_autopm_get_interface(tp->intf);3421	if (ret < 0)3422		goto out;3423 3424	mutex_lock(&tp->control);3425 3426	if (changed & NETIF_F_HW_VLAN_CTAG_RX) {3427		if (features & NETIF_F_HW_VLAN_CTAG_RX)3428			rtl_rx_vlan_en(tp, true);3429		else3430			rtl_rx_vlan_en(tp, false);3431	}3432 3433	mutex_unlock(&tp->control);3434 3435	usb_autopm_put_interface(tp->intf);3436 3437out:3438	return ret;3439}3440 3441#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)3442 3443static u32 __rtl_get_wol(struct r8152 *tp)3444{3445	u32 ocp_data;3446	u32 wolopts = 0;3447 3448	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);3449	if (ocp_data & LINK_ON_WAKE_EN)3450		wolopts |= WAKE_PHY;3451 3452	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);3453	if (ocp_data & UWF_EN)3454		wolopts |= WAKE_UCAST;3455	if (ocp_data & BWF_EN)3456		wolopts |= WAKE_BCAST;3457	if (ocp_data & MWF_EN)3458		wolopts |= WAKE_MCAST;3459 3460	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);3461	if (ocp_data & MAGIC_EN)3462		wolopts |= WAKE_MAGIC;3463 3464	return wolopts;3465}3466 3467static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)3468{3469	u32 ocp_data;3470 3471	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);3472 3473	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);3474	ocp_data &= ~LINK_ON_WAKE_EN;3475	if (wolopts & WAKE_PHY)3476		ocp_data |= LINK_ON_WAKE_EN;3477	ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);3478 3479	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);3480	ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN);3481	if (wolopts & WAKE_UCAST)3482		ocp_data |= UWF_EN;3483	if (wolopts & WAKE_BCAST)3484		ocp_data |= BWF_EN;3485	if (wolopts & WAKE_MCAST)3486		ocp_data |= MWF_EN;3487	ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);3488 3489	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);3490 3491	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);3492	ocp_data &= ~MAGIC_EN;3493	if (wolopts & WAKE_MAGIC)3494		ocp_data |= MAGIC_EN;3495	ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);3496 3497	if (wolopts & WAKE_ANY)3498		device_set_wakeup_enable(&tp->udev->dev, true);3499	else3500		device_set_wakeup_enable(&tp->udev->dev, false);3501}3502 3503static void r8153_mac_clk_speed_down(struct r8152 *tp, bool enable)3504{3505	u32 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);3506 3507	/* MAC clock speed down */3508	if (enable)3509		ocp_data |= MAC_CLK_SPDWN_EN;3510	else3511		ocp_data &= ~MAC_CLK_SPDWN_EN;3512 3513	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);3514}3515 3516static void r8156_mac_clk_spd(struct r8152 *tp, bool enable)3517{3518	u32 ocp_data;3519 3520	/* MAC clock speed down */3521	if (enable) {3522		/* aldps_spdwn_ratio, tp10_spdwn_ratio */3523		ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL,3524			       0x0403);3525 3526		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);3527		ocp_data &= ~EEE_SPDWN_RATIO_MASK;3528		ocp_data |= MAC_CLK_SPDWN_EN | 0x03; /* eee_spdwn_ratio */3529		ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);3530	} else {3531		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);3532		ocp_data &= ~MAC_CLK_SPDWN_EN;3533		ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);3534	}3535}3536 3537static void r8153_u1u2en(struct r8152 *tp, bool enable)3538{3539	u8 u1u2[8];3540 3541	if (enable)3542		memset(u1u2, 0xff, sizeof(u1u2));3543	else3544		memset(u1u2, 0x00, sizeof(u1u2));3545 3546	usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);3547}3548 3549static void r8153b_u1u2en(struct r8152 *tp, bool enable)3550{3551	u32 ocp_data;3552 3553	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG);3554	if (enable)3555		ocp_data |= LPM_U1U2_EN;3556	else3557		ocp_data &= ~LPM_U1U2_EN;3558 3559	ocp_write_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG, ocp_data);3560}3561 3562static void r8153_u2p3en(struct r8152 *tp, bool enable)3563{3564	u32 ocp_data;3565 3566	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);3567	if (enable)3568		ocp_data |= U2P3_ENABLE;3569	else3570		ocp_data &= ~U2P3_ENABLE;3571	ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);3572}3573 3574static void r8153b_ups_flags(struct r8152 *tp)3575{3576	u32 ups_flags = 0;3577 3578	if (tp->ups_info.green)3579		ups_flags |= UPS_FLAGS_EN_GREEN;3580 3581	if (tp->ups_info.aldps)3582		ups_flags |= UPS_FLAGS_EN_ALDPS;3583 3584	if (tp->ups_info.eee)3585		ups_flags |= UPS_FLAGS_EN_EEE;3586 3587	if (tp->ups_info.flow_control)3588		ups_flags |= UPS_FLAGS_EN_FLOW_CTR;3589 3590	if (tp->ups_info.eee_ckdiv)3591		ups_flags |= UPS_FLAGS_EN_EEE_CKDIV;3592 3593	if (tp->ups_info.eee_cmod_lv)3594		ups_flags |= UPS_FLAGS_EEE_CMOD_LV_EN;3595 3596	if (tp->ups_info.r_tune)3597		ups_flags |= UPS_FLAGS_R_TUNE;3598 3599	if (tp->ups_info._10m_ckdiv)3600		ups_flags |= UPS_FLAGS_EN_10M_CKDIV;3601 3602	if (tp->ups_info.eee_plloff_100)3603		ups_flags |= UPS_FLAGS_EEE_PLLOFF_100;3604 3605	if (tp->ups_info.eee_plloff_giga)3606		ups_flags |= UPS_FLAGS_EEE_PLLOFF_GIGA;3607 3608	if (tp->ups_info._250m_ckdiv)3609		ups_flags |= UPS_FLAGS_250M_CKDIV;3610 3611	if (tp->ups_info.ctap_short_off)3612		ups_flags |= UPS_FLAGS_CTAP_SHORT_DIS;3613 3614	switch (tp->ups_info.speed_duplex) {3615	case NWAY_10M_HALF:3616		ups_flags |= ups_flags_speed(1);3617		break;3618	case NWAY_10M_FULL:3619		ups_flags |= ups_flags_speed(2);3620		break;3621	case NWAY_100M_HALF:3622		ups_flags |= ups_flags_speed(3);3623		break;3624	case NWAY_100M_FULL:3625		ups_flags |= ups_flags_speed(4);3626		break;3627	case NWAY_1000M_FULL:3628		ups_flags |= ups_flags_speed(5);3629		break;3630	case FORCE_10M_HALF:3631		ups_flags |= ups_flags_speed(6);3632		break;3633	case FORCE_10M_FULL:3634		ups_flags |= ups_flags_speed(7);3635		break;3636	case FORCE_100M_HALF:3637		ups_flags |= ups_flags_speed(8);3638		break;3639	case FORCE_100M_FULL:3640		ups_flags |= ups_flags_speed(9);3641		break;3642	default:3643		break;3644	}3645 3646	ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ups_flags);3647}3648 3649static void r8156_ups_flags(struct r8152 *tp)3650{3651	u32 ups_flags = 0;3652 3653	if (tp->ups_info.green)3654		ups_flags |= UPS_FLAGS_EN_GREEN;3655 3656	if (tp->ups_info.aldps)3657		ups_flags |= UPS_FLAGS_EN_ALDPS;3658 3659	if (tp->ups_info.eee)3660		ups_flags |= UPS_FLAGS_EN_EEE;3661 3662	if (tp->ups_info.flow_control)3663		ups_flags |= UPS_FLAGS_EN_FLOW_CTR;3664 3665	if (tp->ups_info.eee_ckdiv)3666		ups_flags |= UPS_FLAGS_EN_EEE_CKDIV;3667 3668	if (tp->ups_info._10m_ckdiv)3669		ups_flags |= UPS_FLAGS_EN_10M_CKDIV;3670 3671	if (tp->ups_info.eee_plloff_100)3672		ups_flags |= UPS_FLAGS_EEE_PLLOFF_100;3673 3674	if (tp->ups_info.eee_plloff_giga)3675		ups_flags |= UPS_FLAGS_EEE_PLLOFF_GIGA;3676 3677	if (tp->ups_info._250m_ckdiv)3678		ups_flags |= UPS_FLAGS_250M_CKDIV;3679 3680	switch (tp->ups_info.speed_duplex) {3681	case FORCE_10M_HALF:3682		ups_flags |= ups_flags_speed(0);3683		break;3684	case FORCE_10M_FULL:3685		ups_flags |= ups_flags_speed(1);3686		break;3687	case FORCE_100M_HALF:3688		ups_flags |= ups_flags_speed(2);3689		break;3690	case FORCE_100M_FULL:3691		ups_flags |= ups_flags_speed(3);3692		break;3693	case NWAY_10M_HALF:3694		ups_flags |= ups_flags_speed(4);3695		break;3696	case NWAY_10M_FULL:3697		ups_flags |= ups_flags_speed(5);3698		break;3699	case NWAY_100M_HALF:3700		ups_flags |= ups_flags_speed(6);3701		break;3702	case NWAY_100M_FULL:3703		ups_flags |= ups_flags_speed(7);3704		break;3705	case NWAY_1000M_FULL:3706		ups_flags |= ups_flags_speed(8);3707		break;3708	case NWAY_2500M_FULL:3709		ups_flags |= ups_flags_speed(9);3710		break;3711	default:3712		break;3713	}3714 3715	switch (tp->ups_info.lite_mode) {3716	case 1:3717		ups_flags |= 0 << 5;3718		break;3719	case 2:3720		ups_flags |= 2 << 5;3721		break;3722	case 0:3723	default:3724		ups_flags |= 1 << 5;3725		break;3726	}3727 3728	ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ups_flags);3729}3730 3731static void rtl_green_en(struct r8152 *tp, bool enable)3732{3733	u16 data;3734 3735	data = sram_read(tp, SRAM_GREEN_CFG);3736	if (enable)3737		data |= GREEN_ETH_EN;3738	else3739		data &= ~GREEN_ETH_EN;3740	sram_write(tp, SRAM_GREEN_CFG, data);3741 3742	tp->ups_info.green = enable;3743}3744 3745static void r8153b_green_en(struct r8152 *tp, bool enable)3746{3747	if (enable) {3748		sram_write(tp, 0x8045, 0);	/* 10M abiq&ldvbias */3749		sram_write(tp, 0x804d, 0x1222);	/* 100M short abiq&ldvbias */3750		sram_write(tp, 0x805d, 0x0022);	/* 1000M short abiq&ldvbias */3751	} else {3752		sram_write(tp, 0x8045, 0x2444);	/* 10M abiq&ldvbias */3753		sram_write(tp, 0x804d, 0x2444);	/* 100M short abiq&ldvbias */3754		sram_write(tp, 0x805d, 0x2444);	/* 1000M short abiq&ldvbias */3755	}3756 3757	rtl_green_en(tp, true);3758}3759 3760static u16 r8153_phy_status(struct r8152 *tp, u16 desired)3761{3762	u16 data;3763	int i;3764 3765	for (i = 0; i < 500; i++) {3766		data = ocp_reg_read(tp, OCP_PHY_STATUS);3767		data &= PHY_STAT_MASK;3768		if (desired) {3769			if (data == desired)3770				break;3771		} else if (data == PHY_STAT_LAN_ON || data == PHY_STAT_PWRDN ||3772			   data == PHY_STAT_EXT_INIT) {3773			break;3774		}3775 3776		msleep(20);3777		if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))3778			break;3779	}3780 3781	return data;3782}3783 3784static void r8153b_ups_en(struct r8152 *tp, bool enable)3785{3786	u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);3787 3788	if (enable) {3789		r8153b_ups_flags(tp);3790 3791		ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;3792		ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);3793 3794		ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);3795		ocp_data |= UPS_FORCE_PWR_DOWN;3796		ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);3797	} else {3798		ocp_data &= ~(UPS_EN | USP_PREWAKE);3799		ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);3800 3801		ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);3802		ocp_data &= ~UPS_FORCE_PWR_DOWN;3803		ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);3804 3805		if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) {3806			int i;3807 3808			for (i = 0; i < 500; i++) {3809				if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))3810					return;3811				if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &3812				    AUTOLOAD_DONE)3813					break;3814				msleep(20);3815			}3816 3817			tp->rtl_ops.hw_phy_cfg(tp);3818 3819			rtl8152_set_speed(tp, tp->autoneg, tp->speed,3820					  tp->duplex, tp->advertising);3821		}3822	}3823}3824 3825static void r8153c_ups_en(struct r8152 *tp, bool enable)3826{3827	u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);3828 3829	if (enable) {3830		r8153b_ups_flags(tp);3831 3832		ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;3833		ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);3834 3835		ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);3836		ocp_data |= UPS_FORCE_PWR_DOWN;3837		ocp_data &= ~BIT(7);3838		ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);3839	} else {3840		ocp_data &= ~(UPS_EN | USP_PREWAKE);3841		ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);3842 3843		ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);3844		ocp_data &= ~UPS_FORCE_PWR_DOWN;3845		ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);3846 3847		if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) {3848			int i;3849 3850			for (i = 0; i < 500; i++) {3851				if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))3852					return;3853				if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &3854				    AUTOLOAD_DONE)3855					break;3856				msleep(20);3857			}3858 3859			tp->rtl_ops.hw_phy_cfg(tp);3860 3861			rtl8152_set_speed(tp, tp->autoneg, tp->speed,3862					  tp->duplex, tp->advertising);3863		}3864 3865		ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);3866 3867		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);3868		ocp_data |= BIT(8);3869		ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);3870 3871		ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);3872	}3873}3874 3875static void r8156_ups_en(struct r8152 *tp, bool enable)3876{3877	u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);3878 3879	if (enable) {3880		r8156_ups_flags(tp);3881 3882		ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;3883		ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);3884 3885		ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);3886		ocp_data |= UPS_FORCE_PWR_DOWN;3887		ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);3888 3889		switch (tp->version) {3890		case RTL_VER_13:3891		case RTL_VER_15:3892			ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPHY_XTAL);3893			ocp_data &= ~OOBS_POLLING;3894			ocp_write_byte(tp, MCU_TYPE_USB, USB_UPHY_XTAL, ocp_data);3895			break;3896		default:3897			break;3898		}3899	} else {3900		ocp_data &= ~(UPS_EN | USP_PREWAKE);3901		ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);3902 3903		ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);3904		ocp_data &= ~UPS_FORCE_PWR_DOWN;3905		ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);3906 3907		if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) {3908			tp->rtl_ops.hw_phy_cfg(tp);3909 3910			rtl8152_set_speed(tp, tp->autoneg, tp->speed,3911					  tp->duplex, tp->advertising);3912		}3913	}3914}3915 3916static void r8153_power_cut_en(struct r8152 *tp, bool enable)3917{3918	u32 ocp_data;3919 3920	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);3921	if (enable)3922		ocp_data |= PWR_EN | PHASE2_EN;3923	else3924		ocp_data &= ~(PWR_EN | PHASE2_EN);3925	ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);3926 3927	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);3928	ocp_data &= ~PCUT_STATUS;3929	ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);3930}3931 3932static void r8153b_power_cut_en(struct r8152 *tp, bool enable)3933{3934	u32 ocp_data;3935 3936	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);3937	if (enable)3938		ocp_data |= PWR_EN | PHASE2_EN;3939	else3940		ocp_data &= ~PWR_EN;3941	ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);3942 3943	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);3944	ocp_data &= ~PCUT_STATUS;3945	ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);3946}3947 3948static void r8153_queue_wake(struct r8152 *tp, bool enable)3949{3950	u32 ocp_data;3951 3952	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG);3953	if (enable)3954		ocp_data |= UPCOMING_RUNTIME_D3;3955	else3956		ocp_data &= ~UPCOMING_RUNTIME_D3;3957	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG, ocp_data);3958 3959	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG);3960	ocp_data &= ~LINK_CHG_EVENT;3961	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG, ocp_data);3962 3963	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);3964	ocp_data &= ~LINK_CHANGE_FLAG;3965	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);3966}3967 3968static bool rtl_can_wakeup(struct r8152 *tp)3969{3970	struct usb_device *udev = tp->udev;3971 3972	return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP);3973}3974 3975static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)3976{3977	if (enable) {3978		u32 ocp_data;3979 3980		__rtl_set_wol(tp, WAKE_ANY);3981 3982		ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);3983 3984		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);3985		ocp_data |= LINK_OFF_WAKE_EN;3986		ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);3987 3988		ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);3989	} else {3990		u32 ocp_data;3991 3992		__rtl_set_wol(tp, tp->saved_wolopts);3993 3994		ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);3995 3996		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);3997		ocp_data &= ~LINK_OFF_WAKE_EN;3998		ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);3999 4000		ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);4001	}4002}4003 4004static void rtl8153_runtime_enable(struct r8152 *tp, bool enable)4005{4006	if (enable) {4007		r8153_u1u2en(tp, false);4008		r8153_u2p3en(tp, false);4009		rtl_runtime_suspend_enable(tp, true);4010	} else {4011		rtl_runtime_suspend_enable(tp, false);4012 4013		switch (tp->version) {4014		case RTL_VER_03:4015		case RTL_VER_04:4016			break;4017		case RTL_VER_05:4018		case RTL_VER_06:4019		default:4020			r8153_u2p3en(tp, true);4021			break;4022		}4023 4024		r8153_u1u2en(tp, true);4025	}4026}4027 4028static void rtl8153b_runtime_enable(struct r8152 *tp, bool enable)4029{4030	if (enable) {4031		r8153_queue_wake(tp, true);4032		r8153b_u1u2en(tp, false);4033		r8153_u2p3en(tp, false);4034		rtl_runtime_suspend_enable(tp, true);4035		r8153b_ups_en(tp, true);4036	} else {4037		r8153b_ups_en(tp, false);4038		r8153_queue_wake(tp, false);4039		rtl_runtime_suspend_enable(tp, false);4040		if (tp->udev->speed >= USB_SPEED_SUPER)4041			r8153b_u1u2en(tp, true);4042	}4043}4044 4045static void rtl8153c_runtime_enable(struct r8152 *tp, bool enable)4046{4047	if (enable) {4048		r8153_queue_wake(tp, true);4049		r8153b_u1u2en(tp, false);4050		r8153_u2p3en(tp, false);4051		rtl_runtime_suspend_enable(tp, true);4052		r8153c_ups_en(tp, true);4053	} else {4054		r8153c_ups_en(tp, false);4055		r8153_queue_wake(tp, false);4056		rtl_runtime_suspend_enable(tp, false);4057		r8153b_u1u2en(tp, true);4058	}4059}4060 4061static void rtl8156_runtime_enable(struct r8152 *tp, bool enable)4062{4063	if (enable) {4064		r8153_queue_wake(tp, true);4065		r8153b_u1u2en(tp, false);4066		r8153_u2p3en(tp, false);4067		rtl_runtime_suspend_enable(tp, true);4068	} else {4069		r8153_queue_wake(tp, false);4070		rtl_runtime_suspend_enable(tp, false);4071		r8153_u2p3en(tp, true);4072		if (tp->udev->speed >= USB_SPEED_SUPER)4073			r8153b_u1u2en(tp, true);4074	}4075}4076 4077static void r8153_teredo_off(struct r8152 *tp)4078{4079	u32 ocp_data;4080 4081	switch (tp->version) {4082	case RTL_VER_01:4083	case RTL_VER_02:4084	case RTL_VER_03:4085	case RTL_VER_04:4086	case RTL_VER_05:4087	case RTL_VER_06:4088	case RTL_VER_07:4089		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);4090		ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK |4091			      OOB_TEREDO_EN);4092		ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);4093		break;4094 4095	case RTL_VER_08:4096	case RTL_VER_09:4097	case RTL_TEST_01:4098	case RTL_VER_10:4099	case RTL_VER_11:4100	case RTL_VER_12:4101	case RTL_VER_13:4102	case RTL_VER_14:4103	case RTL_VER_15:4104	default:4105		/* The bit 0 ~ 7 are relative with teredo settings. They are4106		 * W1C (write 1 to clear), so set all 1 to disable it.4107		 */4108		ocp_write_byte(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, 0xff);4109		break;4110	}4111 4112	ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);4113	ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);4114	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);4115}4116 4117static void rtl_reset_bmu(struct r8152 *tp)4118{4119	u32 ocp_data;4120 4121	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET);4122	ocp_data &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT);4123	ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);4124	ocp_data |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT;4125	ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);4126}4127 4128/* Clear the bp to stop the firmware before loading a new one */4129static void rtl_clear_bp(struct r8152 *tp, u16 type)4130{4131	u16 bp[16] = {0};4132	u16 bp_num;4133 4134	switch (tp->version) {4135	case RTL_VER_08:4136	case RTL_VER_09:4137	case RTL_VER_10:4138	case RTL_VER_11:4139	case RTL_VER_12:4140	case RTL_VER_13:4141	case RTL_VER_15:4142		if (type == MCU_TYPE_USB) {4143			ocp_write_word(tp, MCU_TYPE_USB, USB_BP2_EN, 0);4144			bp_num = 16;4145			break;4146		}4147		fallthrough;4148	case RTL_VER_03:4149	case RTL_VER_04:4150	case RTL_VER_05:4151	case RTL_VER_06:4152		ocp_write_byte(tp, type, PLA_BP_EN, 0);4153		fallthrough;4154	case RTL_VER_01:4155	case RTL_VER_02:4156	case RTL_VER_07:4157		bp_num = 8;4158		break;4159	case RTL_VER_14:4160	default:4161		ocp_write_word(tp, type, USB_BP2_EN, 0);4162		bp_num = 16;4163		break;4164	}4165 4166	generic_ocp_write(tp, PLA_BP_0, BYTE_EN_DWORD, bp_num << 1, bp, type);4167 4168	/* wait 3 ms to make sure the firmware is stopped */4169	usleep_range(3000, 6000);4170	ocp_write_word(tp, type, PLA_BP_BA, 0);4171}4172 4173static inline void rtl_reset_ocp_base(struct r8152 *tp)4174{4175	tp->ocp_base = -1;4176}4177 4178static int rtl_phy_patch_request(struct r8152 *tp, bool request, bool wait)4179{4180	u16 data, check;4181	int i;4182 4183	data = ocp_reg_read(tp, OCP_PHY_PATCH_CMD);4184	if (request) {4185		data |= PATCH_REQUEST;4186		check = 0;4187	} else {4188		data &= ~PATCH_REQUEST;4189		check = PATCH_READY;4190	}4191	ocp_reg_write(tp, OCP_PHY_PATCH_CMD, data);4192 4193	for (i = 0; wait && i < 5000; i++) {4194		u32 ocp_data;4195 4196		if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))4197			return -ENODEV;4198 4199		usleep_range(1000, 2000);4200		ocp_data = ocp_reg_read(tp, OCP_PHY_PATCH_STAT);4201		if ((ocp_data & PATCH_READY) ^ check)4202			break;4203	}4204 4205	if (request && wait &&4206	    !(ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)) {4207		dev_err(&tp->intf->dev, "PHY patch request fail\n");4208		rtl_phy_patch_request(tp, false, false);4209		return -ETIME;4210	} else {4211		return 0;4212	}4213}4214 4215static void rtl_patch_key_set(struct r8152 *tp, u16 key_addr, u16 patch_key)4216{4217	if (patch_key && key_addr) {4218		sram_write(tp, key_addr, patch_key);4219		sram_write(tp, SRAM_PHY_LOCK, PHY_PATCH_LOCK);4220	} else if (key_addr) {4221		u16 data;4222 4223		sram_write(tp, 0x0000, 0x0000);4224 4225		data = ocp_reg_read(tp, OCP_PHY_LOCK);4226		data &= ~PATCH_LOCK;4227		ocp_reg_write(tp, OCP_PHY_LOCK, data);4228 4229		sram_write(tp, key_addr, 0x0000);4230	} else {4231		WARN_ON_ONCE(1);4232	}4233}4234 4235static int4236rtl_pre_ram_code(struct r8152 *tp, u16 key_addr, u16 patch_key, bool wait)4237{4238	if (rtl_phy_patch_request(tp, true, wait))4239		return -ETIME;4240 4241	rtl_patch_key_set(tp, key_addr, patch_key);4242 4243	return 0;4244}4245 4246static int rtl_post_ram_code(struct r8152 *tp, u16 key_addr, bool wait)4247{4248	rtl_patch_key_set(tp, key_addr, 0);4249 4250	rtl_phy_patch_request(tp, false, wait);4251 4252	return 0;4253}4254 4255static bool rtl8152_is_fw_phy_speed_up_ok(struct r8152 *tp, struct fw_phy_speed_up *phy)4256{4257	u16 fw_offset;4258	u32 length;4259	bool rc = false;4260 4261	switch (tp->version) {4262	case RTL_VER_01:4263	case RTL_VER_02:4264	case RTL_VER_03:4265	case RTL_VER_04:4266	case RTL_VER_05:4267	case RTL_VER_06:4268	case RTL_VER_07:4269	case RTL_VER_08:4270	case RTL_VER_09:4271	case RTL_VER_10:4272	case RTL_VER_11:4273	case RTL_VER_12:4274	case RTL_VER_14:4275		goto out;4276	case RTL_VER_13:4277	case RTL_VER_15:4278	default:4279		break;4280	}4281 4282	fw_offset = __le16_to_cpu(phy->fw_offset);4283	length = __le32_to_cpu(phy->blk_hdr.length);4284	if (fw_offset < sizeof(*phy) || length <= fw_offset) {4285		dev_err(&tp->intf->dev, "invalid fw_offset\n");4286		goto out;4287	}4288 4289	length -= fw_offset;4290	if (length & 3) {4291		dev_err(&tp->intf->dev, "invalid block length\n");4292		goto out;4293	}4294 4295	if (__le16_to_cpu(phy->fw_reg) != 0x9A00) {4296		dev_err(&tp->intf->dev, "invalid register to load firmware\n");4297		goto out;4298	}4299 4300	rc = true;4301out:4302	return rc;4303}4304 4305static bool rtl8152_is_fw_phy_ver_ok(struct r8152 *tp, struct fw_phy_ver *ver)4306{4307	bool rc = false;4308 4309	switch (tp->version) {4310	case RTL_VER_10:4311	case RTL_VER_11:4312	case RTL_VER_12:4313	case RTL_VER_13:4314	case RTL_VER_15:4315		break;4316	default:4317		goto out;4318	}4319 4320	if (__le32_to_cpu(ver->blk_hdr.length) != sizeof(*ver)) {4321		dev_err(&tp->intf->dev, "invalid block length\n");4322		goto out;4323	}4324 4325	if (__le16_to_cpu(ver->ver.addr) != SRAM_GPHY_FW_VER) {4326		dev_err(&tp->intf->dev, "invalid phy ver addr\n");4327		goto out;4328	}4329 4330	rc = true;4331out:4332	return rc;4333}4334 4335static bool rtl8152_is_fw_phy_fixup_ok(struct r8152 *tp, struct fw_phy_fixup *fix)4336{4337	bool rc = false;4338 4339	switch (tp->version) {4340	case RTL_VER_10:4341	case RTL_VER_11:4342	case RTL_VER_12:4343	case RTL_VER_13:4344	case RTL_VER_15:4345		break;4346	default:4347		goto out;4348	}4349 4350	if (__le32_to_cpu(fix->blk_hdr.length) != sizeof(*fix)) {4351		dev_err(&tp->intf->dev, "invalid block length\n");4352		goto out;4353	}4354 4355	if (__le16_to_cpu(fix->setting.addr) != OCP_PHY_PATCH_CMD ||4356	    __le16_to_cpu(fix->setting.data) != BIT(7)) {4357		dev_err(&tp->intf->dev, "invalid phy fixup\n");4358		goto out;4359	}4360 4361	rc = true;4362out:4363	return rc;4364}4365 4366static bool rtl8152_is_fw_phy_union_ok(struct r8152 *tp, struct fw_phy_union *phy)4367{4368	u16 fw_offset;4369	u32 length;4370	bool rc = false;4371 4372	switch (tp->version) {4373	case RTL_VER_10:4374	case RTL_VER_11:4375	case RTL_VER_12:4376	case RTL_VER_13:4377	case RTL_VER_15:4378		break;4379	default:4380		goto out;4381	}4382 4383	fw_offset = __le16_to_cpu(phy->fw_offset);4384	length = __le32_to_cpu(phy->blk_hdr.length);4385	if (fw_offset < sizeof(*phy) || length <= fw_offset) {4386		dev_err(&tp->intf->dev, "invalid fw_offset\n");4387		goto out;4388	}4389 4390	length -= fw_offset;4391	if (length & 1) {4392		dev_err(&tp->intf->dev, "invalid block length\n");4393		goto out;4394	}4395 4396	if (phy->pre_num > 2) {4397		dev_err(&tp->intf->dev, "invalid pre_num %d\n", phy->pre_num);4398		goto out;4399	}4400 4401	if (phy->bp_num > 8) {4402		dev_err(&tp->intf->dev, "invalid bp_num %d\n", phy->bp_num);4403		goto out;4404	}4405 4406	rc = true;4407out:4408	return rc;4409}4410 4411static bool rtl8152_is_fw_phy_nc_ok(struct r8152 *tp, struct fw_phy_nc *phy)4412{4413	u32 length;4414	u16 fw_offset, fw_reg, ba_reg, patch_en_addr, mode_reg, bp_start;4415	bool rc = false;4416 4417	switch (tp->version) {4418	case RTL_VER_04:4419	case RTL_VER_05:4420	case RTL_VER_06:4421		fw_reg = 0xa014;4422		ba_reg = 0xa012;4423		patch_en_addr = 0xa01a;4424		mode_reg = 0xb820;4425		bp_start = 0xa000;4426		break;4427	default:4428		goto out;4429	}4430 4431	fw_offset = __le16_to_cpu(phy->fw_offset);4432	if (fw_offset < sizeof(*phy)) {4433		dev_err(&tp->intf->dev, "fw_offset too small\n");4434		goto out;4435	}4436 4437	length = __le32_to_cpu(phy->blk_hdr.length);4438	if (length < fw_offset) {4439		dev_err(&tp->intf->dev, "invalid fw_offset\n");4440		goto out;4441	}4442 4443	length -= __le16_to_cpu(phy->fw_offset);4444	if (!length || (length & 1)) {4445		dev_err(&tp->intf->dev, "invalid block length\n");4446		goto out;4447	}4448 4449	if (__le16_to_cpu(phy->fw_reg) != fw_reg) {4450		dev_err(&tp->intf->dev, "invalid register to load firmware\n");4451		goto out;4452	}4453 4454	if (__le16_to_cpu(phy->ba_reg) != ba_reg) {4455		dev_err(&tp->intf->dev, "invalid base address register\n");4456		goto out;4457	}4458 4459	if (__le16_to_cpu(phy->patch_en_addr) != patch_en_addr) {4460		dev_err(&tp->intf->dev,4461			"invalid patch mode enabled register\n");4462		goto out;4463	}4464 4465	if (__le16_to_cpu(phy->mode_reg) != mode_reg) {4466		dev_err(&tp->intf->dev,4467			"invalid register to switch the mode\n");4468		goto out;4469	}4470 4471	if (__le16_to_cpu(phy->bp_start) != bp_start) {4472		dev_err(&tp->intf->dev,4473			"invalid start register of break point\n");4474		goto out;4475	}4476 4477	if (__le16_to_cpu(phy->bp_num) > 4) {4478		dev_err(&tp->intf->dev, "invalid break point number\n");4479		goto out;4480	}4481 4482	rc = true;4483out:4484	return rc;4485}4486 4487static bool rtl8152_is_fw_mac_ok(struct r8152 *tp, struct fw_mac *mac)4488{4489	u16 fw_reg, bp_ba_addr, bp_en_addr, bp_start, fw_offset;4490	bool rc = false;4491	u32 length, type;4492	int i, max_bp;4493 4494	type = __le32_to_cpu(mac->blk_hdr.type);4495	if (type == RTL_FW_PLA) {4496		switch (tp->version) {4497		case RTL_VER_01:4498		case RTL_VER_02:4499		case RTL_VER_07:4500			fw_reg = 0xf800;4501			bp_ba_addr = PLA_BP_BA;4502			bp_en_addr = 0;4503			bp_start = PLA_BP_0;4504			max_bp = 8;4505			break;4506		case RTL_VER_03:4507		case RTL_VER_04:4508		case RTL_VER_05:4509		case RTL_VER_06:4510		case RTL_VER_08:4511		case RTL_VER_09:4512		case RTL_VER_11:4513		case RTL_VER_12:4514		case RTL_VER_13:4515		case RTL_VER_15:4516			fw_reg = 0xf800;4517			bp_ba_addr = PLA_BP_BA;4518			bp_en_addr = PLA_BP_EN;4519			bp_start = PLA_BP_0;4520			max_bp = 8;4521			break;4522		case RTL_VER_14:4523			fw_reg = 0xf800;4524			bp_ba_addr = PLA_BP_BA;4525			bp_en_addr = USB_BP2_EN;4526			bp_start = PLA_BP_0;4527			max_bp = 16;4528			break;4529		default:4530			goto out;4531		}4532	} else if (type == RTL_FW_USB) {4533		switch (tp->version) {4534		case RTL_VER_03:4535		case RTL_VER_04:4536		case RTL_VER_05:4537		case RTL_VER_06:4538			fw_reg = 0xf800;4539			bp_ba_addr = USB_BP_BA;4540			bp_en_addr = USB_BP_EN;4541			bp_start = USB_BP_0;4542			max_bp = 8;4543			break;4544		case RTL_VER_08:4545		case RTL_VER_09:4546		case RTL_VER_11:4547		case RTL_VER_12:4548		case RTL_VER_13:4549		case RTL_VER_14:4550		case RTL_VER_15:4551			fw_reg = 0xe600;4552			bp_ba_addr = USB_BP_BA;4553			bp_en_addr = USB_BP2_EN;4554			bp_start = USB_BP_0;4555			max_bp = 16;4556			break;4557		case RTL_VER_01:4558		case RTL_VER_02:4559		case RTL_VER_07:4560		default:4561			goto out;4562		}4563	} else {4564		goto out;4565	}4566 4567	fw_offset = __le16_to_cpu(mac->fw_offset);4568	if (fw_offset < sizeof(*mac)) {4569		dev_err(&tp->intf->dev, "fw_offset too small\n");4570		goto out;4571	}4572 4573	length = __le32_to_cpu(mac->blk_hdr.length);4574	if (length < fw_offset) {4575		dev_err(&tp->intf->dev, "invalid fw_offset\n");4576		goto out;4577	}4578 4579	length -= fw_offset;4580	if (length < 4 || (length & 3)) {4581		dev_err(&tp->intf->dev, "invalid block length\n");4582		goto out;4583	}4584 4585	if (__le16_to_cpu(mac->fw_reg) != fw_reg) {4586		dev_err(&tp->intf->dev, "invalid register to load firmware\n");4587		goto out;4588	}4589 4590	if (__le16_to_cpu(mac->bp_ba_addr) != bp_ba_addr) {4591		dev_err(&tp->intf->dev, "invalid base address register\n");4592		goto out;4593	}4594 4595	if (__le16_to_cpu(mac->bp_en_addr) != bp_en_addr) {4596		dev_err(&tp->intf->dev, "invalid enabled mask register\n");4597		goto out;4598	}4599 4600	if (__le16_to_cpu(mac->bp_start) != bp_start) {4601		dev_err(&tp->intf->dev,4602			"invalid start register of break point\n");4603		goto out;4604	}4605 4606	if (__le16_to_cpu(mac->bp_num) > max_bp) {4607		dev_err(&tp->intf->dev, "invalid break point number\n");4608		goto out;4609	}4610 4611	for (i = __le16_to_cpu(mac->bp_num); i < max_bp; i++) {4612		if (mac->bp[i]) {4613			dev_err(&tp->intf->dev, "unused bp%u is not zero\n", i);4614			goto out;4615		}4616	}4617 4618	rc = true;4619out:4620	return rc;4621}4622 4623/* Verify the checksum for the firmware file. It is calculated from the version4624 * field to the end of the file. Compare the result with the checksum field to4625 * make sure the file is correct.4626 */4627static long rtl8152_fw_verify_checksum(struct r8152 *tp,4628				       struct fw_header *fw_hdr, size_t size)4629{4630	unsigned char checksum[sizeof(fw_hdr->checksum)];4631	struct crypto_shash *alg;4632	struct shash_desc *sdesc;4633	size_t len;4634	long rc;4635 4636	alg = crypto_alloc_shash("sha256", 0, 0);4637	if (IS_ERR(alg)) {4638		rc = PTR_ERR(alg);4639		goto out;4640	}4641 4642	if (crypto_shash_digestsize(alg) != sizeof(fw_hdr->checksum)) {4643		rc = -EFAULT;4644		dev_err(&tp->intf->dev, "digestsize incorrect (%u)\n",4645			crypto_shash_digestsize(alg));4646		goto free_shash;4647	}4648 4649	len = sizeof(*sdesc) + crypto_shash_descsize(alg);4650	sdesc = kmalloc(len, GFP_KERNEL);4651	if (!sdesc) {4652		rc = -ENOMEM;4653		goto free_shash;4654	}4655	sdesc->tfm = alg;4656 4657	len = size - sizeof(fw_hdr->checksum);4658	rc = crypto_shash_digest(sdesc, fw_hdr->version, len, checksum);4659	kfree(sdesc);4660	if (rc)4661		goto free_shash;4662 4663	if (memcmp(fw_hdr->checksum, checksum, sizeof(fw_hdr->checksum))) {4664		dev_err(&tp->intf->dev, "checksum fail\n");4665		rc = -EFAULT;4666	}4667 4668free_shash:4669	crypto_free_shash(alg);4670out:4671	return rc;4672}4673 4674static long rtl8152_check_firmware(struct r8152 *tp, struct rtl_fw *rtl_fw)4675{4676	const struct firmware *fw = rtl_fw->fw;4677	struct fw_header *fw_hdr = (struct fw_header *)fw->data;4678	unsigned long fw_flags = 0;4679	long ret = -EFAULT;4680	int i;4681 4682	if (fw->size < sizeof(*fw_hdr)) {4683		dev_err(&tp->intf->dev, "file too small\n");4684		goto fail;4685	}4686 4687	ret = rtl8152_fw_verify_checksum(tp, fw_hdr, fw->size);4688	if (ret)4689		goto fail;4690 4691	ret = -EFAULT;4692 4693	for (i = sizeof(*fw_hdr); i < fw->size;) {4694		struct fw_block *block = (struct fw_block *)&fw->data[i];4695		u32 type;4696 4697		if ((i + sizeof(*block)) > fw->size)4698			goto fail;4699 4700		type = __le32_to_cpu(block->type);4701		switch (type) {4702		case RTL_FW_END:4703			if (__le32_to_cpu(block->length) != sizeof(*block))4704				goto fail;4705			goto fw_end;4706		case RTL_FW_PLA:4707			if (test_bit(FW_FLAGS_PLA, &fw_flags)) {4708				dev_err(&tp->intf->dev,4709					"multiple PLA firmware encountered");4710				goto fail;4711			}4712 4713			if (!rtl8152_is_fw_mac_ok(tp, (struct fw_mac *)block)) {4714				dev_err(&tp->intf->dev,4715					"check PLA firmware failed\n");4716				goto fail;4717			}4718			__set_bit(FW_FLAGS_PLA, &fw_flags);4719			break;4720		case RTL_FW_USB:4721			if (test_bit(FW_FLAGS_USB, &fw_flags)) {4722				dev_err(&tp->intf->dev,4723					"multiple USB firmware encountered");4724				goto fail;4725			}4726 4727			if (!rtl8152_is_fw_mac_ok(tp, (struct fw_mac *)block)) {4728				dev_err(&tp->intf->dev,4729					"check USB firmware failed\n");4730				goto fail;4731			}4732			__set_bit(FW_FLAGS_USB, &fw_flags);4733			break;4734		case RTL_FW_PHY_START:4735			if (test_bit(FW_FLAGS_START, &fw_flags) ||4736			    test_bit(FW_FLAGS_NC, &fw_flags) ||4737			    test_bit(FW_FLAGS_NC1, &fw_flags) ||4738			    test_bit(FW_FLAGS_NC2, &fw_flags) ||4739			    test_bit(FW_FLAGS_UC2, &fw_flags) ||4740			    test_bit(FW_FLAGS_UC, &fw_flags) ||4741			    test_bit(FW_FLAGS_STOP, &fw_flags)) {4742				dev_err(&tp->intf->dev,4743					"check PHY_START fail\n");4744				goto fail;4745			}4746 4747			if (__le32_to_cpu(block->length) != sizeof(struct fw_phy_patch_key)) {4748				dev_err(&tp->intf->dev,4749					"Invalid length for PHY_START\n");4750				goto fail;4751			}4752			__set_bit(FW_FLAGS_START, &fw_flags);4753			break;4754		case RTL_FW_PHY_STOP:4755			if (test_bit(FW_FLAGS_STOP, &fw_flags) ||4756			    !test_bit(FW_FLAGS_START, &fw_flags)) {4757				dev_err(&tp->intf->dev,4758					"Check PHY_STOP fail\n");4759				goto fail;4760			}4761 4762			if (__le32_to_cpu(block->length) != sizeof(*block)) {4763				dev_err(&tp->intf->dev,4764					"Invalid length for PHY_STOP\n");4765				goto fail;4766			}4767			__set_bit(FW_FLAGS_STOP, &fw_flags);4768			break;4769		case RTL_FW_PHY_NC:4770			if (!test_bit(FW_FLAGS_START, &fw_flags) ||4771			    test_bit(FW_FLAGS_STOP, &fw_flags)) {4772				dev_err(&tp->intf->dev,4773					"check PHY_NC fail\n");4774				goto fail;4775			}4776 4777			if (test_bit(FW_FLAGS_NC, &fw_flags)) {4778				dev_err(&tp->intf->dev,4779					"multiple PHY NC encountered\n");4780				goto fail;4781			}4782 4783			if (!rtl8152_is_fw_phy_nc_ok(tp, (struct fw_phy_nc *)block)) {4784				dev_err(&tp->intf->dev,4785					"check PHY NC firmware failed\n");4786				goto fail;4787			}4788			__set_bit(FW_FLAGS_NC, &fw_flags);4789			break;4790		case RTL_FW_PHY_UNION_NC:4791			if (!test_bit(FW_FLAGS_START, &fw_flags) ||4792			    test_bit(FW_FLAGS_NC1, &fw_flags) ||4793			    test_bit(FW_FLAGS_NC2, &fw_flags) ||4794			    test_bit(FW_FLAGS_UC2, &fw_flags) ||4795			    test_bit(FW_FLAGS_UC, &fw_flags) ||4796			    test_bit(FW_FLAGS_STOP, &fw_flags)) {4797				dev_err(&tp->intf->dev, "PHY_UNION_NC out of order\n");4798				goto fail;4799			}4800 4801			if (test_bit(FW_FLAGS_NC, &fw_flags)) {4802				dev_err(&tp->intf->dev, "multiple PHY_UNION_NC encountered\n");4803				goto fail;4804			}4805 4806			if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {4807				dev_err(&tp->intf->dev, "check PHY_UNION_NC failed\n");4808				goto fail;4809			}4810			__set_bit(FW_FLAGS_NC, &fw_flags);4811			break;4812		case RTL_FW_PHY_UNION_NC1:4813			if (!test_bit(FW_FLAGS_START, &fw_flags) ||4814			    test_bit(FW_FLAGS_NC2, &fw_flags) ||4815			    test_bit(FW_FLAGS_UC2, &fw_flags) ||4816			    test_bit(FW_FLAGS_UC, &fw_flags) ||4817			    test_bit(FW_FLAGS_STOP, &fw_flags)) {4818				dev_err(&tp->intf->dev, "PHY_UNION_NC1 out of order\n");4819				goto fail;4820			}4821 4822			if (test_bit(FW_FLAGS_NC1, &fw_flags)) {4823				dev_err(&tp->intf->dev, "multiple PHY NC1 encountered\n");4824				goto fail;4825			}4826 4827			if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {4828				dev_err(&tp->intf->dev, "check PHY_UNION_NC1 failed\n");4829				goto fail;4830			}4831			__set_bit(FW_FLAGS_NC1, &fw_flags);4832			break;4833		case RTL_FW_PHY_UNION_NC2:4834			if (!test_bit(FW_FLAGS_START, &fw_flags) ||4835			    test_bit(FW_FLAGS_UC2, &fw_flags) ||4836			    test_bit(FW_FLAGS_UC, &fw_flags) ||4837			    test_bit(FW_FLAGS_STOP, &fw_flags)) {4838				dev_err(&tp->intf->dev, "PHY_UNION_NC2 out of order\n");4839				goto fail;4840			}4841 4842			if (test_bit(FW_FLAGS_NC2, &fw_flags)) {4843				dev_err(&tp->intf->dev, "multiple PHY NC2 encountered\n");4844				goto fail;4845			}4846 4847			if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {4848				dev_err(&tp->intf->dev, "check PHY_UNION_NC2 failed\n");4849				goto fail;4850			}4851			__set_bit(FW_FLAGS_NC2, &fw_flags);4852			break;4853		case RTL_FW_PHY_UNION_UC2:4854			if (!test_bit(FW_FLAGS_START, &fw_flags) ||4855			    test_bit(FW_FLAGS_UC, &fw_flags) ||4856			    test_bit(FW_FLAGS_STOP, &fw_flags)) {4857				dev_err(&tp->intf->dev, "PHY_UNION_UC2 out of order\n");4858				goto fail;4859			}4860 4861			if (test_bit(FW_FLAGS_UC2, &fw_flags)) {4862				dev_err(&tp->intf->dev, "multiple PHY UC2 encountered\n");4863				goto fail;4864			}4865 4866			if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {4867				dev_err(&tp->intf->dev, "check PHY_UNION_UC2 failed\n");4868				goto fail;4869			}4870			__set_bit(FW_FLAGS_UC2, &fw_flags);4871			break;4872		case RTL_FW_PHY_UNION_UC:4873			if (!test_bit(FW_FLAGS_START, &fw_flags) ||4874			    test_bit(FW_FLAGS_STOP, &fw_flags)) {4875				dev_err(&tp->intf->dev, "PHY_UNION_UC out of order\n");4876				goto fail;4877			}4878 4879			if (test_bit(FW_FLAGS_UC, &fw_flags)) {4880				dev_err(&tp->intf->dev, "multiple PHY UC encountered\n");4881				goto fail;4882			}4883 4884			if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {4885				dev_err(&tp->intf->dev, "check PHY_UNION_UC failed\n");4886				goto fail;4887			}4888			__set_bit(FW_FLAGS_UC, &fw_flags);4889			break;4890		case RTL_FW_PHY_UNION_MISC:4891			if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {4892				dev_err(&tp->intf->dev, "check RTL_FW_PHY_UNION_MISC failed\n");4893				goto fail;4894			}4895			break;4896		case RTL_FW_PHY_FIXUP:4897			if (!rtl8152_is_fw_phy_fixup_ok(tp, (struct fw_phy_fixup *)block)) {4898				dev_err(&tp->intf->dev, "check PHY fixup failed\n");4899				goto fail;4900			}4901			break;4902		case RTL_FW_PHY_SPEED_UP:4903			if (test_bit(FW_FLAGS_SPEED_UP, &fw_flags)) {4904				dev_err(&tp->intf->dev, "multiple PHY firmware encountered");4905				goto fail;4906			}4907 4908			if (!rtl8152_is_fw_phy_speed_up_ok(tp, (struct fw_phy_speed_up *)block)) {4909				dev_err(&tp->intf->dev, "check PHY speed up failed\n");4910				goto fail;4911			}4912			__set_bit(FW_FLAGS_SPEED_UP, &fw_flags);4913			break;4914		case RTL_FW_PHY_VER:4915			if (test_bit(FW_FLAGS_START, &fw_flags) ||4916			    test_bit(FW_FLAGS_NC, &fw_flags) ||4917			    test_bit(FW_FLAGS_NC1, &fw_flags) ||4918			    test_bit(FW_FLAGS_NC2, &fw_flags) ||4919			    test_bit(FW_FLAGS_UC2, &fw_flags) ||4920			    test_bit(FW_FLAGS_UC, &fw_flags) ||4921			    test_bit(FW_FLAGS_STOP, &fw_flags)) {4922				dev_err(&tp->intf->dev, "Invalid order to set PHY version\n");4923				goto fail;4924			}4925 4926			if (test_bit(FW_FLAGS_VER, &fw_flags)) {4927				dev_err(&tp->intf->dev, "multiple PHY version encountered");4928				goto fail;4929			}4930 4931			if (!rtl8152_is_fw_phy_ver_ok(tp, (struct fw_phy_ver *)block)) {4932				dev_err(&tp->intf->dev, "check PHY version failed\n");4933				goto fail;4934			}4935			__set_bit(FW_FLAGS_VER, &fw_flags);4936			break;4937		default:4938			dev_warn(&tp->intf->dev, "Unknown type %u is found\n",4939				 type);4940			break;4941		}4942 4943		/* next block */4944		i += ALIGN(__le32_to_cpu(block->length), 8);4945	}4946 4947fw_end:4948	if (test_bit(FW_FLAGS_START, &fw_flags) && !test_bit(FW_FLAGS_STOP, &fw_flags)) {4949		dev_err(&tp->intf->dev, "without PHY_STOP\n");4950		goto fail;4951	}4952 4953	return 0;4954fail:4955	return ret;4956}4957 4958static void rtl_ram_code_speed_up(struct r8152 *tp, struct fw_phy_speed_up *phy, bool wait)4959{4960	u32 len;4961	u8 *data;4962 4963	rtl_reset_ocp_base(tp);4964 4965	if (sram_read(tp, SRAM_GPHY_FW_VER) >= __le16_to_cpu(phy->version)) {4966		dev_dbg(&tp->intf->dev, "PHY firmware has been the newest\n");4967		return;4968	}4969 4970	len = __le32_to_cpu(phy->blk_hdr.length);4971	len -= __le16_to_cpu(phy->fw_offset);4972	data = (u8 *)phy + __le16_to_cpu(phy->fw_offset);4973 4974	if (rtl_phy_patch_request(tp, true, wait))4975		return;4976 4977	while (len) {4978		u32 ocp_data, size;4979		int i;4980 4981		if (len < 2048)4982			size = len;4983		else4984			size = 2048;4985 4986		ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL);4987		ocp_data |= GPHY_PATCH_DONE | BACKUP_RESTRORE;4988		ocp_write_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL, ocp_data);4989 4990		generic_ocp_write(tp, __le16_to_cpu(phy->fw_reg), 0xff, size, data, MCU_TYPE_USB);4991 4992		data += size;4993		len -= size;4994 4995		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL);4996		ocp_data |= POL_GPHY_PATCH;4997		ocp_write_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL, ocp_data);4998 4999		for (i = 0; i < 1000; i++) {5000			if (!(ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL) & POL_GPHY_PATCH))5001				break;5002		}5003 5004		if (i == 1000) {5005			dev_err(&tp->intf->dev, "ram code speedup mode timeout\n");5006			break;5007		}5008	}5009 5010	rtl_reset_ocp_base(tp);5011 5012	rtl_phy_patch_request(tp, false, wait);5013 5014	if (sram_read(tp, SRAM_GPHY_FW_VER) == __le16_to_cpu(phy->version))5015		dev_dbg(&tp->intf->dev, "successfully applied %s\n", phy->info);5016	else5017		dev_err(&tp->intf->dev, "ram code speedup mode fail\n");5018}5019 5020static int rtl8152_fw_phy_ver(struct r8152 *tp, struct fw_phy_ver *phy_ver)5021{5022	u16 ver_addr, ver;5023 5024	ver_addr = __le16_to_cpu(phy_ver->ver.addr);5025	ver = __le16_to_cpu(phy_ver->ver.data);5026 5027	rtl_reset_ocp_base(tp);5028 5029	if (sram_read(tp, ver_addr) >= ver) {5030		dev_dbg(&tp->intf->dev, "PHY firmware has been the newest\n");5031		return 0;5032	}5033 5034	sram_write(tp, ver_addr, ver);5035 5036	dev_dbg(&tp->intf->dev, "PHY firmware version %x\n", ver);5037 5038	return ver;5039}5040 5041static void rtl8152_fw_phy_fixup(struct r8152 *tp, struct fw_phy_fixup *fix)5042{5043	u16 addr, data;5044 5045	rtl_reset_ocp_base(tp);5046 5047	addr = __le16_to_cpu(fix->setting.addr);5048	data = ocp_reg_read(tp, addr);5049 5050	switch (__le16_to_cpu(fix->bit_cmd)) {5051	case FW_FIXUP_AND:5052		data &= __le16_to_cpu(fix->setting.data);5053		break;5054	case FW_FIXUP_OR:5055		data |= __le16_to_cpu(fix->setting.data);5056		break;5057	case FW_FIXUP_NOT:5058		data &= ~__le16_to_cpu(fix->setting.data);5059		break;5060	case FW_FIXUP_XOR:5061		data ^= __le16_to_cpu(fix->setting.data);5062		break;5063	default:5064		return;5065	}5066 5067	ocp_reg_write(tp, addr, data);5068 5069	dev_dbg(&tp->intf->dev, "applied ocp %x %x\n", addr, data);5070}5071 5072static void rtl8152_fw_phy_union_apply(struct r8152 *tp, struct fw_phy_union *phy)5073{5074	__le16 *data;5075	u32 length;5076	int i, num;5077 5078	rtl_reset_ocp_base(tp);5079 5080	num = phy->pre_num;5081	for (i = 0; i < num; i++)5082		sram_write(tp, __le16_to_cpu(phy->pre_set[i].addr),5083			   __le16_to_cpu(phy->pre_set[i].data));5084 5085	length = __le32_to_cpu(phy->blk_hdr.length);5086	length -= __le16_to_cpu(phy->fw_offset);5087	num = length / 2;5088	data = (__le16 *)((u8 *)phy + __le16_to_cpu(phy->fw_offset));5089 5090	ocp_reg_write(tp, OCP_SRAM_ADDR, __le16_to_cpu(phy->fw_reg));5091	for (i = 0; i < num; i++)5092		ocp_reg_write(tp, OCP_SRAM_DATA, __le16_to_cpu(data[i]));5093 5094	num = phy->bp_num;5095	for (i = 0; i < num; i++)5096		sram_write(tp, __le16_to_cpu(phy->bp[i].addr), __le16_to_cpu(phy->bp[i].data));5097 5098	if (phy->bp_num && phy->bp_en.addr)5099		sram_write(tp, __le16_to_cpu(phy->bp_en.addr), __le16_to_cpu(phy->bp_en.data));5100 5101	dev_dbg(&tp->intf->dev, "successfully applied %s\n", phy->info);5102}5103 5104static void rtl8152_fw_phy_nc_apply(struct r8152 *tp, struct fw_phy_nc *phy)5105{5106	u16 mode_reg, bp_index;5107	u32 length, i, num;5108	__le16 *data;5109 5110	rtl_reset_ocp_base(tp);5111 5112	mode_reg = __le16_to_cpu(phy->mode_reg);5113	sram_write(tp, mode_reg, __le16_to_cpu(phy->mode_pre));5114	sram_write(tp, __le16_to_cpu(phy->ba_reg),5115		   __le16_to_cpu(phy->ba_data));5116 5117	length = __le32_to_cpu(phy->blk_hdr.length);5118	length -= __le16_to_cpu(phy->fw_offset);5119	num = length / 2;5120	data = (__le16 *)((u8 *)phy + __le16_to_cpu(phy->fw_offset));5121 5122	ocp_reg_write(tp, OCP_SRAM_ADDR, __le16_to_cpu(phy->fw_reg));5123	for (i = 0; i < num; i++)5124		ocp_reg_write(tp, OCP_SRAM_DATA, __le16_to_cpu(data[i]));5125 5126	sram_write(tp, __le16_to_cpu(phy->patch_en_addr),5127		   __le16_to_cpu(phy->patch_en_value));5128 5129	bp_index = __le16_to_cpu(phy->bp_start);5130	num = __le16_to_cpu(phy->bp_num);5131	for (i = 0; i < num; i++) {5132		sram_write(tp, bp_index, __le16_to_cpu(phy->bp[i]));5133		bp_index += 2;5134	}5135 5136	sram_write(tp, mode_reg, __le16_to_cpu(phy->mode_post));5137 5138	dev_dbg(&tp->intf->dev, "successfully applied %s\n", phy->info);5139}5140 5141static void rtl8152_fw_mac_apply(struct r8152 *tp, struct fw_mac *mac)5142{5143	u16 bp_en_addr, type, fw_ver_reg;5144	u32 length;5145	u8 *data;5146 5147	switch (__le32_to_cpu(mac->blk_hdr.type)) {5148	case RTL_FW_PLA:5149		type = MCU_TYPE_PLA;5150		break;5151	case RTL_FW_USB:5152		type = MCU_TYPE_USB;5153		break;5154	default:5155		return;5156	}5157 5158	fw_ver_reg = __le16_to_cpu(mac->fw_ver_reg);5159	if (fw_ver_reg && ocp_read_byte(tp, MCU_TYPE_USB, fw_ver_reg) >= mac->fw_ver_data) {5160		dev_dbg(&tp->intf->dev, "%s firmware has been the newest\n", type ? "PLA" : "USB");5161		return;5162	}5163 5164	rtl_clear_bp(tp, type);5165 5166	/* Enable backup/restore of MACDBG. This is required after clearing PLA5167	 * break points and before applying the PLA firmware.5168	 */5169	if (tp->version == RTL_VER_04 && type == MCU_TYPE_PLA &&5170	    !(ocp_read_word(tp, MCU_TYPE_PLA, PLA_MACDBG_POST) & DEBUG_OE)) {5171		ocp_write_word(tp, MCU_TYPE_PLA, PLA_MACDBG_PRE, DEBUG_LTSSM);5172		ocp_write_word(tp, MCU_TYPE_PLA, PLA_MACDBG_POST, DEBUG_LTSSM);5173	}5174 5175	length = __le32_to_cpu(mac->blk_hdr.length);5176	length -= __le16_to_cpu(mac->fw_offset);5177 5178	data = (u8 *)mac;5179	data += __le16_to_cpu(mac->fw_offset);5180 5181	if (generic_ocp_write(tp, __le16_to_cpu(mac->fw_reg), 0xff, length,5182			      data, type) < 0) {5183		dev_err(&tp->intf->dev, "Write %s fw fail\n",5184			type ? "PLA" : "USB");5185		return;5186	}5187 5188	ocp_write_word(tp, type, __le16_to_cpu(mac->bp_ba_addr),5189		       __le16_to_cpu(mac->bp_ba_value));5190 5191	if (generic_ocp_write(tp, __le16_to_cpu(mac->bp_start), BYTE_EN_DWORD,5192			      ALIGN(__le16_to_cpu(mac->bp_num) << 1, 4),5193			      mac->bp, type) < 0) {5194		dev_err(&tp->intf->dev, "Write %s bp fail\n",5195			type ? "PLA" : "USB");5196		return;5197	}5198 5199	bp_en_addr = __le16_to_cpu(mac->bp_en_addr);5200	if (bp_en_addr)5201		ocp_write_word(tp, type, bp_en_addr,5202			       __le16_to_cpu(mac->bp_en_value));5203 5204	if (fw_ver_reg)5205		ocp_write_byte(tp, MCU_TYPE_USB, fw_ver_reg,5206			       mac->fw_ver_data);5207 5208	dev_dbg(&tp->intf->dev, "successfully applied %s\n", mac->info);5209}5210 5211static void rtl8152_apply_firmware(struct r8152 *tp, bool power_cut)5212{5213	struct rtl_fw *rtl_fw = &tp->rtl_fw;5214	const struct firmware *fw;5215	struct fw_header *fw_hdr;5216	struct fw_phy_patch_key *key;5217	u16 key_addr = 0;5218	int i, patch_phy = 1;5219 5220	if (IS_ERR_OR_NULL(rtl_fw->fw))5221		return;5222 5223	fw = rtl_fw->fw;5224	fw_hdr = (struct fw_header *)fw->data;5225 5226	if (rtl_fw->pre_fw)5227		rtl_fw->pre_fw(tp);5228 5229	for (i = offsetof(struct fw_header, blocks); i < fw->size;) {5230		struct fw_block *block = (struct fw_block *)&fw->data[i];5231 5232		switch (__le32_to_cpu(block->type)) {5233		case RTL_FW_END:5234			goto post_fw;5235		case RTL_FW_PLA:5236		case RTL_FW_USB:5237			rtl8152_fw_mac_apply(tp, (struct fw_mac *)block);5238			break;5239		case RTL_FW_PHY_START:5240			if (!patch_phy)5241				break;5242			key = (struct fw_phy_patch_key *)block;5243			key_addr = __le16_to_cpu(key->key_reg);5244			rtl_pre_ram_code(tp, key_addr, __le16_to_cpu(key->key_data), !power_cut);5245			break;5246		case RTL_FW_PHY_STOP:5247			if (!patch_phy)5248				break;5249			WARN_ON(!key_addr);5250			rtl_post_ram_code(tp, key_addr, !power_cut);5251			break;5252		case RTL_FW_PHY_NC:5253			rtl8152_fw_phy_nc_apply(tp, (struct fw_phy_nc *)block);5254			break;5255		case RTL_FW_PHY_VER:5256			patch_phy = rtl8152_fw_phy_ver(tp, (struct fw_phy_ver *)block);5257			break;5258		case RTL_FW_PHY_UNION_NC:5259		case RTL_FW_PHY_UNION_NC1:5260		case RTL_FW_PHY_UNION_NC2:5261		case RTL_FW_PHY_UNION_UC2:5262		case RTL_FW_PHY_UNION_UC:5263		case RTL_FW_PHY_UNION_MISC:5264			if (patch_phy)5265				rtl8152_fw_phy_union_apply(tp, (struct fw_phy_union *)block);5266			break;5267		case RTL_FW_PHY_FIXUP:5268			if (patch_phy)5269				rtl8152_fw_phy_fixup(tp, (struct fw_phy_fixup *)block);5270			break;5271		case RTL_FW_PHY_SPEED_UP:5272			rtl_ram_code_speed_up(tp, (struct fw_phy_speed_up *)block, !power_cut);5273			break;5274		default:5275			break;5276		}5277 5278		i += ALIGN(__le32_to_cpu(block->length), 8);5279	}5280 5281post_fw:5282	if (rtl_fw->post_fw)5283		rtl_fw->post_fw(tp);5284 5285	rtl_reset_ocp_base(tp);5286	strscpy(rtl_fw->version, fw_hdr->version, RTL_VER_SIZE);5287	dev_dbg(&tp->intf->dev, "load %s successfully\n", rtl_fw->version);5288}5289 5290static void rtl8152_release_firmware(struct r8152 *tp)5291{5292	struct rtl_fw *rtl_fw = &tp->rtl_fw;5293 5294	if (!IS_ERR_OR_NULL(rtl_fw->fw)) {5295		release_firmware(rtl_fw->fw);5296		rtl_fw->fw = NULL;5297	}5298}5299 5300static int rtl8152_request_firmware(struct r8152 *tp)5301{5302	struct rtl_fw *rtl_fw = &tp->rtl_fw;5303	long rc;5304 5305	if (rtl_fw->fw || !rtl_fw->fw_name) {5306		dev_info(&tp->intf->dev, "skip request firmware\n");5307		rc = 0;5308		goto result;5309	}5310 5311	rc = request_firmware(&rtl_fw->fw, rtl_fw->fw_name, &tp->intf->dev);5312	if (rc < 0)5313		goto result;5314 5315	rc = rtl8152_check_firmware(tp, rtl_fw);5316	if (rc < 0)5317		release_firmware(rtl_fw->fw);5318 5319result:5320	if (rc) {5321		rtl_fw->fw = ERR_PTR(rc);5322 5323		dev_warn(&tp->intf->dev,5324			 "unable to load firmware patch %s (%ld)\n",5325			 rtl_fw->fw_name, rc);5326	}5327 5328	return rc;5329}5330 5331static void r8152_aldps_en(struct r8152 *tp, bool enable)5332{5333	if (enable) {5334		ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |5335						    LINKENA | DIS_SDSAVE);5336	} else {5337		ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA |5338						    DIS_SDSAVE);5339		msleep(20);5340	}5341}5342 5343static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)5344{5345	ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);5346	ocp_reg_write(tp, OCP_EEE_DATA, reg);5347	ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);5348}5349 5350static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)5351{5352	u16 data;5353 5354	r8152_mmd_indirect(tp, dev, reg);5355	data = ocp_reg_read(tp, OCP_EEE_DATA);5356	ocp_reg_write(tp, OCP_EEE_AR, 0x0000);5357 5358	return data;5359}5360 5361static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)5362{5363	r8152_mmd_indirect(tp, dev, reg);5364	ocp_reg_write(tp, OCP_EEE_DATA, data);5365	ocp_reg_write(tp, OCP_EEE_AR, 0x0000);5366}5367 5368static void r8152_eee_en(struct r8152 *tp, bool enable)5369{5370	u16 config1, config2, config3;5371	u32 ocp_data;5372 5373	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);5374	config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;5375	config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);5376	config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;5377 5378	if (enable) {5379		ocp_data |= EEE_RX_EN | EEE_TX_EN;5380		config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;5381		config1 |= sd_rise_time(1);5382		config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;5383		config3 |= fast_snr(42);5384	} else {5385		ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);5386		config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |5387			     RX_QUIET_EN);5388		config1 |= sd_rise_time(7);5389		config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);5390		config3 |= fast_snr(511);5391	}5392 5393	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);5394	ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);5395	ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);5396	ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);5397}5398 5399static void r8153_eee_en(struct r8152 *tp, bool enable)5400{5401	u32 ocp_data;5402	u16 config;5403 5404	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);5405	config = ocp_reg_read(tp, OCP_EEE_CFG);5406 5407	if (enable) {5408		ocp_data |= EEE_RX_EN | EEE_TX_EN;5409		config |= EEE10_EN;5410	} else {5411		ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);5412		config &= ~EEE10_EN;5413	}5414 5415	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);5416	ocp_reg_write(tp, OCP_EEE_CFG, config);5417 5418	tp->ups_info.eee = enable;5419}5420 5421static void r8156_eee_en(struct r8152 *tp, bool enable)5422{5423	u16 config;5424 5425	r8153_eee_en(tp, enable);5426 5427	config = ocp_reg_read(tp, OCP_EEE_ADV2);5428 5429	if (enable)5430		config |= MDIO_EEE_2_5GT;5431	else5432		config &= ~MDIO_EEE_2_5GT;5433 5434	ocp_reg_write(tp, OCP_EEE_ADV2, config);5435}5436 5437static void rtl_eee_enable(struct r8152 *tp, bool enable)5438{5439	switch (tp->version) {5440	case RTL_VER_01:5441	case RTL_VER_02:5442	case RTL_VER_07:5443		if (enable) {5444			r8152_eee_en(tp, true);5445			r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV,5446					tp->eee_adv);5447		} else {5448			r8152_eee_en(tp, false);5449			r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0);5450		}5451		break;5452	case RTL_VER_03:5453	case RTL_VER_04:5454	case RTL_VER_05:5455	case RTL_VER_06:5456	case RTL_VER_08:5457	case RTL_VER_09:5458	case RTL_VER_14:5459		if (enable) {5460			r8153_eee_en(tp, true);5461			ocp_reg_write(tp, OCP_EEE_ADV, tp->eee_adv);5462		} else {5463			r8153_eee_en(tp, false);5464			ocp_reg_write(tp, OCP_EEE_ADV, 0);5465		}5466		break;5467	case RTL_VER_10:5468	case RTL_VER_11:5469	case RTL_VER_12:5470	case RTL_VER_13:5471	case RTL_VER_15:5472		if (enable) {5473			r8156_eee_en(tp, true);5474			ocp_reg_write(tp, OCP_EEE_ADV, tp->eee_adv);5475		} else {5476			r8156_eee_en(tp, false);5477			ocp_reg_write(tp, OCP_EEE_ADV, 0);5478		}5479		break;5480	default:5481		break;5482	}5483}5484 5485static void r8152b_enable_fc(struct r8152 *tp)5486{5487	u16 anar;5488 5489	anar = r8152_mdio_read(tp, MII_ADVERTISE);5490	anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;5491	r8152_mdio_write(tp, MII_ADVERTISE, anar);5492 5493	tp->ups_info.flow_control = true;5494}5495 5496static void rtl8152_disable(struct r8152 *tp)5497{5498	r8152_aldps_en(tp, false);5499	rtl_disable(tp);5500	r8152_aldps_en(tp, true);5501}5502 5503static void r8152b_hw_phy_cfg(struct r8152 *tp)5504{5505	rtl8152_apply_firmware(tp, false);5506	rtl_eee_enable(tp, tp->eee_en);5507	r8152_aldps_en(tp, true);5508	r8152b_enable_fc(tp);5509 5510	set_bit(PHY_RESET, &tp->flags);5511}5512 5513static void wait_oob_link_list_ready(struct r8152 *tp)5514{5515	u32 ocp_data;5516	int i;5517 5518	for (i = 0; i < 1000; i++) {5519		if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))5520			break;5521		ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);5522		if (ocp_data & LINK_LIST_READY)5523			break;5524		usleep_range(1000, 2000);5525	}5526}5527 5528static void r8156b_wait_loading_flash(struct r8152 *tp)5529{5530	if ((ocp_read_word(tp, MCU_TYPE_PLA, PLA_GPHY_CTRL) & GPHY_FLASH) &&5531	    !(ocp_read_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL) & BYPASS_FLASH)) {5532		int i;5533 5534		for (i = 0; i < 100; i++) {5535			if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))5536				break;5537			if (ocp_read_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL) & GPHY_PATCH_DONE)5538				break;5539			usleep_range(1000, 2000);5540		}5541	}5542}5543 5544static void r8152b_exit_oob(struct r8152 *tp)5545{5546	u32 ocp_data;5547 5548	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);5549	ocp_data &= ~RCR_ACPT_ALL;5550	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);5551 5552	rxdy_gated_en(tp, true);5553	r8153_teredo_off(tp);5554	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);5555	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);5556 5557	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);5558	ocp_data &= ~NOW_IS_OOB;5559	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);5560 5561	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);5562	ocp_data &= ~MCU_BORW_EN;5563	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);5564 5565	wait_oob_link_list_ready(tp);5566 5567	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);5568	ocp_data |= RE_INIT_LL;5569	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);5570 5571	wait_oob_link_list_ready(tp);5572 5573	rtl8152_nic_reset(tp);5574 5575	/* rx share fifo credit full threshold */5576	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);5577 5578	if (tp->udev->speed == USB_SPEED_FULL ||5579	    tp->udev->speed == USB_SPEED_LOW) {5580		/* rx share fifo credit near full threshold */5581		ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,5582				RXFIFO_THR2_FULL);5583		ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,5584				RXFIFO_THR3_FULL);5585	} else {5586		/* rx share fifo credit near full threshold */5587		ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,5588				RXFIFO_THR2_HIGH);5589		ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,5590				RXFIFO_THR3_HIGH);5591	}5592 5593	/* TX share fifo free credit full threshold */5594	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);5595 5596	ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);5597	ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);5598	ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,5599			TEST_MODE_DISABLE | TX_SIZE_ADJUST1);5600 5601	rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);5602 5603	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);5604 5605	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);5606	ocp_data |= TCR0_AUTO_FIFO;5607	ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);5608}5609 5610static void r8152b_enter_oob(struct r8152 *tp)5611{5612	u32 ocp_data;5613 5614	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);5615	ocp_data &= ~NOW_IS_OOB;5616	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);5617 5618	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);5619	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);5620	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);5621 5622	rtl_disable(tp);5623 5624	wait_oob_link_list_ready(tp);5625 5626	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);5627	ocp_data |= RE_INIT_LL;5628	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);5629 5630	wait_oob_link_list_ready(tp);5631 5632	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);5633 5634	rtl_rx_vlan_en(tp, true);5635 5636	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR);5637	ocp_data |= ALDPS_PROXY_MODE;5638	ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data);5639 5640	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);5641	ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;5642	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);5643 5644	rxdy_gated_en(tp, false);5645 5646	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);5647	ocp_data |= RCR_APM | RCR_AM | RCR_AB;5648	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);5649}5650 5651static int r8153_pre_firmware_1(struct r8152 *tp)5652{5653	int i;5654 5655	/* Wait till the WTD timer is ready. It would take at most 104 ms. */5656	for (i = 0; i < 104; i++) {5657		u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_WDT1_CTRL);5658 5659		if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))5660			return -ENODEV;5661		if (!(ocp_data & WTD1_EN))5662			break;5663		usleep_range(1000, 2000);5664	}5665 5666	return 0;5667}5668 5669static int r8153_post_firmware_1(struct r8152 *tp)5670{5671	/* set USB_BP_4 to support USB_SPEED_SUPER only */5672	if (ocp_read_byte(tp, MCU_TYPE_USB, USB_CSTMR) & FORCE_SUPER)5673		ocp_write_word(tp, MCU_TYPE_USB, USB_BP_4, BP4_SUPER_ONLY);5674 5675	/* reset UPHY timer to 36 ms */5676	ocp_write_word(tp, MCU_TYPE_PLA, PLA_UPHY_TIMER, 36000 / 16);5677 5678	return 0;5679}5680 5681static int r8153_pre_firmware_2(struct r8152 *tp)5682{5683	u32 ocp_data;5684 5685	r8153_pre_firmware_1(tp);5686 5687	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0);5688	ocp_data &= ~FW_FIX_SUSPEND;5689	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0, ocp_data);5690 5691	return 0;5692}5693 5694static int r8153_post_firmware_2(struct r8152 *tp)5695{5696	u32 ocp_data;5697 5698	/* enable bp0 if support USB_SPEED_SUPER only */5699	if (ocp_read_byte(tp, MCU_TYPE_USB, USB_CSTMR) & FORCE_SUPER) {5700		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BP_EN);5701		ocp_data |= BIT(0);5702		ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, ocp_data);5703	}5704 5705	/* reset UPHY timer to 36 ms */5706	ocp_write_word(tp, MCU_TYPE_PLA, PLA_UPHY_TIMER, 36000 / 16);5707 5708	/* enable U3P3 check, set the counter to 4 */5709	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, U3P3_CHECK_EN | 4);5710 5711	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0);5712	ocp_data |= FW_FIX_SUSPEND;5713	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0, ocp_data);5714 5715	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);5716	ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;5717	ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);5718 5719	return 0;5720}5721 5722static int r8153_post_firmware_3(struct r8152 *tp)5723{5724	u32 ocp_data;5725 5726	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);5727	ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;5728	ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);5729 5730	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1);5731	ocp_data |= FW_IP_RESET_EN;5732	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data);5733 5734	return 0;5735}5736 5737static int r8153b_pre_firmware_1(struct r8152 *tp)5738{5739	/* enable fc timer and set timer to 1 second. */5740	ocp_write_word(tp, MCU_TYPE_USB, USB_FC_TIMER,5741		       CTRL_TIMER_EN | (1000 / 8));5742 5743	return 0;5744}5745 5746static int r8153b_post_firmware_1(struct r8152 *tp)5747{5748	u32 ocp_data;5749 5750	/* enable bp0 for RTL8153-BND */5751	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1);5752	if (ocp_data & BND_MASK) {5753		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BP_EN);5754		ocp_data |= BIT(0);5755		ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, ocp_data);5756	}5757 5758	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL);5759	ocp_data |= FLOW_CTRL_PATCH_OPT;5760	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data);5761 5762	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);5763	ocp_data |= FC_PATCH_TASK;5764	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);5765 5766	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1);5767	ocp_data |= FW_IP_RESET_EN;5768	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data);5769 5770	return 0;5771}5772 5773static int r8153c_post_firmware_1(struct r8152 *tp)5774{5775	u32 ocp_data;5776 5777	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL);5778	ocp_data |= FLOW_CTRL_PATCH_2;5779	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data);5780 5781	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);5782	ocp_data |= FC_PATCH_TASK;5783	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);5784 5785	return 0;5786}5787 5788static int r8156a_post_firmware_1(struct r8152 *tp)5789{5790	u32 ocp_data;5791 5792	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1);5793	ocp_data |= FW_IP_RESET_EN;5794	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data);5795 5796	/* Modify U3PHY parameter for compatibility issue */5797	ocp_write_dword(tp, MCU_TYPE_USB, USB_UPHY3_MDCMDIO, 0x4026840e);5798	ocp_write_dword(tp, MCU_TYPE_USB, USB_UPHY3_MDCMDIO, 0x4001acc9);5799 5800	return 0;5801}5802 5803static void r8153_aldps_en(struct r8152 *tp, bool enable)5804{5805	u16 data;5806 5807	data = ocp_reg_read(tp, OCP_POWER_CFG);5808	if (enable) {5809		data |= EN_ALDPS;5810		ocp_reg_write(tp, OCP_POWER_CFG, data);5811	} else {5812		int i;5813 5814		data &= ~EN_ALDPS;5815		ocp_reg_write(tp, OCP_POWER_CFG, data);5816		for (i = 0; i < 20; i++) {5817			if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))5818				return;5819			usleep_range(1000, 2000);5820			if (ocp_read_word(tp, MCU_TYPE_PLA, 0xe000) & 0x0100)5821				break;5822		}5823	}5824 5825	tp->ups_info.aldps = enable;5826}5827 5828static void r8153_hw_phy_cfg(struct r8152 *tp)5829{5830	u32 ocp_data;5831	u16 data;5832 5833	/* disable ALDPS before updating the PHY parameters */5834	r8153_aldps_en(tp, false);5835 5836	/* disable EEE before updating the PHY parameters */5837	rtl_eee_enable(tp, false);5838 5839	rtl8152_apply_firmware(tp, false);5840 5841	if (tp->version == RTL_VER_03) {5842		data = ocp_reg_read(tp, OCP_EEE_CFG);5843		data &= ~CTAP_SHORT_EN;5844		ocp_reg_write(tp, OCP_EEE_CFG, data);5845	}5846 5847	data = ocp_reg_read(tp, OCP_POWER_CFG);5848	data |= EEE_CLKDIV_EN;5849	ocp_reg_write(tp, OCP_POWER_CFG, data);5850 5851	data = ocp_reg_read(tp, OCP_DOWN_SPEED);5852	data |= EN_10M_BGOFF;5853	ocp_reg_write(tp, OCP_DOWN_SPEED, data);5854	data = ocp_reg_read(tp, OCP_POWER_CFG);5855	data |= EN_10M_PLLOFF;5856	ocp_reg_write(tp, OCP_POWER_CFG, data);5857	sram_write(tp, SRAM_IMPEDANCE, 0x0b13);5858 5859	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);5860	ocp_data |= PFM_PWM_SWITCH;5861	ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);5862 5863	/* Enable LPF corner auto tune */5864	sram_write(tp, SRAM_LPF_CFG, 0xf70f);5865 5866	/* Adjust 10M Amplitude */5867	sram_write(tp, SRAM_10M_AMP1, 0x00af);5868	sram_write(tp, SRAM_10M_AMP2, 0x0208);5869 5870	if (tp->eee_en)5871		rtl_eee_enable(tp, true);5872 5873	r8153_aldps_en(tp, true);5874	r8152b_enable_fc(tp);5875 5876	switch (tp->version) {5877	case RTL_VER_03:5878	case RTL_VER_04:5879		break;5880	case RTL_VER_05:5881	case RTL_VER_06:5882	default:5883		r8153_u2p3en(tp, true);5884		break;5885	}5886 5887	set_bit(PHY_RESET, &tp->flags);5888}5889 5890static u32 r8152_efuse_read(struct r8152 *tp, u8 addr)5891{5892	u32 ocp_data;5893 5894	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD, EFUSE_READ_CMD | addr);5895	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD);5896	ocp_data = (ocp_data & EFUSE_DATA_BIT16) << 9;	/* data of bit16 */5897	ocp_data |= ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_DATA);5898 5899	return ocp_data;5900}5901 5902static void r8153b_hw_phy_cfg(struct r8152 *tp)5903{5904	u32 ocp_data;5905	u16 data;5906 5907	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);5908	if (ocp_data & PCUT_STATUS) {5909		ocp_data &= ~PCUT_STATUS;5910		ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);5911	}5912 5913	/* disable ALDPS before updating the PHY parameters */5914	r8153_aldps_en(tp, false);5915 5916	/* disable EEE before updating the PHY parameters */5917	rtl_eee_enable(tp, false);5918 5919	/* U1/U2/L1 idle timer. 500 us */5920	ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500);5921 5922	data = r8153_phy_status(tp, 0);5923 5924	switch (data) {5925	case PHY_STAT_PWRDN:5926	case PHY_STAT_EXT_INIT:5927		rtl8152_apply_firmware(tp, true);5928 5929		data = r8152_mdio_read(tp, MII_BMCR);5930		data &= ~BMCR_PDOWN;5931		r8152_mdio_write(tp, MII_BMCR, data);5932		break;5933	case PHY_STAT_LAN_ON:5934	default:5935		rtl8152_apply_firmware(tp, false);5936		break;5937	}5938 5939	r8153b_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));5940 5941	data = sram_read(tp, SRAM_GREEN_CFG);5942	data |= R_TUNE_EN;5943	sram_write(tp, SRAM_GREEN_CFG, data);5944	data = ocp_reg_read(tp, OCP_NCTL_CFG);5945	data |= PGA_RETURN_EN;5946	ocp_reg_write(tp, OCP_NCTL_CFG, data);5947 5948	/* ADC Bias Calibration:5949	 * read efuse offset 0x7d to get a 17-bit data. Remove the dummy/fake5950	 * bit (bit3) to rebuild the real 16-bit data. Write the data to the5951	 * ADC ioffset.5952	 */5953	ocp_data = r8152_efuse_read(tp, 0x7d);5954	data = (u16)(((ocp_data & 0x1fff0) >> 1) | (ocp_data & 0x7));5955	if (data != 0xffff)5956		ocp_reg_write(tp, OCP_ADC_IOFFSET, data);5957 5958	/* ups mode tx-link-pulse timing adjustment:5959	 * rg_saw_cnt = OCP reg 0xC426 Bit[13:0]5960	 * swr_cnt_1ms_ini = 16000000 / rg_saw_cnt5961	 */5962	ocp_data = ocp_reg_read(tp, 0xc426);5963	ocp_data &= 0x3fff;5964	if (ocp_data) {5965		u32 swr_cnt_1ms_ini;5966 5967		swr_cnt_1ms_ini = (16000000 / ocp_data) & SAW_CNT_1MS_MASK;5968		ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG);5969		ocp_data = (ocp_data & ~SAW_CNT_1MS_MASK) | swr_cnt_1ms_ini;5970		ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CFG, ocp_data);5971	}5972 5973	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);5974	ocp_data |= PFM_PWM_SWITCH;5975	ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);5976 5977	/* Advnace EEE */5978	if (!rtl_phy_patch_request(tp, true, true)) {5979		data = ocp_reg_read(tp, OCP_POWER_CFG);5980		data |= EEE_CLKDIV_EN;5981		ocp_reg_write(tp, OCP_POWER_CFG, data);5982		tp->ups_info.eee_ckdiv = true;5983 5984		data = ocp_reg_read(tp, OCP_DOWN_SPEED);5985		data |= EN_EEE_CMODE | EN_EEE_1000 | EN_10M_CLKDIV;5986		ocp_reg_write(tp, OCP_DOWN_SPEED, data);5987		tp->ups_info.eee_cmod_lv = true;5988		tp->ups_info._10m_ckdiv = true;5989		tp->ups_info.eee_plloff_giga = true;5990 5991		ocp_reg_write(tp, OCP_SYSCLK_CFG, 0);5992		ocp_reg_write(tp, OCP_SYSCLK_CFG, clk_div_expo(5));5993		tp->ups_info._250m_ckdiv = true;5994 5995		rtl_phy_patch_request(tp, false, true);5996	}5997 5998	if (tp->eee_en)5999		rtl_eee_enable(tp, true);6000 6001	r8153_aldps_en(tp, true);6002	r8152b_enable_fc(tp);6003 6004	set_bit(PHY_RESET, &tp->flags);6005}6006 6007static void r8153c_hw_phy_cfg(struct r8152 *tp)6008{6009	r8153b_hw_phy_cfg(tp);6010 6011	tp->ups_info.r_tune = true;6012}6013 6014static void rtl8153_change_mtu(struct r8152 *tp)6015{6016	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, mtu_to_size(tp->netdev->mtu));6017	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);6018}6019 6020static void r8153_first_init(struct r8152 *tp)6021{6022	u32 ocp_data;6023 6024	rxdy_gated_en(tp, true);6025	r8153_teredo_off(tp);6026 6027	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);6028	ocp_data &= ~RCR_ACPT_ALL;6029	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);6030 6031	rtl8152_nic_reset(tp);6032	rtl_reset_bmu(tp);6033 6034	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);6035	ocp_data &= ~NOW_IS_OOB;6036	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);6037 6038	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);6039	ocp_data &= ~MCU_BORW_EN;6040	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);6041 6042	wait_oob_link_list_ready(tp);6043 6044	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);6045	ocp_data |= RE_INIT_LL;6046	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);6047 6048	wait_oob_link_list_ready(tp);6049 6050	rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);6051 6052	rtl8153_change_mtu(tp);6053 6054	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);6055	ocp_data |= TCR0_AUTO_FIFO;6056	ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);6057 6058	rtl8152_nic_reset(tp);6059 6060	/* rx share fifo credit full threshold */6061	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);6062	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);6063	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);6064	/* TX share fifo free credit full threshold */6065	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);6066}6067 6068static void r8153_enter_oob(struct r8152 *tp)6069{6070	u32 ocp_data;6071 6072	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);6073	ocp_data &= ~NOW_IS_OOB;6074	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);6075 6076	/* RX FIFO settings for OOB */6077	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);6078	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);6079	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);6080 6081	rtl_disable(tp);6082	rtl_reset_bmu(tp);6083 6084	wait_oob_link_list_ready(tp);6085 6086	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);6087	ocp_data |= RE_INIT_LL;6088	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);6089 6090	wait_oob_link_list_ready(tp);6091 6092	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, 1522);6093	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_DEFAULT);6094 6095	switch (tp->version) {6096	case RTL_VER_03:6097	case RTL_VER_04:6098	case RTL_VER_05:6099	case RTL_VER_06:6100		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);6101		ocp_data &= ~TEREDO_WAKE_MASK;6102		ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);6103		break;6104 6105	case RTL_VER_08:6106	case RTL_VER_09:6107	case RTL_VER_14:6108		/* Clear teredo wake event. bit[15:8] is the teredo wakeup6109		 * type. Set it to zero. bits[7:0] are the W1C bits about6110		 * the events. Set them to all 1 to clear them.6111		 */6112		ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff);6113		break;6114 6115	default:6116		break;6117	}6118 6119	rtl_rx_vlan_en(tp, true);6120 6121	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR);6122	ocp_data |= ALDPS_PROXY_MODE;6123	ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data);6124 6125	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);6126	ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;6127	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);6128 6129	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);6130	ocp_data |= MCU_BORW_EN;6131	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);6132 6133	rxdy_gated_en(tp, false);6134 6135	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);6136	ocp_data |= RCR_APM | RCR_AM | RCR_AB;6137	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);6138}6139 6140static void rtl8153_disable(struct r8152 *tp)6141{6142	r8153_aldps_en(tp, false);6143	rtl_disable(tp);6144	rtl_reset_bmu(tp);6145	r8153_aldps_en(tp, true);6146}6147 6148static u32 fc_pause_on_auto(struct r8152 *tp)6149{6150	return (ALIGN(mtu_to_size(tp->netdev->mtu), 1024) + 6 * 1024);6151}6152 6153static u32 fc_pause_off_auto(struct r8152 *tp)6154{6155	return (ALIGN(mtu_to_size(tp->netdev->mtu), 1024) + 14 * 1024);6156}6157 6158static void r8156_fc_parameter(struct r8152 *tp)6159{6160	u32 pause_on = tp->fc_pause_on ? tp->fc_pause_on : fc_pause_on_auto(tp);6161	u32 pause_off = tp->fc_pause_off ? tp->fc_pause_off : fc_pause_off_auto(tp);6162 6163	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_FULL, pause_on / 16);6164	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_EMPTY, pause_off / 16);6165}6166 6167static int rtl8156_enable(struct r8152 *tp)6168{6169	u32 ocp_data;6170	u16 speed;6171 6172	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))6173		return -ENODEV;6174 6175	r8156_fc_parameter(tp);6176	set_tx_qlen(tp);6177	rtl_set_eee_plus(tp);6178	r8153_set_rx_early_timeout(tp);6179	r8153_set_rx_early_size(tp);6180 6181	speed = rtl8152_get_speed(tp);6182	rtl_set_ifg(tp, speed);6183 6184	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);6185	if (speed & _2500bps)6186		ocp_data &= ~IDLE_SPDWN_EN;6187	else6188		ocp_data |= IDLE_SPDWN_EN;6189	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);6190 6191	if (speed & _1000bps)6192		ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS, 0x11);6193	else if (speed & _500bps)6194		ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS, 0x3d);6195 6196	if (tp->udev->speed == USB_SPEED_HIGH) {6197		/* USB 0xb45e[3:0] l1_nyet_hird */6198		ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_L1_CTRL);6199		ocp_data &= ~0xf;6200		if (is_flow_control(speed))6201			ocp_data |= 0xf;6202		else6203			ocp_data |= 0x1;6204		ocp_write_word(tp, MCU_TYPE_USB, USB_L1_CTRL, ocp_data);6205	}6206 6207	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);6208	ocp_data &= ~FC_PATCH_TASK;6209	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);6210	usleep_range(1000, 2000);6211	ocp_data |= FC_PATCH_TASK;6212	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);6213 6214	return rtl_enable(tp);6215}6216 6217static void rtl8156_disable(struct r8152 *tp)6218{6219	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_FULL, 0);6220	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_EMPTY, 0);6221 6222	rtl8153_disable(tp);6223}6224 6225static int rtl8156b_enable(struct r8152 *tp)6226{6227	u32 ocp_data;6228	u16 speed;6229 6230	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))6231		return -ENODEV;6232 6233	set_tx_qlen(tp);6234	rtl_set_eee_plus(tp);6235 6236	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_RX_AGGR_NUM);6237	ocp_data &= ~RX_AGGR_NUM_MASK;6238	ocp_write_word(tp, MCU_TYPE_USB, USB_RX_AGGR_NUM, ocp_data);6239 6240	r8153_set_rx_early_timeout(tp);6241	r8153_set_rx_early_size(tp);6242 6243	speed = rtl8152_get_speed(tp);6244	rtl_set_ifg(tp, speed);6245 6246	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);6247	if (speed & _2500bps)6248		ocp_data &= ~IDLE_SPDWN_EN;6249	else6250		ocp_data |= IDLE_SPDWN_EN;6251	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);6252 6253	if (tp->udev->speed == USB_SPEED_HIGH) {6254		ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_L1_CTRL);6255		ocp_data &= ~0xf;6256		if (is_flow_control(speed))6257			ocp_data |= 0xf;6258		else6259			ocp_data |= 0x1;6260		ocp_write_word(tp, MCU_TYPE_USB, USB_L1_CTRL, ocp_data);6261	}6262 6263	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);6264	ocp_data &= ~FC_PATCH_TASK;6265	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);6266	usleep_range(1000, 2000);6267	ocp_data |= FC_PATCH_TASK;6268	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);6269 6270	return rtl_enable(tp);6271}6272 6273static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u32 speed, u8 duplex,6274			     u32 advertising)6275{6276	u16 bmcr;6277	int ret = 0;6278 6279	if (autoneg == AUTONEG_DISABLE) {6280		if (duplex != DUPLEX_HALF && duplex != DUPLEX_FULL)6281			return -EINVAL;6282 6283		switch (speed) {6284		case SPEED_10:6285			bmcr = BMCR_SPEED10;6286			if (duplex == DUPLEX_FULL) {6287				bmcr |= BMCR_FULLDPLX;6288				tp->ups_info.speed_duplex = FORCE_10M_FULL;6289			} else {6290				tp->ups_info.speed_duplex = FORCE_10M_HALF;6291			}6292			break;6293		case SPEED_100:6294			bmcr = BMCR_SPEED100;6295			if (duplex == DUPLEX_FULL) {6296				bmcr |= BMCR_FULLDPLX;6297				tp->ups_info.speed_duplex = FORCE_100M_FULL;6298			} else {6299				tp->ups_info.speed_duplex = FORCE_100M_HALF;6300			}6301			break;6302		case SPEED_1000:6303			if (tp->mii.supports_gmii) {6304				bmcr = BMCR_SPEED1000 | BMCR_FULLDPLX;6305				tp->ups_info.speed_duplex = NWAY_1000M_FULL;6306				break;6307			}6308			fallthrough;6309		default:6310			ret = -EINVAL;6311			goto out;6312		}6313 6314		if (duplex == DUPLEX_FULL)6315			tp->mii.full_duplex = 1;6316		else6317			tp->mii.full_duplex = 0;6318 6319		tp->mii.force_media = 1;6320	} else {6321		u16 orig, new1;6322		u32 support;6323 6324		support = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL |6325			  RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL;6326 6327		if (tp->mii.supports_gmii) {6328			support |= RTL_ADVERTISED_1000_FULL;6329 6330			if (tp->support_2500full)6331				support |= RTL_ADVERTISED_2500_FULL;6332		}6333 6334		if (!(advertising & support))6335			return -EINVAL;6336 6337		orig = r8152_mdio_read(tp, MII_ADVERTISE);6338		new1 = orig & ~(ADVERTISE_10HALF | ADVERTISE_10FULL |6339				ADVERTISE_100HALF | ADVERTISE_100FULL);6340		if (advertising & RTL_ADVERTISED_10_HALF) {6341			new1 |= ADVERTISE_10HALF;6342			tp->ups_info.speed_duplex = NWAY_10M_HALF;6343		}6344		if (advertising & RTL_ADVERTISED_10_FULL) {6345			new1 |= ADVERTISE_10FULL;6346			tp->ups_info.speed_duplex = NWAY_10M_FULL;6347		}6348 6349		if (advertising & RTL_ADVERTISED_100_HALF) {6350			new1 |= ADVERTISE_100HALF;6351			tp->ups_info.speed_duplex = NWAY_100M_HALF;6352		}6353		if (advertising & RTL_ADVERTISED_100_FULL) {6354			new1 |= ADVERTISE_100FULL;6355			tp->ups_info.speed_duplex = NWAY_100M_FULL;6356		}6357 6358		if (orig != new1) {6359			r8152_mdio_write(tp, MII_ADVERTISE, new1);6360			tp->mii.advertising = new1;6361		}6362 6363		if (tp->mii.supports_gmii) {6364			orig = r8152_mdio_read(tp, MII_CTRL1000);6365			new1 = orig & ~(ADVERTISE_1000FULL |6366					ADVERTISE_1000HALF);6367 6368			if (advertising & RTL_ADVERTISED_1000_FULL) {6369				new1 |= ADVERTISE_1000FULL;6370				tp->ups_info.speed_duplex = NWAY_1000M_FULL;6371			}6372 6373			if (orig != new1)6374				r8152_mdio_write(tp, MII_CTRL1000, new1);6375		}6376 6377		if (tp->support_2500full) {6378			orig = ocp_reg_read(tp, OCP_10GBT_CTRL);6379			new1 = orig & ~MDIO_AN_10GBT_CTRL_ADV2_5G;6380 6381			if (advertising & RTL_ADVERTISED_2500_FULL) {6382				new1 |= MDIO_AN_10GBT_CTRL_ADV2_5G;6383				tp->ups_info.speed_duplex = NWAY_2500M_FULL;6384			}6385 6386			if (orig != new1)6387				ocp_reg_write(tp, OCP_10GBT_CTRL, new1);6388		}6389 6390		bmcr = BMCR_ANENABLE | BMCR_ANRESTART;6391 6392		tp->mii.force_media = 0;6393	}6394 6395	if (test_and_clear_bit(PHY_RESET, &tp->flags))6396		bmcr |= BMCR_RESET;6397 6398	r8152_mdio_write(tp, MII_BMCR, bmcr);6399 6400	if (bmcr & BMCR_RESET) {6401		int i;6402 6403		for (i = 0; i < 50; i++) {6404			msleep(20);6405			if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)6406				break;6407		}6408	}6409 6410out:6411	return ret;6412}6413 6414static void rtl8152_up(struct r8152 *tp)6415{6416	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))6417		return;6418 6419	r8152_aldps_en(tp, false);6420	r8152b_exit_oob(tp);6421	r8152_aldps_en(tp, true);6422}6423 6424static void rtl8152_down(struct r8152 *tp)6425{6426	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) {6427		rtl_drop_queued_tx(tp);6428		return;6429	}6430 6431	r8152_power_cut_en(tp, false);6432	r8152_aldps_en(tp, false);6433	r8152b_enter_oob(tp);6434	r8152_aldps_en(tp, true);6435}6436 6437static void rtl8153_up(struct r8152 *tp)6438{6439	u32 ocp_data;6440 6441	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))6442		return;6443 6444	r8153_u1u2en(tp, false);6445	r8153_u2p3en(tp, false);6446	r8153_aldps_en(tp, false);6447	r8153_first_init(tp);6448 6449	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);6450	ocp_data |= LANWAKE_CLR_EN;6451	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data);6452 6453	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG);6454	ocp_data &= ~LANWAKE_PIN;6455	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG, ocp_data);6456 6457	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK1);6458	ocp_data &= ~DELAY_PHY_PWR_CHG;6459	ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK1, ocp_data);6460 6461	r8153_aldps_en(tp, true);6462 6463	switch (tp->version) {6464	case RTL_VER_03:6465	case RTL_VER_04:6466		break;6467	case RTL_VER_05:6468	case RTL_VER_06:6469	default:6470		r8153_u2p3en(tp, true);6471		break;6472	}6473 6474	r8153_u1u2en(tp, true);6475}6476 6477static void rtl8153_down(struct r8152 *tp)6478{6479	u32 ocp_data;6480 6481	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) {6482		rtl_drop_queued_tx(tp);6483		return;6484	}6485 6486	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);6487	ocp_data &= ~LANWAKE_CLR_EN;6488	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data);6489 6490	r8153_u1u2en(tp, false);6491	r8153_u2p3en(tp, false);6492	r8153_power_cut_en(tp, false);6493	r8153_aldps_en(tp, false);6494	r8153_enter_oob(tp);6495	r8153_aldps_en(tp, true);6496}6497 6498static void rtl8153b_up(struct r8152 *tp)6499{6500	u32 ocp_data;6501 6502	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))6503		return;6504 6505	r8153b_u1u2en(tp, false);6506	r8153_u2p3en(tp, false);6507	r8153_aldps_en(tp, false);6508 6509	r8153_first_init(tp);6510	ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B);6511 6512	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);6513	ocp_data &= ~PLA_MCU_SPDWN_EN;6514	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);6515 6516	r8153_aldps_en(tp, true);6517 6518	if (tp->udev->speed >= USB_SPEED_SUPER)6519		r8153b_u1u2en(tp, true);6520}6521 6522static void rtl8153b_down(struct r8152 *tp)6523{6524	u32 ocp_data;6525 6526	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) {6527		rtl_drop_queued_tx(tp);6528		return;6529	}6530 6531	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);6532	ocp_data |= PLA_MCU_SPDWN_EN;6533	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);6534 6535	r8153b_u1u2en(tp, false);6536	r8153_u2p3en(tp, false);6537	r8153b_power_cut_en(tp, false);6538	r8153_aldps_en(tp, false);6539	r8153_enter_oob(tp);6540	r8153_aldps_en(tp, true);6541}6542 6543static void rtl8153c_change_mtu(struct r8152 *tp)6544{6545	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, mtu_to_size(tp->netdev->mtu));6546	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, 10 * 1024 / 64);6547 6548	ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, 512 / 64);6549 6550	/* Adjust the tx fifo free credit full threshold, otherwise6551	 * the fifo would be too small to send a jumbo frame packet.6552	 */6553	if (tp->netdev->mtu < 8000)6554		ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_FULL, 2048 / 8);6555	else6556		ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_FULL, 900 / 8);6557}6558 6559static void rtl8153c_up(struct r8152 *tp)6560{6561	u32 ocp_data;6562 6563	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))6564		return;6565 6566	r8153b_u1u2en(tp, false);6567	r8153_u2p3en(tp, false);6568	r8153_aldps_en(tp, false);6569 6570	rxdy_gated_en(tp, true);6571	r8153_teredo_off(tp);6572 6573	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);6574	ocp_data &= ~RCR_ACPT_ALL;6575	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);6576 6577	rtl8152_nic_reset(tp);6578	rtl_reset_bmu(tp);6579 6580	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);6581	ocp_data &= ~NOW_IS_OOB;6582	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);6583 6584	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);6585	ocp_data &= ~MCU_BORW_EN;6586	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);6587 6588	wait_oob_link_list_ready(tp);6589 6590	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);6591	ocp_data |= RE_INIT_LL;6592	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);6593 6594	wait_oob_link_list_ready(tp);6595 6596	rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);6597 6598	rtl8153c_change_mtu(tp);6599 6600	rtl8152_nic_reset(tp);6601 6602	/* rx share fifo credit full threshold */6603	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, 0x02);6604	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL, 0x08);6605	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);6606	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);6607 6608	ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B);6609 6610	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);6611 6612	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);6613	ocp_data |= BIT(8);6614	ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);6615 6616	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);6617 6618	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);6619	ocp_data &= ~PLA_MCU_SPDWN_EN;6620	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);6621 6622	r8153_aldps_en(tp, true);6623	r8153b_u1u2en(tp, true);6624}6625 6626static void rtl8156_change_mtu(struct r8152 *tp)6627{6628	u32 rx_max_size = mtu_to_size(tp->netdev->mtu);6629 6630	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, rx_max_size);6631	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);6632	r8156_fc_parameter(tp);6633 6634	/* TX share fifo free credit full threshold */6635	ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, 512 / 64);6636	ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_FULL,6637		       ALIGN(rx_max_size + sizeof(struct tx_desc), 1024) / 16);6638}6639 6640static void rtl8156_up(struct r8152 *tp)6641{6642	u32 ocp_data;6643 6644	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))6645		return;6646 6647	r8153b_u1u2en(tp, false);6648	r8153_u2p3en(tp, false);6649	r8153_aldps_en(tp, false);6650 6651	rxdy_gated_en(tp, true);6652	r8153_teredo_off(tp);6653 6654	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);6655	ocp_data &= ~RCR_ACPT_ALL;6656	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);6657 6658	rtl8152_nic_reset(tp);6659	rtl_reset_bmu(tp);6660 6661	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);6662	ocp_data &= ~NOW_IS_OOB;6663	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);6664 6665	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);6666	ocp_data &= ~MCU_BORW_EN;6667	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);6668 6669	rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);6670 6671	rtl8156_change_mtu(tp);6672 6673	switch (tp->version) {6674	case RTL_TEST_01:6675	case RTL_VER_10:6676	case RTL_VER_11:6677		ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_CONFIG);6678		ocp_data |= ACT_ODMA;6679		ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_CONFIG, ocp_data);6680		break;6681	default:6682		break;6683	}6684 6685	/* share FIFO settings */6686	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL);6687	ocp_data &= ~RXFIFO_FULL_MASK;6688	ocp_data |= 0x08;6689	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL, ocp_data);6690 6691	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);6692	ocp_data &= ~PLA_MCU_SPDWN_EN;6693	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);6694 6695	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION);6696	ocp_data &= ~(RG_PWRDN_EN | ALL_SPEED_OFF);6697	ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, ocp_data);6698 6699	ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, 0x00600400);6700 6701	if (tp->saved_wolopts != __rtl_get_wol(tp)) {6702		netif_warn(tp, ifup, tp->netdev, "wol setting is changed\n");6703		__rtl_set_wol(tp, tp->saved_wolopts);6704	}6705 6706	r8153_aldps_en(tp, true);6707	r8153_u2p3en(tp, true);6708 6709	if (tp->udev->speed >= USB_SPEED_SUPER)6710		r8153b_u1u2en(tp, true);6711}6712 6713static void rtl8156_down(struct r8152 *tp)6714{6715	u32 ocp_data;6716 6717	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) {6718		rtl_drop_queued_tx(tp);6719		return;6720	}6721 6722	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);6723	ocp_data |= PLA_MCU_SPDWN_EN;6724	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);6725 6726	r8153b_u1u2en(tp, false);6727	r8153_u2p3en(tp, false);6728	r8153b_power_cut_en(tp, false);6729	r8153_aldps_en(tp, false);6730 6731	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);6732	ocp_data &= ~NOW_IS_OOB;6733	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);6734 6735	/* RX FIFO settings for OOB */6736	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL, 64 / 16);6737	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_FULL, 1024 / 16);6738	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_EMPTY, 4096 / 16);6739 6740	rtl_disable(tp);6741	rtl_reset_bmu(tp);6742 6743	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, 1522);6744	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_DEFAULT);6745 6746	/* Clear teredo wake event. bit[15:8] is the teredo wakeup6747	 * type. Set it to zero. bits[7:0] are the W1C bits about6748	 * the events. Set them to all 1 to clear them.6749	 */6750	ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff);6751 6752	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);6753	ocp_data |= NOW_IS_OOB;6754	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);6755 6756	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);6757	ocp_data |= MCU_BORW_EN;6758	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);6759 6760	rtl_rx_vlan_en(tp, true);6761	rxdy_gated_en(tp, false);6762 6763	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);6764	ocp_data |= RCR_APM | RCR_AM | RCR_AB;6765	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);6766 6767	r8153_aldps_en(tp, true);6768}6769 6770static bool rtl8152_in_nway(struct r8152 *tp)6771{6772	u16 nway_state;6773 6774	ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000);6775	tp->ocp_base = 0x2000;6776	ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c);		/* phy state */6777	nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a);6778 6779	/* bit 15: TXDIS_STATE, bit 14: ABD_STATE */6780	if (nway_state & 0xc000)6781		return false;6782	else6783		return true;6784}6785 6786static bool rtl8153_in_nway(struct r8152 *tp)6787{6788	u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff;6789 6790	if (phy_state == TXDIS_STATE || phy_state == ABD_STATE)6791		return false;6792	else6793		return true;6794}6795 6796static void r8156_mdio_force_mode(struct r8152 *tp)6797{6798	u16 data;6799 6800	/* Select force mode through 0xa5b4 bit 156801	 * 0: MDIO force mode6802	 * 1: MMD force mode6803	 */6804	data = ocp_reg_read(tp, 0xa5b4);6805	if (data & BIT(15)) {6806		data &= ~BIT(15);6807		ocp_reg_write(tp, 0xa5b4, data);6808	}6809}6810 6811static void set_carrier(struct r8152 *tp)6812{6813	struct net_device *netdev = tp->netdev;6814	struct napi_struct *napi = &tp->napi;6815	u16 speed;6816 6817	speed = rtl8152_get_speed(tp);6818 6819	if (speed & LINK_STATUS) {6820		if (!netif_carrier_ok(netdev)) {6821			tp->rtl_ops.enable(tp);6822			netif_stop_queue(netdev);6823			napi_disable(napi);6824			netif_carrier_on(netdev);6825			rtl_start_rx(tp);6826			clear_bit(RTL8152_SET_RX_MODE, &tp->flags);6827			_rtl8152_set_rx_mode(netdev);6828			napi_enable(napi);6829			netif_wake_queue(netdev);6830			netif_info(tp, link, netdev, "carrier on\n");6831		} else if (netif_queue_stopped(netdev) &&6832			   skb_queue_len(&tp->tx_queue) < tp->tx_qlen) {6833			netif_wake_queue(netdev);6834		}6835	} else {6836		if (netif_carrier_ok(netdev)) {6837			netif_carrier_off(netdev);6838			tasklet_disable(&tp->tx_tl);6839			napi_disable(napi);6840			tp->rtl_ops.disable(tp);6841			napi_enable(napi);6842			tasklet_enable(&tp->tx_tl);6843			netif_info(tp, link, netdev, "carrier off\n");6844		}6845	}6846}6847 6848static void rtl_work_func_t(struct work_struct *work)6849{6850	struct r8152 *tp = container_of(work, struct r8152, schedule.work);6851 6852	/* If the device is unplugged or !netif_running(), the workqueue6853	 * doesn't need to wake the device, and could return directly.6854	 */6855	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags) || !netif_running(tp->netdev))6856		return;6857 6858	if (usb_autopm_get_interface(tp->intf) < 0)6859		return;6860 6861	if (!test_bit(WORK_ENABLE, &tp->flags))6862		goto out1;6863 6864	if (!mutex_trylock(&tp->control)) {6865		schedule_delayed_work(&tp->schedule, 0);6866		goto out1;6867	}6868 6869	if (test_and_clear_bit(RTL8152_LINK_CHG, &tp->flags))6870		set_carrier(tp);6871 6872	if (test_and_clear_bit(RTL8152_SET_RX_MODE, &tp->flags))6873		_rtl8152_set_rx_mode(tp->netdev);6874 6875	/* don't schedule tasket before linking */6876	if (test_and_clear_bit(SCHEDULE_TASKLET, &tp->flags) &&6877	    netif_carrier_ok(tp->netdev))6878		tasklet_schedule(&tp->tx_tl);6879 6880	if (test_and_clear_bit(RX_EPROTO, &tp->flags) &&6881	    !list_empty(&tp->rx_done))6882		napi_schedule(&tp->napi);6883 6884	mutex_unlock(&tp->control);6885 6886out1:6887	usb_autopm_put_interface(tp->intf);6888}6889 6890static void rtl_hw_phy_work_func_t(struct work_struct *work)6891{6892	struct r8152 *tp = container_of(work, struct r8152, hw_phy_work.work);6893 6894	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))6895		return;6896 6897	if (usb_autopm_get_interface(tp->intf) < 0)6898		return;6899 6900	mutex_lock(&tp->control);6901 6902	if (rtl8152_request_firmware(tp) == -ENODEV && tp->rtl_fw.retry) {6903		tp->rtl_fw.retry = false;6904		tp->rtl_fw.fw = NULL;6905 6906		/* Delay execution in case request_firmware() is not ready yet.6907		 */6908		queue_delayed_work(system_long_wq, &tp->hw_phy_work, HZ * 10);6909		goto ignore_once;6910	}6911 6912	tp->rtl_ops.hw_phy_cfg(tp);6913 6914	rtl8152_set_speed(tp, tp->autoneg, tp->speed, tp->duplex,6915			  tp->advertising);6916 6917ignore_once:6918	mutex_unlock(&tp->control);6919 6920	usb_autopm_put_interface(tp->intf);6921}6922 6923#ifdef CONFIG_PM_SLEEP6924static int rtl_notifier(struct notifier_block *nb, unsigned long action,6925			void *data)6926{6927	struct r8152 *tp = container_of(nb, struct r8152, pm_notifier);6928 6929	switch (action) {6930	case PM_HIBERNATION_PREPARE:6931	case PM_SUSPEND_PREPARE:6932		usb_autopm_get_interface(tp->intf);6933		break;6934 6935	case PM_POST_HIBERNATION:6936	case PM_POST_SUSPEND:6937		usb_autopm_put_interface(tp->intf);6938		break;6939 6940	case PM_POST_RESTORE:6941	case PM_RESTORE_PREPARE:6942	default:6943		break;6944	}6945 6946	return NOTIFY_DONE;6947}6948#endif6949 6950static int rtl8152_open(struct net_device *netdev)6951{6952	struct r8152 *tp = netdev_priv(netdev);6953	int res = 0;6954 6955	if (work_busy(&tp->hw_phy_work.work) & WORK_BUSY_PENDING) {6956		cancel_delayed_work_sync(&tp->hw_phy_work);6957		rtl_hw_phy_work_func_t(&tp->hw_phy_work.work);6958	}6959 6960	res = alloc_all_mem(tp);6961	if (res)6962		goto out;6963 6964	res = usb_autopm_get_interface(tp->intf);6965	if (res < 0)6966		goto out_free;6967 6968	mutex_lock(&tp->control);6969 6970	tp->rtl_ops.up(tp);6971 6972	netif_carrier_off(netdev);6973	netif_start_queue(netdev);6974	set_bit(WORK_ENABLE, &tp->flags);6975 6976	res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);6977	if (res) {6978		if (res == -ENODEV)6979			netif_device_detach(tp->netdev);6980		netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",6981			   res);6982		goto out_unlock;6983	}6984	napi_enable(&tp->napi);6985	tasklet_enable(&tp->tx_tl);6986 6987	mutex_unlock(&tp->control);6988 6989	usb_autopm_put_interface(tp->intf);6990#ifdef CONFIG_PM_SLEEP6991	tp->pm_notifier.notifier_call = rtl_notifier;6992	register_pm_notifier(&tp->pm_notifier);6993#endif6994	return 0;6995 6996out_unlock:6997	mutex_unlock(&tp->control);6998	usb_autopm_put_interface(tp->intf);6999out_free:7000	free_all_mem(tp);7001out:7002	return res;7003}7004 7005static int rtl8152_close(struct net_device *netdev)7006{7007	struct r8152 *tp = netdev_priv(netdev);7008	int res = 0;7009 7010#ifdef CONFIG_PM_SLEEP7011	unregister_pm_notifier(&tp->pm_notifier);7012#endif7013	tasklet_disable(&tp->tx_tl);7014	clear_bit(WORK_ENABLE, &tp->flags);7015	usb_kill_urb(tp->intr_urb);7016	cancel_delayed_work_sync(&tp->schedule);7017	napi_disable(&tp->napi);7018	netif_stop_queue(netdev);7019 7020	res = usb_autopm_get_interface(tp->intf);7021	if (res < 0 || test_bit(RTL8152_INACCESSIBLE, &tp->flags)) {7022		rtl_drop_queued_tx(tp);7023		rtl_stop_rx(tp);7024	} else {7025		mutex_lock(&tp->control);7026 7027		tp->rtl_ops.down(tp);7028 7029		mutex_unlock(&tp->control);7030	}7031 7032	if (!res)7033		usb_autopm_put_interface(tp->intf);7034 7035	free_all_mem(tp);7036 7037	return res;7038}7039 7040static void rtl_tally_reset(struct r8152 *tp)7041{7042	u32 ocp_data;7043 7044	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);7045	ocp_data |= TALLY_RESET;7046	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);7047}7048 7049static void r8152b_init(struct r8152 *tp)7050{7051	u32 ocp_data;7052	u16 data;7053 7054	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))7055		return;7056 7057	data = r8152_mdio_read(tp, MII_BMCR);7058	if (data & BMCR_PDOWN) {7059		data &= ~BMCR_PDOWN;7060		r8152_mdio_write(tp, MII_BMCR, data);7061	}7062 7063	r8152_aldps_en(tp, false);7064 7065	if (tp->version == RTL_VER_01) {7066		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);7067		ocp_data &= ~LED_MODE_MASK;7068		ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);7069	}7070 7071	r8152_power_cut_en(tp, false);7072 7073	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);7074	ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;7075	ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);7076	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);7077	ocp_data &= ~MCU_CLK_RATIO_MASK;7078	ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;7079	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);7080	ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |7081		   SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;7082	ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);7083 7084	rtl_tally_reset(tp);7085 7086	/* enable rx aggregation */7087	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);7088	ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);7089	ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);7090}7091 7092static void r8153_init(struct r8152 *tp)7093{7094	u32 ocp_data;7095	u16 data;7096	int i;7097 7098	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))7099		return;7100 7101	r8153_u1u2en(tp, false);7102 7103	for (i = 0; i < 500; i++) {7104		if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &7105		    AUTOLOAD_DONE)7106			break;7107 7108		msleep(20);7109		if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))7110			break;7111	}7112 7113	data = r8153_phy_status(tp, 0);7114 7115	if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 ||7116	    tp->version == RTL_VER_05)7117		ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);7118 7119	data = r8152_mdio_read(tp, MII_BMCR);7120	if (data & BMCR_PDOWN) {7121		data &= ~BMCR_PDOWN;7122		r8152_mdio_write(tp, MII_BMCR, data);7123	}7124 7125	data = r8153_phy_status(tp, PHY_STAT_LAN_ON);7126 7127	r8153_u2p3en(tp, false);7128 7129	if (tp->version == RTL_VER_04) {7130		ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2);7131		ocp_data &= ~pwd_dn_scale_mask;7132		ocp_data |= pwd_dn_scale(96);7133		ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data);7134 7135		ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);7136		ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;7137		ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);7138	} else if (tp->version == RTL_VER_05) {7139		ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0);7140		ocp_data &= ~ECM_ALDPS;7141		ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data);7142 7143		ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);7144		if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)7145			ocp_data &= ~DYNAMIC_BURST;7146		else7147			ocp_data |= DYNAMIC_BURST;7148		ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);7149	} else if (tp->version == RTL_VER_06) {7150		ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);7151		if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)7152			ocp_data &= ~DYNAMIC_BURST;7153		else7154			ocp_data |= DYNAMIC_BURST;7155		ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);7156 7157		r8153_queue_wake(tp, false);7158 7159		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);7160		if (rtl8152_get_speed(tp) & LINK_STATUS)7161			ocp_data |= CUR_LINK_OK;7162		else7163			ocp_data &= ~CUR_LINK_OK;7164		ocp_data |= POLL_LINK_CHG;7165		ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);7166	}7167 7168	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2);7169	ocp_data |= EP4_FULL_FC;7170	ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data);7171 7172	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);7173	ocp_data &= ~TIMER11_EN;7174	ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);7175 7176	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);7177	ocp_data &= ~LED_MODE_MASK;7178	ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);7179 7180	ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM;7181	if (tp->version == RTL_VER_04 && tp->udev->speed < USB_SPEED_SUPER)7182		ocp_data |= LPM_TIMER_500MS;7183	else7184		ocp_data |= LPM_TIMER_500US;7185	ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);7186 7187	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);7188	ocp_data &= ~SEN_VAL_MASK;7189	ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;7190	ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);7191 7192	ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001);7193 7194	r8153_power_cut_en(tp, false);7195	rtl_runtime_suspend_enable(tp, false);7196	r8153_mac_clk_speed_down(tp, false);7197	r8153_u1u2en(tp, true);7198	usb_enable_lpm(tp->udev);7199 7200	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);7201	ocp_data |= LANWAKE_CLR_EN;7202	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data);7203 7204	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG);7205	ocp_data &= ~LANWAKE_PIN;7206	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG, ocp_data);7207 7208	/* rx aggregation */7209	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);7210	ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);7211	if (tp->dell_tb_rx_agg_bug)7212		ocp_data |= RX_AGG_DISABLE;7213 7214	ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);7215 7216	rtl_tally_reset(tp);7217 7218	switch (tp->udev->speed) {7219	case USB_SPEED_SUPER:7220	case USB_SPEED_SUPER_PLUS:7221		tp->coalesce = COALESCE_SUPER;7222		break;7223	case USB_SPEED_HIGH:7224		tp->coalesce = COALESCE_HIGH;7225		break;7226	default:7227		tp->coalesce = COALESCE_SLOW;7228		break;7229	}7230}7231 7232static void r8153b_init(struct r8152 *tp)7233{7234	u32 ocp_data;7235	u16 data;7236	int i;7237 7238	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))7239		return;7240 7241	r8153b_u1u2en(tp, false);7242 7243	for (i = 0; i < 500; i++) {7244		if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &7245		    AUTOLOAD_DONE)7246			break;7247 7248		msleep(20);7249		if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))7250			break;7251	}7252 7253	data = r8153_phy_status(tp, 0);7254 7255	data = r8152_mdio_read(tp, MII_BMCR);7256	if (data & BMCR_PDOWN) {7257		data &= ~BMCR_PDOWN;7258		r8152_mdio_write(tp, MII_BMCR, data);7259	}7260 7261	data = r8153_phy_status(tp, PHY_STAT_LAN_ON);7262 7263	r8153_u2p3en(tp, false);7264 7265	/* MSC timer = 0xfff * 8ms = 32760 ms */7266	ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);7267 7268	r8153b_power_cut_en(tp, false);7269	r8153b_ups_en(tp, false);7270	r8153_queue_wake(tp, false);7271	rtl_runtime_suspend_enable(tp, false);7272 7273	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);7274	if (rtl8152_get_speed(tp) & LINK_STATUS)7275		ocp_data |= CUR_LINK_OK;7276	else7277		ocp_data &= ~CUR_LINK_OK;7278	ocp_data |= POLL_LINK_CHG;7279	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);7280 7281	if (tp->udev->speed >= USB_SPEED_SUPER)7282		r8153b_u1u2en(tp, true);7283 7284	usb_enable_lpm(tp->udev);7285 7286	/* MAC clock speed down */7287	r8153_mac_clk_speed_down(tp, true);7288 7289	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);7290	ocp_data &= ~PLA_MCU_SPDWN_EN;7291	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);7292 7293	if (tp->version == RTL_VER_09) {7294		/* Disable Test IO for 32QFN */7295		if (ocp_read_byte(tp, MCU_TYPE_PLA, 0xdc00) & BIT(5)) {7296			ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);7297			ocp_data |= TEST_IO_OFF;7298			ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);7299		}7300	}7301 7302	set_bit(GREEN_ETHERNET, &tp->flags);7303 7304	/* rx aggregation */7305	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);7306	ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);7307	ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);7308 7309	rtl_tally_reset(tp);7310 7311	tp->coalesce = 15000;	/* 15 us */7312}7313 7314static void r8153c_init(struct r8152 *tp)7315{7316	u32 ocp_data;7317	u16 data;7318	int i;7319 7320	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))7321		return;7322 7323	r8153b_u1u2en(tp, false);7324 7325	/* Disable spi_en */7326	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);7327	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);7328	ocp_data &= ~BIT(3);7329	ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);7330	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, 0xcbf0);7331	ocp_data |= BIT(1);7332	ocp_write_word(tp, MCU_TYPE_USB, 0xcbf0, ocp_data);7333 7334	for (i = 0; i < 500; i++) {7335		if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &7336		    AUTOLOAD_DONE)7337			break;7338 7339		msleep(20);7340		if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))7341			return;7342	}7343 7344	data = r8153_phy_status(tp, 0);7345 7346	data = r8152_mdio_read(tp, MII_BMCR);7347	if (data & BMCR_PDOWN) {7348		data &= ~BMCR_PDOWN;7349		r8152_mdio_write(tp, MII_BMCR, data);7350	}7351 7352	data = r8153_phy_status(tp, PHY_STAT_LAN_ON);7353 7354	r8153_u2p3en(tp, false);7355 7356	/* MSC timer = 0xfff * 8ms = 32760 ms */7357	ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);7358 7359	r8153b_power_cut_en(tp, false);7360	r8153c_ups_en(tp, false);7361	r8153_queue_wake(tp, false);7362	rtl_runtime_suspend_enable(tp, false);7363 7364	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);7365	if (rtl8152_get_speed(tp) & LINK_STATUS)7366		ocp_data |= CUR_LINK_OK;7367	else7368		ocp_data &= ~CUR_LINK_OK;7369 7370	ocp_data |= POLL_LINK_CHG;7371	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);7372 7373	r8153b_u1u2en(tp, true);7374 7375	usb_enable_lpm(tp->udev);7376 7377	/* MAC clock speed down */7378	r8153_mac_clk_speed_down(tp, true);7379 7380	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);7381	ocp_data &= ~BIT(7);7382	ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);7383 7384	set_bit(GREEN_ETHERNET, &tp->flags);7385 7386	/* rx aggregation */7387	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);7388	ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);7389	ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);7390 7391	rtl_tally_reset(tp);7392 7393	tp->coalesce = 15000;	/* 15 us */7394}7395 7396static void r8156_hw_phy_cfg(struct r8152 *tp)7397{7398	u32 ocp_data;7399	u16 data;7400 7401	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);7402	if (ocp_data & PCUT_STATUS) {7403		ocp_data &= ~PCUT_STATUS;7404		ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);7405	}7406 7407	data = r8153_phy_status(tp, 0);7408	switch (data) {7409	case PHY_STAT_EXT_INIT:7410		rtl8152_apply_firmware(tp, true);7411 7412		data = ocp_reg_read(tp, 0xa468);7413		data &= ~(BIT(3) | BIT(1));7414		ocp_reg_write(tp, 0xa468, data);7415		break;7416	case PHY_STAT_LAN_ON:7417	case PHY_STAT_PWRDN:7418	default:7419		rtl8152_apply_firmware(tp, false);7420		break;7421	}7422 7423	/* disable ALDPS before updating the PHY parameters */7424	r8153_aldps_en(tp, false);7425 7426	/* disable EEE before updating the PHY parameters */7427	rtl_eee_enable(tp, false);7428 7429	data = r8153_phy_status(tp, PHY_STAT_LAN_ON);7430	WARN_ON_ONCE(data != PHY_STAT_LAN_ON);7431 7432	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);7433	ocp_data |= PFM_PWM_SWITCH;7434	ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);7435 7436	switch (tp->version) {7437	case RTL_VER_10:7438		data = ocp_reg_read(tp, 0xad40);7439		data &= ~0x3ff;7440		data |= BIT(7) | BIT(2);7441		ocp_reg_write(tp, 0xad40, data);7442 7443		data = ocp_reg_read(tp, 0xad4e);7444		data |= BIT(4);7445		ocp_reg_write(tp, 0xad4e, data);7446		data = ocp_reg_read(tp, 0xad16);7447		data &= ~0x3ff;7448		data |= 0x6;7449		ocp_reg_write(tp, 0xad16, data);7450		data = ocp_reg_read(tp, 0xad32);7451		data &= ~0x3f;7452		data |= 6;7453		ocp_reg_write(tp, 0xad32, data);7454		data = ocp_reg_read(tp, 0xac08);7455		data &= ~(BIT(12) | BIT(8));7456		ocp_reg_write(tp, 0xac08, data);7457		data = ocp_reg_read(tp, 0xac8a);7458		data |= BIT(12) | BIT(13) | BIT(14);7459		data &= ~BIT(15);7460		ocp_reg_write(tp, 0xac8a, data);7461		data = ocp_reg_read(tp, 0xad18);7462		data |= BIT(10);7463		ocp_reg_write(tp, 0xad18, data);7464		data = ocp_reg_read(tp, 0xad1a);7465		data |= 0x3ff;7466		ocp_reg_write(tp, 0xad1a, data);7467		data = ocp_reg_read(tp, 0xad1c);7468		data |= 0x3ff;7469		ocp_reg_write(tp, 0xad1c, data);7470 7471		data = sram_read(tp, 0x80ea);7472		data &= ~0xff00;7473		data |= 0xc400;7474		sram_write(tp, 0x80ea, data);7475		data = sram_read(tp, 0x80eb);7476		data &= ~0x0700;7477		data |= 0x0300;7478		sram_write(tp, 0x80eb, data);7479		data = sram_read(tp, 0x80f8);7480		data &= ~0xff00;7481		data |= 0x1c00;7482		sram_write(tp, 0x80f8, data);7483		data = sram_read(tp, 0x80f1);7484		data &= ~0xff00;7485		data |= 0x3000;7486		sram_write(tp, 0x80f1, data);7487 7488		data = sram_read(tp, 0x80fe);7489		data &= ~0xff00;7490		data |= 0xa500;7491		sram_write(tp, 0x80fe, data);7492		data = sram_read(tp, 0x8102);7493		data &= ~0xff00;7494		data |= 0x5000;7495		sram_write(tp, 0x8102, data);7496		data = sram_read(tp, 0x8015);7497		data &= ~0xff00;7498		data |= 0x3300;7499		sram_write(tp, 0x8015, data);7500		data = sram_read(tp, 0x8100);7501		data &= ~0xff00;7502		data |= 0x7000;7503		sram_write(tp, 0x8100, data);7504		data = sram_read(tp, 0x8014);7505		data &= ~0xff00;7506		data |= 0xf000;7507		sram_write(tp, 0x8014, data);7508		data = sram_read(tp, 0x8016);7509		data &= ~0xff00;7510		data |= 0x6500;7511		sram_write(tp, 0x8016, data);7512		data = sram_read(tp, 0x80dc);7513		data &= ~0xff00;7514		data |= 0xed00;7515		sram_write(tp, 0x80dc, data);7516		data = sram_read(tp, 0x80df);7517		data |= BIT(8);7518		sram_write(tp, 0x80df, data);7519		data = sram_read(tp, 0x80e1);7520		data &= ~BIT(8);7521		sram_write(tp, 0x80e1, data);7522 7523		data = ocp_reg_read(tp, 0xbf06);7524		data &= ~0x003f;7525		data |= 0x0038;7526		ocp_reg_write(tp, 0xbf06, data);7527 7528		sram_write(tp, 0x819f, 0xddb6);7529 7530		ocp_reg_write(tp, 0xbc34, 0x5555);7531		data = ocp_reg_read(tp, 0xbf0a);7532		data &= ~0x0e00;7533		data |= 0x0a00;7534		ocp_reg_write(tp, 0xbf0a, data);7535 7536		data = ocp_reg_read(tp, 0xbd2c);7537		data &= ~BIT(13);7538		ocp_reg_write(tp, 0xbd2c, data);7539		break;7540	case RTL_VER_11:7541		data = ocp_reg_read(tp, 0xad16);7542		data |= 0x3ff;7543		ocp_reg_write(tp, 0xad16, data);7544		data = ocp_reg_read(tp, 0xad32);7545		data &= ~0x3f;7546		data |= 6;7547		ocp_reg_write(tp, 0xad32, data);7548		data = ocp_reg_read(tp, 0xac08);7549		data &= ~(BIT(12) | BIT(8));7550		ocp_reg_write(tp, 0xac08, data);7551		data = ocp_reg_read(tp, 0xacc0);7552		data &= ~0x3;7553		data |= BIT(1);7554		ocp_reg_write(tp, 0xacc0, data);7555		data = ocp_reg_read(tp, 0xad40);7556		data &= ~0xe7;7557		data |= BIT(6) | BIT(2);7558		ocp_reg_write(tp, 0xad40, data);7559		data = ocp_reg_read(tp, 0xac14);7560		data &= ~BIT(7);7561		ocp_reg_write(tp, 0xac14, data);7562		data = ocp_reg_read(tp, 0xac80);7563		data &= ~(BIT(8) | BIT(9));7564		ocp_reg_write(tp, 0xac80, data);7565		data = ocp_reg_read(tp, 0xac5e);7566		data &= ~0x7;7567		data |= BIT(1);7568		ocp_reg_write(tp, 0xac5e, data);7569		ocp_reg_write(tp, 0xad4c, 0x00a8);7570		ocp_reg_write(tp, 0xac5c, 0x01ff);7571		data = ocp_reg_read(tp, 0xac8a);7572		data &= ~0xf0;7573		data |= BIT(4) | BIT(5);7574		ocp_reg_write(tp, 0xac8a, data);7575		ocp_reg_write(tp, 0xb87c, 0x8157);7576		data = ocp_reg_read(tp, 0xb87e);7577		data &= ~0xff00;7578		data |= 0x0500;7579		ocp_reg_write(tp, 0xb87e, data);7580		ocp_reg_write(tp, 0xb87c, 0x8159);7581		data = ocp_reg_read(tp, 0xb87e);7582		data &= ~0xff00;7583		data |= 0x0700;7584		ocp_reg_write(tp, 0xb87e, data);7585 7586		/* AAGC */7587		ocp_reg_write(tp, 0xb87c, 0x80a2);7588		ocp_reg_write(tp, 0xb87e, 0x0153);7589		ocp_reg_write(tp, 0xb87c, 0x809c);7590		ocp_reg_write(tp, 0xb87e, 0x0153);7591 7592		/* EEE parameter */7593		ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS_2P5G, 0x0056);7594 7595		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_USB_CFG);7596		ocp_data |= EN_XG_LIP | EN_G_LIP;7597		ocp_write_word(tp, MCU_TYPE_PLA, PLA_USB_CFG, ocp_data);7598 7599		sram_write(tp, 0x8257, 0x020f); /*  XG PLL */7600		sram_write(tp, 0x80ea, 0x7843); /* GIGA Master */7601 7602		if (rtl_phy_patch_request(tp, true, true))7603			return;7604 7605		/* Advance EEE */7606		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);7607		ocp_data |= EEE_SPDWN_EN;7608		ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);7609 7610		data = ocp_reg_read(tp, OCP_DOWN_SPEED);7611		data &= ~(EN_EEE_100 | EN_EEE_1000);7612		data |= EN_10M_CLKDIV;7613		ocp_reg_write(tp, OCP_DOWN_SPEED, data);7614		tp->ups_info._10m_ckdiv = true;7615		tp->ups_info.eee_plloff_100 = false;7616		tp->ups_info.eee_plloff_giga = false;7617 7618		data = ocp_reg_read(tp, OCP_POWER_CFG);7619		data &= ~EEE_CLKDIV_EN;7620		ocp_reg_write(tp, OCP_POWER_CFG, data);7621		tp->ups_info.eee_ckdiv = false;7622 7623		ocp_reg_write(tp, OCP_SYSCLK_CFG, 0);7624		ocp_reg_write(tp, OCP_SYSCLK_CFG, sysclk_div_expo(5));7625		tp->ups_info._250m_ckdiv = false;7626 7627		rtl_phy_patch_request(tp, false, true);7628 7629		/* enable ADC Ibias Cal */7630		data = ocp_reg_read(tp, 0xd068);7631		data |= BIT(13);7632		ocp_reg_write(tp, 0xd068, data);7633 7634		/* enable Thermal Sensor */7635		data = sram_read(tp, 0x81a2);7636		data &= ~BIT(8);7637		sram_write(tp, 0x81a2, data);7638		data = ocp_reg_read(tp, 0xb54c);7639		data &= ~0xff00;7640		data |= 0xdb00;7641		ocp_reg_write(tp, 0xb54c, data);7642 7643		/* Nway 2.5G Lite */7644		data = ocp_reg_read(tp, 0xa454);7645		data &= ~BIT(0);7646		ocp_reg_write(tp, 0xa454, data);7647 7648		/* CS DSP solution */7649		data = ocp_reg_read(tp, OCP_10GBT_CTRL);7650		data |= RTL_ADV2_5G_F_R;7651		ocp_reg_write(tp, OCP_10GBT_CTRL, data);7652		data = ocp_reg_read(tp, 0xad4e);7653		data &= ~BIT(4);7654		ocp_reg_write(tp, 0xad4e, data);7655		data = ocp_reg_read(tp, 0xa86a);7656		data &= ~BIT(0);7657		ocp_reg_write(tp, 0xa86a, data);7658 7659		/* MDI SWAP */7660		if ((ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG) & MID_REVERSE) &&7661		    (ocp_reg_read(tp, 0xd068) & BIT(1))) {7662			u16 swap_a, swap_b;7663 7664			data = ocp_reg_read(tp, 0xd068);7665			data &= ~0x1f;7666			data |= 0x1; /* p0 */7667			ocp_reg_write(tp, 0xd068, data);7668			swap_a = ocp_reg_read(tp, 0xd06a);7669			data &= ~0x18;7670			data |= 0x18; /* p3 */7671			ocp_reg_write(tp, 0xd068, data);7672			swap_b = ocp_reg_read(tp, 0xd06a);7673			data &= ~0x18; /* p0 */7674			ocp_reg_write(tp, 0xd068, data);7675			ocp_reg_write(tp, 0xd06a,7676				      (swap_a & ~0x7ff) | (swap_b & 0x7ff));7677			data |= 0x18; /* p3 */7678			ocp_reg_write(tp, 0xd068, data);7679			ocp_reg_write(tp, 0xd06a,7680				      (swap_b & ~0x7ff) | (swap_a & 0x7ff));7681			data &= ~0x18;7682			data |= 0x08; /* p1 */7683			ocp_reg_write(tp, 0xd068, data);7684			swap_a = ocp_reg_read(tp, 0xd06a);7685			data &= ~0x18;7686			data |= 0x10; /* p2 */7687			ocp_reg_write(tp, 0xd068, data);7688			swap_b = ocp_reg_read(tp, 0xd06a);7689			data &= ~0x18;7690			data |= 0x08; /* p1 */7691			ocp_reg_write(tp, 0xd068, data);7692			ocp_reg_write(tp, 0xd06a,7693				      (swap_a & ~0x7ff) | (swap_b & 0x7ff));7694			data &= ~0x18;7695			data |= 0x10; /* p2 */7696			ocp_reg_write(tp, 0xd068, data);7697			ocp_reg_write(tp, 0xd06a,7698				      (swap_b & ~0x7ff) | (swap_a & 0x7ff));7699			swap_a = ocp_reg_read(tp, 0xbd5a);7700			swap_b = ocp_reg_read(tp, 0xbd5c);7701			ocp_reg_write(tp, 0xbd5a, (swap_a & ~0x1f1f) |7702				      ((swap_b & 0x1f) << 8) |7703				      ((swap_b >> 8) & 0x1f));7704			ocp_reg_write(tp, 0xbd5c, (swap_b & ~0x1f1f) |7705				      ((swap_a & 0x1f) << 8) |7706				      ((swap_a >> 8) & 0x1f));7707			swap_a = ocp_reg_read(tp, 0xbc18);7708			swap_b = ocp_reg_read(tp, 0xbc1a);7709			ocp_reg_write(tp, 0xbc18, (swap_a & ~0x1f1f) |7710				      ((swap_b & 0x1f) << 8) |7711				      ((swap_b >> 8) & 0x1f));7712			ocp_reg_write(tp, 0xbc1a, (swap_b & ~0x1f1f) |7713				      ((swap_a & 0x1f) << 8) |7714				      ((swap_a >> 8) & 0x1f));7715		}7716 7717		/* Notify the MAC when the speed is changed to force mode. */7718		data = ocp_reg_read(tp, OCP_INTR_EN);7719		data |= INTR_SPEED_FORCE;7720		ocp_reg_write(tp, OCP_INTR_EN, data);7721		break;7722	default:7723		break;7724	}7725 7726	rtl_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));7727 7728	data = ocp_reg_read(tp, 0xa428);7729	data &= ~BIT(9);7730	ocp_reg_write(tp, 0xa428, data);7731	data = ocp_reg_read(tp, 0xa5ea);7732	data &= ~BIT(0);7733	ocp_reg_write(tp, 0xa5ea, data);7734	tp->ups_info.lite_mode = 0;7735 7736	if (tp->eee_en)7737		rtl_eee_enable(tp, true);7738 7739	r8153_aldps_en(tp, true);7740	r8152b_enable_fc(tp);7741	r8153_u2p3en(tp, true);7742 7743	set_bit(PHY_RESET, &tp->flags);7744}7745 7746static void r8156b_hw_phy_cfg(struct r8152 *tp)7747{7748	u32 ocp_data;7749	u16 data;7750 7751	switch (tp->version) {7752	case RTL_VER_12:7753		ocp_reg_write(tp, 0xbf86, 0x9000);7754		data = ocp_reg_read(tp, 0xc402);7755		data |= BIT(10);7756		ocp_reg_write(tp, 0xc402, data);7757		data &= ~BIT(10);7758		ocp_reg_write(tp, 0xc402, data);7759		ocp_reg_write(tp, 0xbd86, 0x1010);7760		ocp_reg_write(tp, 0xbd88, 0x1010);7761		data = ocp_reg_read(tp, 0xbd4e);7762		data &= ~(BIT(10) | BIT(11));7763		data |= BIT(11);7764		ocp_reg_write(tp, 0xbd4e, data);7765		data = ocp_reg_read(tp, 0xbf46);7766		data &= ~0xf00;7767		data |= 0x700;7768		ocp_reg_write(tp, 0xbf46, data);7769		break;7770	case RTL_VER_13:7771	case RTL_VER_15:7772		r8156b_wait_loading_flash(tp);7773		break;7774	default:7775		break;7776	}7777 7778	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);7779	if (ocp_data & PCUT_STATUS) {7780		ocp_data &= ~PCUT_STATUS;7781		ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);7782	}7783 7784	data = r8153_phy_status(tp, 0);7785	switch (data) {7786	case PHY_STAT_EXT_INIT:7787		rtl8152_apply_firmware(tp, true);7788 7789		data = ocp_reg_read(tp, 0xa466);7790		data &= ~BIT(0);7791		ocp_reg_write(tp, 0xa466, data);7792 7793		data = ocp_reg_read(tp, 0xa468);7794		data &= ~(BIT(3) | BIT(1));7795		ocp_reg_write(tp, 0xa468, data);7796		break;7797	case PHY_STAT_LAN_ON:7798	case PHY_STAT_PWRDN:7799	default:7800		rtl8152_apply_firmware(tp, false);7801		break;7802	}7803 7804	data = r8152_mdio_read(tp, MII_BMCR);7805	if (data & BMCR_PDOWN) {7806		data &= ~BMCR_PDOWN;7807		r8152_mdio_write(tp, MII_BMCR, data);7808	}7809 7810	/* disable ALDPS before updating the PHY parameters */7811	r8153_aldps_en(tp, false);7812 7813	/* disable EEE before updating the PHY parameters */7814	rtl_eee_enable(tp, false);7815 7816	data = r8153_phy_status(tp, PHY_STAT_LAN_ON);7817	WARN_ON_ONCE(data != PHY_STAT_LAN_ON);7818 7819	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);7820	ocp_data |= PFM_PWM_SWITCH;7821	ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);7822 7823	switch (tp->version) {7824	case RTL_VER_12:7825		data = ocp_reg_read(tp, 0xbc08);7826		data |= BIT(3) | BIT(2);7827		ocp_reg_write(tp, 0xbc08, data);7828 7829		data = sram_read(tp, 0x8fff);7830		data &= ~0xff00;7831		data |= 0x0400;7832		sram_write(tp, 0x8fff, data);7833 7834		data = ocp_reg_read(tp, 0xacda);7835		data |= 0xff00;7836		ocp_reg_write(tp, 0xacda, data);7837		data = ocp_reg_read(tp, 0xacde);7838		data |= 0xf000;7839		ocp_reg_write(tp, 0xacde, data);7840		ocp_reg_write(tp, 0xac8c, 0x0ffc);7841		ocp_reg_write(tp, 0xac46, 0xb7b4);7842		ocp_reg_write(tp, 0xac50, 0x0fbc);7843		ocp_reg_write(tp, 0xac3c, 0x9240);7844		ocp_reg_write(tp, 0xac4e, 0x0db4);7845		ocp_reg_write(tp, 0xacc6, 0x0707);7846		ocp_reg_write(tp, 0xacc8, 0xa0d3);7847		ocp_reg_write(tp, 0xad08, 0x0007);7848 7849		ocp_reg_write(tp, 0xb87c, 0x8560);7850		ocp_reg_write(tp, 0xb87e, 0x19cc);7851		ocp_reg_write(tp, 0xb87c, 0x8562);7852		ocp_reg_write(tp, 0xb87e, 0x19cc);7853		ocp_reg_write(tp, 0xb87c, 0x8564);7854		ocp_reg_write(tp, 0xb87e, 0x19cc);7855		ocp_reg_write(tp, 0xb87c, 0x8566);7856		ocp_reg_write(tp, 0xb87e, 0x147d);7857		ocp_reg_write(tp, 0xb87c, 0x8568);7858		ocp_reg_write(tp, 0xb87e, 0x147d);7859		ocp_reg_write(tp, 0xb87c, 0x856a);7860		ocp_reg_write(tp, 0xb87e, 0x147d);7861		ocp_reg_write(tp, 0xb87c, 0x8ffe);7862		ocp_reg_write(tp, 0xb87e, 0x0907);7863		ocp_reg_write(tp, 0xb87c, 0x80d6);7864		ocp_reg_write(tp, 0xb87e, 0x2801);7865		ocp_reg_write(tp, 0xb87c, 0x80f2);7866		ocp_reg_write(tp, 0xb87e, 0x2801);7867		ocp_reg_write(tp, 0xb87c, 0x80f4);7868		ocp_reg_write(tp, 0xb87e, 0x6077);7869		ocp_reg_write(tp, 0xb506, 0x01e7);7870 7871		ocp_reg_write(tp, 0xb87c, 0x8013);7872		ocp_reg_write(tp, 0xb87e, 0x0700);7873		ocp_reg_write(tp, 0xb87c, 0x8fb9);7874		ocp_reg_write(tp, 0xb87e, 0x2801);7875		ocp_reg_write(tp, 0xb87c, 0x8fba);7876		ocp_reg_write(tp, 0xb87e, 0x0100);7877		ocp_reg_write(tp, 0xb87c, 0x8fbc);7878		ocp_reg_write(tp, 0xb87e, 0x1900);7879		ocp_reg_write(tp, 0xb87c, 0x8fbe);7880		ocp_reg_write(tp, 0xb87e, 0xe100);7881		ocp_reg_write(tp, 0xb87c, 0x8fc0);7882		ocp_reg_write(tp, 0xb87e, 0x0800);7883		ocp_reg_write(tp, 0xb87c, 0x8fc2);7884		ocp_reg_write(tp, 0xb87e, 0xe500);7885		ocp_reg_write(tp, 0xb87c, 0x8fc4);7886		ocp_reg_write(tp, 0xb87e, 0x0f00);7887		ocp_reg_write(tp, 0xb87c, 0x8fc6);7888		ocp_reg_write(tp, 0xb87e, 0xf100);7889		ocp_reg_write(tp, 0xb87c, 0x8fc8);7890		ocp_reg_write(tp, 0xb87e, 0x0400);7891		ocp_reg_write(tp, 0xb87c, 0x8fca);7892		ocp_reg_write(tp, 0xb87e, 0xf300);7893		ocp_reg_write(tp, 0xb87c, 0x8fcc);7894		ocp_reg_write(tp, 0xb87e, 0xfd00);7895		ocp_reg_write(tp, 0xb87c, 0x8fce);7896		ocp_reg_write(tp, 0xb87e, 0xff00);7897		ocp_reg_write(tp, 0xb87c, 0x8fd0);7898		ocp_reg_write(tp, 0xb87e, 0xfb00);7899		ocp_reg_write(tp, 0xb87c, 0x8fd2);7900		ocp_reg_write(tp, 0xb87e, 0x0100);7901		ocp_reg_write(tp, 0xb87c, 0x8fd4);7902		ocp_reg_write(tp, 0xb87e, 0xf400);7903		ocp_reg_write(tp, 0xb87c, 0x8fd6);7904		ocp_reg_write(tp, 0xb87e, 0xff00);7905		ocp_reg_write(tp, 0xb87c, 0x8fd8);7906		ocp_reg_write(tp, 0xb87e, 0xf600);7907 7908		ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_USB_CFG);7909		ocp_data |= EN_XG_LIP | EN_G_LIP;7910		ocp_write_byte(tp, MCU_TYPE_PLA, PLA_USB_CFG, ocp_data);7911		ocp_reg_write(tp, 0xb87c, 0x813d);7912		ocp_reg_write(tp, 0xb87e, 0x390e);7913		ocp_reg_write(tp, 0xb87c, 0x814f);7914		ocp_reg_write(tp, 0xb87e, 0x790e);7915		ocp_reg_write(tp, 0xb87c, 0x80b0);7916		ocp_reg_write(tp, 0xb87e, 0x0f31);7917		data = ocp_reg_read(tp, 0xbf4c);7918		data |= BIT(1);7919		ocp_reg_write(tp, 0xbf4c, data);7920		data = ocp_reg_read(tp, 0xbcca);7921		data |= BIT(9) | BIT(8);7922		ocp_reg_write(tp, 0xbcca, data);7923		ocp_reg_write(tp, 0xb87c, 0x8141);7924		ocp_reg_write(tp, 0xb87e, 0x320e);7925		ocp_reg_write(tp, 0xb87c, 0x8153);7926		ocp_reg_write(tp, 0xb87e, 0x720e);7927		ocp_reg_write(tp, 0xb87c, 0x8529);7928		ocp_reg_write(tp, 0xb87e, 0x050e);7929		data = ocp_reg_read(tp, OCP_EEE_CFG);7930		data &= ~CTAP_SHORT_EN;7931		ocp_reg_write(tp, OCP_EEE_CFG, data);7932 7933		sram_write(tp, 0x816c, 0xc4a0);7934		sram_write(tp, 0x8170, 0xc4a0);7935		sram_write(tp, 0x8174, 0x04a0);7936		sram_write(tp, 0x8178, 0x04a0);7937		sram_write(tp, 0x817c, 0x0719);7938		sram_write(tp, 0x8ff4, 0x0400);7939		sram_write(tp, 0x8ff1, 0x0404);7940 7941		ocp_reg_write(tp, 0xbf4a, 0x001b);7942		ocp_reg_write(tp, 0xb87c, 0x8033);7943		ocp_reg_write(tp, 0xb87e, 0x7c13);7944		ocp_reg_write(tp, 0xb87c, 0x8037);7945		ocp_reg_write(tp, 0xb87e, 0x7c13);7946		ocp_reg_write(tp, 0xb87c, 0x803b);7947		ocp_reg_write(tp, 0xb87e, 0xfc32);7948		ocp_reg_write(tp, 0xb87c, 0x803f);7949		ocp_reg_write(tp, 0xb87e, 0x7c13);7950		ocp_reg_write(tp, 0xb87c, 0x8043);7951		ocp_reg_write(tp, 0xb87e, 0x7c13);7952		ocp_reg_write(tp, 0xb87c, 0x8047);7953		ocp_reg_write(tp, 0xb87e, 0x7c13);7954 7955		ocp_reg_write(tp, 0xb87c, 0x8145);7956		ocp_reg_write(tp, 0xb87e, 0x370e);7957		ocp_reg_write(tp, 0xb87c, 0x8157);7958		ocp_reg_write(tp, 0xb87e, 0x770e);7959		ocp_reg_write(tp, 0xb87c, 0x8169);7960		ocp_reg_write(tp, 0xb87e, 0x0d0a);7961		ocp_reg_write(tp, 0xb87c, 0x817b);7962		ocp_reg_write(tp, 0xb87e, 0x1d0a);7963 7964		data = sram_read(tp, 0x8217);7965		data &= ~0xff00;7966		data |= 0x5000;7967		sram_write(tp, 0x8217, data);7968		data = sram_read(tp, 0x821a);7969		data &= ~0xff00;7970		data |= 0x5000;7971		sram_write(tp, 0x821a, data);7972		sram_write(tp, 0x80da, 0x0403);7973		data = sram_read(tp, 0x80dc);7974		data &= ~0xff00;7975		data |= 0x1000;7976		sram_write(tp, 0x80dc, data);7977		sram_write(tp, 0x80b3, 0x0384);7978		sram_write(tp, 0x80b7, 0x2007);7979		data = sram_read(tp, 0x80ba);7980		data &= ~0xff00;7981		data |= 0x6c00;7982		sram_write(tp, 0x80ba, data);7983		sram_write(tp, 0x80b5, 0xf009);7984		data = sram_read(tp, 0x80bd);7985		data &= ~0xff00;7986		data |= 0x9f00;7987		sram_write(tp, 0x80bd, data);7988		sram_write(tp, 0x80c7, 0xf083);7989		sram_write(tp, 0x80dd, 0x03f0);7990		data = sram_read(tp, 0x80df);7991		data &= ~0xff00;7992		data |= 0x1000;7993		sram_write(tp, 0x80df, data);7994		sram_write(tp, 0x80cb, 0x2007);7995		data = sram_read(tp, 0x80ce);7996		data &= ~0xff00;7997		data |= 0x6c00;7998		sram_write(tp, 0x80ce, data);7999		sram_write(tp, 0x80c9, 0x8009);8000		data = sram_read(tp, 0x80d1);8001		data &= ~0xff00;8002		data |= 0x8000;8003		sram_write(tp, 0x80d1, data);8004		sram_write(tp, 0x80a3, 0x200a);8005		sram_write(tp, 0x80a5, 0xf0ad);8006		sram_write(tp, 0x809f, 0x6073);8007		sram_write(tp, 0x80a1, 0x000b);8008		data = sram_read(tp, 0x80a9);8009		data &= ~0xff00;8010		data |= 0xc000;8011		sram_write(tp, 0x80a9, data);8012 8013		if (rtl_phy_patch_request(tp, true, true))8014			return;8015 8016		data = ocp_reg_read(tp, 0xb896);8017		data &= ~BIT(0);8018		ocp_reg_write(tp, 0xb896, data);8019		data = ocp_reg_read(tp, 0xb892);8020		data &= ~0xff00;8021		ocp_reg_write(tp, 0xb892, data);8022		ocp_reg_write(tp, 0xb88e, 0xc23e);8023		ocp_reg_write(tp, 0xb890, 0x0000);8024		ocp_reg_write(tp, 0xb88e, 0xc240);8025		ocp_reg_write(tp, 0xb890, 0x0103);8026		ocp_reg_write(tp, 0xb88e, 0xc242);8027		ocp_reg_write(tp, 0xb890, 0x0507);8028		ocp_reg_write(tp, 0xb88e, 0xc244);8029		ocp_reg_write(tp, 0xb890, 0x090b);8030		ocp_reg_write(tp, 0xb88e, 0xc246);8031		ocp_reg_write(tp, 0xb890, 0x0c0e);8032		ocp_reg_write(tp, 0xb88e, 0xc248);8033		ocp_reg_write(tp, 0xb890, 0x1012);8034		ocp_reg_write(tp, 0xb88e, 0xc24a);8035		ocp_reg_write(tp, 0xb890, 0x1416);8036		data = ocp_reg_read(tp, 0xb896);8037		data |= BIT(0);8038		ocp_reg_write(tp, 0xb896, data);8039 8040		rtl_phy_patch_request(tp, false, true);8041 8042		data = ocp_reg_read(tp, 0xa86a);8043		data |= BIT(0);8044		ocp_reg_write(tp, 0xa86a, data);8045		data = ocp_reg_read(tp, 0xa6f0);8046		data |= BIT(0);8047		ocp_reg_write(tp, 0xa6f0, data);8048 8049		ocp_reg_write(tp, 0xbfa0, 0xd70d);8050		ocp_reg_write(tp, 0xbfa2, 0x4100);8051		ocp_reg_write(tp, 0xbfa4, 0xe868);8052		ocp_reg_write(tp, 0xbfa6, 0xdc59);8053		ocp_reg_write(tp, 0xb54c, 0x3c18);8054		data = ocp_reg_read(tp, 0xbfa4);8055		data &= ~BIT(5);8056		ocp_reg_write(tp, 0xbfa4, data);8057		data = sram_read(tp, 0x817d);8058		data |= BIT(12);8059		sram_write(tp, 0x817d, data);8060		break;8061	case RTL_VER_13:8062		/* 2.5G INRX */8063		data = ocp_reg_read(tp, 0xac46);8064		data &= ~0x00f0;8065		data |= 0x0090;8066		ocp_reg_write(tp, 0xac46, data);8067		data = ocp_reg_read(tp, 0xad30);8068		data &= ~0x0003;8069		data |= 0x0001;8070		ocp_reg_write(tp, 0xad30, data);8071		fallthrough;8072	case RTL_VER_15:8073		/* EEE parameter */8074		ocp_reg_write(tp, 0xb87c, 0x80f5);8075		ocp_reg_write(tp, 0xb87e, 0x760e);8076		ocp_reg_write(tp, 0xb87c, 0x8107);8077		ocp_reg_write(tp, 0xb87e, 0x360e);8078		ocp_reg_write(tp, 0xb87c, 0x8551);8079		data = ocp_reg_read(tp, 0xb87e);8080		data &= ~0xff00;8081		data |= 0x0800;8082		ocp_reg_write(tp, 0xb87e, data);8083 8084		/* ADC_PGA parameter */8085		data = ocp_reg_read(tp, 0xbf00);8086		data &= ~0xe000;8087		data |= 0xa000;8088		ocp_reg_write(tp, 0xbf00, data);8089		data = ocp_reg_read(tp, 0xbf46);8090		data &= ~0x0f00;8091		data |= 0x0300;8092		ocp_reg_write(tp, 0xbf46, data);8093 8094		/* Green Table-PGA, 1G full viterbi */8095		sram_write(tp, 0x8044, 0x2417);8096		sram_write(tp, 0x804a, 0x2417);8097		sram_write(tp, 0x8050, 0x2417);8098		sram_write(tp, 0x8056, 0x2417);8099		sram_write(tp, 0x805c, 0x2417);8100		sram_write(tp, 0x8062, 0x2417);8101		sram_write(tp, 0x8068, 0x2417);8102		sram_write(tp, 0x806e, 0x2417);8103		sram_write(tp, 0x8074, 0x2417);8104		sram_write(tp, 0x807a, 0x2417);8105 8106		/* XG PLL */8107		data = ocp_reg_read(tp, 0xbf84);8108		data &= ~0xe000;8109		data |= 0xa000;8110		ocp_reg_write(tp, 0xbf84, data);8111		break;8112	default:8113		break;8114	}8115 8116	/* Notify the MAC when the speed is changed to force mode. */8117	data = ocp_reg_read(tp, OCP_INTR_EN);8118	data |= INTR_SPEED_FORCE;8119	ocp_reg_write(tp, OCP_INTR_EN, data);8120 8121	if (rtl_phy_patch_request(tp, true, true))8122		return;8123 8124	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);8125	ocp_data |= EEE_SPDWN_EN;8126	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);8127 8128	data = ocp_reg_read(tp, OCP_DOWN_SPEED);8129	data &= ~(EN_EEE_100 | EN_EEE_1000);8130	data |= EN_10M_CLKDIV;8131	ocp_reg_write(tp, OCP_DOWN_SPEED, data);8132	tp->ups_info._10m_ckdiv = true;8133	tp->ups_info.eee_plloff_100 = false;8134	tp->ups_info.eee_plloff_giga = false;8135 8136	data = ocp_reg_read(tp, OCP_POWER_CFG);8137	data &= ~EEE_CLKDIV_EN;8138	ocp_reg_write(tp, OCP_POWER_CFG, data);8139	tp->ups_info.eee_ckdiv = false;8140 8141	rtl_phy_patch_request(tp, false, true);8142 8143	rtl_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));8144 8145	data = ocp_reg_read(tp, 0xa428);8146	data &= ~BIT(9);8147	ocp_reg_write(tp, 0xa428, data);8148	data = ocp_reg_read(tp, 0xa5ea);8149	data &= ~BIT(0);8150	ocp_reg_write(tp, 0xa5ea, data);8151	tp->ups_info.lite_mode = 0;8152 8153	if (tp->eee_en)8154		rtl_eee_enable(tp, true);8155 8156	r8153_aldps_en(tp, true);8157	r8152b_enable_fc(tp);8158	r8153_u2p3en(tp, true);8159 8160	set_bit(PHY_RESET, &tp->flags);8161}8162 8163static void r8156_init(struct r8152 *tp)8164{8165	u32 ocp_data;8166	u16 data;8167	int i;8168 8169	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))8170		return;8171 8172	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_ECM_OP);8173	ocp_data &= ~EN_ALL_SPEED;8174	ocp_write_byte(tp, MCU_TYPE_USB, USB_ECM_OP, ocp_data);8175 8176	ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, 0);8177 8178	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_ECM_OPTION);8179	ocp_data |= BYPASS_MAC_RESET;8180	ocp_write_word(tp, MCU_TYPE_USB, USB_ECM_OPTION, ocp_data);8181 8182	r8153b_u1u2en(tp, false);8183 8184	for (i = 0; i < 500; i++) {8185		if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &8186		    AUTOLOAD_DONE)8187			break;8188 8189		msleep(20);8190		if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))8191			return;8192	}8193 8194	data = r8153_phy_status(tp, 0);8195	if (data == PHY_STAT_EXT_INIT) {8196		data = ocp_reg_read(tp, 0xa468);8197		data &= ~(BIT(3) | BIT(1));8198		ocp_reg_write(tp, 0xa468, data);8199	}8200 8201	data = r8152_mdio_read(tp, MII_BMCR);8202	if (data & BMCR_PDOWN) {8203		data &= ~BMCR_PDOWN;8204		r8152_mdio_write(tp, MII_BMCR, data);8205	}8206 8207	data = r8153_phy_status(tp, PHY_STAT_LAN_ON);8208	WARN_ON_ONCE(data != PHY_STAT_LAN_ON);8209 8210	r8153_u2p3en(tp, false);8211 8212	/* MSC timer = 0xfff * 8ms = 32760 ms */8213	ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);8214 8215	/* U1/U2/L1 idle timer. 500 us */8216	ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500);8217 8218	r8153b_power_cut_en(tp, false);8219	r8156_ups_en(tp, false);8220	r8153_queue_wake(tp, false);8221	rtl_runtime_suspend_enable(tp, false);8222 8223	if (tp->udev->speed >= USB_SPEED_SUPER)8224		r8153b_u1u2en(tp, true);8225 8226	usb_enable_lpm(tp->udev);8227 8228	r8156_mac_clk_spd(tp, true);8229 8230	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);8231	ocp_data &= ~PLA_MCU_SPDWN_EN;8232	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);8233 8234	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);8235	if (rtl8152_get_speed(tp) & LINK_STATUS)8236		ocp_data |= CUR_LINK_OK;8237	else8238		ocp_data &= ~CUR_LINK_OK;8239	ocp_data |= POLL_LINK_CHG;8240	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);8241 8242	set_bit(GREEN_ETHERNET, &tp->flags);8243 8244	/* rx aggregation */8245	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);8246	ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);8247	ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);8248 8249	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_CONFIG);8250	ocp_data |= ACT_ODMA;8251	ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_CONFIG, ocp_data);8252 8253	r8156_mdio_force_mode(tp);8254	rtl_tally_reset(tp);8255 8256	tp->coalesce = 15000;	/* 15 us */8257}8258 8259static void r8156b_init(struct r8152 *tp)8260{8261	u32 ocp_data;8262	u16 data;8263	int i;8264 8265	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))8266		return;8267 8268	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_ECM_OP);8269	ocp_data &= ~EN_ALL_SPEED;8270	ocp_write_byte(tp, MCU_TYPE_USB, USB_ECM_OP, ocp_data);8271 8272	ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, 0);8273 8274	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_ECM_OPTION);8275	ocp_data |= BYPASS_MAC_RESET;8276	ocp_write_word(tp, MCU_TYPE_USB, USB_ECM_OPTION, ocp_data);8277 8278	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);8279	ocp_data |= RX_DETECT8;8280	ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);8281 8282	r8153b_u1u2en(tp, false);8283 8284	switch (tp->version) {8285	case RTL_VER_13:8286	case RTL_VER_15:8287		r8156b_wait_loading_flash(tp);8288		break;8289	default:8290		break;8291	}8292 8293	for (i = 0; i < 500; i++) {8294		if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &8295		    AUTOLOAD_DONE)8296			break;8297 8298		msleep(20);8299		if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))8300			return;8301	}8302 8303	data = r8153_phy_status(tp, 0);8304	if (data == PHY_STAT_EXT_INIT) {8305		data = ocp_reg_read(tp, 0xa468);8306		data &= ~(BIT(3) | BIT(1));8307		ocp_reg_write(tp, 0xa468, data);8308 8309		data = ocp_reg_read(tp, 0xa466);8310		data &= ~BIT(0);8311		ocp_reg_write(tp, 0xa466, data);8312	}8313 8314	data = r8152_mdio_read(tp, MII_BMCR);8315	if (data & BMCR_PDOWN) {8316		data &= ~BMCR_PDOWN;8317		r8152_mdio_write(tp, MII_BMCR, data);8318	}8319 8320	data = r8153_phy_status(tp, PHY_STAT_LAN_ON);8321 8322	r8153_u2p3en(tp, false);8323 8324	/* MSC timer = 0xfff * 8ms = 32760 ms */8325	ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);8326 8327	/* U1/U2/L1 idle timer. 500 us */8328	ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500);8329 8330	r8153b_power_cut_en(tp, false);8331	r8156_ups_en(tp, false);8332	r8153_queue_wake(tp, false);8333	rtl_runtime_suspend_enable(tp, false);8334 8335	if (tp->udev->speed >= USB_SPEED_SUPER)8336		r8153b_u1u2en(tp, true);8337 8338	usb_enable_lpm(tp->udev);8339 8340	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RCR);8341	ocp_data &= ~SLOT_EN;8342	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);8343 8344	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);8345	ocp_data |= FLOW_CTRL_EN;8346	ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);8347 8348	/* enable fc timer and set timer to 600 ms. */8349	ocp_write_word(tp, MCU_TYPE_USB, USB_FC_TIMER,8350		       CTRL_TIMER_EN | (600 / 8));8351 8352	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL);8353	if (!(ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL) & DACK_DET_EN))8354		ocp_data |= FLOW_CTRL_PATCH_2;8355	ocp_data &= ~AUTO_SPEEDUP;8356	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data);8357 8358	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);8359	ocp_data |= FC_PATCH_TASK;8360	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);8361 8362	r8156_mac_clk_spd(tp, true);8363 8364	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);8365	ocp_data &= ~PLA_MCU_SPDWN_EN;8366	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);8367 8368	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);8369	if (rtl8152_get_speed(tp) & LINK_STATUS)8370		ocp_data |= CUR_LINK_OK;8371	else8372		ocp_data &= ~CUR_LINK_OK;8373	ocp_data |= POLL_LINK_CHG;8374	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);8375 8376	set_bit(GREEN_ETHERNET, &tp->flags);8377 8378	/* rx aggregation */8379	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);8380	ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);8381	ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);8382 8383	r8156_mdio_force_mode(tp);8384	rtl_tally_reset(tp);8385 8386	tp->coalesce = 15000;	/* 15 us */8387}8388 8389static bool rtl_check_vendor_ok(struct usb_interface *intf)8390{8391	struct usb_host_interface *alt = intf->cur_altsetting;8392	struct usb_endpoint_descriptor *in, *out, *intr;8393 8394	if (usb_find_common_endpoints(alt, &in, &out, &intr, NULL) < 0) {8395		dev_err(&intf->dev, "Expected endpoints are not found\n");8396		return false;8397	}8398 8399	/* Check Rx endpoint address */8400	if (usb_endpoint_num(in) != 1) {8401		dev_err(&intf->dev, "Invalid Rx endpoint address\n");8402		return false;8403	}8404 8405	/* Check Tx endpoint address */8406	if (usb_endpoint_num(out) != 2) {8407		dev_err(&intf->dev, "Invalid Tx endpoint address\n");8408		return false;8409	}8410 8411	/* Check interrupt endpoint address */8412	if (usb_endpoint_num(intr) != 3) {8413		dev_err(&intf->dev, "Invalid interrupt endpoint address\n");8414		return false;8415	}8416 8417	return true;8418}8419 8420static int rtl8152_pre_reset(struct usb_interface *intf)8421{8422	struct r8152 *tp = usb_get_intfdata(intf);8423	struct net_device *netdev;8424 8425	rtnl_lock();8426 8427	if (!tp || !test_bit(PROBED_WITH_NO_ERRORS, &tp->flags))8428		return 0;8429 8430	netdev = tp->netdev;8431	if (!netif_running(netdev))8432		return 0;8433 8434	netif_stop_queue(netdev);8435	tasklet_disable(&tp->tx_tl);8436	clear_bit(WORK_ENABLE, &tp->flags);8437	usb_kill_urb(tp->intr_urb);8438	cancel_delayed_work_sync(&tp->schedule);8439	napi_disable(&tp->napi);8440	if (netif_carrier_ok(netdev)) {8441		mutex_lock(&tp->control);8442		set_bit(IN_PRE_RESET, &tp->flags);8443		tp->rtl_ops.disable(tp);8444		clear_bit(IN_PRE_RESET, &tp->flags);8445		mutex_unlock(&tp->control);8446	}8447 8448	return 0;8449}8450 8451static int rtl8152_post_reset(struct usb_interface *intf)8452{8453	struct r8152 *tp = usb_get_intfdata(intf);8454	struct net_device *netdev;8455	struct sockaddr sa;8456 8457	if (!tp || !test_bit(PROBED_WITH_NO_ERRORS, &tp->flags))8458		goto exit;8459 8460	rtl_set_accessible(tp);8461 8462	/* reset the MAC address in case of policy change */8463	if (determine_ethernet_addr(tp, &sa) >= 0)8464		dev_set_mac_address (tp->netdev, &sa, NULL);8465 8466	netdev = tp->netdev;8467	if (!netif_running(netdev))8468		goto exit;8469 8470	set_bit(WORK_ENABLE, &tp->flags);8471	if (netif_carrier_ok(netdev)) {8472		mutex_lock(&tp->control);8473		tp->rtl_ops.enable(tp);8474		rtl_start_rx(tp);8475		_rtl8152_set_rx_mode(netdev);8476		mutex_unlock(&tp->control);8477	}8478 8479	napi_enable(&tp->napi);8480	tasklet_enable(&tp->tx_tl);8481	netif_wake_queue(netdev);8482	usb_submit_urb(tp->intr_urb, GFP_KERNEL);8483 8484	if (!list_empty(&tp->rx_done))8485		napi_schedule(&tp->napi);8486 8487exit:8488	rtnl_unlock();8489	return 0;8490}8491 8492static bool delay_autosuspend(struct r8152 *tp)8493{8494	bool sw_linking = !!netif_carrier_ok(tp->netdev);8495	bool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS);8496 8497	/* This means a linking change occurs and the driver doesn't detect it,8498	 * yet. If the driver has disabled tx/rx and hw is linking on, the8499	 * device wouldn't wake up by receiving any packet.8500	 */8501	if (work_busy(&tp->schedule.work) || sw_linking != hw_linking)8502		return true;8503 8504	/* If the linking down is occurred by nway, the device may miss the8505	 * linking change event. And it wouldn't wake when linking on.8506	 */8507	if (!sw_linking && tp->rtl_ops.in_nway(tp))8508		return true;8509	else if (!skb_queue_empty(&tp->tx_queue))8510		return true;8511	else8512		return false;8513}8514 8515static int rtl8152_runtime_resume(struct r8152 *tp)8516{8517	struct net_device *netdev = tp->netdev;8518 8519	if (netif_running(netdev) && netdev->flags & IFF_UP) {8520		struct napi_struct *napi = &tp->napi;8521 8522		tp->rtl_ops.autosuspend_en(tp, false);8523		napi_disable(napi);8524		set_bit(WORK_ENABLE, &tp->flags);8525 8526		if (netif_carrier_ok(netdev)) {8527			if (rtl8152_get_speed(tp) & LINK_STATUS) {8528				rtl_start_rx(tp);8529			} else {8530				netif_carrier_off(netdev);8531				tp->rtl_ops.disable(tp);8532				netif_info(tp, link, netdev, "linking down\n");8533			}8534		}8535 8536		napi_enable(napi);8537		clear_bit(SELECTIVE_SUSPEND, &tp->flags);8538		smp_mb__after_atomic();8539 8540		if (!list_empty(&tp->rx_done))8541			napi_schedule(&tp->napi);8542 8543		usb_submit_urb(tp->intr_urb, GFP_NOIO);8544	} else {8545		if (netdev->flags & IFF_UP)8546			tp->rtl_ops.autosuspend_en(tp, false);8547 8548		clear_bit(SELECTIVE_SUSPEND, &tp->flags);8549	}8550 8551	return 0;8552}8553 8554static int rtl8152_system_resume(struct r8152 *tp)8555{8556	struct net_device *netdev = tp->netdev;8557 8558	netif_device_attach(netdev);8559 8560	if (netif_running(netdev) && (netdev->flags & IFF_UP)) {8561		tp->rtl_ops.up(tp);8562		netif_carrier_off(netdev);8563		set_bit(WORK_ENABLE, &tp->flags);8564		usb_submit_urb(tp->intr_urb, GFP_NOIO);8565	}8566 8567	/* If the device is RTL8152_INACCESSIBLE here then we should do a8568	 * reset. This is important because the usb_lock_device_for_reset()8569	 * that happens as a result of usb_queue_reset_device() will silently8570	 * fail if the device was suspended or if too much time passed.8571	 *8572	 * NOTE: The device is locked here so we can directly do the reset.8573	 * We don't need usb_lock_device_for_reset() because that's just a8574	 * wrapper over device_lock() and device_resume() (which calls us)8575	 * does that for us.8576	 */8577	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))8578		usb_reset_device(tp->udev);8579 8580	return 0;8581}8582 8583static int rtl8152_runtime_suspend(struct r8152 *tp)8584{8585	struct net_device *netdev = tp->netdev;8586	int ret = 0;8587 8588	if (!tp->rtl_ops.autosuspend_en)8589		return -EBUSY;8590 8591	set_bit(SELECTIVE_SUSPEND, &tp->flags);8592	smp_mb__after_atomic();8593 8594	if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {8595		u32 rcr = 0;8596 8597		if (netif_carrier_ok(netdev)) {8598			u32 ocp_data;8599 8600			rcr = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);8601			ocp_data = rcr & ~RCR_ACPT_ALL;8602			ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);8603			rxdy_gated_en(tp, true);8604			ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA,8605						 PLA_OOB_CTRL);8606			if (!(ocp_data & RXFIFO_EMPTY)) {8607				rxdy_gated_en(tp, false);8608				ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);8609				clear_bit(SELECTIVE_SUSPEND, &tp->flags);8610				smp_mb__after_atomic();8611				ret = -EBUSY;8612				goto out1;8613			}8614		}8615 8616		clear_bit(WORK_ENABLE, &tp->flags);8617		usb_kill_urb(tp->intr_urb);8618 8619		tp->rtl_ops.autosuspend_en(tp, true);8620 8621		if (netif_carrier_ok(netdev)) {8622			struct napi_struct *napi = &tp->napi;8623 8624			napi_disable(napi);8625			rtl_stop_rx(tp);8626			rxdy_gated_en(tp, false);8627			ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);8628			napi_enable(napi);8629		}8630 8631		if (delay_autosuspend(tp)) {8632			rtl8152_runtime_resume(tp);8633			ret = -EBUSY;8634		}8635	}8636 8637out1:8638	return ret;8639}8640 8641static int rtl8152_system_suspend(struct r8152 *tp)8642{8643	struct net_device *netdev = tp->netdev;8644 8645	netif_device_detach(netdev);8646 8647	if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {8648		struct napi_struct *napi = &tp->napi;8649 8650		clear_bit(WORK_ENABLE, &tp->flags);8651		usb_kill_urb(tp->intr_urb);8652		tasklet_disable(&tp->tx_tl);8653		napi_disable(napi);8654		cancel_delayed_work_sync(&tp->schedule);8655		tp->rtl_ops.down(tp);8656		napi_enable(napi);8657		tasklet_enable(&tp->tx_tl);8658	}8659 8660	/* If we're inaccessible here then some of the work that we did to8661	 * get the adapter ready for suspend didn't work. Queue up a wakeup8662	 * event so we can try again.8663	 */8664	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))8665		pm_wakeup_event(&tp->udev->dev, 0);8666 8667	return 0;8668}8669 8670static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)8671{8672	struct r8152 *tp = usb_get_intfdata(intf);8673	int ret;8674 8675	mutex_lock(&tp->control);8676 8677	if (PMSG_IS_AUTO(message))8678		ret = rtl8152_runtime_suspend(tp);8679	else8680		ret = rtl8152_system_suspend(tp);8681 8682	mutex_unlock(&tp->control);8683 8684	return ret;8685}8686 8687static int rtl8152_resume(struct usb_interface *intf)8688{8689	struct r8152 *tp = usb_get_intfdata(intf);8690	int ret;8691 8692	mutex_lock(&tp->control);8693 8694	rtl_reset_ocp_base(tp);8695 8696	if (test_bit(SELECTIVE_SUSPEND, &tp->flags))8697		ret = rtl8152_runtime_resume(tp);8698	else8699		ret = rtl8152_system_resume(tp);8700 8701	mutex_unlock(&tp->control);8702 8703	return ret;8704}8705 8706static int rtl8152_reset_resume(struct usb_interface *intf)8707{8708	struct r8152 *tp = usb_get_intfdata(intf);8709 8710	clear_bit(SELECTIVE_SUSPEND, &tp->flags);8711	rtl_reset_ocp_base(tp);8712	tp->rtl_ops.init(tp);8713	queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);8714	set_ethernet_addr(tp, true);8715	return rtl8152_resume(intf);8716}8717 8718static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)8719{8720	struct r8152 *tp = netdev_priv(dev);8721 8722	if (usb_autopm_get_interface(tp->intf) < 0)8723		return;8724 8725	if (!rtl_can_wakeup(tp)) {8726		wol->supported = 0;8727		wol->wolopts = 0;8728	} else {8729		mutex_lock(&tp->control);8730		wol->supported = WAKE_ANY;8731		wol->wolopts = __rtl_get_wol(tp);8732		mutex_unlock(&tp->control);8733	}8734 8735	usb_autopm_put_interface(tp->intf);8736}8737 8738static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)8739{8740	struct r8152 *tp = netdev_priv(dev);8741	int ret;8742 8743	if (!rtl_can_wakeup(tp))8744		return -EOPNOTSUPP;8745 8746	if (wol->wolopts & ~WAKE_ANY)8747		return -EINVAL;8748 8749	ret = usb_autopm_get_interface(tp->intf);8750	if (ret < 0)8751		goto out_set_wol;8752 8753	mutex_lock(&tp->control);8754 8755	__rtl_set_wol(tp, wol->wolopts);8756	tp->saved_wolopts = wol->wolopts & WAKE_ANY;8757 8758	mutex_unlock(&tp->control);8759 8760	usb_autopm_put_interface(tp->intf);8761 8762out_set_wol:8763	return ret;8764}8765 8766static u32 rtl8152_get_msglevel(struct net_device *dev)8767{8768	struct r8152 *tp = netdev_priv(dev);8769 8770	return tp->msg_enable;8771}8772 8773static void rtl8152_set_msglevel(struct net_device *dev, u32 value)8774{8775	struct r8152 *tp = netdev_priv(dev);8776 8777	tp->msg_enable = value;8778}8779 8780static void rtl8152_get_drvinfo(struct net_device *netdev,8781				struct ethtool_drvinfo *info)8782{8783	struct r8152 *tp = netdev_priv(netdev);8784 8785	strscpy(info->driver, MODULENAME, sizeof(info->driver));8786	strscpy(info->version, DRIVER_VERSION, sizeof(info->version));8787	usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));8788	if (!IS_ERR_OR_NULL(tp->rtl_fw.fw))8789		strscpy(info->fw_version, tp->rtl_fw.version,8790			sizeof(info->fw_version));8791}8792 8793static8794int rtl8152_get_link_ksettings(struct net_device *netdev,8795			       struct ethtool_link_ksettings *cmd)8796{8797	struct r8152 *tp = netdev_priv(netdev);8798	int ret;8799 8800	if (!tp->mii.mdio_read)8801		return -EOPNOTSUPP;8802 8803	ret = usb_autopm_get_interface(tp->intf);8804	if (ret < 0)8805		goto out;8806 8807	mutex_lock(&tp->control);8808 8809	mii_ethtool_get_link_ksettings(&tp->mii, cmd);8810 8811	linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,8812			 cmd->link_modes.supported, tp->support_2500full);8813 8814	if (tp->support_2500full) {8815		linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,8816				 cmd->link_modes.advertising,8817				 ocp_reg_read(tp, OCP_10GBT_CTRL) & MDIO_AN_10GBT_CTRL_ADV2_5G);8818 8819		linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,8820				 cmd->link_modes.lp_advertising,8821				 ocp_reg_read(tp, OCP_10GBT_STAT) & MDIO_AN_10GBT_STAT_LP2_5G);8822 8823		if (is_speed_2500(rtl8152_get_speed(tp)))8824			cmd->base.speed = SPEED_2500;8825	}8826 8827	mutex_unlock(&tp->control);8828 8829	usb_autopm_put_interface(tp->intf);8830 8831out:8832	return ret;8833}8834 8835static int rtl8152_set_link_ksettings(struct net_device *dev,8836				      const struct ethtool_link_ksettings *cmd)8837{8838	struct r8152 *tp = netdev_priv(dev);8839	u32 advertising = 0;8840	int ret;8841 8842	ret = usb_autopm_get_interface(tp->intf);8843	if (ret < 0)8844		goto out;8845 8846	if (test_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT,8847		     cmd->link_modes.advertising))8848		advertising |= RTL_ADVERTISED_10_HALF;8849 8850	if (test_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,8851		     cmd->link_modes.advertising))8852		advertising |= RTL_ADVERTISED_10_FULL;8853 8854	if (test_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT,8855		     cmd->link_modes.advertising))8856		advertising |= RTL_ADVERTISED_100_HALF;8857 8858	if (test_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,8859		     cmd->link_modes.advertising))8860		advertising |= RTL_ADVERTISED_100_FULL;8861 8862	if (test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,8863		     cmd->link_modes.advertising))8864		advertising |= RTL_ADVERTISED_1000_HALF;8865 8866	if (test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,8867		     cmd->link_modes.advertising))8868		advertising |= RTL_ADVERTISED_1000_FULL;8869 8870	if (test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,8871		     cmd->link_modes.advertising))8872		advertising |= RTL_ADVERTISED_2500_FULL;8873 8874	mutex_lock(&tp->control);8875 8876	ret = rtl8152_set_speed(tp, cmd->base.autoneg, cmd->base.speed,8877				cmd->base.duplex, advertising);8878	if (!ret) {8879		tp->autoneg = cmd->base.autoneg;8880		tp->speed = cmd->base.speed;8881		tp->duplex = cmd->base.duplex;8882		tp->advertising = advertising;8883	}8884 8885	mutex_unlock(&tp->control);8886 8887	usb_autopm_put_interface(tp->intf);8888 8889out:8890	return ret;8891}8892 8893static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {8894	"tx_packets",8895	"rx_packets",8896	"tx_errors",8897	"rx_errors",8898	"rx_missed",8899	"align_errors",8900	"tx_single_collisions",8901	"tx_multi_collisions",8902	"rx_unicast",8903	"rx_broadcast",8904	"rx_multicast",8905	"tx_aborted",8906	"tx_underrun",8907};8908 8909static int rtl8152_get_sset_count(struct net_device *dev, int sset)8910{8911	switch (sset) {8912	case ETH_SS_STATS:8913		return ARRAY_SIZE(rtl8152_gstrings);8914	default:8915		return -EOPNOTSUPP;8916	}8917}8918 8919static void rtl8152_get_ethtool_stats(struct net_device *dev,8920				      struct ethtool_stats *stats, u64 *data)8921{8922	struct r8152 *tp = netdev_priv(dev);8923	struct tally_counter tally;8924 8925	if (usb_autopm_get_interface(tp->intf) < 0)8926		return;8927 8928	generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);8929 8930	usb_autopm_put_interface(tp->intf);8931 8932	data[0] = le64_to_cpu(tally.tx_packets);8933	data[1] = le64_to_cpu(tally.rx_packets);8934	data[2] = le64_to_cpu(tally.tx_errors);8935	data[3] = le32_to_cpu(tally.rx_errors);8936	data[4] = le16_to_cpu(tally.rx_missed);8937	data[5] = le16_to_cpu(tally.align_errors);8938	data[6] = le32_to_cpu(tally.tx_one_collision);8939	data[7] = le32_to_cpu(tally.tx_multi_collision);8940	data[8] = le64_to_cpu(tally.rx_unicast);8941	data[9] = le64_to_cpu(tally.rx_broadcast);8942	data[10] = le32_to_cpu(tally.rx_multicast);8943	data[11] = le16_to_cpu(tally.tx_aborted);8944	data[12] = le16_to_cpu(tally.tx_underrun);8945}8946 8947static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)8948{8949	switch (stringset) {8950	case ETH_SS_STATS:8951		memcpy(data, rtl8152_gstrings, sizeof(rtl8152_gstrings));8952		break;8953	}8954}8955 8956static int r8152_get_eee(struct r8152 *tp, struct ethtool_keee *eee)8957{8958	__ETHTOOL_DECLARE_LINK_MODE_MASK(common);8959	u16 val;8960 8961	val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);8962	mii_eee_cap1_mod_linkmode_t(eee->supported, val);8963 8964	val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV);8965	mii_eee_cap1_mod_linkmode_t(eee->advertised, val);8966 8967	val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);8968	mii_eee_cap1_mod_linkmode_t(eee->lp_advertised, val);8969 8970	eee->eee_enabled = tp->eee_en;8971 8972	linkmode_and(common, eee->advertised, eee->lp_advertised);8973	eee->eee_active = phy_check_valid(tp->speed, tp->duplex, common);8974 8975	return 0;8976}8977 8978static int r8152_set_eee(struct r8152 *tp, struct ethtool_keee *eee)8979{8980	u16 val = linkmode_to_mii_eee_cap1_t(eee->advertised);8981 8982	tp->eee_en = eee->eee_enabled;8983	tp->eee_adv = val;8984 8985	rtl_eee_enable(tp, tp->eee_en);8986 8987	return 0;8988}8989 8990static int r8153_get_eee(struct r8152 *tp, struct ethtool_keee *eee)8991{8992	__ETHTOOL_DECLARE_LINK_MODE_MASK(common);8993	u16 val;8994 8995	val = ocp_reg_read(tp, OCP_EEE_ABLE);8996	mii_eee_cap1_mod_linkmode_t(eee->supported, val);8997 8998	val = ocp_reg_read(tp, OCP_EEE_ADV);8999	mii_eee_cap1_mod_linkmode_t(eee->advertised, val);9000 9001	val = ocp_reg_read(tp, OCP_EEE_LPABLE);9002	mii_eee_cap1_mod_linkmode_t(eee->lp_advertised, val);9003 9004	eee->eee_enabled = tp->eee_en;9005 9006	linkmode_and(common, eee->advertised, eee->lp_advertised);9007	eee->eee_active = phy_check_valid(tp->speed, tp->duplex, common);9008 9009	return 0;9010}9011 9012static int9013rtl_ethtool_get_eee(struct net_device *net, struct ethtool_keee *edata)9014{9015	struct r8152 *tp = netdev_priv(net);9016	int ret;9017 9018	if (!tp->rtl_ops.eee_get) {9019		ret = -EOPNOTSUPP;9020		goto out;9021	}9022 9023	ret = usb_autopm_get_interface(tp->intf);9024	if (ret < 0)9025		goto out;9026 9027	mutex_lock(&tp->control);9028 9029	ret = tp->rtl_ops.eee_get(tp, edata);9030 9031	mutex_unlock(&tp->control);9032 9033	usb_autopm_put_interface(tp->intf);9034 9035out:9036	return ret;9037}9038 9039static int9040rtl_ethtool_set_eee(struct net_device *net, struct ethtool_keee *edata)9041{9042	struct r8152 *tp = netdev_priv(net);9043	int ret;9044 9045	if (!tp->rtl_ops.eee_set) {9046		ret = -EOPNOTSUPP;9047		goto out;9048	}9049 9050	ret = usb_autopm_get_interface(tp->intf);9051	if (ret < 0)9052		goto out;9053 9054	mutex_lock(&tp->control);9055 9056	ret = tp->rtl_ops.eee_set(tp, edata);9057	if (!ret)9058		ret = mii_nway_restart(&tp->mii);9059 9060	mutex_unlock(&tp->control);9061 9062	usb_autopm_put_interface(tp->intf);9063 9064out:9065	return ret;9066}9067 9068static int rtl8152_nway_reset(struct net_device *dev)9069{9070	struct r8152 *tp = netdev_priv(dev);9071	int ret;9072 9073	ret = usb_autopm_get_interface(tp->intf);9074	if (ret < 0)9075		goto out;9076 9077	mutex_lock(&tp->control);9078 9079	ret = mii_nway_restart(&tp->mii);9080 9081	mutex_unlock(&tp->control);9082 9083	usb_autopm_put_interface(tp->intf);9084 9085out:9086	return ret;9087}9088 9089static int rtl8152_get_coalesce(struct net_device *netdev,9090				struct ethtool_coalesce *coalesce,9091				struct kernel_ethtool_coalesce *kernel_coal,9092				struct netlink_ext_ack *extack)9093{9094	struct r8152 *tp = netdev_priv(netdev);9095 9096	switch (tp->version) {9097	case RTL_VER_01:9098	case RTL_VER_02:9099	case RTL_VER_07:9100		return -EOPNOTSUPP;9101	default:9102		break;9103	}9104 9105	coalesce->rx_coalesce_usecs = tp->coalesce;9106 9107	return 0;9108}9109 9110static int rtl8152_set_coalesce(struct net_device *netdev,9111				struct ethtool_coalesce *coalesce,9112				struct kernel_ethtool_coalesce *kernel_coal,9113				struct netlink_ext_ack *extack)9114{9115	struct r8152 *tp = netdev_priv(netdev);9116	int ret;9117 9118	switch (tp->version) {9119	case RTL_VER_01:9120	case RTL_VER_02:9121	case RTL_VER_07:9122		return -EOPNOTSUPP;9123	default:9124		break;9125	}9126 9127	if (coalesce->rx_coalesce_usecs > COALESCE_SLOW)9128		return -EINVAL;9129 9130	ret = usb_autopm_get_interface(tp->intf);9131	if (ret < 0)9132		return ret;9133 9134	mutex_lock(&tp->control);9135 9136	if (tp->coalesce != coalesce->rx_coalesce_usecs) {9137		tp->coalesce = coalesce->rx_coalesce_usecs;9138 9139		if (netif_running(netdev) && netif_carrier_ok(netdev)) {9140			netif_stop_queue(netdev);9141			napi_disable(&tp->napi);9142			tp->rtl_ops.disable(tp);9143			tp->rtl_ops.enable(tp);9144			rtl_start_rx(tp);9145			clear_bit(RTL8152_SET_RX_MODE, &tp->flags);9146			_rtl8152_set_rx_mode(netdev);9147			napi_enable(&tp->napi);9148			netif_wake_queue(netdev);9149		}9150	}9151 9152	mutex_unlock(&tp->control);9153 9154	usb_autopm_put_interface(tp->intf);9155 9156	return ret;9157}9158 9159static int rtl8152_get_tunable(struct net_device *netdev,9160			       const struct ethtool_tunable *tunable, void *d)9161{9162	struct r8152 *tp = netdev_priv(netdev);9163 9164	switch (tunable->id) {9165	case ETHTOOL_RX_COPYBREAK:9166		*(u32 *)d = tp->rx_copybreak;9167		break;9168	default:9169		return -EOPNOTSUPP;9170	}9171 9172	return 0;9173}9174 9175static int rtl8152_set_tunable(struct net_device *netdev,9176			       const struct ethtool_tunable *tunable,9177			       const void *d)9178{9179	struct r8152 *tp = netdev_priv(netdev);9180	u32 val;9181 9182	switch (tunable->id) {9183	case ETHTOOL_RX_COPYBREAK:9184		val = *(u32 *)d;9185		if (val < ETH_ZLEN) {9186			netif_err(tp, rx_err, netdev,9187				  "Invalid rx copy break value\n");9188			return -EINVAL;9189		}9190 9191		if (tp->rx_copybreak != val) {9192			if (netdev->flags & IFF_UP) {9193				mutex_lock(&tp->control);9194				napi_disable(&tp->napi);9195				tp->rx_copybreak = val;9196				napi_enable(&tp->napi);9197				mutex_unlock(&tp->control);9198			} else {9199				tp->rx_copybreak = val;9200			}9201		}9202		break;9203	default:9204		return -EOPNOTSUPP;9205	}9206 9207	return 0;9208}9209 9210static void rtl8152_get_ringparam(struct net_device *netdev,9211				  struct ethtool_ringparam *ring,9212				  struct kernel_ethtool_ringparam *kernel_ring,9213				  struct netlink_ext_ack *extack)9214{9215	struct r8152 *tp = netdev_priv(netdev);9216 9217	ring->rx_max_pending = RTL8152_RX_MAX_PENDING;9218	ring->rx_pending = tp->rx_pending;9219}9220 9221static int rtl8152_set_ringparam(struct net_device *netdev,9222				 struct ethtool_ringparam *ring,9223				 struct kernel_ethtool_ringparam *kernel_ring,9224				 struct netlink_ext_ack *extack)9225{9226	struct r8152 *tp = netdev_priv(netdev);9227 9228	if (ring->rx_pending < (RTL8152_MAX_RX * 2))9229		return -EINVAL;9230 9231	if (tp->rx_pending != ring->rx_pending) {9232		if (netdev->flags & IFF_UP) {9233			mutex_lock(&tp->control);9234			napi_disable(&tp->napi);9235			tp->rx_pending = ring->rx_pending;9236			napi_enable(&tp->napi);9237			mutex_unlock(&tp->control);9238		} else {9239			tp->rx_pending = ring->rx_pending;9240		}9241	}9242 9243	return 0;9244}9245 9246static void rtl8152_get_pauseparam(struct net_device *netdev, struct ethtool_pauseparam *pause)9247{9248	struct r8152 *tp = netdev_priv(netdev);9249	u16 bmcr, lcladv, rmtadv;9250	u8 cap;9251 9252	if (usb_autopm_get_interface(tp->intf) < 0)9253		return;9254 9255	mutex_lock(&tp->control);9256 9257	bmcr = r8152_mdio_read(tp, MII_BMCR);9258	lcladv = r8152_mdio_read(tp, MII_ADVERTISE);9259	rmtadv = r8152_mdio_read(tp, MII_LPA);9260 9261	mutex_unlock(&tp->control);9262 9263	usb_autopm_put_interface(tp->intf);9264 9265	if (!(bmcr & BMCR_ANENABLE)) {9266		pause->autoneg = 0;9267		pause->rx_pause = 0;9268		pause->tx_pause = 0;9269		return;9270	}9271 9272	pause->autoneg = 1;9273 9274	cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);9275 9276	if (cap & FLOW_CTRL_RX)9277		pause->rx_pause = 1;9278 9279	if (cap & FLOW_CTRL_TX)9280		pause->tx_pause = 1;9281}9282 9283static int rtl8152_set_pauseparam(struct net_device *netdev, struct ethtool_pauseparam *pause)9284{9285	struct r8152 *tp = netdev_priv(netdev);9286	u16 old, new1;9287	u8 cap = 0;9288	int ret;9289 9290	ret = usb_autopm_get_interface(tp->intf);9291	if (ret < 0)9292		return ret;9293 9294	mutex_lock(&tp->control);9295 9296	if (pause->autoneg && !(r8152_mdio_read(tp, MII_BMCR) & BMCR_ANENABLE)) {9297		ret = -EINVAL;9298		goto out;9299	}9300 9301	if (pause->rx_pause)9302		cap |= FLOW_CTRL_RX;9303 9304	if (pause->tx_pause)9305		cap |= FLOW_CTRL_TX;9306 9307	old = r8152_mdio_read(tp, MII_ADVERTISE);9308	new1 = (old & ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) | mii_advertise_flowctrl(cap);9309	if (old != new1)9310		r8152_mdio_write(tp, MII_ADVERTISE, new1);9311 9312out:9313	mutex_unlock(&tp->control);9314	usb_autopm_put_interface(tp->intf);9315 9316	return ret;9317}9318 9319static const struct ethtool_ops ops = {9320	.supported_coalesce_params = ETHTOOL_COALESCE_USECS,9321	.get_drvinfo = rtl8152_get_drvinfo,9322	.get_link = ethtool_op_get_link,9323	.nway_reset = rtl8152_nway_reset,9324	.get_msglevel = rtl8152_get_msglevel,9325	.set_msglevel = rtl8152_set_msglevel,9326	.get_wol = rtl8152_get_wol,9327	.set_wol = rtl8152_set_wol,9328	.get_strings = rtl8152_get_strings,9329	.get_sset_count = rtl8152_get_sset_count,9330	.get_ethtool_stats = rtl8152_get_ethtool_stats,9331	.get_coalesce = rtl8152_get_coalesce,9332	.set_coalesce = rtl8152_set_coalesce,9333	.get_eee = rtl_ethtool_get_eee,9334	.set_eee = rtl_ethtool_set_eee,9335	.get_link_ksettings = rtl8152_get_link_ksettings,9336	.set_link_ksettings = rtl8152_set_link_ksettings,9337	.get_tunable = rtl8152_get_tunable,9338	.set_tunable = rtl8152_set_tunable,9339	.get_ringparam = rtl8152_get_ringparam,9340	.set_ringparam = rtl8152_set_ringparam,9341	.get_pauseparam = rtl8152_get_pauseparam,9342	.set_pauseparam = rtl8152_set_pauseparam,9343};9344 9345static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)9346{9347	struct r8152 *tp = netdev_priv(netdev);9348	struct mii_ioctl_data *data = if_mii(rq);9349	int res;9350 9351	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))9352		return -ENODEV;9353 9354	res = usb_autopm_get_interface(tp->intf);9355	if (res < 0)9356		goto out;9357 9358	switch (cmd) {9359	case SIOCGMIIPHY:9360		data->phy_id = R8152_PHY_ID; /* Internal PHY */9361		break;9362 9363	case SIOCGMIIREG:9364		mutex_lock(&tp->control);9365		data->val_out = r8152_mdio_read(tp, data->reg_num);9366		mutex_unlock(&tp->control);9367		break;9368 9369	case SIOCSMIIREG:9370		if (!capable(CAP_NET_ADMIN)) {9371			res = -EPERM;9372			break;9373		}9374		mutex_lock(&tp->control);9375		r8152_mdio_write(tp, data->reg_num, data->val_in);9376		mutex_unlock(&tp->control);9377		break;9378 9379	default:9380		res = -EOPNOTSUPP;9381	}9382 9383	usb_autopm_put_interface(tp->intf);9384 9385out:9386	return res;9387}9388 9389static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)9390{9391	struct r8152 *tp = netdev_priv(dev);9392	int ret;9393 9394	switch (tp->version) {9395	case RTL_VER_01:9396	case RTL_VER_02:9397	case RTL_VER_07:9398		WRITE_ONCE(dev->mtu, new_mtu);9399		return 0;9400	default:9401		break;9402	}9403 9404	ret = usb_autopm_get_interface(tp->intf);9405	if (ret < 0)9406		return ret;9407 9408	mutex_lock(&tp->control);9409 9410	WRITE_ONCE(dev->mtu, new_mtu);9411 9412	if (netif_running(dev)) {9413		if (tp->rtl_ops.change_mtu)9414			tp->rtl_ops.change_mtu(tp);9415 9416		if (netif_carrier_ok(dev)) {9417			netif_stop_queue(dev);9418			napi_disable(&tp->napi);9419			tasklet_disable(&tp->tx_tl);9420			tp->rtl_ops.disable(tp);9421			tp->rtl_ops.enable(tp);9422			rtl_start_rx(tp);9423			tasklet_enable(&tp->tx_tl);9424			napi_enable(&tp->napi);9425			rtl8152_set_rx_mode(dev);9426			netif_wake_queue(dev);9427		}9428	}9429 9430	mutex_unlock(&tp->control);9431 9432	usb_autopm_put_interface(tp->intf);9433 9434	return ret;9435}9436 9437static const struct net_device_ops rtl8152_netdev_ops = {9438	.ndo_open		= rtl8152_open,9439	.ndo_stop		= rtl8152_close,9440	.ndo_eth_ioctl		= rtl8152_ioctl,9441	.ndo_start_xmit		= rtl8152_start_xmit,9442	.ndo_tx_timeout		= rtl8152_tx_timeout,9443	.ndo_set_features	= rtl8152_set_features,9444	.ndo_set_rx_mode	= rtl8152_set_rx_mode,9445	.ndo_set_mac_address	= rtl8152_set_mac_address,9446	.ndo_change_mtu		= rtl8152_change_mtu,9447	.ndo_validate_addr	= eth_validate_addr,9448	.ndo_features_check	= rtl8152_features_check,9449};9450 9451static void rtl8152_unload(struct r8152 *tp)9452{9453	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))9454		return;9455 9456	if (tp->version != RTL_VER_01)9457		r8152_power_cut_en(tp, true);9458}9459 9460static void rtl8153_unload(struct r8152 *tp)9461{9462	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))9463		return;9464 9465	r8153_power_cut_en(tp, false);9466}9467 9468static void rtl8153b_unload(struct r8152 *tp)9469{9470	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))9471		return;9472 9473	r8153b_power_cut_en(tp, false);9474}9475 9476static int rtl_ops_init(struct r8152 *tp)9477{9478	struct rtl_ops *ops = &tp->rtl_ops;9479	int ret = 0;9480 9481	switch (tp->version) {9482	case RTL_VER_01:9483	case RTL_VER_02:9484	case RTL_VER_07:9485		ops->init		= r8152b_init;9486		ops->enable		= rtl8152_enable;9487		ops->disable		= rtl8152_disable;9488		ops->up			= rtl8152_up;9489		ops->down		= rtl8152_down;9490		ops->unload		= rtl8152_unload;9491		ops->eee_get		= r8152_get_eee;9492		ops->eee_set		= r8152_set_eee;9493		ops->in_nway		= rtl8152_in_nway;9494		ops->hw_phy_cfg		= r8152b_hw_phy_cfg;9495		ops->autosuspend_en	= rtl_runtime_suspend_enable;9496		tp->rx_buf_sz		= 16 * 1024;9497		tp->eee_en		= true;9498		tp->eee_adv		= MDIO_EEE_100TX;9499		break;9500 9501	case RTL_VER_03:9502	case RTL_VER_04:9503	case RTL_VER_05:9504	case RTL_VER_06:9505		ops->init		= r8153_init;9506		ops->enable		= rtl8153_enable;9507		ops->disable		= rtl8153_disable;9508		ops->up			= rtl8153_up;9509		ops->down		= rtl8153_down;9510		ops->unload		= rtl8153_unload;9511		ops->eee_get		= r8153_get_eee;9512		ops->eee_set		= r8152_set_eee;9513		ops->in_nway		= rtl8153_in_nway;9514		ops->hw_phy_cfg		= r8153_hw_phy_cfg;9515		ops->autosuspend_en	= rtl8153_runtime_enable;9516		ops->change_mtu		= rtl8153_change_mtu;9517		if (tp->udev->speed < USB_SPEED_SUPER)9518			tp->rx_buf_sz	= 16 * 1024;9519		else9520			tp->rx_buf_sz	= 32 * 1024;9521		tp->eee_en		= true;9522		tp->eee_adv		= MDIO_EEE_1000T | MDIO_EEE_100TX;9523		break;9524 9525	case RTL_VER_08:9526	case RTL_VER_09:9527		ops->init		= r8153b_init;9528		ops->enable		= rtl8153_enable;9529		ops->disable		= rtl8153_disable;9530		ops->up			= rtl8153b_up;9531		ops->down		= rtl8153b_down;9532		ops->unload		= rtl8153b_unload;9533		ops->eee_get		= r8153_get_eee;9534		ops->eee_set		= r8152_set_eee;9535		ops->in_nway		= rtl8153_in_nway;9536		ops->hw_phy_cfg		= r8153b_hw_phy_cfg;9537		ops->autosuspend_en	= rtl8153b_runtime_enable;9538		ops->change_mtu		= rtl8153_change_mtu;9539		tp->rx_buf_sz		= 32 * 1024;9540		tp->eee_en		= true;9541		tp->eee_adv		= MDIO_EEE_1000T | MDIO_EEE_100TX;9542		break;9543 9544	case RTL_VER_11:9545		tp->eee_en		= true;9546		tp->eee_adv		= MDIO_EEE_1000T | MDIO_EEE_100TX;9547		fallthrough;9548	case RTL_VER_10:9549		ops->init		= r8156_init;9550		ops->enable		= rtl8156_enable;9551		ops->disable		= rtl8156_disable;9552		ops->up			= rtl8156_up;9553		ops->down		= rtl8156_down;9554		ops->unload		= rtl8153_unload;9555		ops->eee_get		= r8153_get_eee;9556		ops->eee_set		= r8152_set_eee;9557		ops->in_nway		= rtl8153_in_nway;9558		ops->hw_phy_cfg		= r8156_hw_phy_cfg;9559		ops->autosuspend_en	= rtl8156_runtime_enable;9560		ops->change_mtu		= rtl8156_change_mtu;9561		tp->rx_buf_sz		= 48 * 1024;9562		tp->support_2500full	= 1;9563		break;9564 9565	case RTL_VER_12:9566	case RTL_VER_13:9567		tp->support_2500full	= 1;9568		fallthrough;9569	case RTL_VER_15:9570		tp->eee_en		= true;9571		tp->eee_adv		= MDIO_EEE_1000T | MDIO_EEE_100TX;9572		ops->init		= r8156b_init;9573		ops->enable		= rtl8156b_enable;9574		ops->disable		= rtl8153_disable;9575		ops->up			= rtl8156_up;9576		ops->down		= rtl8156_down;9577		ops->unload		= rtl8153_unload;9578		ops->eee_get		= r8153_get_eee;9579		ops->eee_set		= r8152_set_eee;9580		ops->in_nway		= rtl8153_in_nway;9581		ops->hw_phy_cfg		= r8156b_hw_phy_cfg;9582		ops->autosuspend_en	= rtl8156_runtime_enable;9583		ops->change_mtu		= rtl8156_change_mtu;9584		tp->rx_buf_sz		= 48 * 1024;9585		break;9586 9587	case RTL_VER_14:9588		ops->init		= r8153c_init;9589		ops->enable		= rtl8153_enable;9590		ops->disable		= rtl8153_disable;9591		ops->up			= rtl8153c_up;9592		ops->down		= rtl8153b_down;9593		ops->unload		= rtl8153_unload;9594		ops->eee_get		= r8153_get_eee;9595		ops->eee_set		= r8152_set_eee;9596		ops->in_nway		= rtl8153_in_nway;9597		ops->hw_phy_cfg		= r8153c_hw_phy_cfg;9598		ops->autosuspend_en	= rtl8153c_runtime_enable;9599		ops->change_mtu		= rtl8153c_change_mtu;9600		tp->rx_buf_sz		= 32 * 1024;9601		tp->eee_en		= true;9602		tp->eee_adv		= MDIO_EEE_1000T | MDIO_EEE_100TX;9603		break;9604 9605	default:9606		ret = -ENODEV;9607		dev_err(&tp->intf->dev, "Unknown Device\n");9608		break;9609	}9610 9611	return ret;9612}9613 9614#define FIRMWARE_8153A_2	"rtl_nic/rtl8153a-2.fw"9615#define FIRMWARE_8153A_3	"rtl_nic/rtl8153a-3.fw"9616#define FIRMWARE_8153A_4	"rtl_nic/rtl8153a-4.fw"9617#define FIRMWARE_8153B_2	"rtl_nic/rtl8153b-2.fw"9618#define FIRMWARE_8153C_1	"rtl_nic/rtl8153c-1.fw"9619#define FIRMWARE_8156A_2	"rtl_nic/rtl8156a-2.fw"9620#define FIRMWARE_8156B_2	"rtl_nic/rtl8156b-2.fw"9621 9622MODULE_FIRMWARE(FIRMWARE_8153A_2);9623MODULE_FIRMWARE(FIRMWARE_8153A_3);9624MODULE_FIRMWARE(FIRMWARE_8153A_4);9625MODULE_FIRMWARE(FIRMWARE_8153B_2);9626MODULE_FIRMWARE(FIRMWARE_8153C_1);9627MODULE_FIRMWARE(FIRMWARE_8156A_2);9628MODULE_FIRMWARE(FIRMWARE_8156B_2);9629 9630static int rtl_fw_init(struct r8152 *tp)9631{9632	struct rtl_fw *rtl_fw = &tp->rtl_fw;9633 9634	switch (tp->version) {9635	case RTL_VER_04:9636		rtl_fw->fw_name		= FIRMWARE_8153A_2;9637		rtl_fw->pre_fw		= r8153_pre_firmware_1;9638		rtl_fw->post_fw		= r8153_post_firmware_1;9639		break;9640	case RTL_VER_05:9641		rtl_fw->fw_name		= FIRMWARE_8153A_3;9642		rtl_fw->pre_fw		= r8153_pre_firmware_2;9643		rtl_fw->post_fw		= r8153_post_firmware_2;9644		break;9645	case RTL_VER_06:9646		rtl_fw->fw_name		= FIRMWARE_8153A_4;9647		rtl_fw->post_fw		= r8153_post_firmware_3;9648		break;9649	case RTL_VER_09:9650		rtl_fw->fw_name		= FIRMWARE_8153B_2;9651		rtl_fw->pre_fw		= r8153b_pre_firmware_1;9652		rtl_fw->post_fw		= r8153b_post_firmware_1;9653		break;9654	case RTL_VER_11:9655		rtl_fw->fw_name		= FIRMWARE_8156A_2;9656		rtl_fw->post_fw		= r8156a_post_firmware_1;9657		break;9658	case RTL_VER_13:9659	case RTL_VER_15:9660		rtl_fw->fw_name		= FIRMWARE_8156B_2;9661		break;9662	case RTL_VER_14:9663		rtl_fw->fw_name		= FIRMWARE_8153C_1;9664		rtl_fw->pre_fw		= r8153b_pre_firmware_1;9665		rtl_fw->post_fw		= r8153c_post_firmware_1;9666		break;9667	default:9668		break;9669	}9670 9671	return 0;9672}9673 9674static u8 __rtl_get_hw_ver(struct usb_device *udev)9675{9676	u32 ocp_data = 0;9677	__le32 *tmp;9678	u8 version;9679	int ret;9680	int i;9681 9682	tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);9683	if (!tmp)9684		return 0;9685 9686	/* Retry up to 3 times in case there is a transitory error. We do this9687	 * since retrying a read of the version is always safe and this9688	 * function doesn't take advantage of r8152_control_msg().9689	 */9690	for (i = 0; i < 3; i++) {9691		ret = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),9692				      RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,9693				      PLA_TCR0, MCU_TYPE_PLA, tmp, sizeof(*tmp),9694				      USB_CTRL_GET_TIMEOUT);9695		if (ret > 0) {9696			ocp_data = (__le32_to_cpu(*tmp) >> 16) & VERSION_MASK;9697			break;9698		}9699	}9700 9701	if (i != 0 && ret > 0)9702		dev_warn(&udev->dev, "Needed %d retries to read version\n", i);9703 9704	kfree(tmp);9705 9706	switch (ocp_data) {9707	case 0x4c00:9708		version = RTL_VER_01;9709		break;9710	case 0x4c10:9711		version = RTL_VER_02;9712		break;9713	case 0x5c00:9714		version = RTL_VER_03;9715		break;9716	case 0x5c10:9717		version = RTL_VER_04;9718		break;9719	case 0x5c20:9720		version = RTL_VER_05;9721		break;9722	case 0x5c30:9723		version = RTL_VER_06;9724		break;9725	case 0x4800:9726		version = RTL_VER_07;9727		break;9728	case 0x6000:9729		version = RTL_VER_08;9730		break;9731	case 0x6010:9732		version = RTL_VER_09;9733		break;9734	case 0x7010:9735		version = RTL_TEST_01;9736		break;9737	case 0x7020:9738		version = RTL_VER_10;9739		break;9740	case 0x7030:9741		version = RTL_VER_11;9742		break;9743	case 0x7400:9744		version = RTL_VER_12;9745		break;9746	case 0x7410:9747		version = RTL_VER_13;9748		break;9749	case 0x6400:9750		version = RTL_VER_14;9751		break;9752	case 0x7420:9753		version = RTL_VER_15;9754		break;9755	default:9756		version = RTL_VER_UNKNOWN;9757		dev_info(&udev->dev, "Unknown version 0x%04x\n", ocp_data);9758		break;9759	}9760 9761	return version;9762}9763 9764u8 rtl8152_get_version(struct usb_interface *intf)9765{9766	u8 version;9767 9768	version = __rtl_get_hw_ver(interface_to_usbdev(intf));9769 9770	dev_dbg(&intf->dev, "Detected version 0x%04x\n", version);9771 9772	return version;9773}9774EXPORT_SYMBOL_GPL(rtl8152_get_version);9775 9776static bool rtl8152_supports_lenovo_macpassthru(struct usb_device *udev)9777{9778	int parent_vendor_id = le16_to_cpu(udev->parent->descriptor.idVendor);9779	int product_id = le16_to_cpu(udev->descriptor.idProduct);9780	int vendor_id = le16_to_cpu(udev->descriptor.idVendor);9781 9782	if (vendor_id == VENDOR_ID_LENOVO) {9783		switch (product_id) {9784		case DEVICE_ID_LENOVO_USB_C_TRAVEL_HUB:9785		case DEVICE_ID_THINKPAD_ONELINK_PLUS_DOCK:9786		case DEVICE_ID_THINKPAD_THUNDERBOLT3_DOCK_GEN2:9787		case DEVICE_ID_THINKPAD_USB_C_DOCK_GEN2:9788		case DEVICE_ID_THINKPAD_USB_C_DOCK_GEN3:9789		case DEVICE_ID_THINKPAD_USB_C_DONGLE:9790			return 1;9791		}9792	} else if (vendor_id == VENDOR_ID_REALTEK && parent_vendor_id == VENDOR_ID_LENOVO) {9793		switch (product_id) {9794		case 0x8153:9795			return 1;9796		}9797	}9798	return 0;9799}9800 9801static int rtl8152_probe_once(struct usb_interface *intf,9802			      const struct usb_device_id *id, u8 version)9803{9804	struct usb_device *udev = interface_to_usbdev(intf);9805	struct r8152 *tp;9806	struct net_device *netdev;9807	int ret;9808 9809	usb_reset_device(udev);9810	netdev = alloc_etherdev(sizeof(struct r8152));9811	if (!netdev) {9812		dev_err(&intf->dev, "Out of memory\n");9813		return -ENOMEM;9814	}9815 9816	SET_NETDEV_DEV(netdev, &intf->dev);9817	tp = netdev_priv(netdev);9818	tp->msg_enable = 0x7FFF;9819 9820	tp->udev = udev;9821	tp->netdev = netdev;9822	tp->intf = intf;9823	tp->version = version;9824 9825	tp->pipe_ctrl_in = usb_rcvctrlpipe(udev, 0);9826	tp->pipe_ctrl_out = usb_sndctrlpipe(udev, 0);9827	tp->pipe_in = usb_rcvbulkpipe(udev, 1);9828	tp->pipe_out = usb_sndbulkpipe(udev, 2);9829	tp->pipe_intr = usb_rcvintpipe(udev, 3);9830 9831	switch (version) {9832	case RTL_VER_01:9833	case RTL_VER_02:9834	case RTL_VER_07:9835		tp->mii.supports_gmii = 0;9836		break;9837	default:9838		tp->mii.supports_gmii = 1;9839		break;9840	}9841 9842	ret = rtl_ops_init(tp);9843	if (ret)9844		goto out;9845 9846	rtl_fw_init(tp);9847 9848	mutex_init(&tp->control);9849	INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);9850	INIT_DELAYED_WORK(&tp->hw_phy_work, rtl_hw_phy_work_func_t);9851	tasklet_setup(&tp->tx_tl, bottom_half);9852	tasklet_disable(&tp->tx_tl);9853 9854	netdev->netdev_ops = &rtl8152_netdev_ops;9855	netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;9856 9857	netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |9858			    NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |9859			    NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |9860			    NETIF_F_HW_VLAN_CTAG_TX;9861	netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |9862			      NETIF_F_TSO | NETIF_F_FRAGLIST |9863			      NETIF_F_IPV6_CSUM | NETIF_F_TSO6 |9864			      NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX;9865	netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |9866				NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |9867				NETIF_F_IPV6_CSUM | NETIF_F_TSO6;9868 9869	if (tp->version == RTL_VER_01) {9870		netdev->features &= ~NETIF_F_RXCSUM;9871		netdev->hw_features &= ~NETIF_F_RXCSUM;9872	}9873 9874	tp->lenovo_macpassthru = rtl8152_supports_lenovo_macpassthru(udev);9875 9876	if (le16_to_cpu(udev->descriptor.bcdDevice) == 0x3011 && udev->serial &&9877	    (!strcmp(udev->serial, "000001000000") ||9878	     !strcmp(udev->serial, "000002000000"))) {9879		dev_info(&udev->dev, "Dell TB16 Dock, disable RX aggregation");9880		tp->dell_tb_rx_agg_bug = 1;9881	}9882 9883	netdev->ethtool_ops = &ops;9884	netif_set_tso_max_size(netdev, RTL_LIMITED_TSO_SIZE);9885 9886	/* MTU range: 68 - 1500 or 9194 */9887	netdev->min_mtu = ETH_MIN_MTU;9888	switch (tp->version) {9889	case RTL_VER_03:9890	case RTL_VER_04:9891	case RTL_VER_05:9892	case RTL_VER_06:9893	case RTL_VER_08:9894	case RTL_VER_09:9895	case RTL_VER_14:9896		netdev->max_mtu = size_to_mtu(9 * 1024);9897		break;9898	case RTL_VER_10:9899	case RTL_VER_11:9900		netdev->max_mtu = size_to_mtu(15 * 1024);9901		break;9902	case RTL_VER_12:9903	case RTL_VER_13:9904	case RTL_VER_15:9905		netdev->max_mtu = size_to_mtu(16 * 1024);9906		break;9907	case RTL_VER_01:9908	case RTL_VER_02:9909	case RTL_VER_07:9910	default:9911		netdev->max_mtu = ETH_DATA_LEN;9912		break;9913	}9914 9915	tp->mii.dev = netdev;9916	tp->mii.mdio_read = read_mii_word;9917	tp->mii.mdio_write = write_mii_word;9918	tp->mii.phy_id_mask = 0x3f;9919	tp->mii.reg_num_mask = 0x1f;9920	tp->mii.phy_id = R8152_PHY_ID;9921 9922	tp->autoneg = AUTONEG_ENABLE;9923	tp->speed = SPEED_100;9924	tp->advertising = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL |9925			  RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL;9926	if (tp->mii.supports_gmii) {9927		if (tp->support_2500full &&9928		    tp->udev->speed >= USB_SPEED_SUPER) {9929			tp->speed = SPEED_2500;9930			tp->advertising |= RTL_ADVERTISED_2500_FULL;9931		} else {9932			tp->speed = SPEED_1000;9933		}9934		tp->advertising |= RTL_ADVERTISED_1000_FULL;9935	}9936	tp->duplex = DUPLEX_FULL;9937 9938	tp->rx_copybreak = RTL8152_RXFG_HEADSZ;9939	tp->rx_pending = 10 * RTL8152_MAX_RX;9940 9941	intf->needs_remote_wakeup = 1;9942 9943	if (!rtl_can_wakeup(tp))9944		__rtl_set_wol(tp, 0);9945	else9946		tp->saved_wolopts = __rtl_get_wol(tp);9947 9948	tp->rtl_ops.init(tp);9949#if IS_BUILTIN(CONFIG_USB_RTL8152)9950	/* Retry in case request_firmware() is not ready yet. */9951	tp->rtl_fw.retry = true;9952#endif9953	queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);9954	set_ethernet_addr(tp, false);9955 9956	usb_set_intfdata(intf, tp);9957 9958	netif_napi_add(netdev, &tp->napi, r8152_poll);9959 9960	ret = register_netdev(netdev);9961	if (ret != 0) {9962		dev_err(&intf->dev, "couldn't register the device\n");9963		goto out1;9964	}9965 9966	if (tp->saved_wolopts)9967		device_set_wakeup_enable(&udev->dev, true);9968	else9969		device_set_wakeup_enable(&udev->dev, false);9970 9971	/* If we saw a control transfer error while probing then we may9972	 * want to try probe() again. Consider this an error.9973	 */9974	if (test_bit(PROBE_SHOULD_RETRY, &tp->flags))9975		goto out2;9976 9977	set_bit(PROBED_WITH_NO_ERRORS, &tp->flags);9978	netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);9979 9980	return 0;9981 9982out2:9983	unregister_netdev(netdev);9984 9985out1:9986	tasklet_kill(&tp->tx_tl);9987	cancel_delayed_work_sync(&tp->hw_phy_work);9988	if (tp->rtl_ops.unload)9989		tp->rtl_ops.unload(tp);9990	rtl8152_release_firmware(tp);9991	usb_set_intfdata(intf, NULL);9992out:9993	if (test_bit(PROBE_SHOULD_RETRY, &tp->flags))9994		ret = -EAGAIN;9995 9996	free_netdev(netdev);9997	return ret;9998}9999 10000#define RTL8152_PROBE_TRIES	310001 10002static int rtl8152_probe(struct usb_interface *intf,10003			 const struct usb_device_id *id)10004{10005	u8 version;10006	int ret;10007	int i;10008 10009	if (intf->cur_altsetting->desc.bInterfaceClass != USB_CLASS_VENDOR_SPEC)10010		return -ENODEV;10011 10012	if (!rtl_check_vendor_ok(intf))10013		return -ENODEV;10014 10015	version = rtl8152_get_version(intf);10016	if (version == RTL_VER_UNKNOWN)10017		return -ENODEV;10018 10019	for (i = 0; i < RTL8152_PROBE_TRIES; i++) {10020		ret = rtl8152_probe_once(intf, id, version);10021		if (ret != -EAGAIN)10022			break;10023	}10024	if (ret == -EAGAIN) {10025		dev_err(&intf->dev,10026			"r8152 failed probe after %d tries; giving up\n", i);10027		return -ENODEV;10028	}10029 10030	return ret;10031}10032 10033static void rtl8152_disconnect(struct usb_interface *intf)10034{10035	struct r8152 *tp = usb_get_intfdata(intf);10036 10037	usb_set_intfdata(intf, NULL);10038	if (tp) {10039		rtl_set_unplug(tp);10040 10041		unregister_netdev(tp->netdev);10042		tasklet_kill(&tp->tx_tl);10043		cancel_delayed_work_sync(&tp->hw_phy_work);10044		if (tp->rtl_ops.unload)10045			tp->rtl_ops.unload(tp);10046		rtl8152_release_firmware(tp);10047		free_netdev(tp->netdev);10048	}10049}10050 10051/* table of devices that work with this driver */10052static const struct usb_device_id rtl8152_table[] = {10053	/* Realtek */10054	{ USB_DEVICE(VENDOR_ID_REALTEK, 0x8050) },10055	{ USB_DEVICE(VENDOR_ID_REALTEK, 0x8053) },10056	{ USB_DEVICE(VENDOR_ID_REALTEK, 0x8152) },10057	{ USB_DEVICE(VENDOR_ID_REALTEK, 0x8153) },10058	{ USB_DEVICE(VENDOR_ID_REALTEK, 0x8155) },10059	{ USB_DEVICE(VENDOR_ID_REALTEK, 0x8156) },10060 10061	/* Microsoft */10062	{ USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07ab) },10063	{ USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07c6) },10064	{ USB_DEVICE(VENDOR_ID_MICROSOFT, 0x0927) },10065	{ USB_DEVICE(VENDOR_ID_MICROSOFT, 0x0c5e) },10066	{ USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101) },10067	{ USB_DEVICE(VENDOR_ID_LENOVO,  0x304f) },10068	{ USB_DEVICE(VENDOR_ID_LENOVO,  0x3054) },10069	{ USB_DEVICE(VENDOR_ID_LENOVO,  0x3062) },10070	{ USB_DEVICE(VENDOR_ID_LENOVO,  0x3069) },10071	{ USB_DEVICE(VENDOR_ID_LENOVO,  0x3082) },10072	{ USB_DEVICE(VENDOR_ID_LENOVO,  0x3098) },10073	{ USB_DEVICE(VENDOR_ID_LENOVO,  0x7205) },10074	{ USB_DEVICE(VENDOR_ID_LENOVO,  0x720c) },10075	{ USB_DEVICE(VENDOR_ID_LENOVO,  0x7214) },10076	{ USB_DEVICE(VENDOR_ID_LENOVO,  0x721e) },10077	{ USB_DEVICE(VENDOR_ID_LENOVO,  0xa387) },10078	{ USB_DEVICE(VENDOR_ID_LINKSYS, 0x0041) },10079	{ USB_DEVICE(VENDOR_ID_NVIDIA,  0x09ff) },10080	{ USB_DEVICE(VENDOR_ID_TPLINK,  0x0601) },10081	{ USB_DEVICE(VENDOR_ID_DLINK,   0xb301) },10082	{ USB_DEVICE(VENDOR_ID_ASUS,    0x1976) },10083	{}10084};10085 10086MODULE_DEVICE_TABLE(usb, rtl8152_table);10087 10088static struct usb_driver rtl8152_driver = {10089	.name =		MODULENAME,10090	.id_table =	rtl8152_table,10091	.probe =	rtl8152_probe,10092	.disconnect =	rtl8152_disconnect,10093	.suspend =	rtl8152_suspend,10094	.resume =	rtl8152_resume,10095	.reset_resume =	rtl8152_reset_resume,10096	.pre_reset =	rtl8152_pre_reset,10097	.post_reset =	rtl8152_post_reset,10098	.supports_autosuspend = 1,10099	.disable_hub_initiated_lpm = 1,10100};10101 10102static int rtl8152_cfgselector_choose_configuration(struct usb_device *udev)10103{10104	struct usb_host_config *c;10105	int i, num_configs;10106 10107	/* Switch the device to vendor mode, if and only if the vendor mode10108	 * driver supports it.10109	 */10110	if (__rtl_get_hw_ver(udev) == RTL_VER_UNKNOWN)10111		return -ENODEV;10112 10113	/* The vendor mode is not always config #1, so to find it out. */10114	c = udev->config;10115	num_configs = udev->descriptor.bNumConfigurations;10116	for (i = 0; i < num_configs; (i++, c++)) {10117		struct usb_interface_descriptor	*desc = NULL;10118 10119		if (!c->desc.bNumInterfaces)10120			continue;10121		desc = &c->intf_cache[0]->altsetting->desc;10122		if (desc->bInterfaceClass == USB_CLASS_VENDOR_SPEC)10123			break;10124	}10125 10126	if (i == num_configs)10127		return -ENODEV;10128 10129	return c->desc.bConfigurationValue;10130}10131 10132static struct usb_device_driver rtl8152_cfgselector_driver = {10133	.name =	MODULENAME "-cfgselector",10134	.choose_configuration = rtl8152_cfgselector_choose_configuration,10135	.id_table = rtl8152_table,10136	.generic_subclass = 1,10137	.supports_autosuspend = 1,10138};10139 10140static int __init rtl8152_driver_init(void)10141{10142	int ret;10143 10144	ret = usb_register_device_driver(&rtl8152_cfgselector_driver, THIS_MODULE);10145	if (ret)10146		return ret;10147	return usb_register(&rtl8152_driver);10148}10149 10150static void __exit rtl8152_driver_exit(void)10151{10152	usb_deregister(&rtl8152_driver);10153	usb_deregister_device_driver(&rtl8152_cfgselector_driver);10154}10155 10156module_init(rtl8152_driver_init);10157module_exit(rtl8152_driver_exit);10158 10159MODULE_AUTHOR(DRIVER_AUTHOR);10160MODULE_DESCRIPTION(DRIVER_DESC);10161MODULE_LICENSE("GPL");10162MODULE_VERSION(DRIVER_VERSION);10163