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1/*2 * Linux driver for VMware's vmxnet3 ethernet NIC.3 *4 * Copyright (C) 2008-2024, VMware, Inc. All Rights Reserved.5 *6 * This program is free software; you can redistribute it and/or modify it7 * under the terms of the GNU General Public License as published by the8 * Free Software Foundation; version 2 of the License and no later version.9 *10 * This program is distributed in the hope that it will be useful, but11 * WITHOUT ANY WARRANTY; without even the implied warranty of12 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or13 * NON INFRINGEMENT. See the GNU General Public License for more14 * details.15 *16 * You should have received a copy of the GNU General Public License17 * along with this program; if not, write to the Free Software18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.19 *20 * The full GNU General Public License is included in this distribution in21 * the file called "COPYING".22 *23 * Maintained by: pv-drivers@vmware.com24 *25 */26 27#ifndef _VMXNET3_DEFS_H_28#define _VMXNET3_DEFS_H_29 30#include "upt1_defs.h"31 32/* all registers are 32 bit wide */33/* BAR 1 */34enum {35 VMXNET3_REG_VRRS = 0x0, /* Vmxnet3 Revision Report Selection */36 VMXNET3_REG_UVRS = 0x8, /* UPT Version Report Selection */37 VMXNET3_REG_DSAL = 0x10, /* Driver Shared Address Low */38 VMXNET3_REG_DSAH = 0x18, /* Driver Shared Address High */39 VMXNET3_REG_CMD = 0x20, /* Command */40 VMXNET3_REG_MACL = 0x28, /* MAC Address Low */41 VMXNET3_REG_MACH = 0x30, /* MAC Address High */42 VMXNET3_REG_ICR = 0x38, /* Interrupt Cause Register */43 VMXNET3_REG_ECR = 0x40, /* Event Cause Register */44 VMXNET3_REG_DCR = 0x48, /* Device capability register,45 * from 0x48 to 0x8046 */47 VMXNET3_REG_PTCR = 0x88, /* Passthru capbility register48 * from 0x88 to 0xb049 */50};51 52/* BAR 0 */53enum {54 VMXNET3_REG_IMR = 0x0, /* Interrupt Mask Register */55 VMXNET3_REG_TXPROD = 0x600, /* Tx Producer Index */56 VMXNET3_REG_RXPROD = 0x800, /* Rx Producer Index for ring 1 */57 VMXNET3_REG_RXPROD2 = 0xA00 /* Rx Producer Index for ring 2 */58};59 60/* For Large PT BAR, the following offset to DB register */61enum {62 VMXNET3_REG_LB_TXPROD = 0x1000, /* Tx Producer Index */63 VMXNET3_REG_LB_RXPROD = 0x1400, /* Rx Producer Index for ring 1 */64 VMXNET3_REG_LB_RXPROD2 = 0x1800, /* Rx Producer Index for ring 2 */65};66 67#define VMXNET3_PT_REG_SIZE 4096 /* BAR 0 */68#define VMXNET3_LARGE_PT_REG_SIZE 8192 /* large PT pages */69#define VMXNET3_VD_REG_SIZE 4096 /* BAR 1 */70#define VMXNET3_LARGE_BAR0_REG_SIZE (4096 * 4096) /* LARGE BAR 0 */71#define VMXNET3_OOB_REG_SIZE (4094 * 4096) /* OOB pages */72 73#define VMXNET3_REG_ALIGN 8 /* All registers are 8-byte aligned. */74#define VMXNET3_REG_ALIGN_MASK 0x775 76/* I/O Mapped access to registers */77#define VMXNET3_IO_TYPE_PT 078#define VMXNET3_IO_TYPE_VD 179#define VMXNET3_IO_ADDR(type, reg) (((type) << 24) | ((reg) & 0xFFFFFF))80#define VMXNET3_IO_TYPE(addr) ((addr) >> 24)81#define VMXNET3_IO_REG(addr) ((addr) & 0xFFFFFF)82 83#define VMXNET3_PMC_PSEUDO_TSC 0x1000384 85enum {86 VMXNET3_CMD_FIRST_SET = 0xCAFE0000,87 VMXNET3_CMD_ACTIVATE_DEV = VMXNET3_CMD_FIRST_SET,88 VMXNET3_CMD_QUIESCE_DEV,89 VMXNET3_CMD_RESET_DEV,90 VMXNET3_CMD_UPDATE_RX_MODE,91 VMXNET3_CMD_UPDATE_MAC_FILTERS,92 VMXNET3_CMD_UPDATE_VLAN_FILTERS,93 VMXNET3_CMD_UPDATE_RSSIDT,94 VMXNET3_CMD_UPDATE_IML,95 VMXNET3_CMD_UPDATE_PMCFG,96 VMXNET3_CMD_UPDATE_FEATURE,97 VMXNET3_CMD_RESERVED1,98 VMXNET3_CMD_LOAD_PLUGIN,99 VMXNET3_CMD_RESERVED2,100 VMXNET3_CMD_RESERVED3,101 VMXNET3_CMD_SET_COALESCE,102 VMXNET3_CMD_REGISTER_MEMREGS,103 VMXNET3_CMD_SET_RSS_FIELDS,104 VMXNET3_CMD_RESERVED4,105 VMXNET3_CMD_RESERVED5,106 VMXNET3_CMD_SET_RING_BUFFER_SIZE,107 108 VMXNET3_CMD_FIRST_GET = 0xF00D0000,109 VMXNET3_CMD_GET_QUEUE_STATUS = VMXNET3_CMD_FIRST_GET,110 VMXNET3_CMD_GET_STATS,111 VMXNET3_CMD_GET_LINK,112 VMXNET3_CMD_GET_PERM_MAC_LO,113 VMXNET3_CMD_GET_PERM_MAC_HI,114 VMXNET3_CMD_GET_DID_LO,115 VMXNET3_CMD_GET_DID_HI,116 VMXNET3_CMD_GET_DEV_EXTRA_INFO,117 VMXNET3_CMD_GET_CONF_INTR,118 VMXNET3_CMD_GET_RESERVED1,119 VMXNET3_CMD_GET_TXDATA_DESC_SIZE,120 VMXNET3_CMD_GET_COALESCE,121 VMXNET3_CMD_GET_RSS_FIELDS,122 VMXNET3_CMD_GET_RESERVED2,123 VMXNET3_CMD_GET_RESERVED3,124 VMXNET3_CMD_GET_MAX_QUEUES_CONF,125 VMXNET3_CMD_GET_RESERVED4,126 VMXNET3_CMD_GET_MAX_CAPABILITIES,127 VMXNET3_CMD_GET_DCR0_REG,128 VMXNET3_CMD_GET_TSRING_DESC_SIZE,129 VMXNET3_CMD_GET_DISABLED_OFFLOADS,130};131 132/*133 * Little Endian layout of bitfields -134 * Byte 0 : 7.....len.....0135 * Byte 1 : oco gen 13.len.8136 * Byte 2 : 5.msscof.0 ext1 dtype137 * Byte 3 : 13...msscof...6138 *139 * Big Endian layout of bitfields -140 * Byte 0: 13...msscof...6141 * Byte 1 : 5.msscof.0 ext1 dtype142 * Byte 2 : oco gen 13.len.8143 * Byte 3 : 7.....len.....0144 *145 * Thus, le32_to_cpu on the dword will allow the big endian driver to read146 * the bit fields correctly. And cpu_to_le32 will convert bitfields147 * bit fields written by big endian driver to format required by device.148 */149 150struct Vmxnet3_TxDesc {151 __le64 addr;152 153#ifdef __BIG_ENDIAN_BITFIELD154 u32 msscof:14; /* MSS, checksum offset, flags */155 u32 ext1:1; /* set to 1 to indicate inner csum/tso, vmxnet3 v7 */156 u32 dtype:1; /* descriptor type */157 u32 oco:1; /* Outer csum offload */158 u32 gen:1; /* generation bit */159 u32 len:14;160#else161 u32 len:14;162 u32 gen:1; /* generation bit */163 u32 oco:1; /* Outer csum offload */164 u32 dtype:1; /* descriptor type */165 u32 ext1:1; /* set to 1 to indicate inner csum/tso, vmxnet3 v7 */166 u32 msscof:14; /* MSS, checksum offset, flags */167#endif /* __BIG_ENDIAN_BITFIELD */168 169#ifdef __BIG_ENDIAN_BITFIELD170 u32 tci:16; /* Tag to Insert */171 u32 ti:1; /* VLAN Tag Insertion */172 u32 ext2:1;173 u32 cq:1; /* completion request */174 u32 eop:1; /* End Of Packet */175 u32 om:2; /* offload mode */176 u32 hlen:10; /* header len */177#else178 u32 hlen:10; /* header len */179 u32 om:2; /* offload mode */180 u32 eop:1; /* End Of Packet */181 u32 cq:1; /* completion request */182 u32 ext2:1;183 u32 ti:1; /* VLAN Tag Insertion */184 u32 tci:16; /* Tag to Insert */185#endif /* __BIG_ENDIAN_BITFIELD */186};187 188/* TxDesc.OM values */189#define VMXNET3_OM_NONE 0190#define VMXNET3_OM_ENCAP 1191#define VMXNET3_OM_CSUM 2192#define VMXNET3_OM_TSO 3193 194/* fields in TxDesc we access w/o using bit fields */195#define VMXNET3_TXD_EOP_SHIFT 12196#define VMXNET3_TXD_CQ_SHIFT 13197#define VMXNET3_TXD_GEN_SHIFT 14198#define VMXNET3_TXD_EOP_DWORD_SHIFT 3199#define VMXNET3_TXD_GEN_DWORD_SHIFT 2200 201#define VMXNET3_TXD_CQ (1 << VMXNET3_TXD_CQ_SHIFT)202#define VMXNET3_TXD_EOP (1 << VMXNET3_TXD_EOP_SHIFT)203#define VMXNET3_TXD_GEN (1 << VMXNET3_TXD_GEN_SHIFT)204 205#define VMXNET3_HDR_COPY_SIZE 128206 207 208struct Vmxnet3_TxDataDesc {209 u8 data[VMXNET3_HDR_COPY_SIZE];210};211 212typedef u8 Vmxnet3_RxDataDesc;213 214#define VMXNET3_TCD_GEN_SHIFT 31215#define VMXNET3_TCD_GEN_SIZE 1216#define VMXNET3_TCD_TXIDX_SHIFT 0217#define VMXNET3_TCD_TXIDX_SIZE 12218#define VMXNET3_TCD_GEN_DWORD_SHIFT 3219 220struct Vmxnet3_TxCompDesc {221 u32 txdIdx:12; /* Index of the EOP TxDesc */222 u32 ext1:20;223 224 __le32 ext2;225 __le32 ext3;226 227 u32 rsvd:24;228 u32 type:7; /* completion type */229 u32 gen:1; /* generation bit */230};231 232struct Vmxnet3_RxDesc {233 __le64 addr;234 235#ifdef __BIG_ENDIAN_BITFIELD236 u32 gen:1; /* Generation bit */237 u32 rsvd:15;238 u32 dtype:1; /* Descriptor type */239 u32 btype:1; /* Buffer Type */240 u32 len:14;241#else242 u32 len:14;243 u32 btype:1; /* Buffer Type */244 u32 dtype:1; /* Descriptor type */245 u32 rsvd:15;246 u32 gen:1; /* Generation bit */247#endif248 u32 ext1;249};250 251/* values of RXD.BTYPE */252#define VMXNET3_RXD_BTYPE_HEAD 0 /* head only */253#define VMXNET3_RXD_BTYPE_BODY 1 /* body only */254 255/* fields in RxDesc we access w/o using bit fields */256#define VMXNET3_RXD_BTYPE_SHIFT 14257#define VMXNET3_RXD_GEN_SHIFT 31258 259#define VMXNET3_RCD_HDR_INNER_SHIFT 13260 261struct Vmxnet3TSInfo {262 u64 tsData:56;263 u64 tsType:4;264 u64 tsi:1; //bit to indicate to set ts265 u64 pad:3;266 u64 pad2;267};268 269struct Vmxnet3_TxTSDesc {270 struct Vmxnet3TSInfo ts;271 u64 pad[14];272};273 274struct Vmxnet3_RxTSDesc {275 struct Vmxnet3TSInfo ts;276 u64 pad[14];277};278 279struct Vmxnet3_RxCompDesc {280#ifdef __BIG_ENDIAN_BITFIELD281 u32 ext2:1;282 u32 cnc:1; /* Checksum Not Calculated */283 u32 rssType:4; /* RSS hash type used */284 u32 rqID:10; /* rx queue/ring ID */285 u32 sop:1; /* Start of Packet */286 u32 eop:1; /* End of Packet */287 u32 ext1:2; /* bit 0: indicating v4/v6/.. is for inner header */288 /* bit 1: indicating rssType is based on inner header */289 u32 rxdIdx:12; /* Index of the RxDesc */290#else291 u32 rxdIdx:12; /* Index of the RxDesc */292 u32 ext1:2; /* bit 0: indicating v4/v6/.. is for inner header */293 /* bit 1: indicating rssType is based on inner header */294 u32 eop:1; /* End of Packet */295 u32 sop:1; /* Start of Packet */296 u32 rqID:10; /* rx queue/ring ID */297 u32 rssType:4; /* RSS hash type used */298 u32 cnc:1; /* Checksum Not Calculated */299 u32 ext2:1;300#endif /* __BIG_ENDIAN_BITFIELD */301 302 __le32 rssHash; /* RSS hash value */303 304#ifdef __BIG_ENDIAN_BITFIELD305 u32 tci:16; /* Tag stripped */306 u32 ts:1; /* Tag is stripped */307 u32 err:1; /* Error */308 u32 len:14; /* data length */309#else310 u32 len:14; /* data length */311 u32 err:1; /* Error */312 u32 ts:1; /* Tag is stripped */313 u32 tci:16; /* Tag stripped */314#endif /* __BIG_ENDIAN_BITFIELD */315 316 317#ifdef __BIG_ENDIAN_BITFIELD318 u32 gen:1; /* generation bit */319 u32 type:7; /* completion type */320 u32 fcs:1; /* Frame CRC correct */321 u32 frg:1; /* IP Fragment */322 u32 v4:1; /* IPv4 */323 u32 v6:1; /* IPv6 */324 u32 ipc:1; /* IP Checksum Correct */325 u32 tcp:1; /* TCP packet */326 u32 udp:1; /* UDP packet */327 u32 tuc:1; /* TCP/UDP Checksum Correct */328 u32 csum:16;329#else330 u32 csum:16;331 u32 tuc:1; /* TCP/UDP Checksum Correct */332 u32 udp:1; /* UDP packet */333 u32 tcp:1; /* TCP packet */334 u32 ipc:1; /* IP Checksum Correct */335 u32 v6:1; /* IPv6 */336 u32 v4:1; /* IPv4 */337 u32 frg:1; /* IP Fragment */338 u32 fcs:1; /* Frame CRC correct */339 u32 type:7; /* completion type */340 u32 gen:1; /* generation bit */341#endif /* __BIG_ENDIAN_BITFIELD */342};343 344struct Vmxnet3_RxCompDescExt {345 __le32 dword1;346 u8 segCnt; /* Number of aggregated packets */347 u8 dupAckCnt; /* Number of duplicate Acks */348 __le16 tsDelta; /* TCP timestamp difference */349 __le32 dword2;350#ifdef __BIG_ENDIAN_BITFIELD351 u32 gen:1; /* generation bit */352 u32 type:7; /* completion type */353 u32 fcs:1; /* Frame CRC correct */354 u32 frg:1; /* IP Fragment */355 u32 v4:1; /* IPv4 */356 u32 v6:1; /* IPv6 */357 u32 ipc:1; /* IP Checksum Correct */358 u32 tcp:1; /* TCP packet */359 u32 udp:1; /* UDP packet */360 u32 tuc:1; /* TCP/UDP Checksum Correct */361 u32 mss:16;362#else363 u32 mss:16;364 u32 tuc:1; /* TCP/UDP Checksum Correct */365 u32 udp:1; /* UDP packet */366 u32 tcp:1; /* TCP packet */367 u32 ipc:1; /* IP Checksum Correct */368 u32 v6:1; /* IPv6 */369 u32 v4:1; /* IPv4 */370 u32 frg:1; /* IP Fragment */371 u32 fcs:1; /* Frame CRC correct */372 u32 type:7; /* completion type */373 u32 gen:1; /* generation bit */374#endif /* __BIG_ENDIAN_BITFIELD */375};376 377 378/* fields in RxCompDesc we access via Vmxnet3_GenericDesc.dword[3] */379#define VMXNET3_RCD_TUC_SHIFT 16380#define VMXNET3_RCD_IPC_SHIFT 19381 382/* fields in RxCompDesc we access via Vmxnet3_GenericDesc.qword[1] */383#define VMXNET3_RCD_TYPE_SHIFT 56384#define VMXNET3_RCD_GEN_SHIFT 63385 386/* csum OK for TCP/UDP pkts over IP */387#define VMXNET3_RCD_CSUM_OK (1 << VMXNET3_RCD_TUC_SHIFT | \388 1 << VMXNET3_RCD_IPC_SHIFT)389#define VMXNET3_TXD_GEN_SIZE 1390#define VMXNET3_TXD_EOP_SIZE 1391 392/* value of RxCompDesc.rssType */393#define VMXNET3_RCD_RSS_TYPE_NONE 0394#define VMXNET3_RCD_RSS_TYPE_IPV4 1395#define VMXNET3_RCD_RSS_TYPE_TCPIPV4 2396#define VMXNET3_RCD_RSS_TYPE_IPV6 3397#define VMXNET3_RCD_RSS_TYPE_TCPIPV6 4398#define VMXNET3_RCD_RSS_TYPE_UDPIPV4 5399#define VMXNET3_RCD_RSS_TYPE_UDPIPV6 6400#define VMXNET3_RCD_RSS_TYPE_ESPIPV4 7401#define VMXNET3_RCD_RSS_TYPE_ESPIPV6 8402 403 404/* a union for accessing all cmd/completion descriptors */405union Vmxnet3_GenericDesc {406 __le64 qword[2];407 __le32 dword[4];408 __le16 word[8];409 struct Vmxnet3_TxDesc txd;410 struct Vmxnet3_RxDesc rxd;411 struct Vmxnet3_TxCompDesc tcd;412 struct Vmxnet3_RxCompDesc rcd;413 struct Vmxnet3_RxCompDescExt rcdExt;414};415 416#define VMXNET3_INIT_GEN 1417 418/* Max size of a single tx buffer */419#define VMXNET3_MAX_TX_BUF_SIZE (1 << 14)420 421/* # of tx desc needed for a tx buffer size */422#define VMXNET3_TXD_NEEDED(size) (((size) + VMXNET3_MAX_TX_BUF_SIZE - 1) / \423 VMXNET3_MAX_TX_BUF_SIZE)424 425/* max # of tx descs for a non-tso pkt */426#define VMXNET3_MAX_TXD_PER_PKT 16427/* max # of tx descs for a tso pkt */428#define VMXNET3_MAX_TSO_TXD_PER_PKT 24429 430/* Max size of a single rx buffer */431#define VMXNET3_MAX_RX_BUF_SIZE ((1 << 14) - 1)432/* Minimum size of a type 0 buffer */433#define VMXNET3_MIN_T0_BUF_SIZE 128434#define VMXNET3_MAX_CSUM_OFFSET 1024435 436/* Ring base address alignment */437#define VMXNET3_RING_BA_ALIGN 512438#define VMXNET3_RING_BA_MASK (VMXNET3_RING_BA_ALIGN - 1)439 440/* Ring size must be a multiple of 32 */441#define VMXNET3_RING_SIZE_ALIGN 32442#define VMXNET3_RING_SIZE_MASK (VMXNET3_RING_SIZE_ALIGN - 1)443 444/* Tx Data Ring buffer size must be a multiple of 64 */445#define VMXNET3_TXDATA_DESC_SIZE_ALIGN 64446#define VMXNET3_TXDATA_DESC_SIZE_MASK (VMXNET3_TXDATA_DESC_SIZE_ALIGN - 1)447 448/* Rx Data Ring buffer size must be a multiple of 64 */449#define VMXNET3_RXDATA_DESC_SIZE_ALIGN 64450#define VMXNET3_RXDATA_DESC_SIZE_MASK (VMXNET3_RXDATA_DESC_SIZE_ALIGN - 1)451 452/* Rx TS Ring buffer size must be a multiple of 64 bytes */453#define VMXNET3_RXTS_DESC_SIZE_ALIGN 64454#define VMXNET3_RXTS_DESC_SIZE_MASK (VMXNET3_RXTS_DESC_SIZE_ALIGN - 1)455/* Tx TS Ring buffer size must be a multiple of 64 bytes */456#define VMXNET3_TXTS_DESC_SIZE_ALIGN 64457#define VMXNET3_TXTS_DESC_SIZE_MASK (VMXNET3_TXTS_DESC_SIZE_ALIGN - 1)458 459/* Max ring size */460#define VMXNET3_TX_RING_MAX_SIZE 4096461#define VMXNET3_TC_RING_MAX_SIZE 4096462#define VMXNET3_RX_RING_MAX_SIZE 4096463#define VMXNET3_RX_RING2_MAX_SIZE 4096464#define VMXNET3_RC_RING_MAX_SIZE 8192465 466#define VMXNET3_TXDATA_DESC_MIN_SIZE 128467#define VMXNET3_TXDATA_DESC_MAX_SIZE 2048468 469#define VMXNET3_RXDATA_DESC_MAX_SIZE 2048470 471#define VMXNET3_TXTS_DESC_MAX_SIZE 256472#define VMXNET3_RXTS_DESC_MAX_SIZE 256473 474/* a list of reasons for queue stop */475 476enum {477 VMXNET3_ERR_NOEOP = 0x80000000, /* cannot find the EOP desc of a pkt */478 VMXNET3_ERR_TXD_REUSE = 0x80000001, /* reuse TxDesc before tx completion */479 VMXNET3_ERR_BIG_PKT = 0x80000002, /* too many TxDesc for a pkt */480 VMXNET3_ERR_DESC_NOT_SPT = 0x80000003, /* descriptor type not supported */481 VMXNET3_ERR_SMALL_BUF = 0x80000004, /* type 0 buffer too small */482 VMXNET3_ERR_STRESS = 0x80000005, /* stress option firing in vmkernel */483 VMXNET3_ERR_SWITCH = 0x80000006, /* mode switch failure */484 VMXNET3_ERR_TXD_INVALID = 0x80000007, /* invalid TxDesc */485};486 487/* completion descriptor types */488#define VMXNET3_CDTYPE_TXCOMP 0 /* Tx Completion Descriptor */489#define VMXNET3_CDTYPE_RXCOMP 3 /* Rx Completion Descriptor */490#define VMXNET3_CDTYPE_RXCOMP_LRO 4 /* Rx Completion Descriptor for LRO */491 492enum {493 VMXNET3_GOS_BITS_UNK = 0, /* unknown */494 VMXNET3_GOS_BITS_32 = 1,495 VMXNET3_GOS_BITS_64 = 2,496};497 498#define VMXNET3_GOS_TYPE_LINUX 1499 500 501struct Vmxnet3_GOSInfo {502#ifdef __BIG_ENDIAN_BITFIELD503 u32 gosMisc:10; /* other info about gos */504 u32 gosVer:16; /* gos version */505 u32 gosType:4; /* which guest */506 u32 gosBits:2; /* 32-bit or 64-bit? */507#else508 u32 gosBits:2; /* 32-bit or 64-bit? */509 u32 gosType:4; /* which guest */510 u32 gosVer:16; /* gos version */511 u32 gosMisc:10; /* other info about gos */512#endif /* __BIG_ENDIAN_BITFIELD */513};514 515struct Vmxnet3_DriverInfo {516 __le32 version;517 struct Vmxnet3_GOSInfo gos;518 __le32 vmxnet3RevSpt;519 __le32 uptVerSpt;520};521 522 523#define VMXNET3_REV1_MAGIC 3133079265u524 525/*526 * QueueDescPA must be 128 bytes aligned. It points to an array of527 * Vmxnet3_TxQueueDesc followed by an array of Vmxnet3_RxQueueDesc.528 * The number of Vmxnet3_TxQueueDesc/Vmxnet3_RxQueueDesc are specified by529 * Vmxnet3_MiscConf.numTxQueues/numRxQueues, respectively.530 */531#define VMXNET3_QUEUE_DESC_ALIGN 128532 533 534struct Vmxnet3_MiscConf {535 struct Vmxnet3_DriverInfo driverInfo;536 __le64 uptFeatures;537 __le64 ddPA; /* driver data PA */538 __le64 queueDescPA; /* queue descriptor table PA */539 __le32 ddLen; /* driver data len */540 __le32 queueDescLen; /* queue desc. table len in bytes */541 __le32 mtu;542 __le16 maxNumRxSG;543 u8 numTxQueues;544 u8 numRxQueues;545 __le32 reserved[4];546};547 548 549struct Vmxnet3_TxQueueConf {550 __le64 txRingBasePA;551 __le64 dataRingBasePA;552 __le64 compRingBasePA;553 __le64 ddPA; /* driver data */554 __le64 reserved;555 __le32 txRingSize; /* # of tx desc */556 __le32 dataRingSize; /* # of data desc */557 __le32 compRingSize; /* # of comp desc */558 __le32 ddLen; /* size of driver data */559 u8 intrIdx;560 u8 _pad1[1];561 __le16 txDataRingDescSize;562 u8 _pad2[4];563};564 565 566struct Vmxnet3_RxQueueConf {567 __le64 rxRingBasePA[2];568 __le64 compRingBasePA;569 __le64 ddPA; /* driver data */570 __le64 rxDataRingBasePA;571 __le32 rxRingSize[2]; /* # of rx desc */572 __le32 compRingSize; /* # of rx comp desc */573 __le32 ddLen; /* size of driver data */574 u8 intrIdx;575 u8 _pad1[1];576 __le16 rxDataRingDescSize; /* size of rx data ring buffer */577 u8 _pad2[4];578};579 580 581struct Vmxnet3_LatencyConf {582 u16 sampleRate;583 u16 pad;584};585 586struct Vmxnet3_TxQueueTSConf {587 __le64 txTSRingBasePA;588 __le16 txTSRingDescSize; /* size of tx timestamp ring buffer */589 u16 pad;590 struct Vmxnet3_LatencyConf latencyConf;591};592 593struct Vmxnet3_RxQueueTSConf {594 __le64 rxTSRingBasePA;595 __le16 rxTSRingDescSize; /* size of rx timestamp ring buffer */596 u16 pad[3];597};598 599enum vmxnet3_intr_mask_mode {600 VMXNET3_IMM_AUTO = 0,601 VMXNET3_IMM_ACTIVE = 1,602 VMXNET3_IMM_LAZY = 2603};604 605enum vmxnet3_intr_type {606 VMXNET3_IT_AUTO = 0,607 VMXNET3_IT_INTX = 1,608 VMXNET3_IT_MSI = 2,609 VMXNET3_IT_MSIX = 3610};611 612#define VMXNET3_MAX_TX_QUEUES 8613#define VMXNET3_MAX_RX_QUEUES 16614/* addition 1 for events */615#define VMXNET3_MAX_INTRS 25616 617/* Version 6 and later will use below macros */618#define VMXNET3_EXT_MAX_TX_QUEUES 32619#define VMXNET3_EXT_MAX_RX_QUEUES 32620/* addition 1 for events */621#define VMXNET3_EXT_MAX_INTRS 65622#define VMXNET3_FIRST_SET_INTRS 64623 624/* value of intrCtrl */625#define VMXNET3_IC_DISABLE_ALL 0x1 /* bit 0 */626 627 628struct Vmxnet3_IntrConf {629 bool autoMask;630 u8 numIntrs; /* # of interrupts */631 u8 eventIntrIdx;632 u8 modLevels[VMXNET3_MAX_INTRS]; /* moderation level for633 * each intr */634 __le32 intrCtrl;635 __le32 reserved[2];636};637 638struct Vmxnet3_IntrConfExt {639 u8 autoMask;640 u8 numIntrs; /* # of interrupts */641 u8 eventIntrIdx;642 u8 reserved;643 __le32 intrCtrl;644 __le32 reserved1;645 u8 modLevels[VMXNET3_EXT_MAX_INTRS]; /* moderation level for646 * each intr647 */648 u8 reserved2[3];649};650 651/* one bit per VLAN ID, the size is in the units of u32 */652#define VMXNET3_VFT_SIZE (4096 / (sizeof(u32) * 8))653 654 655struct Vmxnet3_QueueStatus {656 bool stopped;657 u8 _pad[3];658 __le32 error;659};660 661 662struct Vmxnet3_TxQueueCtrl {663 __le32 txNumDeferred;664 __le32 txThreshold;665 __le64 reserved;666};667 668 669struct Vmxnet3_RxQueueCtrl {670 bool updateRxProd;671 u8 _pad[7];672 __le64 reserved;673};674 675enum {676 VMXNET3_RXM_UCAST = 0x01, /* unicast only */677 VMXNET3_RXM_MCAST = 0x02, /* multicast passing the filters */678 VMXNET3_RXM_BCAST = 0x04, /* broadcast only */679 VMXNET3_RXM_ALL_MULTI = 0x08, /* all multicast */680 VMXNET3_RXM_PROMISC = 0x10 /* promiscuous */681};682 683struct Vmxnet3_RxFilterConf {684 __le32 rxMode; /* VMXNET3_RXM_xxx */685 __le16 mfTableLen; /* size of the multicast filter table */686 __le16 _pad1;687 __le64 mfTablePA; /* PA of the multicast filters table */688 __le32 vfTable[VMXNET3_VFT_SIZE]; /* vlan filter */689};690 691 692#define VMXNET3_PM_MAX_FILTERS 6693#define VMXNET3_PM_MAX_PATTERN_SIZE 128694#define VMXNET3_PM_MAX_MASK_SIZE (VMXNET3_PM_MAX_PATTERN_SIZE / 8)695 696#define VMXNET3_PM_WAKEUP_MAGIC cpu_to_le16(0x01) /* wake up on magic pkts */697#define VMXNET3_PM_WAKEUP_FILTER cpu_to_le16(0x02) /* wake up on pkts matching698 * filters */699 700 701struct Vmxnet3_PM_PktFilter {702 u8 maskSize;703 u8 patternSize;704 u8 mask[VMXNET3_PM_MAX_MASK_SIZE];705 u8 pattern[VMXNET3_PM_MAX_PATTERN_SIZE];706 u8 pad[6];707};708 709 710struct Vmxnet3_PMConf {711 __le16 wakeUpEvents; /* VMXNET3_PM_WAKEUP_xxx */712 u8 numFilters;713 u8 pad[5];714 struct Vmxnet3_PM_PktFilter filters[VMXNET3_PM_MAX_FILTERS];715};716 717 718struct Vmxnet3_VariableLenConfDesc {719 __le32 confVer;720 __le32 confLen;721 __le64 confPA;722};723 724 725struct Vmxnet3_TxQueueDesc {726 struct Vmxnet3_TxQueueCtrl ctrl;727 struct Vmxnet3_TxQueueConf conf;728 729 /* Driver read after a GET command */730 struct Vmxnet3_QueueStatus status;731 struct UPT1_TxStats stats;732 struct Vmxnet3_TxQueueTSConf tsConf;733 u8 _pad[72]; /* 128 aligned */734};735 736 737struct Vmxnet3_RxQueueDesc {738 struct Vmxnet3_RxQueueCtrl ctrl;739 struct Vmxnet3_RxQueueConf conf;740 /* Driver read after a GET commad */741 struct Vmxnet3_QueueStatus status;742 struct UPT1_RxStats stats;743 struct Vmxnet3_RxQueueTSConf tsConf;744 u8 __pad[72]; /* 128 aligned */745};746 747struct Vmxnet3_SetPolling {748 u8 enablePolling;749};750 751#define VMXNET3_COAL_STATIC_MAX_DEPTH 128752#define VMXNET3_COAL_RBC_MIN_RATE 100753#define VMXNET3_COAL_RBC_MAX_RATE 100000754 755enum Vmxnet3_CoalesceMode {756 VMXNET3_COALESCE_DISABLED = 0,757 VMXNET3_COALESCE_ADAPT = 1,758 VMXNET3_COALESCE_STATIC = 2,759 VMXNET3_COALESCE_RBC = 3760};761 762struct Vmxnet3_CoalesceRbc {763 u32 rbc_rate;764};765 766struct Vmxnet3_CoalesceStatic {767 u32 tx_depth;768 u32 tx_comp_depth;769 u32 rx_depth;770};771 772struct Vmxnet3_CoalesceScheme {773 enum Vmxnet3_CoalesceMode coalMode;774 union {775 struct Vmxnet3_CoalesceRbc coalRbc;776 struct Vmxnet3_CoalesceStatic coalStatic;777 } coalPara;778};779 780struct Vmxnet3_MemoryRegion {781 __le64 startPA;782 __le32 length;783 __le16 txQueueBits;784 __le16 rxQueueBits;785};786 787#define MAX_MEMORY_REGION_PER_QUEUE 16788#define MAX_MEMORY_REGION_PER_DEVICE 256789 790struct Vmxnet3_MemRegs {791 __le16 numRegs;792 __le16 pad[3];793 struct Vmxnet3_MemoryRegion memRegs[1];794};795 796enum Vmxnet3_RSSField {797 VMXNET3_RSS_FIELDS_TCPIP4 = 0x0001,798 VMXNET3_RSS_FIELDS_TCPIP6 = 0x0002,799 VMXNET3_RSS_FIELDS_UDPIP4 = 0x0004,800 VMXNET3_RSS_FIELDS_UDPIP6 = 0x0008,801 VMXNET3_RSS_FIELDS_ESPIP4 = 0x0010,802 VMXNET3_RSS_FIELDS_ESPIP6 = 0x0020,803};804 805struct Vmxnet3_RingBufferSize {806 __le16 ring1BufSizeType0;807 __le16 ring1BufSizeType1;808 __le16 ring2BufSizeType1;809 __le16 pad;810};811 812/* If the command data <= 16 bytes, use the shared memory directly.813 * otherwise, use variable length configuration descriptor.814 */815union Vmxnet3_CmdInfo {816 struct Vmxnet3_VariableLenConfDesc varConf;817 struct Vmxnet3_SetPolling setPolling;818 enum Vmxnet3_RSSField setRssFields;819 struct Vmxnet3_RingBufferSize ringBufSize;820 __le64 data[2];821};822 823struct Vmxnet3_DSDevRead {824 /* read-only region for device, read by dev in response to a SET cmd */825 struct Vmxnet3_MiscConf misc;826 struct Vmxnet3_IntrConf intrConf;827 struct Vmxnet3_RxFilterConf rxFilterConf;828 struct Vmxnet3_VariableLenConfDesc rssConfDesc;829 struct Vmxnet3_VariableLenConfDesc pmConfDesc;830 struct Vmxnet3_VariableLenConfDesc pluginConfDesc;831};832 833struct Vmxnet3_DSDevReadExt {834 /* read-only region for device, read by dev in response to a SET cmd */835 struct Vmxnet3_IntrConfExt intrConfExt;836};837 838/* All structures in DriverShared are padded to multiples of 8 bytes */839struct Vmxnet3_DriverShared {840 __le32 magic;841 /* make devRead start at 64bit boundaries */842 __le32 size; /* size of DriverShared */843 struct Vmxnet3_DSDevRead devRead;844 __le32 ecr;845 __le32 reserved;846 union {847 __le32 reserved1[4];848 union Vmxnet3_CmdInfo cmdInfo; /* only valid in the context of849 * executing the relevant850 * command851 */852 } cu;853 struct Vmxnet3_DSDevReadExt devReadExt;854};855 856 857#define VMXNET3_ECR_RQERR (1 << 0)858#define VMXNET3_ECR_TQERR (1 << 1)859#define VMXNET3_ECR_LINK (1 << 2)860#define VMXNET3_ECR_DIC (1 << 3)861#define VMXNET3_ECR_DEBUG (1 << 4)862 863/* flip the gen bit of a ring */864#define VMXNET3_FLIP_RING_GEN(gen) ((gen) = (gen) ^ 0x1)865 866/* only use this if moving the idx won't affect the gen bit */867#define VMXNET3_INC_RING_IDX_ONLY(idx, ring_size) \868 do {\869 (idx)++;\870 if (unlikely((idx) == (ring_size))) {\871 (idx) = 0;\872 } \873 } while (0)874 875#define VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid) \876 (vfTable[vid >> 5] |= (1 << (vid & 31)))877#define VMXNET3_CLEAR_VFTABLE_ENTRY(vfTable, vid) \878 (vfTable[vid >> 5] &= ~(1 << (vid & 31)))879 880#define VMXNET3_VFTABLE_ENTRY_IS_SET(vfTable, vid) \881 ((vfTable[vid >> 5] & (1 << (vid & 31))) != 0)882 883#define VMXNET3_MAX_MTU 9000884#define VMXNET3_V6_MAX_MTU 9190885#define VMXNET3_MIN_MTU 60886 887#define VMXNET3_LINK_UP (10000 << 16 | 1) /* 10 Gbps, up */888#define VMXNET3_LINK_DOWN 0889 890#define VMXNET3_DCR_ERROR 31 /* error when bit 31 of DCR is set */891#define VMXNET3_CAP_UDP_RSS 0 /* bit 0 of DCR 0 */892#define VMXNET3_CAP_ESP_RSS_IPV4 1 /* bit 1 of DCR 0 */893#define VMXNET3_CAP_GENEVE_CHECKSUM_OFFLOAD 2 /* bit 2 of DCR 0 */894#define VMXNET3_CAP_GENEVE_TSO 3 /* bit 3 of DCR 0 */895#define VMXNET3_CAP_VXLAN_CHECKSUM_OFFLOAD 4 /* bit 4 of DCR 0 */896#define VMXNET3_CAP_VXLAN_TSO 5 /* bit 5 of DCR 0 */897#define VMXNET3_CAP_GENEVE_OUTER_CHECKSUM_OFFLOAD 6 /* bit 6 of DCR 0 */898#define VMXNET3_CAP_VXLAN_OUTER_CHECKSUM_OFFLOAD 7 /* bit 7 of DCR 0 */899#define VMXNET3_CAP_PKT_STEERING_IPV4 8 /* bit 8 of DCR 0 */900#define VMXNET3_CAP_VERSION_4_MAX VMXNET3_CAP_PKT_STEERING_IPV4901#define VMXNET3_CAP_ESP_RSS_IPV6 9 /* bit 9 of DCR 0 */902#define VMXNET3_CAP_VERSION_5_MAX VMXNET3_CAP_ESP_RSS_IPV6903#define VMXNET3_CAP_ESP_OVER_UDP_RSS 10 /* bit 10 of DCR 0 */904#define VMXNET3_CAP_INNER_RSS 11 /* bit 11 of DCR 0 */905#define VMXNET3_CAP_INNER_ESP_RSS 12 /* bit 12 of DCR 0 */906#define VMXNET3_CAP_CRC32_HASH_FUNC 13 /* bit 13 of DCR 0 */907#define VMXNET3_CAP_VERSION_6_MAX VMXNET3_CAP_CRC32_HASH_FUNC908#define VMXNET3_CAP_OAM_FILTER 14 /* bit 14 of DCR 0 */909#define VMXNET3_CAP_ESP_QS 15 /* bit 15 of DCR 0 */910#define VMXNET3_CAP_LARGE_BAR 16 /* bit 16 of DCR 0 */911#define VMXNET3_CAP_OOORX_COMP 17 /* bit 17 of DCR 0 */912#define VMXNET3_CAP_VERSION_7_MAX 18913/* when new capability is introduced, update VMXNET3_CAP_MAX */914#define VMXNET3_CAP_MAX VMXNET3_CAP_VERSION_7_MAX915 916#define VMXNET3_OFFLOAD_TSO BIT(0)917#define VMXNET3_OFFLOAD_LRO BIT(1)918 919#endif /* _VMXNET3_DEFS_H_ */920