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1// SPDX-License-Identifier: GPL-2.0-or-later2/* FarSync WAN driver for Linux (2.6.x kernel version)3 *4 * Actually sync driver for X.21, V.35 and V.24 on FarSync T-series cards5 *6 * Copyright (C) 2001-2004 FarSite Communications Ltd.7 * www.farsite.co.uk8 *9 * Author: R.J.Dunlop <bob.dunlop@farsite.co.uk>10 * Maintainer: Kevin Curtis <kevin.curtis@farsite.co.uk>11 */12 13#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt14 15#include <linux/module.h>16#include <linux/kernel.h>17#include <linux/version.h>18#include <linux/pci.h>19#include <linux/sched.h>20#include <linux/slab.h>21#include <linux/ioport.h>22#include <linux/init.h>23#include <linux/interrupt.h>24#include <linux/delay.h>25#include <linux/if.h>26#include <linux/hdlc.h>27#include <asm/io.h>28#include <linux/uaccess.h>29 30#include "farsync.h"31 32/* Module info33 */34MODULE_AUTHOR("R.J.Dunlop <bob.dunlop@farsite.co.uk>");35MODULE_DESCRIPTION("FarSync T-Series WAN driver. FarSite Communications Ltd.");36MODULE_LICENSE("GPL");37 38/* Driver configuration and global parameters39 * ==========================================40 */41 42/* Number of ports (per card) and cards supported43 */44#define FST_MAX_PORTS 445#define FST_MAX_CARDS 3246 47/* Default parameters for the link48 */49#define FST_TX_QUEUE_LEN 100 /* At 8Mbps a longer queue length is50 * useful51 */52#define FST_TXQ_DEPTH 16 /* This one is for the buffering53 * of frames on the way down to the card54 * so that we can keep the card busy55 * and maximise throughput56 */57#define FST_HIGH_WATER_MARK 12 /* Point at which we flow control58 * network layer59 */60#define FST_LOW_WATER_MARK 8 /* Point at which we remove flow61 * control from network layer62 */63#define FST_MAX_MTU 8000 /* Huge but possible */64#define FST_DEF_MTU 1500 /* Common sane value */65 66#define FST_TX_TIMEOUT (2 * HZ)67 68#ifdef ARPHRD_RAWHDLC69#define ARPHRD_MYTYPE ARPHRD_RAWHDLC /* Raw frames */70#else71#define ARPHRD_MYTYPE ARPHRD_HDLC /* Cisco-HDLC (keepalives etc) */72#endif73 74/* Modules parameters and associated variables75 */76static int fst_txq_low = FST_LOW_WATER_MARK;77static int fst_txq_high = FST_HIGH_WATER_MARK;78static int fst_max_reads = 7;79static int fst_excluded_cards;80static int fst_excluded_list[FST_MAX_CARDS];81 82module_param(fst_txq_low, int, 0);83module_param(fst_txq_high, int, 0);84module_param(fst_max_reads, int, 0);85module_param(fst_excluded_cards, int, 0);86module_param_array(fst_excluded_list, int, NULL, 0);87 88/* Card shared memory layout89 * =========================90 */91#pragma pack(1)92 93/* This information is derived in part from the FarSite FarSync Smc.h94 * file. Unfortunately various name clashes and the non-portability of the95 * bit field declarations in that file have meant that I have chosen to96 * recreate the information here.97 *98 * The SMC (Shared Memory Configuration) has a version number that is99 * incremented every time there is a significant change. This number can100 * be used to check that we have not got out of step with the firmware101 * contained in the .CDE files.102 */103#define SMC_VERSION 24104 105#define FST_MEMSIZE 0x100000 /* Size of card memory (1Mb) */106 107#define SMC_BASE 0x00002000L /* Base offset of the shared memory window main108 * configuration structure109 */110#define BFM_BASE 0x00010000L /* Base offset of the shared memory window DMA111 * buffers112 */113 114#define LEN_TX_BUFFER 8192 /* Size of packet buffers */115#define LEN_RX_BUFFER 8192116 117#define LEN_SMALL_TX_BUFFER 256 /* Size of obsolete buffs used for DOS diags */118#define LEN_SMALL_RX_BUFFER 256119 120#define NUM_TX_BUFFER 2 /* Must be power of 2. Fixed by firmware */121#define NUM_RX_BUFFER 8122 123/* Interrupt retry time in milliseconds */124#define INT_RETRY_TIME 2125 126/* The Am186CH/CC processors support a SmartDMA mode using circular pools127 * of buffer descriptors. The structure is almost identical to that used128 * in the LANCE Ethernet controllers. Details available as PDF from the129 * AMD web site: https://www.amd.com/products/epd/processors/\130 * 2.16bitcont/3.am186cxfa/a21914/21914.pdf131 */132struct txdesc { /* Transmit descriptor */133 volatile u16 ladr; /* Low order address of packet. This is a134 * linear address in the Am186 memory space135 */136 volatile u8 hadr; /* High order address. Low 4 bits only, high 4137 * bits must be zero138 */139 volatile u8 bits; /* Status and config */140 volatile u16 bcnt; /* 2s complement of packet size in low 15 bits.141 * Transmit terminal count interrupt enable in142 * top bit.143 */144 u16 unused; /* Not used in Tx */145};146 147struct rxdesc { /* Receive descriptor */148 volatile u16 ladr; /* Low order address of packet */149 volatile u8 hadr; /* High order address */150 volatile u8 bits; /* Status and config */151 volatile u16 bcnt; /* 2s complement of buffer size in low 15 bits.152 * Receive terminal count interrupt enable in153 * top bit.154 */155 volatile u16 mcnt; /* Message byte count (15 bits) */156};157 158/* Convert a length into the 15 bit 2's complement */159/* #define cnv_bcnt(len) (( ~(len) + 1 ) & 0x7FFF ) */160/* Since we need to set the high bit to enable the completion interrupt this161 * can be made a lot simpler162 */163#define cnv_bcnt(len) (-(len))164 165/* Status and config bits for the above */166#define DMA_OWN 0x80 /* SmartDMA owns the descriptor */167#define TX_STP 0x02 /* Tx: start of packet */168#define TX_ENP 0x01 /* Tx: end of packet */169#define RX_ERR 0x40 /* Rx: error (OR of next 4 bits) */170#define RX_FRAM 0x20 /* Rx: framing error */171#define RX_OFLO 0x10 /* Rx: overflow error */172#define RX_CRC 0x08 /* Rx: CRC error */173#define RX_HBUF 0x04 /* Rx: buffer error */174#define RX_STP 0x02 /* Rx: start of packet */175#define RX_ENP 0x01 /* Rx: end of packet */176 177/* Interrupts from the card are caused by various events which are presented178 * in a circular buffer as several events may be processed on one physical int179 */180#define MAX_CIRBUFF 32181 182struct cirbuff {183 u8 rdindex; /* read, then increment and wrap */184 u8 wrindex; /* write, then increment and wrap */185 u8 evntbuff[MAX_CIRBUFF];186};187 188/* Interrupt event codes.189 * Where appropriate the two low order bits indicate the port number190 */191#define CTLA_CHG 0x18 /* Control signal changed */192#define CTLB_CHG 0x19193#define CTLC_CHG 0x1A194#define CTLD_CHG 0x1B195 196#define INIT_CPLT 0x20 /* Initialisation complete */197#define INIT_FAIL 0x21 /* Initialisation failed */198 199#define ABTA_SENT 0x24 /* Abort sent */200#define ABTB_SENT 0x25201#define ABTC_SENT 0x26202#define ABTD_SENT 0x27203 204#define TXA_UNDF 0x28 /* Transmission underflow */205#define TXB_UNDF 0x29206#define TXC_UNDF 0x2A207#define TXD_UNDF 0x2B208 209#define F56_INT 0x2C210#define M32_INT 0x2D211 212#define TE1_ALMA 0x30213 214/* Port physical configuration. See farsync.h for field values */215struct port_cfg {216 u16 lineInterface; /* Physical interface type */217 u8 x25op; /* Unused at present */218 u8 internalClock; /* 1 => internal clock, 0 => external */219 u8 transparentMode; /* 1 => on, 0 => off */220 u8 invertClock; /* 0 => normal, 1 => inverted */221 u8 padBytes[6]; /* Padding */222 u32 lineSpeed; /* Speed in bps */223};224 225/* TE1 port physical configuration */226struct su_config {227 u32 dataRate;228 u8 clocking;229 u8 framing;230 u8 structure;231 u8 interface;232 u8 coding;233 u8 lineBuildOut;234 u8 equalizer;235 u8 transparentMode;236 u8 loopMode;237 u8 range;238 u8 txBufferMode;239 u8 rxBufferMode;240 u8 startingSlot;241 u8 losThreshold;242 u8 enableIdleCode;243 u8 idleCode;244 u8 spare[44];245};246 247/* TE1 Status */248struct su_status {249 u32 receiveBufferDelay;250 u32 framingErrorCount;251 u32 codeViolationCount;252 u32 crcErrorCount;253 u32 lineAttenuation;254 u8 portStarted;255 u8 lossOfSignal;256 u8 receiveRemoteAlarm;257 u8 alarmIndicationSignal;258 u8 spare[40];259};260 261/* Finally sling all the above together into the shared memory structure.262 * Sorry it's a hodge podge of arrays, structures and unused bits, it's been263 * evolving under NT for some time so I guess we're stuck with it.264 * The structure starts at offset SMC_BASE.265 * See farsync.h for some field values.266 */267struct fst_shared {268 /* DMA descriptor rings */269 struct rxdesc rxDescrRing[FST_MAX_PORTS][NUM_RX_BUFFER];270 struct txdesc txDescrRing[FST_MAX_PORTS][NUM_TX_BUFFER];271 272 /* Obsolete small buffers */273 u8 smallRxBuffer[FST_MAX_PORTS][NUM_RX_BUFFER][LEN_SMALL_RX_BUFFER];274 u8 smallTxBuffer[FST_MAX_PORTS][NUM_TX_BUFFER][LEN_SMALL_TX_BUFFER];275 276 u8 taskStatus; /* 0x00 => initialising, 0x01 => running,277 * 0xFF => halted278 */279 280 u8 interruptHandshake; /* Set to 0x01 by adapter to signal interrupt,281 * set to 0xEE by host to acknowledge interrupt282 */283 284 u16 smcVersion; /* Must match SMC_VERSION */285 286 u32 smcFirmwareVersion; /* 0xIIVVRRBB where II = product ID, VV = major287 * version, RR = revision and BB = build288 */289 290 u16 txa_done; /* Obsolete completion flags */291 u16 rxa_done;292 u16 txb_done;293 u16 rxb_done;294 u16 txc_done;295 u16 rxc_done;296 u16 txd_done;297 u16 rxd_done;298 299 u16 mailbox[4]; /* Diagnostics mailbox. Not used */300 301 struct cirbuff interruptEvent; /* interrupt causes */302 303 u32 v24IpSts[FST_MAX_PORTS]; /* V.24 control input status */304 u32 v24OpSts[FST_MAX_PORTS]; /* V.24 control output status */305 306 struct port_cfg portConfig[FST_MAX_PORTS];307 308 u16 clockStatus[FST_MAX_PORTS]; /* lsb: 0=> present, 1=> absent */309 310 u16 cableStatus; /* lsb: 0=> present, 1=> absent */311 312 u16 txDescrIndex[FST_MAX_PORTS]; /* transmit descriptor ring index */313 u16 rxDescrIndex[FST_MAX_PORTS]; /* receive descriptor ring index */314 315 u16 portMailbox[FST_MAX_PORTS][2]; /* command, modifier */316 u16 cardMailbox[4]; /* Not used */317 318 /* Number of times the card thinks the host has319 * missed an interrupt by not acknowledging320 * within 2mS (I guess NT has problems)321 */322 u32 interruptRetryCount;323 324 /* Driver private data used as an ID. We'll not325 * use this as I'd rather keep such things326 * in main memory rather than on the PCI bus327 */328 u32 portHandle[FST_MAX_PORTS];329 330 /* Count of Tx underflows for stats */331 u32 transmitBufferUnderflow[FST_MAX_PORTS];332 333 /* Debounced V.24 control input status */334 u32 v24DebouncedSts[FST_MAX_PORTS];335 336 /* Adapter debounce timers. Don't touch */337 u32 ctsTimer[FST_MAX_PORTS];338 u32 ctsTimerRun[FST_MAX_PORTS];339 u32 dcdTimer[FST_MAX_PORTS];340 u32 dcdTimerRun[FST_MAX_PORTS];341 342 u32 numberOfPorts; /* Number of ports detected at startup */343 344 u16 _reserved[64];345 346 u16 cardMode; /* Bit-mask to enable features:347 * Bit 0: 1 enables LED identify mode348 */349 350 u16 portScheduleOffset;351 352 struct su_config suConfig; /* TE1 Bits */353 struct su_status suStatus;354 355 u32 endOfSmcSignature; /* endOfSmcSignature MUST be the last member of356 * the structure and marks the end of shared357 * memory. Adapter code initializes it as358 * END_SIG.359 */360};361 362/* endOfSmcSignature value */363#define END_SIG 0x12345678364 365/* Mailbox values. (portMailbox) */366#define NOP 0 /* No operation */367#define ACK 1 /* Positive acknowledgement to PC driver */368#define NAK 2 /* Negative acknowledgement to PC driver */369#define STARTPORT 3 /* Start an HDLC port */370#define STOPPORT 4 /* Stop an HDLC port */371#define ABORTTX 5 /* Abort the transmitter for a port */372#define SETV24O 6 /* Set V24 outputs */373 374/* PLX Chip Register Offsets */375#define CNTRL_9052 0x50 /* Control Register */376#define CNTRL_9054 0x6c /* Control Register */377 378#define INTCSR_9052 0x4c /* Interrupt control/status register */379#define INTCSR_9054 0x68 /* Interrupt control/status register */380 381/* 9054 DMA Registers */382/* Note that we will be using DMA Channel 0 for copying rx data383 * and Channel 1 for copying tx data384 */385#define DMAMODE0 0x80386#define DMAPADR0 0x84387#define DMALADR0 0x88388#define DMASIZ0 0x8c389#define DMADPR0 0x90390#define DMAMODE1 0x94391#define DMAPADR1 0x98392#define DMALADR1 0x9c393#define DMASIZ1 0xa0394#define DMADPR1 0xa4395#define DMACSR0 0xa8396#define DMACSR1 0xa9397#define DMAARB 0xac398#define DMATHR 0xb0399#define DMADAC0 0xb4400#define DMADAC1 0xb8401#define DMAMARBR 0xac402 403#define FST_MIN_DMA_LEN 64404#define FST_RX_DMA_INT 0x01405#define FST_TX_DMA_INT 0x02406#define FST_CARD_INT 0x04407 408/* Larger buffers are positioned in memory at offset BFM_BASE */409struct buf_window {410 u8 txBuffer[FST_MAX_PORTS][NUM_TX_BUFFER][LEN_TX_BUFFER];411 u8 rxBuffer[FST_MAX_PORTS][NUM_RX_BUFFER][LEN_RX_BUFFER];412};413 414/* Calculate offset of a buffer object within the shared memory window */415#define BUF_OFFSET(X) (BFM_BASE + offsetof(struct buf_window, X))416 417#pragma pack()418 419/* Device driver private information420 * =================================421 */422/* Per port (line or channel) information423 */424struct fst_port_info {425 struct net_device *dev; /* Device struct - must be first */426 struct fst_card_info *card; /* Card we're associated with */427 int index; /* Port index on the card */428 int hwif; /* Line hardware (lineInterface copy) */429 int run; /* Port is running */430 int mode; /* Normal or FarSync raw */431 int rxpos; /* Next Rx buffer to use */432 int txpos; /* Next Tx buffer to use */433 int txipos; /* Next Tx buffer to check for free */434 int start; /* Indication of start/stop to network */435 /* A sixteen entry transmit queue436 */437 int txqs; /* index to get next buffer to tx */438 int txqe; /* index to queue next packet */439 struct sk_buff *txq[FST_TXQ_DEPTH]; /* The queue */440 int rxqdepth;441};442 443/* Per card information444 */445struct fst_card_info {446 char __iomem *mem; /* Card memory mapped to kernel space */447 char __iomem *ctlmem; /* Control memory for PCI cards */448 unsigned int phys_mem; /* Physical memory window address */449 unsigned int phys_ctlmem; /* Physical control memory address */450 unsigned int irq; /* Interrupt request line number */451 unsigned int nports; /* Number of serial ports */452 unsigned int type; /* Type index of card */453 unsigned int state; /* State of card */454 spinlock_t card_lock; /* Lock for SMP access */455 unsigned short pci_conf; /* PCI card config in I/O space */456 /* Per port info */457 struct fst_port_info ports[FST_MAX_PORTS];458 struct pci_dev *device; /* Information about the pci device */459 int card_no; /* Inst of the card on the system */460 int family; /* TxP or TxU */461 int dmarx_in_progress;462 int dmatx_in_progress;463 unsigned long int_count;464 unsigned long int_time_ave;465 void *rx_dma_handle_host;466 dma_addr_t rx_dma_handle_card;467 void *tx_dma_handle_host;468 dma_addr_t tx_dma_handle_card;469 struct sk_buff *dma_skb_rx;470 struct fst_port_info *dma_port_rx;471 struct fst_port_info *dma_port_tx;472 int dma_len_rx;473 int dma_len_tx;474 int dma_txpos;475 int dma_rxpos;476};477 478/* Convert an HDLC device pointer into a port info pointer and similar */479#define dev_to_port(D) (dev_to_hdlc(D)->priv)480#define port_to_dev(P) ((P)->dev)481 482/* Shared memory window access macros483 *484 * We have a nice memory based structure above, which could be directly485 * mapped on i386 but might not work on other architectures unless we use486 * the readb,w,l and writeb,w,l macros. Unfortunately these macros take487 * physical offsets so we have to convert. The only saving grace is that488 * this should all collapse back to a simple indirection eventually.489 */490#define WIN_OFFSET(X) ((long)&(((struct fst_shared *)SMC_BASE)->X))491 492#define FST_RDB(C, E) (readb((C)->mem + WIN_OFFSET(E)))493#define FST_RDW(C, E) (readw((C)->mem + WIN_OFFSET(E)))494#define FST_RDL(C, E) (readl((C)->mem + WIN_OFFSET(E)))495 496#define FST_WRB(C, E, B) (writeb((B), (C)->mem + WIN_OFFSET(E)))497#define FST_WRW(C, E, W) (writew((W), (C)->mem + WIN_OFFSET(E)))498#define FST_WRL(C, E, L) (writel((L), (C)->mem + WIN_OFFSET(E)))499 500/* Debug support501 */502#if FST_DEBUG503 504static int fst_debug_mask = { FST_DEBUG };505 506/* Most common debug activity is to print something if the corresponding bit507 * is set in the debug mask. Note: this uses a non-ANSI extension in GCC to508 * support variable numbers of macro parameters. The inverted if prevents us509 * eating someone else's else clause.510 */511#define dbg(F, fmt, args...) \512do { \513 if (fst_debug_mask & (F)) \514 printk(KERN_DEBUG pr_fmt(fmt), ##args); \515} while (0)516#else517#define dbg(F, fmt, args...) \518do { \519 if (0) \520 printk(KERN_DEBUG pr_fmt(fmt), ##args); \521} while (0)522#endif523 524/* PCI ID lookup table525 */526static const struct pci_device_id fst_pci_dev_id[] = {527 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T2P, PCI_ANY_ID,528 PCI_ANY_ID, 0, 0, FST_TYPE_T2P},529 530 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T4P, PCI_ANY_ID,531 PCI_ANY_ID, 0, 0, FST_TYPE_T4P},532 533 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T1U, PCI_ANY_ID,534 PCI_ANY_ID, 0, 0, FST_TYPE_T1U},535 536 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T2U, PCI_ANY_ID,537 PCI_ANY_ID, 0, 0, FST_TYPE_T2U},538 539 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T4U, PCI_ANY_ID,540 PCI_ANY_ID, 0, 0, FST_TYPE_T4U},541 542 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_TE1, PCI_ANY_ID,543 PCI_ANY_ID, 0, 0, FST_TYPE_TE1},544 545 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_TE1C, PCI_ANY_ID,546 PCI_ANY_ID, 0, 0, FST_TYPE_TE1},547 {0,} /* End */548};549 550MODULE_DEVICE_TABLE(pci, fst_pci_dev_id);551 552/* Device Driver Work Queues553 *554 * So that we don't spend too much time processing events in the555 * Interrupt Service routine, we will declare a work queue per Card556 * and make the ISR schedule a task in the queue for later execution.557 * In the 2.4 Kernel we used to use the immediate queue for BH's558 * Now that they are gone, tasklets seem to be much better than work559 * queues.560 */561 562static void do_bottom_half_tx(struct fst_card_info *card);563static void do_bottom_half_rx(struct fst_card_info *card);564static void fst_process_tx_work_q(struct tasklet_struct *unused);565static void fst_process_int_work_q(struct tasklet_struct *unused);566 567static DECLARE_TASKLET(fst_tx_task, fst_process_tx_work_q);568static DECLARE_TASKLET(fst_int_task, fst_process_int_work_q);569 570static struct fst_card_info *fst_card_array[FST_MAX_CARDS];571static DEFINE_SPINLOCK(fst_work_q_lock);572static u64 fst_work_txq;573static u64 fst_work_intq;574 575static void576fst_q_work_item(u64 *queue, int card_index)577{578 unsigned long flags;579 u64 mask;580 581 /* Grab the queue exclusively582 */583 spin_lock_irqsave(&fst_work_q_lock, flags);584 585 /* Making an entry in the queue is simply a matter of setting586 * a bit for the card indicating that there is work to do in the587 * bottom half for the card. Note the limitation of 64 cards.588 * That ought to be enough589 */590 mask = (u64)1 << card_index;591 *queue |= mask;592 spin_unlock_irqrestore(&fst_work_q_lock, flags);593}594 595static void596fst_process_tx_work_q(struct tasklet_struct *unused)597{598 unsigned long flags;599 u64 work_txq;600 int i;601 602 /* Grab the queue exclusively603 */604 dbg(DBG_TX, "fst_process_tx_work_q\n");605 spin_lock_irqsave(&fst_work_q_lock, flags);606 work_txq = fst_work_txq;607 fst_work_txq = 0;608 spin_unlock_irqrestore(&fst_work_q_lock, flags);609 610 /* Call the bottom half for each card with work waiting611 */612 for (i = 0; i < FST_MAX_CARDS; i++) {613 if (work_txq & 0x01) {614 if (fst_card_array[i]) {615 dbg(DBG_TX, "Calling tx bh for card %d\n", i);616 do_bottom_half_tx(fst_card_array[i]);617 }618 }619 work_txq = work_txq >> 1;620 }621}622 623static void624fst_process_int_work_q(struct tasklet_struct *unused)625{626 unsigned long flags;627 u64 work_intq;628 int i;629 630 /* Grab the queue exclusively631 */632 dbg(DBG_INTR, "fst_process_int_work_q\n");633 spin_lock_irqsave(&fst_work_q_lock, flags);634 work_intq = fst_work_intq;635 fst_work_intq = 0;636 spin_unlock_irqrestore(&fst_work_q_lock, flags);637 638 /* Call the bottom half for each card with work waiting639 */640 for (i = 0; i < FST_MAX_CARDS; i++) {641 if (work_intq & 0x01) {642 if (fst_card_array[i]) {643 dbg(DBG_INTR,644 "Calling rx & tx bh for card %d\n", i);645 do_bottom_half_rx(fst_card_array[i]);646 do_bottom_half_tx(fst_card_array[i]);647 }648 }649 work_intq = work_intq >> 1;650 }651}652 653/* Card control functions654 * ======================655 */656/* Place the processor in reset state657 *658 * Used to be a simple write to card control space but a glitch in the latest659 * AMD Am186CH processor means that we now have to do it by asserting and de-660 * asserting the PLX chip PCI Adapter Software Reset. Bit 30 in CNTRL register661 * at offset 9052_CNTRL. Note the updates for the TXU.662 */663static inline void664fst_cpureset(struct fst_card_info *card)665{666 unsigned char interrupt_line_register;667 unsigned int regval;668 669 if (card->family == FST_FAMILY_TXU) {670 if (pci_read_config_byte671 (card->device, PCI_INTERRUPT_LINE, &interrupt_line_register)) {672 dbg(DBG_ASS,673 "Error in reading interrupt line register\n");674 }675 /* Assert PLX software reset and Am186 hardware reset676 * and then deassert the PLX software reset but 186 still in reset677 */678 outw(0x440f, card->pci_conf + CNTRL_9054 + 2);679 outw(0x040f, card->pci_conf + CNTRL_9054 + 2);680 /* We are delaying here to allow the 9054 to reset itself681 */682 usleep_range(10, 20);683 outw(0x240f, card->pci_conf + CNTRL_9054 + 2);684 /* We are delaying here to allow the 9054 to reload its eeprom685 */686 usleep_range(10, 20);687 outw(0x040f, card->pci_conf + CNTRL_9054 + 2);688 689 if (pci_write_config_byte690 (card->device, PCI_INTERRUPT_LINE, interrupt_line_register)) {691 dbg(DBG_ASS,692 "Error in writing interrupt line register\n");693 }694 695 } else {696 regval = inl(card->pci_conf + CNTRL_9052);697 698 outl(regval | 0x40000000, card->pci_conf + CNTRL_9052);699 outl(regval & ~0x40000000, card->pci_conf + CNTRL_9052);700 }701}702 703/* Release the processor from reset704 */705static inline void706fst_cpurelease(struct fst_card_info *card)707{708 if (card->family == FST_FAMILY_TXU) {709 /* Force posted writes to complete710 */711 (void)readb(card->mem);712 713 /* Release LRESET DO = 1714 * Then release Local Hold, DO = 1715 */716 outw(0x040e, card->pci_conf + CNTRL_9054 + 2);717 outw(0x040f, card->pci_conf + CNTRL_9054 + 2);718 } else {719 (void)readb(card->ctlmem);720 }721}722 723/* Clear the cards interrupt flag724 */725static inline void726fst_clear_intr(struct fst_card_info *card)727{728 if (card->family == FST_FAMILY_TXU) {729 (void)readb(card->ctlmem);730 } else {731 /* Poke the appropriate PLX chip register (same as enabling interrupts)732 */733 outw(0x0543, card->pci_conf + INTCSR_9052);734 }735}736 737/* Enable card interrupts738 */739static inline void740fst_enable_intr(struct fst_card_info *card)741{742 if (card->family == FST_FAMILY_TXU)743 outl(0x0f0c0900, card->pci_conf + INTCSR_9054);744 else745 outw(0x0543, card->pci_conf + INTCSR_9052);746}747 748/* Disable card interrupts749 */750static inline void751fst_disable_intr(struct fst_card_info *card)752{753 if (card->family == FST_FAMILY_TXU)754 outl(0x00000000, card->pci_conf + INTCSR_9054);755 else756 outw(0x0000, card->pci_conf + INTCSR_9052);757}758 759/* Process the result of trying to pass a received frame up the stack760 */761static void762fst_process_rx_status(int rx_status, char *name)763{764 switch (rx_status) {765 case NET_RX_SUCCESS:766 {767 /* Nothing to do here768 */769 break;770 }771 case NET_RX_DROP:772 {773 dbg(DBG_ASS, "%s: Received packet dropped\n", name);774 break;775 }776 }777}778 779/* Initilaise DMA for PLX 9054780 */781static inline void782fst_init_dma(struct fst_card_info *card)783{784 /* This is only required for the PLX 9054785 */786 if (card->family == FST_FAMILY_TXU) {787 pci_set_master(card->device);788 outl(0x00020441, card->pci_conf + DMAMODE0);789 outl(0x00020441, card->pci_conf + DMAMODE1);790 outl(0x0, card->pci_conf + DMATHR);791 }792}793 794/* Tx dma complete interrupt795 */796static void797fst_tx_dma_complete(struct fst_card_info *card, struct fst_port_info *port,798 int len, int txpos)799{800 struct net_device *dev = port_to_dev(port);801 802 /* Everything is now set, just tell the card to go803 */804 dbg(DBG_TX, "fst_tx_dma_complete\n");805 FST_WRB(card, txDescrRing[port->index][txpos].bits,806 DMA_OWN | TX_STP | TX_ENP);807 dev->stats.tx_packets++;808 dev->stats.tx_bytes += len;809 netif_trans_update(dev);810}811 812/* Mark it for our own raw sockets interface813 */814static __be16 farsync_type_trans(struct sk_buff *skb, struct net_device *dev)815{816 skb->dev = dev;817 skb_reset_mac_header(skb);818 skb->pkt_type = PACKET_HOST;819 return htons(ETH_P_CUST);820}821 822/* Rx dma complete interrupt823 */824static void825fst_rx_dma_complete(struct fst_card_info *card, struct fst_port_info *port,826 int len, struct sk_buff *skb, int rxp)827{828 struct net_device *dev = port_to_dev(port);829 int pi;830 int rx_status;831 832 dbg(DBG_TX, "fst_rx_dma_complete\n");833 pi = port->index;834 skb_put_data(skb, card->rx_dma_handle_host, len);835 836 /* Reset buffer descriptor */837 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN);838 839 /* Update stats */840 dev->stats.rx_packets++;841 dev->stats.rx_bytes += len;842 843 /* Push upstream */844 dbg(DBG_RX, "Pushing the frame up the stack\n");845 if (port->mode == FST_RAW)846 skb->protocol = farsync_type_trans(skb, dev);847 else848 skb->protocol = hdlc_type_trans(skb, dev);849 rx_status = netif_rx(skb);850 fst_process_rx_status(rx_status, port_to_dev(port)->name);851 if (rx_status == NET_RX_DROP)852 dev->stats.rx_dropped++;853}854 855/* Receive a frame through the DMA856 */857static inline void858fst_rx_dma(struct fst_card_info *card, dma_addr_t dma, u32 mem, int len)859{860 /* This routine will setup the DMA and start it861 */862 863 dbg(DBG_RX, "In fst_rx_dma %x %x %d\n", (u32)dma, mem, len);864 if (card->dmarx_in_progress)865 dbg(DBG_ASS, "In fst_rx_dma while dma in progress\n");866 867 outl(dma, card->pci_conf + DMAPADR0); /* Copy to here */868 outl(mem, card->pci_conf + DMALADR0); /* from here */869 outl(len, card->pci_conf + DMASIZ0); /* for this length */870 outl(0x00000000c, card->pci_conf + DMADPR0); /* In this direction */871 872 /* We use the dmarx_in_progress flag to flag the channel as busy873 */874 card->dmarx_in_progress = 1;875 outb(0x03, card->pci_conf + DMACSR0); /* Start the transfer */876}877 878/* Send a frame through the DMA879 */880static inline void881fst_tx_dma(struct fst_card_info *card, dma_addr_t dma, u32 mem, int len)882{883 /* This routine will setup the DMA and start it.884 */885 886 dbg(DBG_TX, "In fst_tx_dma %x %x %d\n", (u32)dma, mem, len);887 if (card->dmatx_in_progress)888 dbg(DBG_ASS, "In fst_tx_dma while dma in progress\n");889 890 outl(dma, card->pci_conf + DMAPADR1); /* Copy from here */891 outl(mem, card->pci_conf + DMALADR1); /* to here */892 outl(len, card->pci_conf + DMASIZ1); /* for this length */893 outl(0x000000004, card->pci_conf + DMADPR1); /* In this direction */894 895 /* We use the dmatx_in_progress to flag the channel as busy896 */897 card->dmatx_in_progress = 1;898 outb(0x03, card->pci_conf + DMACSR1); /* Start the transfer */899}900 901/* Issue a Mailbox command for a port.902 * Note we issue them on a fire and forget basis, not expecting to see an903 * error and not waiting for completion.904 */905static void906fst_issue_cmd(struct fst_port_info *port, unsigned short cmd)907{908 struct fst_card_info *card;909 unsigned short mbval;910 unsigned long flags;911 int safety;912 913 card = port->card;914 spin_lock_irqsave(&card->card_lock, flags);915 mbval = FST_RDW(card, portMailbox[port->index][0]);916 917 safety = 0;918 /* Wait for any previous command to complete */919 while (mbval > NAK) {920 spin_unlock_irqrestore(&card->card_lock, flags);921 schedule_timeout_uninterruptible(1);922 spin_lock_irqsave(&card->card_lock, flags);923 924 if (++safety > 2000) {925 pr_err("Mailbox safety timeout\n");926 break;927 }928 929 mbval = FST_RDW(card, portMailbox[port->index][0]);930 }931 if (safety > 0)932 dbg(DBG_CMD, "Mailbox clear after %d jiffies\n", safety);933 934 if (mbval == NAK)935 dbg(DBG_CMD, "issue_cmd: previous command was NAK'd\n");936 937 FST_WRW(card, portMailbox[port->index][0], cmd);938 939 if (cmd == ABORTTX || cmd == STARTPORT) {940 port->txpos = 0;941 port->txipos = 0;942 port->start = 0;943 }944 945 spin_unlock_irqrestore(&card->card_lock, flags);946}947 948/* Port output signals control949 */950static inline void951fst_op_raise(struct fst_port_info *port, unsigned int outputs)952{953 outputs |= FST_RDL(port->card, v24OpSts[port->index]);954 FST_WRL(port->card, v24OpSts[port->index], outputs);955 956 if (port->run)957 fst_issue_cmd(port, SETV24O);958}959 960static inline void961fst_op_lower(struct fst_port_info *port, unsigned int outputs)962{963 outputs = ~outputs & FST_RDL(port->card, v24OpSts[port->index]);964 FST_WRL(port->card, v24OpSts[port->index], outputs);965 966 if (port->run)967 fst_issue_cmd(port, SETV24O);968}969 970/* Setup port Rx buffers971 */972static void973fst_rx_config(struct fst_port_info *port)974{975 int i;976 int pi;977 unsigned int offset;978 unsigned long flags;979 struct fst_card_info *card;980 981 pi = port->index;982 card = port->card;983 spin_lock_irqsave(&card->card_lock, flags);984 for (i = 0; i < NUM_RX_BUFFER; i++) {985 offset = BUF_OFFSET(rxBuffer[pi][i][0]);986 987 FST_WRW(card, rxDescrRing[pi][i].ladr, (u16)offset);988 FST_WRB(card, rxDescrRing[pi][i].hadr, (u8)(offset >> 16));989 FST_WRW(card, rxDescrRing[pi][i].bcnt, cnv_bcnt(LEN_RX_BUFFER));990 FST_WRW(card, rxDescrRing[pi][i].mcnt, LEN_RX_BUFFER);991 FST_WRB(card, rxDescrRing[pi][i].bits, DMA_OWN);992 }993 port->rxpos = 0;994 spin_unlock_irqrestore(&card->card_lock, flags);995}996 997/* Setup port Tx buffers998 */999static void1000fst_tx_config(struct fst_port_info *port)1001{1002 int i;1003 int pi;1004 unsigned int offset;1005 unsigned long flags;1006 struct fst_card_info *card;1007 1008 pi = port->index;1009 card = port->card;1010 spin_lock_irqsave(&card->card_lock, flags);1011 for (i = 0; i < NUM_TX_BUFFER; i++) {1012 offset = BUF_OFFSET(txBuffer[pi][i][0]);1013 1014 FST_WRW(card, txDescrRing[pi][i].ladr, (u16)offset);1015 FST_WRB(card, txDescrRing[pi][i].hadr, (u8)(offset >> 16));1016 FST_WRW(card, txDescrRing[pi][i].bcnt, 0);1017 FST_WRB(card, txDescrRing[pi][i].bits, 0);1018 }1019 port->txpos = 0;1020 port->txipos = 0;1021 port->start = 0;1022 spin_unlock_irqrestore(&card->card_lock, flags);1023}1024 1025/* TE1 Alarm change interrupt event1026 */1027static void1028fst_intr_te1_alarm(struct fst_card_info *card, struct fst_port_info *port)1029{1030 u8 los;1031 u8 rra;1032 u8 ais;1033 1034 los = FST_RDB(card, suStatus.lossOfSignal);1035 rra = FST_RDB(card, suStatus.receiveRemoteAlarm);1036 ais = FST_RDB(card, suStatus.alarmIndicationSignal);1037 1038 if (los) {1039 /* Lost the link1040 */1041 if (netif_carrier_ok(port_to_dev(port))) {1042 dbg(DBG_INTR, "Net carrier off\n");1043 netif_carrier_off(port_to_dev(port));1044 }1045 } else {1046 /* Link available1047 */1048 if (!netif_carrier_ok(port_to_dev(port))) {1049 dbg(DBG_INTR, "Net carrier on\n");1050 netif_carrier_on(port_to_dev(port));1051 }1052 }1053 1054 if (los)1055 dbg(DBG_INTR, "Assert LOS Alarm\n");1056 else1057 dbg(DBG_INTR, "De-assert LOS Alarm\n");1058 if (rra)1059 dbg(DBG_INTR, "Assert RRA Alarm\n");1060 else1061 dbg(DBG_INTR, "De-assert RRA Alarm\n");1062 1063 if (ais)1064 dbg(DBG_INTR, "Assert AIS Alarm\n");1065 else1066 dbg(DBG_INTR, "De-assert AIS Alarm\n");1067}1068 1069/* Control signal change interrupt event1070 */1071static void1072fst_intr_ctlchg(struct fst_card_info *card, struct fst_port_info *port)1073{1074 int signals;1075 1076 signals = FST_RDL(card, v24DebouncedSts[port->index]);1077 1078 if (signals & ((port->hwif == X21 || port->hwif == X21D)1079 ? IPSTS_INDICATE : IPSTS_DCD)) {1080 if (!netif_carrier_ok(port_to_dev(port))) {1081 dbg(DBG_INTR, "DCD active\n");1082 netif_carrier_on(port_to_dev(port));1083 }1084 } else {1085 if (netif_carrier_ok(port_to_dev(port))) {1086 dbg(DBG_INTR, "DCD lost\n");1087 netif_carrier_off(port_to_dev(port));1088 }1089 }1090}1091 1092/* Log Rx Errors1093 */1094static void1095fst_log_rx_error(struct fst_card_info *card, struct fst_port_info *port,1096 unsigned char dmabits, int rxp, unsigned short len)1097{1098 struct net_device *dev = port_to_dev(port);1099 1100 /* Increment the appropriate error counter1101 */1102 dev->stats.rx_errors++;1103 if (dmabits & RX_OFLO) {1104 dev->stats.rx_fifo_errors++;1105 dbg(DBG_ASS, "Rx fifo error on card %d port %d buffer %d\n",1106 card->card_no, port->index, rxp);1107 }1108 if (dmabits & RX_CRC) {1109 dev->stats.rx_crc_errors++;1110 dbg(DBG_ASS, "Rx crc error on card %d port %d\n",1111 card->card_no, port->index);1112 }1113 if (dmabits & RX_FRAM) {1114 dev->stats.rx_frame_errors++;1115 dbg(DBG_ASS, "Rx frame error on card %d port %d\n",1116 card->card_no, port->index);1117 }1118 if (dmabits == (RX_STP | RX_ENP)) {1119 dev->stats.rx_length_errors++;1120 dbg(DBG_ASS, "Rx length error (%d) on card %d port %d\n",1121 len, card->card_no, port->index);1122 }1123}1124 1125/* Rx Error Recovery1126 */1127static void1128fst_recover_rx_error(struct fst_card_info *card, struct fst_port_info *port,1129 unsigned char dmabits, int rxp, unsigned short len)1130{1131 int i;1132 int pi;1133 1134 pi = port->index;1135 /* Discard buffer descriptors until we see the start of the1136 * next frame. Note that for long frames this could be in1137 * a subsequent interrupt.1138 */1139 i = 0;1140 while ((dmabits & (DMA_OWN | RX_STP)) == 0) {1141 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN);1142 rxp = (rxp + 1) % NUM_RX_BUFFER;1143 if (++i > NUM_RX_BUFFER) {1144 dbg(DBG_ASS, "intr_rx: Discarding more bufs"1145 " than we have\n");1146 break;1147 }1148 dmabits = FST_RDB(card, rxDescrRing[pi][rxp].bits);1149 dbg(DBG_ASS, "DMA Bits of next buffer was %x\n", dmabits);1150 }1151 dbg(DBG_ASS, "There were %d subsequent buffers in error\n", i);1152 1153 /* Discard the terminal buffer */1154 if (!(dmabits & DMA_OWN)) {1155 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN);1156 rxp = (rxp + 1) % NUM_RX_BUFFER;1157 }1158 port->rxpos = rxp;1159}1160 1161/* Rx complete interrupt1162 */1163static void1164fst_intr_rx(struct fst_card_info *card, struct fst_port_info *port)1165{1166 unsigned char dmabits;1167 int pi;1168 int rxp;1169 int rx_status;1170 unsigned short len;1171 struct sk_buff *skb;1172 struct net_device *dev = port_to_dev(port);1173 1174 /* Check we have a buffer to process */1175 pi = port->index;1176 rxp = port->rxpos;1177 dmabits = FST_RDB(card, rxDescrRing[pi][rxp].bits);1178 if (dmabits & DMA_OWN) {1179 dbg(DBG_RX | DBG_INTR, "intr_rx: No buffer port %d pos %d\n",1180 pi, rxp);1181 return;1182 }1183 if (card->dmarx_in_progress)1184 return;1185 1186 /* Get buffer length */1187 len = FST_RDW(card, rxDescrRing[pi][rxp].mcnt);1188 /* Discard the CRC */1189 len -= 2;1190 if (len == 0) {1191 /* This seems to happen on the TE1 interface sometimes1192 * so throw the frame away and log the event.1193 */1194 pr_err("Frame received with 0 length. Card %d Port %d\n",1195 card->card_no, port->index);1196 /* Return descriptor to card */1197 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN);1198 1199 rxp = (rxp + 1) % NUM_RX_BUFFER;1200 port->rxpos = rxp;1201 return;1202 }1203 1204 /* Check buffer length and for other errors. We insist on one packet1205 * in one buffer. This simplifies things greatly and since we've1206 * allocated 8K it shouldn't be a real world limitation1207 */1208 dbg(DBG_RX, "intr_rx: %d,%d: flags %x len %d\n", pi, rxp, dmabits, len);1209 if (dmabits != (RX_STP | RX_ENP) || len > LEN_RX_BUFFER - 2) {1210 fst_log_rx_error(card, port, dmabits, rxp, len);1211 fst_recover_rx_error(card, port, dmabits, rxp, len);1212 return;1213 }1214 1215 /* Allocate SKB */1216 skb = dev_alloc_skb(len);1217 if (!skb) {1218 dbg(DBG_RX, "intr_rx: can't allocate buffer\n");1219 1220 dev->stats.rx_dropped++;1221 1222 /* Return descriptor to card */1223 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN);1224 1225 rxp = (rxp + 1) % NUM_RX_BUFFER;1226 port->rxpos = rxp;1227 return;1228 }1229 1230 /* We know the length we need to receive, len.1231 * It's not worth using the DMA for reads of less than1232 * FST_MIN_DMA_LEN1233 */1234 1235 if (len < FST_MIN_DMA_LEN || card->family == FST_FAMILY_TXP) {1236 memcpy_fromio(skb_put(skb, len),1237 card->mem + BUF_OFFSET(rxBuffer[pi][rxp][0]),1238 len);1239 1240 /* Reset buffer descriptor */1241 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN);1242 1243 /* Update stats */1244 dev->stats.rx_packets++;1245 dev->stats.rx_bytes += len;1246 1247 /* Push upstream */1248 dbg(DBG_RX, "Pushing frame up the stack\n");1249 if (port->mode == FST_RAW)1250 skb->protocol = farsync_type_trans(skb, dev);1251 else1252 skb->protocol = hdlc_type_trans(skb, dev);1253 rx_status = netif_rx(skb);1254 fst_process_rx_status(rx_status, port_to_dev(port)->name);1255 if (rx_status == NET_RX_DROP)1256 dev->stats.rx_dropped++;1257 } else {1258 card->dma_skb_rx = skb;1259 card->dma_port_rx = port;1260 card->dma_len_rx = len;1261 card->dma_rxpos = rxp;1262 fst_rx_dma(card, card->rx_dma_handle_card,1263 BUF_OFFSET(rxBuffer[pi][rxp][0]), len);1264 }1265 if (rxp != port->rxpos) {1266 dbg(DBG_ASS, "About to increment rxpos by more than 1\n");1267 dbg(DBG_ASS, "rxp = %d rxpos = %d\n", rxp, port->rxpos);1268 }1269 rxp = (rxp + 1) % NUM_RX_BUFFER;1270 port->rxpos = rxp;1271}1272 1273/* The bottom half to the ISR1274 *1275 */1276 1277static void1278do_bottom_half_tx(struct fst_card_info *card)1279{1280 struct fst_port_info *port;1281 int pi;1282 int txq_length;1283 struct sk_buff *skb;1284 unsigned long flags;1285 struct net_device *dev;1286 1287 /* Find a free buffer for the transmit1288 * Step through each port on this card1289 */1290 1291 dbg(DBG_TX, "do_bottom_half_tx\n");1292 for (pi = 0, port = card->ports; pi < card->nports; pi++, port++) {1293 if (!port->run)1294 continue;1295 1296 dev = port_to_dev(port);1297 while (!(FST_RDB(card, txDescrRing[pi][port->txpos].bits) &1298 DMA_OWN) &&1299 !(card->dmatx_in_progress)) {1300 /* There doesn't seem to be a txdone event per-se1301 * We seem to have to deduce it, by checking the DMA_OWN1302 * bit on the next buffer we think we can use1303 */1304 spin_lock_irqsave(&card->card_lock, flags);1305 txq_length = port->txqe - port->txqs;1306 if (txq_length < 0) {1307 /* This is the case where one has wrapped and the1308 * maths gives us a negative number1309 */1310 txq_length = txq_length + FST_TXQ_DEPTH;1311 }1312 spin_unlock_irqrestore(&card->card_lock, flags);1313 if (txq_length > 0) {1314 /* There is something to send1315 */1316 spin_lock_irqsave(&card->card_lock, flags);1317 skb = port->txq[port->txqs];1318 port->txqs++;1319 if (port->txqs == FST_TXQ_DEPTH)1320 port->txqs = 0;1321 1322 spin_unlock_irqrestore(&card->card_lock, flags);1323 /* copy the data and set the required indicators on the1324 * card.1325 */1326 FST_WRW(card, txDescrRing[pi][port->txpos].bcnt,1327 cnv_bcnt(skb->len));1328 if (skb->len < FST_MIN_DMA_LEN ||1329 card->family == FST_FAMILY_TXP) {1330 /* Enqueue the packet with normal io */1331 memcpy_toio(card->mem +1332 BUF_OFFSET(txBuffer[pi]1333 [port->1334 txpos][0]),1335 skb->data, skb->len);1336 FST_WRB(card,1337 txDescrRing[pi][port->txpos].1338 bits,1339 DMA_OWN | TX_STP | TX_ENP);1340 dev->stats.tx_packets++;1341 dev->stats.tx_bytes += skb->len;1342 netif_trans_update(dev);1343 } else {1344 /* Or do it through dma */1345 memcpy(card->tx_dma_handle_host,1346 skb->data, skb->len);1347 card->dma_port_tx = port;1348 card->dma_len_tx = skb->len;1349 card->dma_txpos = port->txpos;1350 fst_tx_dma(card,1351 card->tx_dma_handle_card,1352 BUF_OFFSET(txBuffer[pi]1353 [port->txpos][0]),1354 skb->len);1355 }1356 if (++port->txpos >= NUM_TX_BUFFER)1357 port->txpos = 0;1358 /* If we have flow control on, can we now release it?1359 */1360 if (port->start) {1361 if (txq_length < fst_txq_low) {1362 netif_wake_queue(port_to_dev1363 (port));1364 port->start = 0;1365 }1366 }1367 dev_kfree_skb(skb);1368 } else {1369 /* Nothing to send so break out of the while loop1370 */1371 break;1372 }1373 }1374 }1375}1376 1377static void1378do_bottom_half_rx(struct fst_card_info *card)1379{1380 struct fst_port_info *port;1381 int pi;1382 int rx_count = 0;1383 1384 /* Check for rx completions on all ports on this card */1385 dbg(DBG_RX, "do_bottom_half_rx\n");1386 for (pi = 0, port = card->ports; pi < card->nports; pi++, port++) {1387 if (!port->run)1388 continue;1389 1390 while (!(FST_RDB(card, rxDescrRing[pi][port->rxpos].bits)1391 & DMA_OWN) && !(card->dmarx_in_progress)) {1392 if (rx_count > fst_max_reads) {1393 /* Don't spend forever in receive processing1394 * Schedule another event1395 */1396 fst_q_work_item(&fst_work_intq, card->card_no);1397 tasklet_schedule(&fst_int_task);1398 break; /* Leave the loop */1399 }1400 fst_intr_rx(card, port);1401 rx_count++;1402 }1403 }1404}1405 1406/* The interrupt service routine1407 * Dev_id is our fst_card_info pointer1408 */1409static irqreturn_t1410fst_intr(int dummy, void *dev_id)1411{1412 struct fst_card_info *card = dev_id;1413 struct fst_port_info *port;1414 int rdidx; /* Event buffer indices */1415 int wridx;1416 int event; /* Actual event for processing */1417 unsigned int dma_intcsr = 0;1418 unsigned int do_card_interrupt;1419 unsigned int int_retry_count;1420 1421 /* Check to see if the interrupt was for this card1422 * return if not1423 * Note that the call to clear the interrupt is important1424 */1425 dbg(DBG_INTR, "intr: %d %p\n", card->irq, card);1426 if (card->state != FST_RUNNING) {1427 pr_err("Interrupt received for card %d in a non running state (%d)\n",1428 card->card_no, card->state);1429 1430 /* It is possible to really be running, i.e. we have re-loaded1431 * a running card1432 * Clear and reprime the interrupt source1433 */1434 fst_clear_intr(card);1435 return IRQ_HANDLED;1436 }1437 1438 /* Clear and reprime the interrupt source */1439 fst_clear_intr(card);1440 1441 /* Is the interrupt for this card (handshake == 1)1442 */1443 do_card_interrupt = 0;1444 if (FST_RDB(card, interruptHandshake) == 1) {1445 do_card_interrupt += FST_CARD_INT;1446 /* Set the software acknowledge */1447 FST_WRB(card, interruptHandshake, 0xEE);1448 }1449 if (card->family == FST_FAMILY_TXU) {1450 /* Is it a DMA Interrupt1451 */1452 dma_intcsr = inl(card->pci_conf + INTCSR_9054);1453 if (dma_intcsr & 0x00200000) {1454 /* DMA Channel 0 (Rx transfer complete)1455 */1456 dbg(DBG_RX, "DMA Rx xfer complete\n");1457 outb(0x8, card->pci_conf + DMACSR0);1458 fst_rx_dma_complete(card, card->dma_port_rx,1459 card->dma_len_rx, card->dma_skb_rx,1460 card->dma_rxpos);1461 card->dmarx_in_progress = 0;1462 do_card_interrupt += FST_RX_DMA_INT;1463 }1464 if (dma_intcsr & 0x00400000) {1465 /* DMA Channel 1 (Tx transfer complete)1466 */1467 dbg(DBG_TX, "DMA Tx xfer complete\n");1468 outb(0x8, card->pci_conf + DMACSR1);1469 fst_tx_dma_complete(card, card->dma_port_tx,1470 card->dma_len_tx, card->dma_txpos);1471 card->dmatx_in_progress = 0;1472 do_card_interrupt += FST_TX_DMA_INT;1473 }1474 }1475 1476 /* Have we been missing Interrupts1477 */1478 int_retry_count = FST_RDL(card, interruptRetryCount);1479 if (int_retry_count) {1480 dbg(DBG_ASS, "Card %d int_retry_count is %d\n",1481 card->card_no, int_retry_count);1482 FST_WRL(card, interruptRetryCount, 0);1483 }1484 1485 if (!do_card_interrupt)1486 return IRQ_HANDLED;1487 1488 /* Scehdule the bottom half of the ISR */1489 fst_q_work_item(&fst_work_intq, card->card_no);1490 tasklet_schedule(&fst_int_task);1491 1492 /* Drain the event queue */1493 rdidx = FST_RDB(card, interruptEvent.rdindex) & 0x1f;1494 wridx = FST_RDB(card, interruptEvent.wrindex) & 0x1f;1495 while (rdidx != wridx) {1496 event = FST_RDB(card, interruptEvent.evntbuff[rdidx]);1497 port = &card->ports[event & 0x03];1498 1499 dbg(DBG_INTR, "Processing Interrupt event: %x\n", event);1500 1501 switch (event) {1502 case TE1_ALMA:1503 dbg(DBG_INTR, "TE1 Alarm intr\n");1504 if (port->run)1505 fst_intr_te1_alarm(card, port);1506 break;1507 1508 case CTLA_CHG:1509 case CTLB_CHG:1510 case CTLC_CHG:1511 case CTLD_CHG:1512 if (port->run)1513 fst_intr_ctlchg(card, port);1514 break;1515 1516 case ABTA_SENT:1517 case ABTB_SENT:1518 case ABTC_SENT:1519 case ABTD_SENT:1520 dbg(DBG_TX, "Abort complete port %d\n", port->index);1521 break;1522 1523 case TXA_UNDF:1524 case TXB_UNDF:1525 case TXC_UNDF:1526 case TXD_UNDF:1527 /* Difficult to see how we'd get this given that we1528 * always load up the entire packet for DMA.1529 */1530 dbg(DBG_TX, "Tx underflow port %d\n", port->index);1531 port_to_dev(port)->stats.tx_errors++;1532 port_to_dev(port)->stats.tx_fifo_errors++;1533 dbg(DBG_ASS, "Tx underflow on card %d port %d\n",1534 card->card_no, port->index);1535 break;1536 1537 case INIT_CPLT:1538 dbg(DBG_INIT, "Card init OK intr\n");1539 break;1540 1541 case INIT_FAIL:1542 dbg(DBG_INIT, "Card init FAILED intr\n");1543 card->state = FST_IFAILED;1544 break;1545 1546 default:1547 pr_err("intr: unknown card event %d. ignored\n", event);1548 break;1549 }1550 1551 /* Bump and wrap the index */1552 if (++rdidx >= MAX_CIRBUFF)1553 rdidx = 0;1554 }1555 FST_WRB(card, interruptEvent.rdindex, rdidx);1556 return IRQ_HANDLED;1557}1558 1559/* Check that the shared memory configuration is one that we can handle1560 * and that some basic parameters are correct1561 */1562static void1563check_started_ok(struct fst_card_info *card)1564{1565 int i;1566 1567 /* Check structure version and end marker */1568 if (FST_RDW(card, smcVersion) != SMC_VERSION) {1569 pr_err("Bad shared memory version %d expected %d\n",1570 FST_RDW(card, smcVersion), SMC_VERSION);1571 card->state = FST_BADVERSION;1572 return;1573 }1574 if (FST_RDL(card, endOfSmcSignature) != END_SIG) {1575 pr_err("Missing shared memory signature\n");1576 card->state = FST_BADVERSION;1577 return;1578 }1579 /* Firmware status flag, 0x00 = initialising, 0x01 = OK, 0xFF = fail */1580 i = FST_RDB(card, taskStatus);1581 if (i == 0x01) {1582 card->state = FST_RUNNING;1583 } else if (i == 0xFF) {1584 pr_err("Firmware initialisation failed. Card halted\n");1585 card->state = FST_HALTED;1586 return;1587 } else if (i != 0x00) {1588 pr_err("Unknown firmware status 0x%x\n", i);1589 card->state = FST_HALTED;1590 return;1591 }1592 1593 /* Finally check the number of ports reported by firmware against the1594 * number we assumed at card detection. Should never happen with1595 * existing firmware etc so we just report it for the moment.1596 */1597 if (FST_RDL(card, numberOfPorts) != card->nports) {1598 pr_warn("Port count mismatch on card %d. Firmware thinks %d we say %d\n",1599 card->card_no,1600 FST_RDL(card, numberOfPorts), card->nports);1601 }1602}1603 1604static int1605set_conf_from_info(struct fst_card_info *card, struct fst_port_info *port,1606 struct fstioc_info *info)1607{1608 int err;1609 unsigned char my_framing;1610 1611 /* Set things according to the user set valid flags1612 * Several of the old options have been invalidated/replaced by the1613 * generic hdlc package.1614 */1615 err = 0;1616 if (info->valid & FSTVAL_PROTO) {1617 if (info->proto == FST_RAW)1618 port->mode = FST_RAW;1619 else1620 port->mode = FST_GEN_HDLC;1621 }1622 1623 if (info->valid & FSTVAL_CABLE)1624 err = -EINVAL;1625 1626 if (info->valid & FSTVAL_SPEED)1627 err = -EINVAL;1628 1629 if (info->valid & FSTVAL_PHASE)1630 FST_WRB(card, portConfig[port->index].invertClock,1631 info->invertClock);1632 if (info->valid & FSTVAL_MODE)1633 FST_WRW(card, cardMode, info->cardMode);1634 if (info->valid & FSTVAL_TE1) {1635 FST_WRL(card, suConfig.dataRate, info->lineSpeed);1636 FST_WRB(card, suConfig.clocking, info->clockSource);1637 my_framing = FRAMING_E1;1638 if (info->framing == E1)1639 my_framing = FRAMING_E1;1640 if (info->framing == T1)1641 my_framing = FRAMING_T1;1642 if (info->framing == J1)1643 my_framing = FRAMING_J1;1644 FST_WRB(card, suConfig.framing, my_framing);1645 FST_WRB(card, suConfig.structure, info->structure);1646 FST_WRB(card, suConfig.interface, info->interface);1647 FST_WRB(card, suConfig.coding, info->coding);1648 FST_WRB(card, suConfig.lineBuildOut, info->lineBuildOut);1649 FST_WRB(card, suConfig.equalizer, info->equalizer);1650 FST_WRB(card, suConfig.transparentMode, info->transparentMode);1651 FST_WRB(card, suConfig.loopMode, info->loopMode);1652 FST_WRB(card, suConfig.range, info->range);1653 FST_WRB(card, suConfig.txBufferMode, info->txBufferMode);1654 FST_WRB(card, suConfig.rxBufferMode, info->rxBufferMode);1655 FST_WRB(card, suConfig.startingSlot, info->startingSlot);1656 FST_WRB(card, suConfig.losThreshold, info->losThreshold);1657 if (info->idleCode)1658 FST_WRB(card, suConfig.enableIdleCode, 1);1659 else1660 FST_WRB(card, suConfig.enableIdleCode, 0);1661 FST_WRB(card, suConfig.idleCode, info->idleCode);1662#if FST_DEBUG1663 if (info->valid & FSTVAL_TE1) {1664 printk("Setting TE1 data\n");1665 printk("Line Speed = %d\n", info->lineSpeed);1666 printk("Start slot = %d\n", info->startingSlot);1667 printk("Clock source = %d\n", info->clockSource);1668 printk("Framing = %d\n", my_framing);1669 printk("Structure = %d\n", info->structure);1670 printk("interface = %d\n", info->interface);1671 printk("Coding = %d\n", info->coding);1672 printk("Line build out = %d\n", info->lineBuildOut);1673 printk("Equaliser = %d\n", info->equalizer);1674 printk("Transparent mode = %d\n",1675 info->transparentMode);1676 printk("Loop mode = %d\n", info->loopMode);1677 printk("Range = %d\n", info->range);1678 printk("Tx Buffer mode = %d\n", info->txBufferMode);1679 printk("Rx Buffer mode = %d\n", info->rxBufferMode);1680 printk("LOS Threshold = %d\n", info->losThreshold);1681 printk("Idle Code = %d\n", info->idleCode);1682 }1683#endif1684 }1685#if FST_DEBUG1686 if (info->valid & FSTVAL_DEBUG)1687 fst_debug_mask = info->debug;1688#endif1689 1690 return err;1691}1692 1693static void1694gather_conf_info(struct fst_card_info *card, struct fst_port_info *port,1695 struct fstioc_info *info)1696{1697 int i;1698 1699 memset(info, 0, sizeof(struct fstioc_info));1700 1701 i = port->index;1702 info->kernelVersion = LINUX_VERSION_CODE;1703 info->nports = card->nports;1704 info->type = card->type;1705 info->state = card->state;1706 info->proto = FST_GEN_HDLC;1707 info->index = i;1708#if FST_DEBUG1709 info->debug = fst_debug_mask;1710#endif1711 1712 /* Only mark information as valid if card is running.1713 * Copy the data anyway in case it is useful for diagnostics1714 */1715 info->valid = ((card->state == FST_RUNNING) ? FSTVAL_ALL : FSTVAL_CARD)1716#if FST_DEBUG1717 | FSTVAL_DEBUG1718#endif1719 ;1720 1721 info->lineInterface = FST_RDW(card, portConfig[i].lineInterface);1722 info->internalClock = FST_RDB(card, portConfig[i].internalClock);1723 info->lineSpeed = FST_RDL(card, portConfig[i].lineSpeed);1724 info->invertClock = FST_RDB(card, portConfig[i].invertClock);1725 info->v24IpSts = FST_RDL(card, v24IpSts[i]);1726 info->v24OpSts = FST_RDL(card, v24OpSts[i]);1727 info->clockStatus = FST_RDW(card, clockStatus[i]);1728 info->cableStatus = FST_RDW(card, cableStatus);1729 info->cardMode = FST_RDW(card, cardMode);1730 info->smcFirmwareVersion = FST_RDL(card, smcFirmwareVersion);1731 1732 /* The T2U can report cable presence for both A or B1733 * in bits 0 and 1 of cableStatus. See which port we are and1734 * do the mapping.1735 */1736 if (card->family == FST_FAMILY_TXU) {1737 if (port->index == 0) {1738 /* Port A1739 */1740 info->cableStatus = info->cableStatus & 1;1741 } else {1742 /* Port B1743 */1744 info->cableStatus = info->cableStatus >> 1;1745 info->cableStatus = info->cableStatus & 1;1746 }1747 }1748 /* Some additional bits if we are TE11749 */1750 if (card->type == FST_TYPE_TE1) {1751 info->lineSpeed = FST_RDL(card, suConfig.dataRate);1752 info->clockSource = FST_RDB(card, suConfig.clocking);1753 info->framing = FST_RDB(card, suConfig.framing);1754 info->structure = FST_RDB(card, suConfig.structure);1755 info->interface = FST_RDB(card, suConfig.interface);1756 info->coding = FST_RDB(card, suConfig.coding);1757 info->lineBuildOut = FST_RDB(card, suConfig.lineBuildOut);1758 info->equalizer = FST_RDB(card, suConfig.equalizer);1759 info->loopMode = FST_RDB(card, suConfig.loopMode);1760 info->range = FST_RDB(card, suConfig.range);1761 info->txBufferMode = FST_RDB(card, suConfig.txBufferMode);1762 info->rxBufferMode = FST_RDB(card, suConfig.rxBufferMode);1763 info->startingSlot = FST_RDB(card, suConfig.startingSlot);1764 info->losThreshold = FST_RDB(card, suConfig.losThreshold);1765 if (FST_RDB(card, suConfig.enableIdleCode))1766 info->idleCode = FST_RDB(card, suConfig.idleCode);1767 else1768 info->idleCode = 0;1769 info->receiveBufferDelay =1770 FST_RDL(card, suStatus.receiveBufferDelay);1771 info->framingErrorCount =1772 FST_RDL(card, suStatus.framingErrorCount);1773 info->codeViolationCount =1774 FST_RDL(card, suStatus.codeViolationCount);1775 info->crcErrorCount = FST_RDL(card, suStatus.crcErrorCount);1776 info->lineAttenuation = FST_RDL(card, suStatus.lineAttenuation);1777 info->lossOfSignal = FST_RDB(card, suStatus.lossOfSignal);1778 info->receiveRemoteAlarm =1779 FST_RDB(card, suStatus.receiveRemoteAlarm);1780 info->alarmIndicationSignal =1781 FST_RDB(card, suStatus.alarmIndicationSignal);1782 }1783}1784 1785static int1786fst_set_iface(struct fst_card_info *card, struct fst_port_info *port,1787 struct if_settings *ifs)1788{1789 sync_serial_settings sync;1790 int i;1791 1792 if (ifs->size != sizeof(sync))1793 return -ENOMEM;1794 1795 if (copy_from_user(&sync, ifs->ifs_ifsu.sync, sizeof(sync)))1796 return -EFAULT;1797 1798 if (sync.loopback)1799 return -EINVAL;1800 1801 i = port->index;1802 1803 switch (ifs->type) {1804 case IF_IFACE_V35:1805 FST_WRW(card, portConfig[i].lineInterface, V35);1806 port->hwif = V35;1807 break;1808 1809 case IF_IFACE_V24:1810 FST_WRW(card, portConfig[i].lineInterface, V24);1811 port->hwif = V24;1812 break;1813 1814 case IF_IFACE_X21:1815 FST_WRW(card, portConfig[i].lineInterface, X21);1816 port->hwif = X21;1817 break;1818 1819 case IF_IFACE_X21D:1820 FST_WRW(card, portConfig[i].lineInterface, X21D);1821 port->hwif = X21D;1822 break;1823 1824 case IF_IFACE_T1:1825 FST_WRW(card, portConfig[i].lineInterface, T1);1826 port->hwif = T1;1827 break;1828 1829 case IF_IFACE_E1:1830 FST_WRW(card, portConfig[i].lineInterface, E1);1831 port->hwif = E1;1832 break;1833 1834 case IF_IFACE_SYNC_SERIAL:1835 break;1836 1837 default:1838 return -EINVAL;1839 }1840 1841 switch (sync.clock_type) {1842 case CLOCK_EXT:1843 FST_WRB(card, portConfig[i].internalClock, EXTCLK);1844 break;1845 1846 case CLOCK_INT:1847 FST_WRB(card, portConfig[i].internalClock, INTCLK);1848 break;1849 1850 default:1851 return -EINVAL;1852 }1853 FST_WRL(card, portConfig[i].lineSpeed, sync.clock_rate);1854 return 0;1855}1856 1857static int1858fst_get_iface(struct fst_card_info *card, struct fst_port_info *port,1859 struct if_settings *ifs)1860{1861 sync_serial_settings sync;1862 int i;1863 1864 /* First check what line type is set, we'll default to reporting X.211865 * if nothing is set as IF_IFACE_SYNC_SERIAL implies it can't be1866 * changed1867 */1868 switch (port->hwif) {1869 case E1:1870 ifs->type = IF_IFACE_E1;1871 break;1872 case T1:1873 ifs->type = IF_IFACE_T1;1874 break;1875 case V35:1876 ifs->type = IF_IFACE_V35;1877 break;1878 case V24:1879 ifs->type = IF_IFACE_V24;1880 break;1881 case X21D:1882 ifs->type = IF_IFACE_X21D;1883 break;1884 case X21:1885 default:1886 ifs->type = IF_IFACE_X21;1887 break;1888 }1889 if (!ifs->size)1890 return 0; /* only type requested */1891 1892 if (ifs->size < sizeof(sync))1893 return -ENOMEM;1894 1895 i = port->index;1896 memset(&sync, 0, sizeof(sync));1897 sync.clock_rate = FST_RDL(card, portConfig[i].lineSpeed);1898 /* Lucky card and linux use same encoding here */1899 sync.clock_type = FST_RDB(card, portConfig[i].internalClock) ==1900 INTCLK ? CLOCK_INT : CLOCK_EXT;1901 sync.loopback = 0;1902 1903 if (copy_to_user(ifs->ifs_ifsu.sync, &sync, sizeof(sync)))1904 return -EFAULT;1905 1906 ifs->size = sizeof(sync);1907 return 0;1908}1909 1910static int1911fst_siocdevprivate(struct net_device *dev, struct ifreq *ifr, void __user *data, int cmd)1912{1913 struct fst_card_info *card;1914 struct fst_port_info *port;1915 struct fstioc_write wrthdr;1916 struct fstioc_info info;1917 unsigned long flags;1918 void *buf;1919 1920 dbg(DBG_IOCTL, "ioctl: %x, %p\n", cmd, data);1921 1922 port = dev_to_port(dev);1923 card = port->card;1924 1925 if (!capable(CAP_NET_ADMIN))1926 return -EPERM;1927 1928 switch (cmd) {1929 case FSTCPURESET:1930 fst_cpureset(card);1931 card->state = FST_RESET;1932 return 0;1933 1934 case FSTCPURELEASE:1935 fst_cpurelease(card);1936 card->state = FST_STARTING;1937 return 0;1938 1939 case FSTWRITE: /* Code write (download) */1940 1941 /* First copy in the header with the length and offset of data1942 * to write1943 */1944 if (!data)1945 return -EINVAL;1946 1947 if (copy_from_user(&wrthdr, data, sizeof(struct fstioc_write)))1948 return -EFAULT;1949 1950 /* Sanity check the parameters. We don't support partial writes1951 * when going over the top1952 */1953 if (wrthdr.size > FST_MEMSIZE || wrthdr.offset > FST_MEMSIZE ||1954 wrthdr.size + wrthdr.offset > FST_MEMSIZE)1955 return -ENXIO;1956 1957 /* Now copy the data to the card. */1958 1959 buf = memdup_user(data + sizeof(struct fstioc_write),1960 wrthdr.size);1961 if (IS_ERR(buf))1962 return PTR_ERR(buf);1963 1964 memcpy_toio(card->mem + wrthdr.offset, buf, wrthdr.size);1965 kfree(buf);1966 1967 /* Writes to the memory of a card in the reset state constitute1968 * a download1969 */1970 if (card->state == FST_RESET)1971 card->state = FST_DOWNLOAD;1972 1973 return 0;1974 1975 case FSTGETCONF:1976 1977 /* If card has just been started check the shared memory config1978 * version and marker1979 */1980 if (card->state == FST_STARTING) {1981 check_started_ok(card);1982 1983 /* If everything checked out enable card interrupts */1984 if (card->state == FST_RUNNING) {1985 spin_lock_irqsave(&card->card_lock, flags);1986 fst_enable_intr(card);1987 FST_WRB(card, interruptHandshake, 0xEE);1988 spin_unlock_irqrestore(&card->card_lock, flags);1989 }1990 }1991 1992 if (!data)1993 return -EINVAL;1994 1995 gather_conf_info(card, port, &info);1996 1997 if (copy_to_user(data, &info, sizeof(info)))1998 return -EFAULT;1999 2000 return 0;2001 2002 case FSTSETCONF:2003 /* Most of the settings have been moved to the generic ioctls2004 * this just covers debug and board ident now2005 */2006 2007 if (card->state != FST_RUNNING) {2008 pr_err("Attempt to configure card %d in non-running state (%d)\n",2009 card->card_no, card->state);2010 return -EIO;2011 }2012 if (copy_from_user(&info, data, sizeof(info)))2013 return -EFAULT;2014 2015 return set_conf_from_info(card, port, &info);2016 default:2017 return -EINVAL;2018 }2019}2020 2021static int2022fst_ioctl(struct net_device *dev, struct if_settings *ifs)2023{2024 struct fst_card_info *card;2025 struct fst_port_info *port;2026 2027 dbg(DBG_IOCTL, "SIOCDEVPRIVATE, %x\n", ifs->type);2028 2029 port = dev_to_port(dev);2030 card = port->card;2031 2032 if (!capable(CAP_NET_ADMIN))2033 return -EPERM;2034 2035 switch (ifs->type) {2036 case IF_GET_IFACE:2037 return fst_get_iface(card, port, ifs);2038 2039 case IF_IFACE_SYNC_SERIAL:2040 case IF_IFACE_V35:2041 case IF_IFACE_V24:2042 case IF_IFACE_X21:2043 case IF_IFACE_X21D:2044 case IF_IFACE_T1:2045 case IF_IFACE_E1:2046 return fst_set_iface(card, port, ifs);2047 2048 case IF_PROTO_RAW:2049 port->mode = FST_RAW;2050 return 0;2051 2052 case IF_GET_PROTO:2053 if (port->mode == FST_RAW) {2054 ifs->type = IF_PROTO_RAW;2055 return 0;2056 }2057 return hdlc_ioctl(dev, ifs);2058 2059 default:2060 port->mode = FST_GEN_HDLC;2061 dbg(DBG_IOCTL, "Passing this type to hdlc %x\n",2062 ifs->type);2063 return hdlc_ioctl(dev, ifs);2064 }2065}2066 2067static void2068fst_openport(struct fst_port_info *port)2069{2070 int signals;2071 2072 /* Only init things if card is actually running. This allows open to2073 * succeed for downloads etc.2074 */2075 if (port->card->state == FST_RUNNING) {2076 if (port->run) {2077 dbg(DBG_OPEN, "open: found port already running\n");2078 2079 fst_issue_cmd(port, STOPPORT);2080 port->run = 0;2081 }2082 2083 fst_rx_config(port);2084 fst_tx_config(port);2085 fst_op_raise(port, OPSTS_RTS | OPSTS_DTR);2086 2087 fst_issue_cmd(port, STARTPORT);2088 port->run = 1;2089 2090 signals = FST_RDL(port->card, v24DebouncedSts[port->index]);2091 if (signals & ((port->hwif == X21 || port->hwif == X21D)2092 ? IPSTS_INDICATE : IPSTS_DCD))2093 netif_carrier_on(port_to_dev(port));2094 else2095 netif_carrier_off(port_to_dev(port));2096 2097 port->txqe = 0;2098 port->txqs = 0;2099 }2100}2101 2102static void2103fst_closeport(struct fst_port_info *port)2104{2105 if (port->card->state == FST_RUNNING) {2106 if (port->run) {2107 port->run = 0;2108 fst_op_lower(port, OPSTS_RTS | OPSTS_DTR);2109 2110 fst_issue_cmd(port, STOPPORT);2111 } else {2112 dbg(DBG_OPEN, "close: port not running\n");2113 }2114 }2115}2116 2117static int2118fst_open(struct net_device *dev)2119{2120 int err;2121 struct fst_port_info *port;2122 2123 port = dev_to_port(dev);2124 if (!try_module_get(THIS_MODULE))2125 return -EBUSY;2126 2127 if (port->mode != FST_RAW) {2128 err = hdlc_open(dev);2129 if (err) {2130 module_put(THIS_MODULE);2131 return err;2132 }2133 }2134 2135 fst_openport(port);2136 netif_wake_queue(dev);2137 return 0;2138}2139 2140static int2141fst_close(struct net_device *dev)2142{2143 struct fst_port_info *port;2144 struct fst_card_info *card;2145 unsigned char tx_dma_done;2146 unsigned char rx_dma_done;2147 2148 port = dev_to_port(dev);2149 card = port->card;2150 2151 tx_dma_done = inb(card->pci_conf + DMACSR1);2152 rx_dma_done = inb(card->pci_conf + DMACSR0);2153 dbg(DBG_OPEN,2154 "Port Close: tx_dma_in_progress = %d (%x) rx_dma_in_progress = %d (%x)\n",2155 card->dmatx_in_progress, tx_dma_done, card->dmarx_in_progress,2156 rx_dma_done);2157 2158 netif_stop_queue(dev);2159 fst_closeport(dev_to_port(dev));2160 if (port->mode != FST_RAW)2161 hdlc_close(dev);2162 2163 module_put(THIS_MODULE);2164 return 0;2165}2166 2167static int2168fst_attach(struct net_device *dev, unsigned short encoding, unsigned short parity)2169{2170 /* Setting currently fixed in FarSync card so we check and forget2171 */2172 if (encoding != ENCODING_NRZ || parity != PARITY_CRC16_PR1_CCITT)2173 return -EINVAL;2174 return 0;2175}2176 2177static void2178fst_tx_timeout(struct net_device *dev, unsigned int txqueue)2179{2180 struct fst_port_info *port;2181 struct fst_card_info *card;2182 2183 port = dev_to_port(dev);2184 card = port->card;2185 dev->stats.tx_errors++;2186 dev->stats.tx_aborted_errors++;2187 dbg(DBG_ASS, "Tx timeout card %d port %d\n",2188 card->card_no, port->index);2189 fst_issue_cmd(port, ABORTTX);2190 2191 netif_trans_update(dev);2192 netif_wake_queue(dev);2193 port->start = 0;2194}2195 2196static netdev_tx_t2197fst_start_xmit(struct sk_buff *skb, struct net_device *dev)2198{2199 struct fst_card_info *card;2200 struct fst_port_info *port;2201 unsigned long flags;2202 int txq_length;2203 2204 port = dev_to_port(dev);2205 card = port->card;2206 dbg(DBG_TX, "fst_start_xmit: length = %d\n", skb->len);2207 2208 /* Drop packet with error if we don't have carrier */2209 if (!netif_carrier_ok(dev)) {2210 dev_kfree_skb(skb);2211 dev->stats.tx_errors++;2212 dev->stats.tx_carrier_errors++;2213 dbg(DBG_ASS,2214 "Tried to transmit but no carrier on card %d port %d\n",2215 card->card_no, port->index);2216 return NETDEV_TX_OK;2217 }2218 2219 /* Drop it if it's too big! MTU failure ? */2220 if (skb->len > LEN_TX_BUFFER) {2221 dbg(DBG_ASS, "Packet too large %d vs %d\n", skb->len,2222 LEN_TX_BUFFER);2223 dev_kfree_skb(skb);2224 dev->stats.tx_errors++;2225 return NETDEV_TX_OK;2226 }2227 2228 /* We are always going to queue the packet2229 * so that the bottom half is the only place we tx from2230 * Check there is room in the port txq2231 */2232 spin_lock_irqsave(&card->card_lock, flags);2233 txq_length = port->txqe - port->txqs;2234 if (txq_length < 0) {2235 /* This is the case where the next free has wrapped but the2236 * last used hasn't2237 */2238 txq_length = txq_length + FST_TXQ_DEPTH;2239 }2240 spin_unlock_irqrestore(&card->card_lock, flags);2241 if (txq_length > fst_txq_high) {2242 /* We have got enough buffers in the pipeline. Ask the network2243 * layer to stop sending frames down2244 */2245 netif_stop_queue(dev);2246 port->start = 1; /* I'm using this to signal stop sent up */2247 }2248 2249 if (txq_length == FST_TXQ_DEPTH - 1) {2250 /* This shouldn't have happened but such is life2251 */2252 dev_kfree_skb(skb);2253 dev->stats.tx_errors++;2254 dbg(DBG_ASS, "Tx queue overflow card %d port %d\n",2255 card->card_no, port->index);2256 return NETDEV_TX_OK;2257 }2258 2259 /* queue the buffer2260 */2261 spin_lock_irqsave(&card->card_lock, flags);2262 port->txq[port->txqe] = skb;2263 port->txqe++;2264 if (port->txqe == FST_TXQ_DEPTH)2265 port->txqe = 0;2266 spin_unlock_irqrestore(&card->card_lock, flags);2267 2268 /* Scehdule the bottom half which now does transmit processing */2269 fst_q_work_item(&fst_work_txq, card->card_no);2270 tasklet_schedule(&fst_tx_task);2271 2272 return NETDEV_TX_OK;2273}2274 2275/* Card setup having checked hardware resources.2276 * Should be pretty bizarre if we get an error here (kernel memory2277 * exhaustion is one possibility). If we do see a problem we report it2278 * via a printk and leave the corresponding interface and all that follow2279 * disabled.2280 */2281static char *type_strings[] = {2282 "no hardware", /* Should never be seen */2283 "FarSync T2P",2284 "FarSync T4P",2285 "FarSync T1U",2286 "FarSync T2U",2287 "FarSync T4U",2288 "FarSync TE1"2289};2290 2291static int2292fst_init_card(struct fst_card_info *card)2293{2294 int i;2295 int err;2296 2297 /* We're working on a number of ports based on the card ID. If the2298 * firmware detects something different later (should never happen)2299 * we'll have to revise it in some way then.2300 */2301 for (i = 0; i < card->nports; i++) {2302 err = register_hdlc_device(card->ports[i].dev);2303 if (err < 0) {2304 pr_err("Cannot register HDLC device for port %d (errno %d)\n",2305 i, -err);2306 while (i--)2307 unregister_hdlc_device(card->ports[i].dev);2308 return err;2309 }2310 }2311 2312 pr_info("%s-%s: %s IRQ%d, %d ports\n",2313 port_to_dev(&card->ports[0])->name,2314 port_to_dev(&card->ports[card->nports - 1])->name,2315 type_strings[card->type], card->irq, card->nports);2316 return 0;2317}2318 2319static const struct net_device_ops fst_ops = {2320 .ndo_open = fst_open,2321 .ndo_stop = fst_close,2322 .ndo_start_xmit = hdlc_start_xmit,2323 .ndo_siocwandev = fst_ioctl,2324 .ndo_siocdevprivate = fst_siocdevprivate,2325 .ndo_tx_timeout = fst_tx_timeout,2326};2327 2328/* Initialise card when detected.2329 * Returns 0 to indicate success, or errno otherwise.2330 */2331static int2332fst_add_one(struct pci_dev *pdev, const struct pci_device_id *ent)2333{2334 static int no_of_cards_added;2335 struct fst_card_info *card;2336 int err = 0;2337 int i;2338 2339 printk_once(KERN_INFO2340 pr_fmt("FarSync WAN driver " FST_USER_VERSION2341 " (c) 2001-2004 FarSite Communications Ltd.\n"));2342#if FST_DEBUG2343 dbg(DBG_ASS, "The value of debug mask is %x\n", fst_debug_mask);2344#endif2345 /* We are going to be clever and allow certain cards not to be2346 * configured. An exclude list can be provided in /etc/modules.conf2347 */2348 if (fst_excluded_cards != 0) {2349 /* There are cards to exclude2350 *2351 */2352 for (i = 0; i < fst_excluded_cards; i++) {2353 if (pdev->devfn >> 3 == fst_excluded_list[i]) {2354 pr_info("FarSync PCI device %d not assigned\n",2355 (pdev->devfn) >> 3);2356 return -EBUSY;2357 }2358 }2359 }2360 2361 /* Allocate driver private data */2362 card = kzalloc(sizeof(struct fst_card_info), GFP_KERNEL);2363 if (!card)2364 return -ENOMEM;2365 2366 /* Try to enable the device */2367 err = pci_enable_device(pdev);2368 if (err) {2369 pr_err("Failed to enable card. Err %d\n", -err);2370 goto enable_fail;2371 }2372 2373 err = pci_request_regions(pdev, "FarSync");2374 if (err) {2375 pr_err("Failed to allocate regions. Err %d\n", -err);2376 goto regions_fail;2377 }2378 2379 /* Get virtual addresses of memory regions */2380 card->pci_conf = pci_resource_start(pdev, 1);2381 card->phys_mem = pci_resource_start(pdev, 2);2382 card->phys_ctlmem = pci_resource_start(pdev, 3);2383 card->mem = ioremap(card->phys_mem, FST_MEMSIZE);2384 if (!card->mem) {2385 pr_err("Physical memory remap failed\n");2386 err = -ENODEV;2387 goto ioremap_physmem_fail;2388 }2389 card->ctlmem = ioremap(card->phys_ctlmem, 0x10);2390 if (!card->ctlmem) {2391 pr_err("Control memory remap failed\n");2392 err = -ENODEV;2393 goto ioremap_ctlmem_fail;2394 }2395 dbg(DBG_PCI, "kernel mem %p, ctlmem %p\n", card->mem, card->ctlmem);2396 2397 /* Register the interrupt handler */2398 if (request_irq(pdev->irq, fst_intr, IRQF_SHARED, FST_DEV_NAME, card)) {2399 pr_err("Unable to register interrupt %d\n", card->irq);2400 err = -ENODEV;2401 goto irq_fail;2402 }2403 2404 /* Record info we need */2405 card->irq = pdev->irq;2406 card->type = ent->driver_data;2407 card->family = ((ent->driver_data == FST_TYPE_T2P) ||2408 (ent->driver_data == FST_TYPE_T4P))2409 ? FST_FAMILY_TXP : FST_FAMILY_TXU;2410 if (ent->driver_data == FST_TYPE_T1U ||2411 ent->driver_data == FST_TYPE_TE1)2412 card->nports = 1;2413 else2414 card->nports = ((ent->driver_data == FST_TYPE_T2P) ||2415 (ent->driver_data == FST_TYPE_T2U)) ? 2 : 4;2416 2417 card->state = FST_UNINIT;2418 spin_lock_init(&card->card_lock);2419 2420 for (i = 0; i < card->nports; i++) {2421 struct net_device *dev = alloc_hdlcdev(&card->ports[i]);2422 hdlc_device *hdlc;2423 2424 if (!dev) {2425 while (i--)2426 free_netdev(card->ports[i].dev);2427 pr_err("FarSync: out of memory\n");2428 err = -ENOMEM;2429 goto hdlcdev_fail;2430 }2431 card->ports[i].dev = dev;2432 card->ports[i].card = card;2433 card->ports[i].index = i;2434 card->ports[i].run = 0;2435 2436 hdlc = dev_to_hdlc(dev);2437 2438 /* Fill in the net device info */2439 /* Since this is a PCI setup this is purely2440 * informational. Give them the buffer addresses2441 * and basic card I/O.2442 */2443 dev->mem_start = card->phys_mem2444 + BUF_OFFSET(txBuffer[i][0][0]);2445 dev->mem_end = card->phys_mem2446 + BUF_OFFSET(txBuffer[i][NUM_TX_BUFFER - 1][LEN_RX_BUFFER - 1]);2447 dev->base_addr = card->pci_conf;2448 dev->irq = card->irq;2449 2450 dev->netdev_ops = &fst_ops;2451 dev->tx_queue_len = FST_TX_QUEUE_LEN;2452 dev->watchdog_timeo = FST_TX_TIMEOUT;2453 hdlc->attach = fst_attach;2454 hdlc->xmit = fst_start_xmit;2455 }2456 2457 card->device = pdev;2458 2459 dbg(DBG_PCI, "type %d nports %d irq %d\n", card->type,2460 card->nports, card->irq);2461 dbg(DBG_PCI, "conf %04x mem %08x ctlmem %08x\n",2462 card->pci_conf, card->phys_mem, card->phys_ctlmem);2463 2464 /* Reset the card's processor */2465 fst_cpureset(card);2466 card->state = FST_RESET;2467 2468 /* Initialise DMA (if required) */2469 fst_init_dma(card);2470 2471 /* Record driver data for later use */2472 pci_set_drvdata(pdev, card);2473 2474 /* Remainder of card setup */2475 if (no_of_cards_added >= FST_MAX_CARDS) {2476 pr_err("FarSync: too many cards\n");2477 err = -ENOMEM;2478 goto card_array_fail;2479 }2480 fst_card_array[no_of_cards_added] = card;2481 card->card_no = no_of_cards_added++; /* Record instance and bump it */2482 err = fst_init_card(card);2483 if (err)2484 goto init_card_fail;2485 if (card->family == FST_FAMILY_TXU) {2486 /* Allocate a dma buffer for transmit and receives2487 */2488 card->rx_dma_handle_host =2489 dma_alloc_coherent(&card->device->dev, FST_MAX_MTU,2490 &card->rx_dma_handle_card, GFP_KERNEL);2491 if (!card->rx_dma_handle_host) {2492 pr_err("Could not allocate rx dma buffer\n");2493 err = -ENOMEM;2494 goto rx_dma_fail;2495 }2496 card->tx_dma_handle_host =2497 dma_alloc_coherent(&card->device->dev, FST_MAX_MTU,2498 &card->tx_dma_handle_card, GFP_KERNEL);2499 if (!card->tx_dma_handle_host) {2500 pr_err("Could not allocate tx dma buffer\n");2501 err = -ENOMEM;2502 goto tx_dma_fail;2503 }2504 }2505 return 0; /* Success */2506 2507tx_dma_fail:2508 dma_free_coherent(&card->device->dev, FST_MAX_MTU,2509 card->rx_dma_handle_host, card->rx_dma_handle_card);2510rx_dma_fail:2511 fst_disable_intr(card);2512 for (i = 0 ; i < card->nports ; i++)2513 unregister_hdlc_device(card->ports[i].dev);2514init_card_fail:2515 fst_card_array[card->card_no] = NULL;2516card_array_fail:2517 for (i = 0 ; i < card->nports ; i++)2518 free_netdev(card->ports[i].dev);2519hdlcdev_fail:2520 free_irq(card->irq, card);2521irq_fail:2522 iounmap(card->ctlmem);2523ioremap_ctlmem_fail:2524 iounmap(card->mem);2525ioremap_physmem_fail:2526 pci_release_regions(pdev);2527regions_fail:2528 pci_disable_device(pdev);2529enable_fail:2530 kfree(card);2531 return err;2532}2533 2534/* Cleanup and close down a card2535 */2536static void2537fst_remove_one(struct pci_dev *pdev)2538{2539 struct fst_card_info *card;2540 int i;2541 2542 card = pci_get_drvdata(pdev);2543 2544 for (i = 0; i < card->nports; i++) {2545 struct net_device *dev = port_to_dev(&card->ports[i]);2546 2547 unregister_hdlc_device(dev);2548 free_netdev(dev);2549 }2550 2551 fst_disable_intr(card);2552 free_irq(card->irq, card);2553 2554 iounmap(card->ctlmem);2555 iounmap(card->mem);2556 pci_release_regions(pdev);2557 if (card->family == FST_FAMILY_TXU) {2558 /* Free dma buffers2559 */2560 dma_free_coherent(&card->device->dev, FST_MAX_MTU,2561 card->rx_dma_handle_host,2562 card->rx_dma_handle_card);2563 dma_free_coherent(&card->device->dev, FST_MAX_MTU,2564 card->tx_dma_handle_host,2565 card->tx_dma_handle_card);2566 }2567 fst_card_array[card->card_no] = NULL;2568 kfree(card);2569}2570 2571static struct pci_driver fst_driver = {2572 .name = FST_NAME,2573 .id_table = fst_pci_dev_id,2574 .probe = fst_add_one,2575 .remove = fst_remove_one,2576};2577 2578static int __init2579fst_init(void)2580{2581 int i;2582 2583 for (i = 0; i < FST_MAX_CARDS; i++)2584 fst_card_array[i] = NULL;2585 return pci_register_driver(&fst_driver);2586}2587 2588static void __exit2589fst_cleanup_module(void)2590{2591 pr_info("FarSync WAN driver unloading\n");2592 pci_unregister_driver(&fst_driver);2593}2594 2595module_init(fst_init);2596module_exit(fst_cleanup_module);2597