146 lines · c
1/* SPDX-License-Identifier: GPL-2.0-or-later */2/* Freescale QUICC Engine HDLC Device Driver3 *4 * Copyright 2014 Freescale Semiconductor Inc.5 */6 7#ifndef _UCC_HDLC_H_8#define _UCC_HDLC_H_9 10#include <linux/kernel.h>11#include <linux/list.h>12 13#include <soc/fsl/qe/immap_qe.h>14#include <soc/fsl/qe/qe.h>15 16#include <soc/fsl/qe/ucc.h>17#include <soc/fsl/qe/ucc_fast.h>18 19/* UCC HDLC event register */20#define UCCE_HDLC_RX_EVENTS \21(UCC_HDLC_UCCE_RXF | UCC_HDLC_UCCE_RXB | UCC_HDLC_UCCE_BSY)22#define UCCE_HDLC_TX_EVENTS (UCC_HDLC_UCCE_TXB | UCC_HDLC_UCCE_TXE)23 24struct ucc_hdlc_param {25 __be16 riptr;26 __be16 tiptr;27 __be16 res0;28 __be16 mrblr;29 __be32 rstate;30 __be32 rbase;31 __be16 rbdstat;32 __be16 rbdlen;33 __be32 rdptr;34 __be32 tstate;35 __be32 tbase;36 __be16 tbdstat;37 __be16 tbdlen;38 __be32 tdptr;39 __be32 rbptr;40 __be32 tbptr;41 __be32 rcrc;42 __be32 res1;43 __be32 tcrc;44 __be32 res2;45 __be32 res3;46 __be32 c_mask;47 __be32 c_pres;48 __be16 disfc;49 __be16 crcec;50 __be16 abtsc;51 __be16 nmarc;52 __be32 max_cnt;53 __be16 mflr;54 __be16 rfthr;55 __be16 rfcnt;56 __be16 hmask;57 __be16 haddr1;58 __be16 haddr2;59 __be16 haddr3;60 __be16 haddr4;61 __be16 ts_tmp;62 __be16 tmp_mb;63};64 65struct ucc_hdlc_private {66 struct ucc_tdm *utdm;67 struct ucc_tdm_info *ut_info;68 struct ucc_fast_private *uccf;69 struct device *dev;70 struct net_device *ndev;71 struct napi_struct napi;72 struct ucc_fast __iomem *uf_regs; /* UCC Fast registers */73 struct ucc_hdlc_param __iomem *ucc_pram;74 u16 tsa;75 bool hdlc_busy;76 bool loopback;77 bool hdlc_bus;78 79 u8 *tx_buffer;80 u8 *rx_buffer;81 dma_addr_t dma_tx_addr;82 dma_addr_t dma_rx_addr;83 84 struct qe_bd *tx_bd_base;85 struct qe_bd *rx_bd_base;86 dma_addr_t dma_tx_bd;87 dma_addr_t dma_rx_bd;88 struct qe_bd *curtx_bd;89 struct qe_bd *currx_bd;90 struct qe_bd *dirty_tx;91 u16 currx_bdnum;92 93 struct sk_buff **tx_skbuff;94 struct sk_buff **rx_skbuff;95 u16 skb_curtx;96 u16 skb_currx;97 unsigned short skb_dirtytx;98 99 unsigned short tx_ring_size;100 unsigned short rx_ring_size;101 s32 ucc_pram_offset;102 103 unsigned short encoding;104 unsigned short parity;105 unsigned short hmask;106 u32 clocking;107 spinlock_t lock; /* lock for Tx BD and Tx buffer */108#ifdef CONFIG_PM109 struct ucc_hdlc_param *ucc_pram_bak;110 u32 gumr;111 u8 guemr;112 u32 cmxsi1cr_l, cmxsi1cr_h;113 u32 cmxsi1syr;114 u32 cmxucr[4];115#endif116};117 118#define TX_BD_RING_LEN 0x10119#define RX_BD_RING_LEN 0x20120#define RX_CLEAN_MAX 0x10121#define NUM_OF_BUF 4122#define MAX_RX_BUF_LENGTH (48 * 0x20)123#define MAX_FRAME_LENGTH (MAX_RX_BUF_LENGTH + 8)124#define ALIGNMENT_OF_UCC_HDLC_PRAM 64125#define SI_BANK_SIZE 128126#define MAX_HDLC_NUM 4127#define HDLC_HEAD_LEN 2128#define HDLC_CRC_SIZE 2129#define TX_RING_MOD_MASK(size) (size - 1)130#define RX_RING_MOD_MASK(size) (size - 1)131 132#define HDLC_HEAD_MASK 0x0000133#define DEFAULT_HDLC_HEAD 0xff44134#define DEFAULT_ADDR_MASK 0x00ff135#define DEFAULT_HDLC_ADDR 0x00ff136 137#define BMR_GBL 0x20000000138#define BMR_BIG_ENDIAN 0x10000000139#define CRC_16BIT_MASK 0x0000F0B8140#define CRC_16BIT_PRES 0x0000FFFF141#define DEFAULT_RFTHR 1142 143#define DEFAULT_PPP_HEAD 0xff03144 145#endif146