243 lines · c
1/* SPDX-License-Identifier: GPL-2.0 */2#ifndef __HD64570_H3#define __HD64570_H4 5/* SCA HD64570 register definitions - all addresses for mode 0 (8086 MPU)6 and 1 (64180 MPU). For modes 2 and 3, XOR the address with 0x01.7 8 Source: HD64570 SCA User's Manual9*/10 11 12 13/* SCA Control Registers */14#define LPR 0x00 /* Low Power */15 16/* Wait controller registers */17#define PABR0 0x02 /* Physical Address Boundary 0 */18#define PABR1 0x03 /* Physical Address Boundary 1 */19#define WCRL 0x04 /* Wait Control L */20#define WCRM 0x05 /* Wait Control M */21#define WCRH 0x06 /* Wait Control H */22 23#define PCR 0x08 /* DMA Priority Control */24#define DMER 0x09 /* DMA Master Enable */25 26 27/* Interrupt registers */28#define ISR0 0x10 /* Interrupt Status 0 */29#define ISR1 0x11 /* Interrupt Status 1 */30#define ISR2 0x12 /* Interrupt Status 2 */31 32#define IER0 0x14 /* Interrupt Enable 0 */33#define IER1 0x15 /* Interrupt Enable 1 */34#define IER2 0x16 /* Interrupt Enable 2 */35 36#define ITCR 0x18 /* Interrupt Control */37#define IVR 0x1A /* Interrupt Vector */38#define IMVR 0x1C /* Interrupt Modified Vector */39 40 41 42/* MSCI channel (port) 0 registers - offset 0x2043 MSCI channel (port) 1 registers - offset 0x40 */44 45#define MSCI0_OFFSET 0x2046#define MSCI1_OFFSET 0x4047 48#define TRBL 0x00 /* TX/RX buffer L */ 49#define TRBH 0x01 /* TX/RX buffer H */ 50#define ST0 0x02 /* Status 0 */51#define ST1 0x03 /* Status 1 */52#define ST2 0x04 /* Status 2 */53#define ST3 0x05 /* Status 3 */54#define FST 0x06 /* Frame Status */55#define IE0 0x08 /* Interrupt Enable 0 */56#define IE1 0x09 /* Interrupt Enable 1 */57#define IE2 0x0A /* Interrupt Enable 2 */58#define FIE 0x0B /* Frame Interrupt Enable */59#define CMD 0x0C /* Command */60#define MD0 0x0E /* Mode 0 */61#define MD1 0x0F /* Mode 1 */62#define MD2 0x10 /* Mode 2 */63#define CTL 0x11 /* Control */64#define SA0 0x12 /* Sync/Address 0 */65#define SA1 0x13 /* Sync/Address 1 */66#define IDL 0x14 /* Idle Pattern */67#define TMC 0x15 /* Time Constant */68#define RXS 0x16 /* RX Clock Source */69#define TXS 0x17 /* TX Clock Source */70#define TRC0 0x18 /* TX Ready Control 0 */ 71#define TRC1 0x19 /* TX Ready Control 1 */ 72#define RRC 0x1A /* RX Ready Control */ 73#define CST0 0x1C /* Current Status 0 */74#define CST1 0x1D /* Current Status 1 */75 76 77/* Timer channel 0 (port 0 RX) registers - offset 0x6078 Timer channel 1 (port 0 TX) registers - offset 0x6879 Timer channel 2 (port 1 RX) registers - offset 0x7080 Timer channel 3 (port 1 TX) registers - offset 0x7881*/82 83#define TIMER0RX_OFFSET 0x6084#define TIMER0TX_OFFSET 0x6885#define TIMER1RX_OFFSET 0x7086#define TIMER1TX_OFFSET 0x7887 88#define TCNTL 0x00 /* Up-counter L */89#define TCNTH 0x01 /* Up-counter H */90#define TCONRL 0x02 /* Constant L */91#define TCONRH 0x03 /* Constant H */92#define TCSR 0x04 /* Control/Status */93#define TEPR 0x05 /* Expand Prescale */94 95 96 97/* DMA channel 0 (port 0 RX) registers - offset 0x8098 DMA channel 1 (port 0 TX) registers - offset 0xA099 DMA channel 2 (port 1 RX) registers - offset 0xC0100 DMA channel 3 (port 1 TX) registers - offset 0xE0101*/102 103#define DMAC0RX_OFFSET 0x80104#define DMAC0TX_OFFSET 0xA0105#define DMAC1RX_OFFSET 0xC0106#define DMAC1TX_OFFSET 0xE0107 108#define BARL 0x00 /* Buffer Address L (chained block) */109#define BARH 0x01 /* Buffer Address H (chained block) */110#define BARB 0x02 /* Buffer Address B (chained block) */111 112#define DARL 0x00 /* RX Destination Addr L (single block) */113#define DARH 0x01 /* RX Destination Addr H (single block) */114#define DARB 0x02 /* RX Destination Addr B (single block) */115 116#define SARL 0x04 /* TX Source Address L (single block) */117#define SARH 0x05 /* TX Source Address H (single block) */118#define SARB 0x06 /* TX Source Address B (single block) */119 120#define CPB 0x06 /* Chain Pointer Base (chained block) */121 122#define CDAL 0x08 /* Current Descriptor Addr L (chained block) */123#define CDAH 0x09 /* Current Descriptor Addr H (chained block) */124#define EDAL 0x0A /* Error Descriptor Addr L (chained block) */125#define EDAH 0x0B /* Error Descriptor Addr H (chained block) */126#define BFLL 0x0C /* RX Receive Buffer Length L (chained block)*/127#define BFLH 0x0D /* RX Receive Buffer Length H (chained block)*/128#define BCRL 0x0E /* Byte Count L */129#define BCRH 0x0F /* Byte Count H */130#define DSR 0x10 /* DMA Status */131#define DSR_RX(node) (DSR + (node ? DMAC1RX_OFFSET : DMAC0RX_OFFSET))132#define DSR_TX(node) (DSR + (node ? DMAC1TX_OFFSET : DMAC0TX_OFFSET))133#define DMR 0x11 /* DMA Mode */134#define DMR_RX(node) (DMR + (node ? DMAC1RX_OFFSET : DMAC0RX_OFFSET))135#define DMR_TX(node) (DMR + (node ? DMAC1TX_OFFSET : DMAC0TX_OFFSET))136#define FCT 0x13 /* Frame End Interrupt Counter */137#define FCT_RX(node) (FCT + (node ? DMAC1RX_OFFSET : DMAC0RX_OFFSET))138#define FCT_TX(node) (FCT + (node ? DMAC1TX_OFFSET : DMAC0TX_OFFSET))139#define DIR 0x14 /* DMA Interrupt Enable */140#define DIR_RX(node) (DIR + (node ? DMAC1RX_OFFSET : DMAC0RX_OFFSET))141#define DIR_TX(node) (DIR + (node ? DMAC1TX_OFFSET : DMAC0TX_OFFSET))142#define DCR 0x15 /* DMA Command */143#define DCR_RX(node) (DCR + (node ? DMAC1RX_OFFSET : DMAC0RX_OFFSET))144#define DCR_TX(node) (DCR + (node ? DMAC1TX_OFFSET : DMAC0TX_OFFSET))145 146 147 148 149/* Descriptor Structure */150 151typedef struct {152 u16 cp; /* Chain Pointer */153 u32 bp; /* Buffer Pointer (24 bits) */154 u16 len; /* Data Length */155 u8 stat; /* Status */156 u8 unused; /* pads to 2-byte boundary */157}__packed pkt_desc;158 159 160/* Packet Descriptor Status bits */161 162#define ST_TX_EOM 0x80 /* End of frame */163#define ST_TX_EOT 0x01 /* End of transmission */164 165#define ST_RX_EOM 0x80 /* End of frame */166#define ST_RX_SHORT 0x40 /* Short frame */167#define ST_RX_ABORT 0x20 /* Abort */168#define ST_RX_RESBIT 0x10 /* Residual bit */169#define ST_RX_OVERRUN 0x08 /* Overrun */170#define ST_RX_CRC 0x04 /* CRC */171 172#define ST_ERROR_MASK 0x7C173 174#define DIR_EOTE 0x80 /* Transfer completed */175#define DIR_EOME 0x40 /* Frame Transfer Completed (chained-block) */176#define DIR_BOFE 0x20 /* Buffer Overflow/Underflow (chained-block)*/177#define DIR_COFE 0x10 /* Counter Overflow (chained-block) */178 179 180#define DSR_EOT 0x80 /* Transfer completed */181#define DSR_EOM 0x40 /* Frame Transfer Completed (chained-block) */182#define DSR_BOF 0x20 /* Buffer Overflow/Underflow (chained-block)*/183#define DSR_COF 0x10 /* Counter Overflow (chained-block) */184#define DSR_DE 0x02 /* DMA Enable */185#define DSR_DWE 0x01 /* DMA Write Disable */186 187/* DMA Master Enable Register (DMER) bits */188#define DMER_DME 0x80 /* DMA Master Enable */189 190 191#define CMD_RESET 0x21 /* Reset Channel */192#define CMD_TX_ENABLE 0x02 /* Start transmitter */193#define CMD_RX_ENABLE 0x12 /* Start receiver */194 195#define MD0_HDLC 0x80 /* Bit-sync HDLC mode */196#define MD0_CRC_ENA 0x04 /* Enable CRC code calculation */197#define MD0_CRC_CCITT 0x02 /* CCITT CRC instead of CRC-16 */198#define MD0_CRC_PR1 0x01 /* Initial all-ones instead of all-zeros */199 200#define MD0_CRC_NONE 0x00201#define MD0_CRC_16_0 0x04202#define MD0_CRC_16 0x05203#define MD0_CRC_ITU_0 0x06204#define MD0_CRC_ITU 0x07205 206#define MD2_NRZ 0x00207#define MD2_NRZI 0x20208#define MD2_MANCHESTER 0x80209#define MD2_FM_MARK 0xA0210#define MD2_FM_SPACE 0xC0211#define MD2_LOOPBACK 0x03 /* Local data Loopback */212 213#define CTL_NORTS 0x01214#define CTL_IDLE 0x10 /* Transmit an idle pattern */215#define CTL_UDRNC 0x20 /* Idle after CRC or FCS+flag transmission */216 217#define ST0_TXRDY 0x02 /* TX ready */218#define ST0_RXRDY 0x01 /* RX ready */219 220#define ST1_UDRN 0x80 /* MSCI TX underrun */221#define ST1_CDCD 0x04 /* DCD level changed */222 223#define ST3_CTS 0x08 /* modem input - /CTS */224#define ST3_DCD 0x04 /* modem input - /DCD */225 226#define IE0_TXINT 0x80 /* TX INT MSCI interrupt enable */227#define IE0_RXINTA 0x40 /* RX INT A MSCI interrupt enable */228#define IE1_UDRN 0x80 /* TX underrun MSCI interrupt enable */229#define IE1_CDCD 0x04 /* DCD level changed */230 231#define DCR_ABORT 0x01 /* Software abort command */232#define DCR_CLEAR_EOF 0x02 /* Clear EOF interrupt */233 234/* TX and RX Clock Source - RXS and TXS */235#define CLK_BRG_MASK 0x0F236#define CLK_LINE_RX 0x00 /* TX/RX clock line input */237#define CLK_LINE_TX 0x00 /* TX/RX line input */238#define CLK_BRG_RX 0x40 /* internal baud rate generator */239#define CLK_BRG_TX 0x40 /* internal baud rate generator */240#define CLK_RXCLK_TX 0x60 /* TX clock from RX clock */241 242#endif243