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1/* SPDX-License-Identifier: GPL-2.0-or-later */2/*3 * hd64572.h Description of the Hitachi HD64572 (SCA-II), valid for 4 * CPU modes 0 & 2.5 *6 * Author: Ivan Passos <ivan@cyclades.com>7 *8 * Copyright: (c) 2000-2001 Cyclades Corp.9 *10 * $Log: hd64572.h,v $11 * Revision 3.1 2001/06/15 12:41:10 regina12 * upping major version number13 *14 * Revision 1.1.1.1 2001/06/13 20:24:49 daniela15 * PC300 initial CVS version (3.4.0-pre1)16 *17 * Revision 1.0 2000/01/25 ivan18 * Initial version.19 */20 21#ifndef __HD64572_H22#define __HD64572_H23 24/* Illegal Access Register */25#define ILAR 0x0026 27/* Wait Controller Registers */28#define PABR0L 0x20 /* Physical Addr Boundary Register 0 L */29#define PABR0H 0x21 /* Physical Addr Boundary Register 0 H */30#define PABR1L 0x22 /* Physical Addr Boundary Register 1 L */31#define PABR1H 0x23 /* Physical Addr Boundary Register 1 H */32#define WCRL 0x24 /* Wait Control Register L */33#define WCRM 0x25 /* Wait Control Register M */34#define WCRH 0x26 /* Wait Control Register H */35 36/* Interrupt Registers */37#define IVR 0x60 /* Interrupt Vector Register */38#define IMVR 0x64 /* Interrupt Modified Vector Register */39#define ITCR 0x68 /* Interrupt Control Register */40#define ISR0 0x6c /* Interrupt Status Register 0 */41#define ISR1 0x70 /* Interrupt Status Register 1 */42#define IER0 0x74 /* Interrupt Enable Register 0 */43#define IER1 0x78 /* Interrupt Enable Register 1 */44 45/* Register Access Macros (chan is 0 or 1 in _any_ case) */46#define M_REG(reg, chan) (reg + 0x80*chan) /* MSCI */47#define DRX_REG(reg, chan) (reg + 0x40*chan) /* DMA Rx */48#define DTX_REG(reg, chan) (reg + 0x20*(2*chan + 1)) /* DMA Tx */49#define TRX_REG(reg, chan) (reg + 0x20*chan) /* Timer Rx */50#define TTX_REG(reg, chan) (reg + 0x10*(2*chan + 1)) /* Timer Tx */51#define ST_REG(reg, chan) (reg + 0x80*chan) /* Status Cnt */52#define IR0_DRX(val, chan) ((val)<<(8*(chan))) /* Int DMA Rx */53#define IR0_DTX(val, chan) ((val)<<(4*(2*chan + 1))) /* Int DMA Tx */54#define IR0_M(val, chan) ((val)<<(8*(chan))) /* Int MSCI */55 56/* MSCI Channel Registers */57#define MSCI0_OFFSET 0x0058#define MSCI1_OFFSET 0x8059 60#define MD0 0x138 /* Mode reg 0 */61#define MD1 0x139 /* Mode reg 1 */62#define MD2 0x13a /* Mode reg 2 */63#define MD3 0x13b /* Mode reg 3 */64#define CTL 0x130 /* Control reg */65#define RXS 0x13c /* RX clock source */66#define TXS 0x13d /* TX clock source */67#define EXS 0x13e /* External clock input selection */68#define TMCT 0x144 /* Time constant (Tx) */69#define TMCR 0x145 /* Time constant (Rx) */70#define CMD 0x128 /* Command reg */71#define ST0 0x118 /* Status reg 0 */72#define ST1 0x119 /* Status reg 1 */73#define ST2 0x11a /* Status reg 2 */74#define ST3 0x11b /* Status reg 3 */75#define ST4 0x11c /* Status reg 4 */76#define FST 0x11d /* frame Status reg */77#define IE0 0x120 /* Interrupt enable reg 0 */78#define IE1 0x121 /* Interrupt enable reg 1 */79#define IE2 0x122 /* Interrupt enable reg 2 */80#define IE4 0x124 /* Interrupt enable reg 4 */81#define FIE 0x125 /* Frame Interrupt enable reg */82#define SA0 0x140 /* Syn Address reg 0 */83#define SA1 0x141 /* Syn Address reg 1 */84#define IDL 0x142 /* Idle register */85#define TRBL 0x100 /* TX/RX buffer reg L */ 86#define TRBK 0x101 /* TX/RX buffer reg K */ 87#define TRBJ 0x102 /* TX/RX buffer reg J */ 88#define TRBH 0x103 /* TX/RX buffer reg H */ 89#define TRC0 0x148 /* TX Ready control reg 0 */ 90#define TRC1 0x149 /* TX Ready control reg 1 */ 91#define RRC 0x14a /* RX Ready control reg */ 92#define CST0 0x108 /* Current Status Register 0 */ 93#define CST1 0x109 /* Current Status Register 1 */ 94#define CST2 0x10a /* Current Status Register 2 */ 95#define CST3 0x10b /* Current Status Register 3 */ 96#define GPO 0x131 /* General Purpose Output Pin Ctl Reg */97#define TFS 0x14b /* Tx Start Threshold Ctl Reg */98#define TFN 0x143 /* Inter-transmit-frame Time Fill Ctl Reg */99#define TBN 0x110 /* Tx Buffer Number Reg */100#define RBN 0x111 /* Rx Buffer Number Reg */101#define TNR0 0x150 /* Tx DMA Request Ctl Reg 0 */102#define TNR1 0x151 /* Tx DMA Request Ctl Reg 1 */103#define TCR 0x152 /* Tx DMA Critical Request Reg */104#define RNR 0x154 /* Rx DMA Request Ctl Reg */105#define RCR 0x156 /* Rx DMA Critical Request Reg */106 107/* Timer Registers */108#define TIMER0RX_OFFSET 0x00109#define TIMER0TX_OFFSET 0x10110#define TIMER1RX_OFFSET 0x20111#define TIMER1TX_OFFSET 0x30112 113#define TCNTL 0x200 /* Timer Upcounter L */114#define TCNTH 0x201 /* Timer Upcounter H */115#define TCONRL 0x204 /* Timer Constant Register L */116#define TCONRH 0x205 /* Timer Constant Register H */117#define TCSR 0x206 /* Timer Control/Status Register */118#define TEPR 0x207 /* Timer Expand Prescale Register */119 120/* DMA registers */121#define PCR 0x40 /* DMA priority control reg */122#define DRR 0x44 /* DMA reset reg */123#define DMER 0x07 /* DMA Master Enable reg */124#define BTCR 0x08 /* Burst Tx Ctl Reg */125#define BOLR 0x0c /* Back-off Length Reg */126#define DSR_RX(chan) (0x48 + 2*chan) /* DMA Status Reg (Rx) */127#define DSR_TX(chan) (0x49 + 2*chan) /* DMA Status Reg (Tx) */128#define DIR_RX(chan) (0x4c + 2*chan) /* DMA Interrupt Enable Reg (Rx) */129#define DIR_TX(chan) (0x4d + 2*chan) /* DMA Interrupt Enable Reg (Tx) */130#define FCT_RX(chan) (0x50 + 2*chan) /* Frame End Interrupt Counter (Rx) */131#define FCT_TX(chan) (0x51 + 2*chan) /* Frame End Interrupt Counter (Tx) */132#define DMR_RX(chan) (0x54 + 2*chan) /* DMA Mode Reg (Rx) */133#define DMR_TX(chan) (0x55 + 2*chan) /* DMA Mode Reg (Tx) */134#define DCR_RX(chan) (0x58 + 2*chan) /* DMA Command Reg (Rx) */135#define DCR_TX(chan) (0x59 + 2*chan) /* DMA Command Reg (Tx) */136 137/* DMA Channel Registers */138#define DMAC0RX_OFFSET 0x00139#define DMAC0TX_OFFSET 0x20140#define DMAC1RX_OFFSET 0x40141#define DMAC1TX_OFFSET 0x60142 143#define DARL 0x80 /* Dest Addr Register L (single-block, RX only) */144#define DARH 0x81 /* Dest Addr Register H (single-block, RX only) */145#define DARB 0x82 /* Dest Addr Register B (single-block, RX only) */146#define DARBH 0x83 /* Dest Addr Register BH (single-block, RX only) */147#define SARL 0x80 /* Source Addr Register L (single-block, TX only) */148#define SARH 0x81 /* Source Addr Register H (single-block, TX only) */149#define SARB 0x82 /* Source Addr Register B (single-block, TX only) */150#define DARBH 0x83 /* Source Addr Register BH (single-block, TX only) */151#define BARL 0x80 /* Buffer Addr Register L (chained-block) */152#define BARH 0x81 /* Buffer Addr Register H (chained-block) */153#define BARB 0x82 /* Buffer Addr Register B (chained-block) */154#define BARBH 0x83 /* Buffer Addr Register BH (chained-block) */155#define CDAL 0x84 /* Current Descriptor Addr Register L */156#define CDAH 0x85 /* Current Descriptor Addr Register H */157#define CDAB 0x86 /* Current Descriptor Addr Register B */158#define CDABH 0x87 /* Current Descriptor Addr Register BH */159#define EDAL 0x88 /* Error Descriptor Addr Register L */160#define EDAH 0x89 /* Error Descriptor Addr Register H */161#define EDAB 0x8a /* Error Descriptor Addr Register B */162#define EDABH 0x8b /* Error Descriptor Addr Register BH */163#define BFLL 0x90 /* RX Buffer Length L (only RX) */164#define BFLH 0x91 /* RX Buffer Length H (only RX) */165#define BCRL 0x8c /* Byte Count Register L */166#define BCRH 0x8d /* Byte Count Register H */167 168/* Block Descriptor Structure */169typedef struct {170 unsigned long next; /* pointer to next block descriptor */171 unsigned long ptbuf; /* buffer pointer */172 unsigned short len; /* data length */173 unsigned char status; /* status */174 unsigned char filler[5]; /* alignment filler (16 bytes) */ 175} pcsca_bd_t;176 177/* Block Descriptor Structure */178typedef struct {179 u32 cp; /* pointer to next block descriptor */180 u32 bp; /* buffer pointer */181 u16 len; /* data length */182 u8 stat; /* status */183 u8 unused; /* pads to 4-byte boundary */184}pkt_desc;185 186 187/*188 Descriptor Status definitions:189 190 Bit Transmission Reception191 192 7 EOM EOM193 6 - Short Frame194 5 - Abort195 4 - Residual bit196 3 Underrun Overrun 197 2 - CRC198 1 Ownership Ownership199 0 EOT -200*/201#define DST_EOT 0x01 /* End of transmit command */202#define DST_OSB 0x02 /* Ownership bit */203#define DST_CRC 0x04 /* CRC Error */204#define DST_OVR 0x08 /* Overrun */205#define DST_UDR 0x08 /* Underrun */206#define DST_RBIT 0x10 /* Residual bit */207#define DST_ABT 0x20 /* Abort */208#define DST_SHRT 0x40 /* Short Frame */209#define DST_EOM 0x80 /* End of Message */210 211/* Packet Descriptor Status bits */212 213#define ST_TX_EOM 0x80 /* End of frame */214#define ST_TX_UNDRRUN 0x08215#define ST_TX_OWNRSHP 0x02216#define ST_TX_EOT 0x01 /* End of transmission */217 218#define ST_RX_EOM 0x80 /* End of frame */219#define ST_RX_SHORT 0x40 /* Short frame */220#define ST_RX_ABORT 0x20 /* Abort */221#define ST_RX_RESBIT 0x10 /* Residual bit */222#define ST_RX_OVERRUN 0x08 /* Overrun */223#define ST_RX_CRC 0x04 /* CRC */224#define ST_RX_OWNRSHP 0x02225 226#define ST_ERROR_MASK 0x7C227 228/* Status Counter Registers */229#define CMCR 0x158 /* Counter Master Ctl Reg */230#define TECNTL 0x160 /* Tx EOM Counter L */231#define TECNTM 0x161 /* Tx EOM Counter M */232#define TECNTH 0x162 /* Tx EOM Counter H */233#define TECCR 0x163 /* Tx EOM Counter Ctl Reg */234#define URCNTL 0x164 /* Underrun Counter L */235#define URCNTH 0x165 /* Underrun Counter H */236#define URCCR 0x167 /* Underrun Counter Ctl Reg */237#define RECNTL 0x168 /* Rx EOM Counter L */238#define RECNTM 0x169 /* Rx EOM Counter M */239#define RECNTH 0x16a /* Rx EOM Counter H */240#define RECCR 0x16b /* Rx EOM Counter Ctl Reg */241#define ORCNTL 0x16c /* Overrun Counter L */242#define ORCNTH 0x16d /* Overrun Counter H */243#define ORCCR 0x16f /* Overrun Counter Ctl Reg */244#define CECNTL 0x170 /* CRC Counter L */245#define CECNTH 0x171 /* CRC Counter H */246#define CECCR 0x173 /* CRC Counter Ctl Reg */247#define ABCNTL 0x174 /* Abort frame Counter L */248#define ABCNTH 0x175 /* Abort frame Counter H */249#define ABCCR 0x177 /* Abort frame Counter Ctl Reg */250#define SHCNTL 0x178 /* Short frame Counter L */251#define SHCNTH 0x179 /* Short frame Counter H */252#define SHCCR 0x17b /* Short frame Counter Ctl Reg */253#define RSCNTL 0x17c /* Residual bit Counter L */254#define RSCNTH 0x17d /* Residual bit Counter H */255#define RSCCR 0x17f /* Residual bit Counter Ctl Reg */256 257/* Register Programming Constants */258 259#define IR0_DMIC 0x00000001260#define IR0_DMIB 0x00000002261#define IR0_DMIA 0x00000004262#define IR0_EFT 0x00000008263#define IR0_DMAREQ 0x00010000264#define IR0_TXINT 0x00020000265#define IR0_RXINTB 0x00040000266#define IR0_RXINTA 0x00080000267#define IR0_TXRDY 0x00100000268#define IR0_RXRDY 0x00200000269 270#define MD0_CRC16_0 0x00271#define MD0_CRC16_1 0x01272#define MD0_CRC32 0x02273#define MD0_CRC_CCITT 0x03274#define MD0_CRCC0 0x04275#define MD0_CRCC1 0x08276#define MD0_AUTO_ENA 0x10277#define MD0_ASYNC 0x00278#define MD0_BY_MSYNC 0x20279#define MD0_BY_BISYNC 0x40280#define MD0_BY_EXT 0x60281#define MD0_BIT_SYNC 0x80282#define MD0_TRANSP 0xc0283 284#define MD0_HDLC 0x80 /* Bit-sync HDLC mode */285 286#define MD0_CRC_NONE 0x00287#define MD0_CRC_16_0 0x04288#define MD0_CRC_16 0x05289#define MD0_CRC_ITU32 0x06290#define MD0_CRC_ITU 0x07291 292#define MD1_NOADDR 0x00293#define MD1_SADDR1 0x40294#define MD1_SADDR2 0x80295#define MD1_DADDR 0xc0296 297#define MD2_NRZI_IEEE 0x40298#define MD2_MANCHESTER 0x80299#define MD2_FM_MARK 0xA0300#define MD2_FM_SPACE 0xC0301#define MD2_LOOPBACK 0x03 /* Local data Loopback */302 303#define MD2_F_DUPLEX 0x00304#define MD2_AUTO_ECHO 0x01305#define MD2_LOOP_HI_Z 0x02306#define MD2_LOOP_MIR 0x03307#define MD2_ADPLL_X8 0x00308#define MD2_ADPLL_X16 0x08309#define MD2_ADPLL_X32 0x10310#define MD2_NRZ 0x00311#define MD2_NRZI 0x20312#define MD2_NRZ_IEEE 0x40313#define MD2_MANCH 0x00314#define MD2_FM1 0x20315#define MD2_FM0 0x40316#define MD2_FM 0x80317 318#define CTL_RTS 0x01319#define CTL_DTR 0x02320#define CTL_SYN 0x04321#define CTL_IDLC 0x10322#define CTL_UDRNC 0x20323#define CTL_URSKP 0x40324#define CTL_URCT 0x80325 326#define CTL_NORTS 0x01327#define CTL_NODTR 0x02328#define CTL_IDLE 0x10329 330#define RXS_BR0 0x01331#define RXS_BR1 0x02332#define RXS_BR2 0x04333#define RXS_BR3 0x08334#define RXS_ECLK 0x00335#define RXS_ECLK_NS 0x20336#define RXS_IBRG 0x40337#define RXS_PLL1 0x50338#define RXS_PLL2 0x60339#define RXS_PLL3 0x70340#define RXS_DRTXC 0x80341 342#define TXS_BR0 0x01343#define TXS_BR1 0x02344#define TXS_BR2 0x04345#define TXS_BR3 0x08346#define TXS_ECLK 0x00347#define TXS_IBRG 0x40348#define TXS_RCLK 0x60349#define TXS_DTRXC 0x80350 351#define EXS_RES0 0x01352#define EXS_RES1 0x02353#define EXS_RES2 0x04354#define EXS_TES0 0x10355#define EXS_TES1 0x20356#define EXS_TES2 0x40357 358#define CLK_BRG_MASK 0x0F359#define CLK_PIN_OUT 0x80360#define CLK_LINE 0x00 /* clock line input */361#define CLK_BRG 0x40 /* internal baud rate generator */362#define CLK_TX_RXCLK 0x60 /* TX clock from RX clock */363 364#define CMD_RX_RST 0x11365#define CMD_RX_ENA 0x12366#define CMD_RX_DIS 0x13367#define CMD_RX_CRC_INIT 0x14368#define CMD_RX_MSG_REJ 0x15369#define CMD_RX_MP_SRCH 0x16370#define CMD_RX_CRC_EXC 0x17371#define CMD_RX_CRC_FRC 0x18372#define CMD_TX_RST 0x01373#define CMD_TX_ENA 0x02374#define CMD_TX_DISA 0x03375#define CMD_TX_CRC_INIT 0x04376#define CMD_TX_CRC_EXC 0x05377#define CMD_TX_EOM 0x06378#define CMD_TX_ABORT 0x07379#define CMD_TX_MP_ON 0x08380#define CMD_TX_BUF_CLR 0x09381#define CMD_TX_DISB 0x0b382#define CMD_CH_RST 0x21383#define CMD_SRCH_MODE 0x31384#define CMD_NOP 0x00385 386#define CMD_RESET 0x21387#define CMD_TX_ENABLE 0x02388#define CMD_RX_ENABLE 0x12389 390#define ST0_RXRDY 0x01391#define ST0_TXRDY 0x02392#define ST0_RXINTB 0x20393#define ST0_RXINTA 0x40394#define ST0_TXINT 0x80395 396#define ST1_IDLE 0x01397#define ST1_ABORT 0x02398#define ST1_CDCD 0x04399#define ST1_CCTS 0x08400#define ST1_SYN_FLAG 0x10401#define ST1_CLMD 0x20402#define ST1_TXIDLE 0x40403#define ST1_UDRN 0x80404 405#define ST2_CRCE 0x04406#define ST2_ONRN 0x08407#define ST2_RBIT 0x10408#define ST2_ABORT 0x20409#define ST2_SHORT 0x40410#define ST2_EOM 0x80411 412#define ST3_RX_ENA 0x01413#define ST3_TX_ENA 0x02414#define ST3_DCD 0x04415#define ST3_CTS 0x08416#define ST3_SRCH_MODE 0x10417#define ST3_SLOOP 0x20418#define ST3_GPI 0x80419 420#define ST4_RDNR 0x01421#define ST4_RDCR 0x02422#define ST4_TDNR 0x04423#define ST4_TDCR 0x08424#define ST4_OCLM 0x20425#define ST4_CFT 0x40426#define ST4_CGPI 0x80427 428#define FST_CRCEF 0x04429#define FST_OVRNF 0x08430#define FST_RBIF 0x10431#define FST_ABTF 0x20432#define FST_SHRTF 0x40433#define FST_EOMF 0x80434 435#define IE0_RXRDY 0x01436#define IE0_TXRDY 0x02437#define IE0_RXINTB 0x20438#define IE0_RXINTA 0x40439#define IE0_TXINT 0x80440#define IE0_UDRN 0x00008000 /* TX underrun MSCI interrupt enable */441#define IE0_CDCD 0x00000400 /* CD level change interrupt enable */442 443#define IE1_IDLD 0x01444#define IE1_ABTD 0x02445#define IE1_CDCD 0x04446#define IE1_CCTS 0x08447#define IE1_SYNCD 0x10448#define IE1_CLMD 0x20449#define IE1_IDL 0x40450#define IE1_UDRN 0x80451 452#define IE2_CRCE 0x04453#define IE2_OVRN 0x08454#define IE2_RBIT 0x10455#define IE2_ABT 0x20456#define IE2_SHRT 0x40457#define IE2_EOM 0x80458 459#define IE4_RDNR 0x01460#define IE4_RDCR 0x02461#define IE4_TDNR 0x04462#define IE4_TDCR 0x08463#define IE4_OCLM 0x20464#define IE4_CFT 0x40465#define IE4_CGPI 0x80466 467#define FIE_CRCEF 0x04468#define FIE_OVRNF 0x08469#define FIE_RBIF 0x10470#define FIE_ABTF 0x20471#define FIE_SHRTF 0x40472#define FIE_EOMF 0x80473 474#define DSR_DWE 0x01475#define DSR_DE 0x02476#define DSR_REF 0x04477#define DSR_UDRF 0x04478#define DSR_COA 0x08479#define DSR_COF 0x10480#define DSR_BOF 0x20481#define DSR_EOM 0x40482#define DSR_EOT 0x80483 484#define DIR_REF 0x04485#define DIR_UDRF 0x04486#define DIR_COA 0x08487#define DIR_COF 0x10488#define DIR_BOF 0x20489#define DIR_EOM 0x40490#define DIR_EOT 0x80491 492#define DIR_REFE 0x04493#define DIR_UDRFE 0x04494#define DIR_COAE 0x08495#define DIR_COFE 0x10496#define DIR_BOFE 0x20497#define DIR_EOME 0x40498#define DIR_EOTE 0x80499 500#define DMR_CNTE 0x02501#define DMR_NF 0x04502#define DMR_SEOME 0x08503#define DMR_TMOD 0x10504 505#define DMER_DME 0x80 /* DMA Master Enable */506 507#define DCR_SW_ABT 0x01508#define DCR_FCT_CLR 0x02509 510#define DCR_ABORT 0x01511#define DCR_CLEAR_EOF 0x02512 513#define PCR_COTE 0x80514#define PCR_PR0 0x01515#define PCR_PR1 0x02516#define PCR_PR2 0x04517#define PCR_CCC 0x08518#define PCR_BRC 0x10519#define PCR_OSB 0x40520#define PCR_BURST 0x80521 522#endif /* (__HD64572_H) */523