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1/* SPDX-License-Identifier: GPL-2.0-only */2.psize 03/*4 wanXL serial card driver for Linux5 card firmware part6 7 Copyright (C) 2003 Krzysztof Halasa <khc@pm.waw.pl>8 9 10 11 12 13 DPRAM BDs:14 0x000 - 0x050 TX#0 0x050 - 0x140 RX#015 0x140 - 0x190 TX#1 0x190 - 0x280 RX#116 0x280 - 0x2D0 TX#2 0x2D0 - 0x3C0 RX#217 0x3C0 - 0x410 TX#3 0x410 - 0x500 RX#318 19 20 000 5FF 1536 Bytes Dual-Port RAM User Data / BDs21 600 6FF 256 Bytes Dual-Port RAM User Data / BDs22 700 7FF 256 Bytes Dual-Port RAM User Data / BDs23 C00 CBF 192 Bytes Dual-Port RAM Parameter RAM Page 124 D00 DBF 192 Bytes Dual-Port RAM Parameter RAM Page 225 E00 EBF 192 Bytes Dual-Port RAM Parameter RAM Page 326 F00 FBF 192 Bytes Dual-Port RAM Parameter RAM Page 427 28 local interrupts level29 NMI 730 PIT timer, CPM (RX/TX complete) 431 PCI9060 DMA and PCI doorbells 332 Cable - not used 133*/34 35#include <linux/hdlc.h>36#include <linux/hdlc/ioctl.h>37#include "wanxl.h"38 39/* memory addresses and offsets */40 41MAX_RAM_SIZE = 16 * 1024 * 1024 // max RAM supported by hardware42 43PCI9060_VECTOR = 0x0000006C44CPM_IRQ_BASE = 0x4045ERROR_VECTOR = CPM_IRQ_BASE * 446SCC1_VECTOR = (CPM_IRQ_BASE + 0x1E) * 447SCC2_VECTOR = (CPM_IRQ_BASE + 0x1D) * 448SCC3_VECTOR = (CPM_IRQ_BASE + 0x1C) * 449SCC4_VECTOR = (CPM_IRQ_BASE + 0x1B) * 450CPM_IRQ_LEVEL = 451TIMER_IRQ = 12852TIMER_IRQ_LEVEL = 453PITR_CONST = 0x100 + 16 // 1 Hz timer54 55MBAR = 0x0003FF0056 57VALUE_WINDOW = 0x4000000058ORDER_WINDOW = 0xC000000059 60PLX = 0xFFF9000061 62CSRA = 0xFFFB000063CSRB = 0xFFFB000264CSRC = 0xFFFB000465CSRD = 0xFFFB000666STATUS_CABLE_LL = 0x200067STATUS_CABLE_DTR = 0x100068 69DPRBASE = 0xFFFC000070 71SCC1_BASE = DPRBASE + 0xC0072MISC_BASE = DPRBASE + 0xCB073SCC2_BASE = DPRBASE + 0xD0074SCC3_BASE = DPRBASE + 0xE0075SCC4_BASE = DPRBASE + 0xF0076 77// offset from SCCx_BASE78// SCC_xBASE contain offsets from DPRBASE and must be divisible by 879SCC_RBASE = 0 // 16-bit RxBD base address80SCC_TBASE = 2 // 16-bit TxBD base address81SCC_RFCR = 4 // 8-bit Rx function code82SCC_TFCR = 5 // 8-bit Tx function code83SCC_MRBLR = 6 // 16-bit maximum Rx buffer length84SCC_C_MASK = 0x34 // 32-bit CRC constant85SCC_C_PRES = 0x38 // 32-bit CRC preset86SCC_MFLR = 0x46 // 16-bit max Rx frame length (without flags)87 88REGBASE = DPRBASE + 0x100089PICR = REGBASE + 0x026 // 16-bit periodic irq control90PITR = REGBASE + 0x02A // 16-bit periodic irq timing91OR1 = REGBASE + 0x064 // 32-bit RAM bank #1 options92CICR = REGBASE + 0x540 // 32(24)-bit CP interrupt config93CIMR = REGBASE + 0x548 // 32-bit CP interrupt mask94CISR = REGBASE + 0x54C // 32-bit CP interrupts in-service95PADIR = REGBASE + 0x550 // 16-bit PortA data direction bitmap96PAPAR = REGBASE + 0x552 // 16-bit PortA pin assignment bitmap97PAODR = REGBASE + 0x554 // 16-bit PortA open drain bitmap98PADAT = REGBASE + 0x556 // 16-bit PortA data register99 100PCDIR = REGBASE + 0x560 // 16-bit PortC data direction bitmap101PCPAR = REGBASE + 0x562 // 16-bit PortC pin assignment bitmap102PCSO = REGBASE + 0x564 // 16-bit PortC special options103PCDAT = REGBASE + 0x566 // 16-bit PortC data register104PCINT = REGBASE + 0x568 // 16-bit PortC interrupt control105CR = REGBASE + 0x5C0 // 16-bit Command register106 107SCC1_REGS = REGBASE + 0x600108SCC2_REGS = REGBASE + 0x620109SCC3_REGS = REGBASE + 0x640110SCC4_REGS = REGBASE + 0x660111SICR = REGBASE + 0x6EC // 32-bit SI clock route112 113// offset from SCCx_REGS114SCC_GSMR_L = 0x00 // 32 bits115SCC_GSMR_H = 0x04 // 32 bits116SCC_PSMR = 0x08 // 16 bits117SCC_TODR = 0x0C // 16 bits118SCC_DSR = 0x0E // 16 bits119SCC_SCCE = 0x10 // 16 bits120SCC_SCCM = 0x14 // 16 bits121SCC_SCCS = 0x17 // 8 bits122 123#if QUICC_MEMCPY_USES_PLX124 .macro memcpy_from_pci src, dest, len // len must be < 8 MB125 addl #3, \len126 andl #0xFFFFFFFC, \len // always copy n * 4 bytes127 movel \src, PLX_DMA_0_PCI128 movel \dest, PLX_DMA_0_LOCAL129 movel \len, PLX_DMA_0_LENGTH130 movel #0x0103, PLX_DMA_CMD_STS // start channel 0 transfer131 bsr memcpy_from_pci_run132 .endm133 134 .macro memcpy_to_pci src, dest, len135 addl #3, \len136 andl #0xFFFFFFFC, \len // always copy n * 4 bytes137 movel \src, PLX_DMA_1_LOCAL138 movel \dest, PLX_DMA_1_PCI139 movel \len, PLX_DMA_1_LENGTH140 movel #0x0301, PLX_DMA_CMD_STS // start channel 1 transfer141 bsr memcpy_to_pci_run142 .endm143 144#else145 146 .macro memcpy src, dest, len // len must be < 65536 bytes147 movel %d7, -(%sp) // src and dest must be < 256 MB148 movel \len, %d7 // bits 0 and 1149 lsrl #2, \len150 andl \len, \len151 beq 99f // only 0 - 3 bytes152 subl #1, \len // for dbf15398: movel (\src)+, (\dest)+154 dbfw \len, 98b15599: movel %d7, \len156 btstl #1, \len157 beq 99f158 movew (\src)+, (\dest)+15999: btstl #0, \len160 beq 99f161 moveb (\src)+, (\dest)+16299:163 movel (%sp)+, %d7164 .endm165 166 .macro memcpy_from_pci src, dest, len167 addl #VALUE_WINDOW, \src168 memcpy \src, \dest, \len169 .endm170 171 .macro memcpy_to_pci src, dest, len172 addl #VALUE_WINDOW, \dest173 memcpy \src, \dest, \len174 .endm175#endif176 177 178 .macro wait_for_command17999: btstl #0, CR180 bne 99b181 .endm182 183 184 185 186/****************************** card initialization *******************/187 .text188 .global _start189_start: bra init190 191 .org _start + 4192ch_status_addr: .long 0, 0, 0, 0193rx_descs_addr: .long 0194 195init:196#if DETECT_RAM197 movel OR1, %d0198 andl #0xF00007FF, %d0 // mask AMxx bits199 orl #0xFFFF800 & ~(MAX_RAM_SIZE - 1), %d0 // update RAM bank size200 movel %d0, OR1201#endif202 203 addl #VALUE_WINDOW, rx_descs_addr // PCI addresses of shared data204 clrl %d0 // D0 = 4 * port205init_1: tstl ch_status_addr(%d0)206 beq init_2207 addl #VALUE_WINDOW, ch_status_addr(%d0)208init_2: addl #4, %d0209 cmpl #4 * 4, %d0210 bne init_1211 212 movel #pci9060_interrupt, PCI9060_VECTOR213 movel #error_interrupt, ERROR_VECTOR214 movel #port_interrupt_1, SCC1_VECTOR215 movel #port_interrupt_2, SCC2_VECTOR216 movel #port_interrupt_3, SCC3_VECTOR217 movel #port_interrupt_4, SCC4_VECTOR218 movel #timer_interrupt, TIMER_IRQ * 4219 220 movel #0x78000000, CIMR // only SCCx IRQs from CPM221 movew #(TIMER_IRQ_LEVEL << 8) + TIMER_IRQ, PICR // interrupt from PIT222 movew #PITR_CONST, PITR223 224 // SCC1=SCCa SCC2=SCCb SCC3=SCCc SCC4=SCCd prio=4 HP=-1 IRQ=64-79225 movel #0xD41F40 + (CPM_IRQ_LEVEL << 13), CICR226 movel #0x543, PLX_DMA_0_MODE // 32-bit, Ready, Burst, IRQ227 movel #0x543, PLX_DMA_1_MODE228 movel #0x0, PLX_DMA_0_DESC // from PCI to local229 movel #0x8, PLX_DMA_1_DESC // from local to PCI230 movel #0x101, PLX_DMA_CMD_STS // enable both DMA channels231 // enable local IRQ, DMA, doorbells and PCI IRQ232 orl #0x000F0300, PLX_INTERRUPT_CS233 234#if DETECT_RAM235 bsr ram_test236#else237 movel #1, PLX_MAILBOX_5 // non-zero value = init complete238#endif239 bsr check_csr240 241 movew #0xFFFF, PAPAR // all pins are clocks/data242 clrw PADIR // first function243 clrw PCSO // CD and CTS always active244 245 246/****************************** main loop *****************************/247 248main: movel channel_stats, %d7 // D7 = doorbell + irq status249 clrl channel_stats250 251 tstl %d7252 bne main_1253 // nothing to do - wait for next event254 stop #0x2200 // supervisor + IRQ level 2255 movew #0x2700, %sr // disable IRQs again256 bra main257 258main_1: clrl %d0 // D0 = 4 * port259 clrl %d6 // D6 = doorbell to host value260 261main_l: btstl #DOORBELL_TO_CARD_CLOSE_0, %d7262 beq main_op263 bclrl #DOORBELL_TO_CARD_OPEN_0, %d7 // in case both bits are set264 bsr close_port265main_op:266 btstl #DOORBELL_TO_CARD_OPEN_0, %d7267 beq main_cl268 bsr open_port269main_cl:270 btstl #DOORBELL_TO_CARD_TX_0, %d7271 beq main_txend272 bsr tx273main_txend:274 btstl #TASK_SCC_0, %d7275 beq main_next276 bsr tx_end277 bsr rx278 279main_next:280 lsrl #1, %d7 // port status for next port281 addl #4, %d0 // D0 = 4 * next port282 cmpl #4 * 4, %d0283 bne main_l284 movel %d6, PLX_DOORBELL_FROM_CARD // signal the host285 bra main286 287 288/****************************** open port *****************************/289 290open_port: // D0 = 4 * port, D6 = doorbell to host291 movel ch_status_addr(%d0), %a0 // A0 = port status address292 tstl STATUS_OPEN(%a0)293 bne open_port_ret // port already open294 movel #1, STATUS_OPEN(%a0) // confirm the port is open295// setup BDs296 clrl tx_in(%d0)297 clrl tx_out(%d0)298 clrl tx_count(%d0)299 clrl rx_in(%d0)300 301 movel SICR, %d1 // D1 = clock settings in SICR302 andl clocking_mask(%d0), %d1303 cmpl #CLOCK_TXFROMRX, STATUS_CLOCKING(%a0)304 bne open_port_clock_ext305 orl clocking_txfromrx(%d0), %d1306 bra open_port_set_clock307 308open_port_clock_ext:309 orl clocking_ext(%d0), %d1310open_port_set_clock:311 movel %d1, SICR // update clock settings in SICR312 313 orw #STATUS_CABLE_DTR, csr_output(%d0) // DTR on314 bsr check_csr // call with disabled timer interrupt315 316// Setup TX descriptors317 movel first_buffer(%d0), %d1 // D1 = starting buffer address318 movel tx_first_bd(%d0), %a1 // A1 = starting TX BD address319 movel #TX_BUFFERS - 2, %d2 // D2 = TX_BUFFERS - 1 counter320 movel #0x18000000, %d3 // D3 = initial TX BD flags: Int + Last321 cmpl #PARITY_NONE, STATUS_PARITY(%a0)322 beq open_port_tx_loop323 bsetl #26, %d3 // TX BD flag: Transmit CRC324open_port_tx_loop:325 movel %d3, (%a1)+ // TX flags + length326 movel %d1, (%a1)+ // buffer address327 addl #BUFFER_LENGTH, %d1328 dbfw %d2, open_port_tx_loop329 330 bsetl #29, %d3 // TX BD flag: Wrap (last BD)331 movel %d3, (%a1)+ // Final TX flags + length332 movel %d1, (%a1)+ // buffer address333 334// Setup RX descriptors // A1 = starting RX BD address335 movel #RX_BUFFERS - 2, %d2 // D2 = RX_BUFFERS - 1 counter336open_port_rx_loop:337 movel #0x90000000, (%a1)+ // RX flags + length338 movel %d1, (%a1)+ // buffer address339 addl #BUFFER_LENGTH, %d1340 dbfw %d2, open_port_rx_loop341 342 movel #0xB0000000, (%a1)+ // Final RX flags + length343 movel %d1, (%a1)+ // buffer address344 345// Setup port parameters346 movel scc_base_addr(%d0), %a1 // A1 = SCC_BASE address347 movel scc_reg_addr(%d0), %a2 // A2 = SCC_REGS address348 349 movel #0xFFFF, SCC_SCCE(%a2) // clear status bits350 movel #0x0000, SCC_SCCM(%a2) // interrupt mask351 352 movel tx_first_bd(%d0), %d1353 movew %d1, SCC_TBASE(%a1) // D1 = offset of first TxBD354 addl #TX_BUFFERS * 8, %d1355 movew %d1, SCC_RBASE(%a1) // D1 = offset of first RxBD356 moveb #0x8, SCC_RFCR(%a1) // Intel mode, 1000357 moveb #0x8, SCC_TFCR(%a1)358 359// Parity settings360 cmpl #PARITY_CRC16_PR1_CCITT, STATUS_PARITY(%a0)361 bne open_port_parity_1362 clrw SCC_PSMR(%a2) // CRC16-CCITT363 movel #0xF0B8, SCC_C_MASK(%a1)364 movel #0xFFFF, SCC_C_PRES(%a1)365 movew #HDLC_MAX_MRU + 2, SCC_MFLR(%a1) // 2 bytes for CRC366 movew #2, parity_bytes(%d0)367 bra open_port_2368 369open_port_parity_1:370 cmpl #PARITY_CRC32_PR1_CCITT, STATUS_PARITY(%a0)371 bne open_port_parity_2372 movew #0x0800, SCC_PSMR(%a2) // CRC32-CCITT373 movel #0xDEBB20E3, SCC_C_MASK(%a1)374 movel #0xFFFFFFFF, SCC_C_PRES(%a1)375 movew #HDLC_MAX_MRU + 4, SCC_MFLR(%a1) // 4 bytes for CRC376 movew #4, parity_bytes(%d0)377 bra open_port_2378 379open_port_parity_2:380 cmpl #PARITY_CRC16_PR0_CCITT, STATUS_PARITY(%a0)381 bne open_port_parity_3382 clrw SCC_PSMR(%a2) // CRC16-CCITT preset 0383 movel #0xF0B8, SCC_C_MASK(%a1)384 clrl SCC_C_PRES(%a1)385 movew #HDLC_MAX_MRU + 2, SCC_MFLR(%a1) // 2 bytes for CRC386 movew #2, parity_bytes(%d0)387 bra open_port_2388 389open_port_parity_3:390 cmpl #PARITY_CRC32_PR0_CCITT, STATUS_PARITY(%a0)391 bne open_port_parity_4392 movew #0x0800, SCC_PSMR(%a2) // CRC32-CCITT preset 0393 movel #0xDEBB20E3, SCC_C_MASK(%a1)394 clrl SCC_C_PRES(%a1)395 movew #HDLC_MAX_MRU + 4, SCC_MFLR(%a1) // 4 bytes for CRC396 movew #4, parity_bytes(%d0)397 bra open_port_2398 399open_port_parity_4:400 clrw SCC_PSMR(%a2) // no parity401 movel #0xF0B8, SCC_C_MASK(%a1)402 movel #0xFFFF, SCC_C_PRES(%a1)403 movew #HDLC_MAX_MRU, SCC_MFLR(%a1) // 0 bytes for CRC404 clrw parity_bytes(%d0)405 406open_port_2:407 movel #0x00000003, SCC_GSMR_H(%a2) // RTSM408 cmpl #ENCODING_NRZI, STATUS_ENCODING(%a0)409 bne open_port_nrz410 movel #0x10040900, SCC_GSMR_L(%a2) // NRZI: TCI Tend RECN+TENC=1411 bra open_port_3412 413open_port_nrz:414 movel #0x10040000, SCC_GSMR_L(%a2) // NRZ: TCI Tend RECN+TENC=0415open_port_3:416 movew #BUFFER_LENGTH, SCC_MRBLR(%a1)417 movel %d0, %d1418 lsll #4, %d1 // D1 bits 7 and 6 = port419 orl #1, %d1420 movew %d1, CR // Init SCC RX and TX params421 wait_for_command422 423 // TCI Tend ENR ENT424 movew #0x001F, SCC_SCCM(%a2) // TXE RXF BSY TXB RXB interrupts425 orl #0x00000030, SCC_GSMR_L(%a2) // enable SCC426open_port_ret:427 rts428 429 430/****************************** close port ****************************/431 432close_port: // D0 = 4 * port, D6 = doorbell to host433 movel scc_reg_addr(%d0), %a0 // A0 = SCC_REGS address434 clrw SCC_SCCM(%a0) // no SCC interrupts435 andl #0xFFFFFFCF, SCC_GSMR_L(%a0) // Disable ENT and ENR436 437 andw #~STATUS_CABLE_DTR, csr_output(%d0) // DTR off438 bsr check_csr // call with disabled timer interrupt439 440 movel ch_status_addr(%d0), %d1441 clrl STATUS_OPEN(%d1) // confirm the port is closed442 rts443 444 445/****************************** transmit packet ***********************/446// queue packets for transmission447tx: // D0 = 4 * port, D6 = doorbell to host448 cmpl #TX_BUFFERS, tx_count(%d0)449 beq tx_ret // all DB's = descs in use450 451 movel tx_out(%d0), %d1452 movel %d1, %d2 // D1 = D2 = tx_out BD# = desc#453 mulul #DESC_LENGTH, %d2 // D2 = TX desc offset454 addl ch_status_addr(%d0), %d2455 addl #STATUS_TX_DESCS, %d2 // D2 = TX desc address456 cmpl #PACKET_FULL, (%d2) // desc status457 bne tx_ret458 459// queue it460 movel 4(%d2), %a0 // PCI address461 lsll #3, %d1 // BD is 8-bytes long462 addl tx_first_bd(%d0), %d1 // D1 = current tx_out BD addr463 464 movel 4(%d1), %a1 // A1 = dest address465 movel 8(%d2), %d2 // D2 = length466 movew %d2, 2(%d1) // length into BD467 memcpy_from_pci %a0, %a1, %d2468 bsetl #31, (%d1) // CP go ahead469 470// update tx_out and tx_count471 movel tx_out(%d0), %d1472 addl #1, %d1473 cmpl #TX_BUFFERS, %d1474 bne tx_1475 clrl %d1476tx_1: movel %d1, tx_out(%d0)477 478 addl #1, tx_count(%d0)479 bra tx480 481tx_ret: rts482 483 484/****************************** packet received ***********************/485 486// Service receive buffers // D0 = 4 * port, D6 = doorbell to host487rx: movel rx_in(%d0), %d1 // D1 = rx_in BD#488 lsll #3, %d1 // BD is 8-bytes long489 addl rx_first_bd(%d0), %d1 // D1 = current rx_in BD address490 movew (%d1), %d2 // D2 = RX BD flags491 btstl #15, %d2492 bne rx_ret // BD still empty493 494 btstl #1, %d2495 bne rx_overrun496 497 tstw parity_bytes(%d0)498 bne rx_parity499 bclrl #2, %d2 // do not test for CRC errors500rx_parity:501 andw #0x0CBC, %d2 // mask status bits502 cmpw #0x0C00, %d2 // correct frame503 bne rx_bad_frame504 clrl %d3505 movew 2(%d1), %d3506 subw parity_bytes(%d0), %d3 // D3 = packet length507 cmpw #HDLC_MAX_MRU, %d3508 bgt rx_bad_frame509 510rx_good_frame:511 movel rx_out, %d2512 mulul #DESC_LENGTH, %d2513 addl rx_descs_addr, %d2 // D2 = RX desc address514 cmpl #PACKET_EMPTY, (%d2) // desc stat515 bne rx_overrun516 517 movel %d3, 8(%d2)518 movel 4(%d1), %a0 // A0 = source address519 movel 4(%d2), %a1520 tstl %a1521 beq rx_ignore_data522 memcpy_to_pci %a0, %a1, %d3523rx_ignore_data:524 movel packet_full(%d0), (%d2) // update desc stat525 526// update D6 and rx_out527 bsetl #DOORBELL_FROM_CARD_RX, %d6 // signal host that RX completed528 movel rx_out, %d2529 addl #1, %d2530 cmpl #RX_QUEUE_LENGTH, %d2531 bne rx_1532 clrl %d2533rx_1: movel %d2, rx_out534 535rx_free_bd:536 andw #0xF000, (%d1) // clear CM and error bits537 bsetl #31, (%d1) // free BD538// update rx_in539 movel rx_in(%d0), %d1540 addl #1, %d1541 cmpl #RX_BUFFERS, %d1542 bne rx_2543 clrl %d1544rx_2: movel %d1, rx_in(%d0)545 bra rx546 547rx_overrun:548 movel ch_status_addr(%d0), %d2549 addl #1, STATUS_RX_OVERRUNS(%d2)550 bra rx_free_bd551 552rx_bad_frame:553 movel ch_status_addr(%d0), %d2554 addl #1, STATUS_RX_FRAME_ERRORS(%d2)555 bra rx_free_bd556 557rx_ret: rts558 559 560/****************************** packet transmitted ********************/561 562// Service transmit buffers // D0 = 4 * port, D6 = doorbell to host563tx_end: tstl tx_count(%d0)564 beq tx_end_ret // TX buffers already empty565 566 movel tx_in(%d0), %d1567 movel %d1, %d2 // D1 = D2 = tx_in BD# = desc#568 lsll #3, %d1 // BD is 8-bytes long569 addl tx_first_bd(%d0), %d1 // D1 = current tx_in BD address570 movew (%d1), %d3 // D3 = TX BD flags571 btstl #15, %d3572 bne tx_end_ret // BD still being transmitted573 574// update D6, tx_in and tx_count575 orl bell_tx(%d0), %d6 // signal host that TX desc freed576 subl #1, tx_count(%d0)577 movel tx_in(%d0), %d1578 addl #1, %d1579 cmpl #TX_BUFFERS, %d1580 bne tx_end_1581 clrl %d1582tx_end_1:583 movel %d1, tx_in(%d0)584 585// free host's descriptor586 mulul #DESC_LENGTH, %d2 // D2 = TX desc offset587 addl ch_status_addr(%d0), %d2588 addl #STATUS_TX_DESCS, %d2 // D2 = TX desc address589 btstl #1, %d3590 bne tx_end_underrun591 movel #PACKET_SENT, (%d2)592 bra tx_end593 594tx_end_underrun:595 movel #PACKET_UNDERRUN, (%d2)596 bra tx_end597 598tx_end_ret: rts599 600 601/****************************** PLX PCI9060 DMA memcpy ****************/602 603#if QUICC_MEMCPY_USES_PLX604// called with interrupts disabled605memcpy_from_pci_run:606 movel %d0, -(%sp)607 movew %sr, -(%sp)608memcpy_1:609 movel PLX_DMA_CMD_STS, %d0 // do not btst PLX register directly610 btstl #4, %d0 // transfer done?611 bne memcpy_end612 stop #0x2200 // enable PCI9060 interrupts613 movew #0x2700, %sr // disable interrupts again614 bra memcpy_1615 616memcpy_to_pci_run:617 movel %d0, -(%sp)618 movew %sr, -(%sp)619memcpy_2:620 movel PLX_DMA_CMD_STS, %d0 // do not btst PLX register directly621 btstl #12, %d0 // transfer done?622 bne memcpy_end623 stop #0x2200 // enable PCI9060 interrupts624 movew #0x2700, %sr // disable interrupts again625 bra memcpy_2626 627memcpy_end:628 movew (%sp)+, %sr629 movel (%sp)+, %d0630 rts631#endif632 633 634 635 636 637 638/****************************** PLX PCI9060 interrupt *****************/639 640pci9060_interrupt:641 movel %d0, -(%sp)642 643 movel PLX_DOORBELL_TO_CARD, %d0644 movel %d0, PLX_DOORBELL_TO_CARD // confirm all requests645 orl %d0, channel_stats646 647 movel #0x0909, PLX_DMA_CMD_STS // clear DMA ch #0 and #1 interrupts648 649 movel (%sp)+, %d0650 rte651 652/****************************** SCC interrupts ************************/653 654port_interrupt_1:655 orl #0, SCC1_REGS + SCC_SCCE; // confirm SCC events656 orl #1 << TASK_SCC_0, channel_stats657 movel #0x40000000, CISR658 rte659 660port_interrupt_2:661 orl #0, SCC2_REGS + SCC_SCCE; // confirm SCC events662 orl #1 << TASK_SCC_1, channel_stats663 movel #0x20000000, CISR664 rte665 666port_interrupt_3:667 orl #0, SCC3_REGS + SCC_SCCE; // confirm SCC events668 orl #1 << TASK_SCC_2, channel_stats669 movel #0x10000000, CISR670 rte671 672port_interrupt_4:673 orl #0, SCC4_REGS + SCC_SCCE; // confirm SCC events674 orl #1 << TASK_SCC_3, channel_stats675 movel #0x08000000, CISR676 rte677 678error_interrupt:679 rte680 681 682/****************************** cable and PM routine ******************/683// modified registers: none684check_csr:685 movel %d0, -(%sp)686 movel %d1, -(%sp)687 movel %d2, -(%sp)688 movel %a0, -(%sp)689 movel %a1, -(%sp)690 691 clrl %d0 // D0 = 4 * port692 movel #CSRA, %a0 // A0 = CSR address693 694check_csr_loop:695 movew (%a0), %d1 // D1 = CSR input bits696 andl #0xE7, %d1 // PM and cable sense bits (no DCE bit)697 cmpw #STATUS_CABLE_V35 * (1 + 1 << STATUS_CABLE_PM_SHIFT), %d1698 bne check_csr_1699 movew #0x0E08, %d1700 bra check_csr_valid701 702check_csr_1:703 cmpw #STATUS_CABLE_X21 * (1 + 1 << STATUS_CABLE_PM_SHIFT), %d1704 bne check_csr_2705 movew #0x0408, %d1706 bra check_csr_valid707 708check_csr_2:709 cmpw #STATUS_CABLE_V24 * (1 + 1 << STATUS_CABLE_PM_SHIFT), %d1710 bne check_csr_3711 movew #0x0208, %d1712 bra check_csr_valid713 714check_csr_3:715 cmpw #STATUS_CABLE_EIA530 * (1 + 1 << STATUS_CABLE_PM_SHIFT), %d1716 bne check_csr_disable717 movew #0x0D08, %d1718 bra check_csr_valid719 720check_csr_disable:721 movew #0x0008, %d1 // D1 = disable everything722 movew #0x80E7, %d2 // D2 = input mask: ignore DSR723 bra check_csr_write724 725check_csr_valid: // D1 = mode and IRQ bits726 movew csr_output(%d0), %d2727 andw #0x3000, %d2 // D2 = requested LL and DTR bits728 orw %d2, %d1 // D1 = all requested output bits729 movew #0x80FF, %d2 // D2 = input mask: include DSR730 731check_csr_write:732 cmpw old_csr_output(%d0), %d1733 beq check_csr_input734 movew %d1, old_csr_output(%d0)735 movew %d1, (%a0) // Write CSR output bits736 737check_csr_input:738 movew (PCDAT), %d1739 andw dcd_mask(%d0), %d1740 beq check_csr_dcd_on // DCD and CTS signals are negated741 movew (%a0), %d1 // D1 = CSR input bits742 andw #~STATUS_CABLE_DCD, %d1 // DCD off743 bra check_csr_previous744 745check_csr_dcd_on:746 movew (%a0), %d1 // D1 = CSR input bits747 orw #STATUS_CABLE_DCD, %d1 // DCD on748check_csr_previous:749 andw %d2, %d1 // input mask750 movel ch_status_addr(%d0), %a1751 cmpl STATUS_CABLE(%a1), %d1 // check for change752 beq check_csr_next753 movel %d1, STATUS_CABLE(%a1) // update status754 movel bell_cable(%d0), PLX_DOORBELL_FROM_CARD // signal the host755 756check_csr_next:757 addl #2, %a0 // next CSR register758 addl #4, %d0 // D0 = 4 * next port759 cmpl #4 * 4, %d0760 bne check_csr_loop761 762 movel (%sp)+, %a1763 movel (%sp)+, %a0764 movel (%sp)+, %d2765 movel (%sp)+, %d1766 movel (%sp)+, %d0767 rts768 769 770/****************************** timer interrupt ***********************/771 772timer_interrupt:773 bsr check_csr774 rte775 776 777/****************************** RAM sizing and test *******************/778#if DETECT_RAM779ram_test:780 movel #0x12345678, %d1 // D1 = test value781 movel %d1, (128 * 1024 - 4)782 movel #128 * 1024, %d0 // D0 = RAM size tested783ram_test_size:784 cmpl #MAX_RAM_SIZE, %d0785 beq ram_test_size_found786 movel %d0, %a0787 addl #128 * 1024 - 4, %a0788 cmpl (%a0), %d1789 beq ram_test_size_check790ram_test_next_size:791 lsll #1, %d0792 bra ram_test_size793 794ram_test_size_check:795 eorl #0xFFFFFFFF, %d1796 movel %d1, (128 * 1024 - 4)797 cmpl (%a0), %d1798 bne ram_test_next_size799 800ram_test_size_found: // D0 = RAM size801 movel %d0, %a0 // A0 = fill ptr802 subl #firmware_end + 4, %d0803 lsrl #2, %d0804 movel %d0, %d1 // D1 = DBf counter805ram_test_fill:806 movel %a0, -(%a0)807 dbfw %d1, ram_test_fill808 subl #0x10000, %d1809 cmpl #0xFFFFFFFF, %d1810 bne ram_test_fill811 812ram_test_loop: // D0 = DBf counter813 cmpl (%a0)+, %a0814 dbnew %d0, ram_test_loop815 bne ram_test_found_bad816 subl #0x10000, %d0817 cmpl #0xFFFFFFFF, %d0818 bne ram_test_loop819 bra ram_test_all_ok820 821ram_test_found_bad:822 subl #4, %a0823ram_test_all_ok:824 movel %a0, PLX_MAILBOX_5825 rts826#endif827 828 829/****************************** constants *****************************/830 831scc_reg_addr:832 .long SCC1_REGS, SCC2_REGS, SCC3_REGS, SCC4_REGS833scc_base_addr:834 .long SCC1_BASE, SCC2_BASE, SCC3_BASE, SCC4_BASE835 836tx_first_bd:837 .long DPRBASE838 .long DPRBASE + (TX_BUFFERS + RX_BUFFERS) * 8839 .long DPRBASE + (TX_BUFFERS + RX_BUFFERS) * 8 * 2840 .long DPRBASE + (TX_BUFFERS + RX_BUFFERS) * 8 * 3841 842rx_first_bd:843 .long DPRBASE + TX_BUFFERS * 8844 .long DPRBASE + TX_BUFFERS * 8 + (TX_BUFFERS + RX_BUFFERS) * 8845 .long DPRBASE + TX_BUFFERS * 8 + (TX_BUFFERS + RX_BUFFERS) * 8 * 2846 .long DPRBASE + TX_BUFFERS * 8 + (TX_BUFFERS + RX_BUFFERS) * 8 * 3847 848first_buffer:849 .long BUFFERS_ADDR850 .long BUFFERS_ADDR + (TX_BUFFERS + RX_BUFFERS) * BUFFER_LENGTH851 .long BUFFERS_ADDR + (TX_BUFFERS + RX_BUFFERS) * BUFFER_LENGTH * 2852 .long BUFFERS_ADDR + (TX_BUFFERS + RX_BUFFERS) * BUFFER_LENGTH * 3853 854bell_tx:855 .long 1 << DOORBELL_FROM_CARD_TX_0, 1 << DOORBELL_FROM_CARD_TX_1856 .long 1 << DOORBELL_FROM_CARD_TX_2, 1 << DOORBELL_FROM_CARD_TX_3857 858bell_cable:859 .long 1 << DOORBELL_FROM_CARD_CABLE_0, 1 << DOORBELL_FROM_CARD_CABLE_1860 .long 1 << DOORBELL_FROM_CARD_CABLE_2, 1 << DOORBELL_FROM_CARD_CABLE_3861 862packet_full:863 .long PACKET_FULL, PACKET_FULL + 1, PACKET_FULL + 2, PACKET_FULL + 3864 865clocking_ext:866 .long 0x0000002C, 0x00003E00, 0x002C0000, 0x3E000000867clocking_txfromrx:868 .long 0x0000002D, 0x00003F00, 0x002D0000, 0x3F000000869clocking_mask:870 .long 0x000000FF, 0x0000FF00, 0x00FF0000, 0xFF000000871dcd_mask:872 .word 0x020, 0, 0x080, 0, 0x200, 0, 0x800873 874 .ascii "wanXL firmware\n"875 .asciz "Copyright (C) 2003 Krzysztof Halasa <khc@pm.waw.pl>\n"876 877 878/****************************** variables *****************************/879 880 .align 4881channel_stats: .long 0882 883tx_in: .long 0, 0, 0, 0 // transmitted884tx_out: .long 0, 0, 0, 0 // received from host for transmission885tx_count: .long 0, 0, 0, 0 // currently in transmit queue886 887rx_in: .long 0, 0, 0, 0 // received from port888rx_out: .long 0 // transmitted to host889parity_bytes: .word 0, 0, 0, 0, 0, 0, 0 // only 4 words are used890 891csr_output: .word 0892old_csr_output: .word 0, 0, 0, 0, 0, 0, 0893 .align 4894firmware_end: // must be dword-aligned895