1157 lines · c
1// SPDX-License-Identifier: ISC2/*3 * Copyright (c) 2014-2017 Qualcomm Atheros, Inc.4 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.5 */6 7#include <linux/types.h>8#include <linux/bitops.h>9#include <linux/bitfield.h>10#include "core.h"11#include "hw.h"12#include "hif.h"13#include "wmi-ops.h"14#include "bmi.h"15#include "rx_desc.h"16 17const struct ath10k_hw_regs qca988x_regs = {18 .rtc_soc_base_address = 0x00004000,19 .rtc_wmac_base_address = 0x00005000,20 .soc_core_base_address = 0x00009000,21 .wlan_mac_base_address = 0x00020000,22 .ce_wrapper_base_address = 0x00057000,23 .ce0_base_address = 0x00057400,24 .ce1_base_address = 0x00057800,25 .ce2_base_address = 0x00057c00,26 .ce3_base_address = 0x00058000,27 .ce4_base_address = 0x00058400,28 .ce5_base_address = 0x00058800,29 .ce6_base_address = 0x00058c00,30 .ce7_base_address = 0x00059000,31 .soc_reset_control_si0_rst_mask = 0x00000001,32 .soc_reset_control_ce_rst_mask = 0x00040000,33 .soc_chip_id_address = 0x000000ec,34 .scratch_3_address = 0x00000030,35 .fw_indicator_address = 0x00009030,36 .pcie_local_base_address = 0x00080000,37 .ce_wrap_intr_sum_host_msi_lsb = 0x00000008,38 .ce_wrap_intr_sum_host_msi_mask = 0x0000ff00,39 .pcie_intr_fw_mask = 0x00000400,40 .pcie_intr_ce_mask_all = 0x0007f800,41 .pcie_intr_clr_address = 0x00000014,42};43 44const struct ath10k_hw_regs qca6174_regs = {45 .rtc_soc_base_address = 0x00000800,46 .rtc_wmac_base_address = 0x00001000,47 .soc_core_base_address = 0x0003a000,48 .wlan_mac_base_address = 0x00010000,49 .ce_wrapper_base_address = 0x00034000,50 .ce0_base_address = 0x00034400,51 .ce1_base_address = 0x00034800,52 .ce2_base_address = 0x00034c00,53 .ce3_base_address = 0x00035000,54 .ce4_base_address = 0x00035400,55 .ce5_base_address = 0x00035800,56 .ce6_base_address = 0x00035c00,57 .ce7_base_address = 0x00036000,58 .soc_reset_control_si0_rst_mask = 0x00000000,59 .soc_reset_control_ce_rst_mask = 0x00000001,60 .soc_chip_id_address = 0x000000f0,61 .scratch_3_address = 0x00000028,62 .fw_indicator_address = 0x0003a028,63 .pcie_local_base_address = 0x00080000,64 .ce_wrap_intr_sum_host_msi_lsb = 0x00000008,65 .ce_wrap_intr_sum_host_msi_mask = 0x0000ff00,66 .pcie_intr_fw_mask = 0x00000400,67 .pcie_intr_ce_mask_all = 0x0007f800,68 .pcie_intr_clr_address = 0x00000014,69 .cpu_pll_init_address = 0x00404020,70 .cpu_speed_address = 0x00404024,71 .core_clk_div_address = 0x00404028,72};73 74const struct ath10k_hw_regs qca99x0_regs = {75 .rtc_soc_base_address = 0x00080000,76 .rtc_wmac_base_address = 0x00000000,77 .soc_core_base_address = 0x00082000,78 .wlan_mac_base_address = 0x00030000,79 .ce_wrapper_base_address = 0x0004d000,80 .ce0_base_address = 0x0004a000,81 .ce1_base_address = 0x0004a400,82 .ce2_base_address = 0x0004a800,83 .ce3_base_address = 0x0004ac00,84 .ce4_base_address = 0x0004b000,85 .ce5_base_address = 0x0004b400,86 .ce6_base_address = 0x0004b800,87 .ce7_base_address = 0x0004bc00,88 /* Note: qca99x0 supports up to 12 Copy Engines. Other than address of89 * CE0 and CE1 no other copy engine is directly referred in the code.90 * It is not really necessary to assign address for newly supported91 * CEs in this address table.92 * Copy Engine Address93 * CE8 0x0004c00094 * CE9 0x0004c40095 * CE10 0x0004c80096 * CE11 0x0004cc0097 */98 .soc_reset_control_si0_rst_mask = 0x00000001,99 .soc_reset_control_ce_rst_mask = 0x00000100,100 .soc_chip_id_address = 0x000000ec,101 .scratch_3_address = 0x00040050,102 .fw_indicator_address = 0x00040050,103 .pcie_local_base_address = 0x00000000,104 .ce_wrap_intr_sum_host_msi_lsb = 0x0000000c,105 .ce_wrap_intr_sum_host_msi_mask = 0x00fff000,106 .pcie_intr_fw_mask = 0x00100000,107 .pcie_intr_ce_mask_all = 0x000fff00,108 .pcie_intr_clr_address = 0x00000010,109};110 111const struct ath10k_hw_regs qca4019_regs = {112 .rtc_soc_base_address = 0x00080000,113 .soc_core_base_address = 0x00082000,114 .wlan_mac_base_address = 0x00030000,115 .ce_wrapper_base_address = 0x0004d000,116 .ce0_base_address = 0x0004a000,117 .ce1_base_address = 0x0004a400,118 .ce2_base_address = 0x0004a800,119 .ce3_base_address = 0x0004ac00,120 .ce4_base_address = 0x0004b000,121 .ce5_base_address = 0x0004b400,122 .ce6_base_address = 0x0004b800,123 .ce7_base_address = 0x0004bc00,124 /* qca4019 supports up to 12 copy engines. Since base address125 * of ce8 to ce11 are not directly referred in the code,126 * no need have them in separate members in this table.127 * Copy Engine Address128 * CE8 0x0004c000129 * CE9 0x0004c400130 * CE10 0x0004c800131 * CE11 0x0004cc00132 */133 .soc_reset_control_si0_rst_mask = 0x00000001,134 .soc_reset_control_ce_rst_mask = 0x00000100,135 .soc_chip_id_address = 0x000000ec,136 .fw_indicator_address = 0x0004f00c,137 .ce_wrap_intr_sum_host_msi_lsb = 0x0000000c,138 .ce_wrap_intr_sum_host_msi_mask = 0x00fff000,139 .pcie_intr_fw_mask = 0x00100000,140 .pcie_intr_ce_mask_all = 0x000fff00,141 .pcie_intr_clr_address = 0x00000010,142};143 144const struct ath10k_hw_values qca988x_values = {145 .rtc_state_val_on = 3,146 .ce_count = 8,147 .msi_assign_ce_max = 7,148 .num_target_ce_config_wlan = 7,149 .ce_desc_meta_data_mask = 0xFFFC,150 .ce_desc_meta_data_lsb = 2,151};152 153const struct ath10k_hw_values qca6174_values = {154 .rtc_state_val_on = 3,155 .ce_count = 8,156 .msi_assign_ce_max = 7,157 .num_target_ce_config_wlan = 7,158 .ce_desc_meta_data_mask = 0xFFFC,159 .ce_desc_meta_data_lsb = 2,160 .rfkill_pin = 16,161 .rfkill_cfg = 0,162 .rfkill_on_level = 1,163};164 165const struct ath10k_hw_values qca99x0_values = {166 .rtc_state_val_on = 7,167 .ce_count = 12,168 .msi_assign_ce_max = 12,169 .num_target_ce_config_wlan = 10,170 .ce_desc_meta_data_mask = 0xFFF0,171 .ce_desc_meta_data_lsb = 4,172};173 174const struct ath10k_hw_values qca9888_values = {175 .rtc_state_val_on = 3,176 .ce_count = 12,177 .msi_assign_ce_max = 12,178 .num_target_ce_config_wlan = 10,179 .ce_desc_meta_data_mask = 0xFFF0,180 .ce_desc_meta_data_lsb = 4,181};182 183const struct ath10k_hw_values qca4019_values = {184 .ce_count = 12,185 .num_target_ce_config_wlan = 10,186 .ce_desc_meta_data_mask = 0xFFF0,187 .ce_desc_meta_data_lsb = 4,188};189 190const struct ath10k_hw_regs wcn3990_regs = {191 .rtc_soc_base_address = 0x00000000,192 .rtc_wmac_base_address = 0x00000000,193 .soc_core_base_address = 0x00000000,194 .ce_wrapper_base_address = 0x0024C000,195 .ce0_base_address = 0x00240000,196 .ce1_base_address = 0x00241000,197 .ce2_base_address = 0x00242000,198 .ce3_base_address = 0x00243000,199 .ce4_base_address = 0x00244000,200 .ce5_base_address = 0x00245000,201 .ce6_base_address = 0x00246000,202 .ce7_base_address = 0x00247000,203 .ce8_base_address = 0x00248000,204 .ce9_base_address = 0x00249000,205 .ce10_base_address = 0x0024A000,206 .ce11_base_address = 0x0024B000,207 .soc_chip_id_address = 0x000000f0,208 .soc_reset_control_si0_rst_mask = 0x00000001,209 .soc_reset_control_ce_rst_mask = 0x00000100,210 .ce_wrap_intr_sum_host_msi_lsb = 0x0000000c,211 .ce_wrap_intr_sum_host_msi_mask = 0x00fff000,212 .pcie_intr_fw_mask = 0x00100000,213};214 215static struct ath10k_hw_ce_regs_addr_map wcn3990_src_ring = {216 .msb = 0x00000010,217 .lsb = 0x00000010,218 .mask = GENMASK(17, 17),219};220 221static struct ath10k_hw_ce_regs_addr_map wcn3990_dst_ring = {222 .msb = 0x00000012,223 .lsb = 0x00000012,224 .mask = GENMASK(18, 18),225};226 227static struct ath10k_hw_ce_regs_addr_map wcn3990_dmax = {228 .msb = 0x00000000,229 .lsb = 0x00000000,230 .mask = GENMASK(15, 0),231};232 233static struct ath10k_hw_ce_ctrl1 wcn3990_ctrl1 = {234 .addr = 0x00000018,235 .src_ring = &wcn3990_src_ring,236 .dst_ring = &wcn3990_dst_ring,237 .dmax = &wcn3990_dmax,238};239 240static struct ath10k_hw_ce_regs_addr_map wcn3990_host_ie_cc = {241 .mask = GENMASK(0, 0),242};243 244static struct ath10k_hw_ce_host_ie wcn3990_host_ie = {245 .copy_complete = &wcn3990_host_ie_cc,246};247 248static struct ath10k_hw_ce_host_wm_regs wcn3990_wm_reg = {249 .dstr_lmask = 0x00000010,250 .dstr_hmask = 0x00000008,251 .srcr_lmask = 0x00000004,252 .srcr_hmask = 0x00000002,253 .cc_mask = 0x00000001,254 .wm_mask = 0x0000001E,255 .addr = 0x00000030,256};257 258static struct ath10k_hw_ce_misc_regs wcn3990_misc_reg = {259 .axi_err = 0x00000100,260 .dstr_add_err = 0x00000200,261 .srcr_len_err = 0x00000100,262 .dstr_mlen_vio = 0x00000080,263 .dstr_overflow = 0x00000040,264 .srcr_overflow = 0x00000020,265 .err_mask = 0x000003E0,266 .addr = 0x00000038,267};268 269static struct ath10k_hw_ce_regs_addr_map wcn3990_src_wm_low = {270 .msb = 0x00000000,271 .lsb = 0x00000010,272 .mask = GENMASK(31, 16),273};274 275static struct ath10k_hw_ce_regs_addr_map wcn3990_src_wm_high = {276 .msb = 0x0000000f,277 .lsb = 0x00000000,278 .mask = GENMASK(15, 0),279};280 281static struct ath10k_hw_ce_dst_src_wm_regs wcn3990_wm_src_ring = {282 .addr = 0x0000004c,283 .low_rst = 0x00000000,284 .high_rst = 0x00000000,285 .wm_low = &wcn3990_src_wm_low,286 .wm_high = &wcn3990_src_wm_high,287};288 289static struct ath10k_hw_ce_regs_addr_map wcn3990_dst_wm_low = {290 .lsb = 0x00000010,291 .mask = GENMASK(31, 16),292};293 294static struct ath10k_hw_ce_regs_addr_map wcn3990_dst_wm_high = {295 .msb = 0x0000000f,296 .lsb = 0x00000000,297 .mask = GENMASK(15, 0),298};299 300static struct ath10k_hw_ce_dst_src_wm_regs wcn3990_wm_dst_ring = {301 .addr = 0x00000050,302 .low_rst = 0x00000000,303 .high_rst = 0x00000000,304 .wm_low = &wcn3990_dst_wm_low,305 .wm_high = &wcn3990_dst_wm_high,306};307 308static struct ath10k_hw_ce_ctrl1_upd wcn3990_ctrl1_upd = {309 .shift = 19,310 .mask = 0x00080000,311 .enable = 0x00000000,312};313 314const struct ath10k_hw_ce_regs wcn3990_ce_regs = {315 .sr_base_addr_lo = 0x00000000,316 .sr_base_addr_hi = 0x00000004,317 .sr_size_addr = 0x00000008,318 .dr_base_addr_lo = 0x0000000c,319 .dr_base_addr_hi = 0x00000010,320 .dr_size_addr = 0x00000014,321 .misc_ie_addr = 0x00000034,322 .sr_wr_index_addr = 0x0000003c,323 .dst_wr_index_addr = 0x00000040,324 .current_srri_addr = 0x00000044,325 .current_drri_addr = 0x00000048,326 .ce_rri_low = 0x0024C004,327 .ce_rri_high = 0x0024C008,328 .host_ie_addr = 0x0000002c,329 .ctrl1_regs = &wcn3990_ctrl1,330 .host_ie = &wcn3990_host_ie,331 .wm_regs = &wcn3990_wm_reg,332 .misc_regs = &wcn3990_misc_reg,333 .wm_srcr = &wcn3990_wm_src_ring,334 .wm_dstr = &wcn3990_wm_dst_ring,335 .upd = &wcn3990_ctrl1_upd,336};337 338const struct ath10k_hw_values wcn3990_values = {339 .rtc_state_val_on = 5,340 .ce_count = 12,341 .msi_assign_ce_max = 12,342 .num_target_ce_config_wlan = 12,343 .ce_desc_meta_data_mask = 0xFFF0,344 .ce_desc_meta_data_lsb = 4,345};346 347static struct ath10k_hw_ce_regs_addr_map qcax_src_ring = {348 .msb = 0x00000010,349 .lsb = 0x00000010,350 .mask = GENMASK(16, 16),351};352 353static struct ath10k_hw_ce_regs_addr_map qcax_dst_ring = {354 .msb = 0x00000011,355 .lsb = 0x00000011,356 .mask = GENMASK(17, 17),357};358 359static struct ath10k_hw_ce_regs_addr_map qcax_dmax = {360 .msb = 0x0000000f,361 .lsb = 0x00000000,362 .mask = GENMASK(15, 0),363};364 365static struct ath10k_hw_ce_ctrl1 qcax_ctrl1 = {366 .addr = 0x00000010,367 .hw_mask = 0x0007ffff,368 .sw_mask = 0x0007ffff,369 .hw_wr_mask = 0x00000000,370 .sw_wr_mask = 0x0007ffff,371 .reset_mask = 0xffffffff,372 .reset = 0x00000080,373 .src_ring = &qcax_src_ring,374 .dst_ring = &qcax_dst_ring,375 .dmax = &qcax_dmax,376};377 378static struct ath10k_hw_ce_regs_addr_map qcax_cmd_halt_status = {379 .msb = 0x00000003,380 .lsb = 0x00000003,381 .mask = GENMASK(3, 3),382};383 384static struct ath10k_hw_ce_cmd_halt qcax_cmd_halt = {385 .msb = 0x00000000,386 .mask = GENMASK(0, 0),387 .status_reset = 0x00000000,388 .status = &qcax_cmd_halt_status,389};390 391static struct ath10k_hw_ce_regs_addr_map qcax_host_ie_cc = {392 .msb = 0x00000000,393 .lsb = 0x00000000,394 .mask = GENMASK(0, 0),395};396 397static struct ath10k_hw_ce_host_ie qcax_host_ie = {398 .copy_complete_reset = 0x00000000,399 .copy_complete = &qcax_host_ie_cc,400};401 402static struct ath10k_hw_ce_host_wm_regs qcax_wm_reg = {403 .dstr_lmask = 0x00000010,404 .dstr_hmask = 0x00000008,405 .srcr_lmask = 0x00000004,406 .srcr_hmask = 0x00000002,407 .cc_mask = 0x00000001,408 .wm_mask = 0x0000001E,409 .addr = 0x00000030,410};411 412static struct ath10k_hw_ce_misc_regs qcax_misc_reg = {413 .axi_err = 0x00000400,414 .dstr_add_err = 0x00000200,415 .srcr_len_err = 0x00000100,416 .dstr_mlen_vio = 0x00000080,417 .dstr_overflow = 0x00000040,418 .srcr_overflow = 0x00000020,419 .err_mask = 0x000007E0,420 .addr = 0x00000038,421};422 423static struct ath10k_hw_ce_regs_addr_map qcax_src_wm_low = {424 .msb = 0x0000001f,425 .lsb = 0x00000010,426 .mask = GENMASK(31, 16),427};428 429static struct ath10k_hw_ce_regs_addr_map qcax_src_wm_high = {430 .msb = 0x0000000f,431 .lsb = 0x00000000,432 .mask = GENMASK(15, 0),433};434 435static struct ath10k_hw_ce_dst_src_wm_regs qcax_wm_src_ring = {436 .addr = 0x0000004c,437 .low_rst = 0x00000000,438 .high_rst = 0x00000000,439 .wm_low = &qcax_src_wm_low,440 .wm_high = &qcax_src_wm_high,441};442 443static struct ath10k_hw_ce_regs_addr_map qcax_dst_wm_low = {444 .lsb = 0x00000010,445 .mask = GENMASK(31, 16),446};447 448static struct ath10k_hw_ce_regs_addr_map qcax_dst_wm_high = {449 .msb = 0x0000000f,450 .lsb = 0x00000000,451 .mask = GENMASK(15, 0),452};453 454static struct ath10k_hw_ce_dst_src_wm_regs qcax_wm_dst_ring = {455 .addr = 0x00000050,456 .low_rst = 0x00000000,457 .high_rst = 0x00000000,458 .wm_low = &qcax_dst_wm_low,459 .wm_high = &qcax_dst_wm_high,460};461 462const struct ath10k_hw_ce_regs qcax_ce_regs = {463 .sr_base_addr_lo = 0x00000000,464 .sr_size_addr = 0x00000004,465 .dr_base_addr_lo = 0x00000008,466 .dr_size_addr = 0x0000000c,467 .ce_cmd_addr = 0x00000018,468 .misc_ie_addr = 0x00000034,469 .sr_wr_index_addr = 0x0000003c,470 .dst_wr_index_addr = 0x00000040,471 .current_srri_addr = 0x00000044,472 .current_drri_addr = 0x00000048,473 .host_ie_addr = 0x0000002c,474 .ctrl1_regs = &qcax_ctrl1,475 .cmd_halt = &qcax_cmd_halt,476 .host_ie = &qcax_host_ie,477 .wm_regs = &qcax_wm_reg,478 .misc_regs = &qcax_misc_reg,479 .wm_srcr = &qcax_wm_src_ring,480 .wm_dstr = &qcax_wm_dst_ring,481};482 483const struct ath10k_hw_clk_params qca6174_clk[ATH10K_HW_REFCLK_COUNT] = {484 {485 .refclk = 48000000,486 .div = 0xe,487 .rnfrac = 0x2aaa8,488 .settle_time = 2400,489 .refdiv = 0,490 .outdiv = 1,491 },492 {493 .refclk = 19200000,494 .div = 0x24,495 .rnfrac = 0x2aaa8,496 .settle_time = 960,497 .refdiv = 0,498 .outdiv = 1,499 },500 {501 .refclk = 24000000,502 .div = 0x1d,503 .rnfrac = 0x15551,504 .settle_time = 1200,505 .refdiv = 0,506 .outdiv = 1,507 },508 {509 .refclk = 26000000,510 .div = 0x1b,511 .rnfrac = 0x4ec4,512 .settle_time = 1300,513 .refdiv = 0,514 .outdiv = 1,515 },516 {517 .refclk = 37400000,518 .div = 0x12,519 .rnfrac = 0x34b49,520 .settle_time = 1870,521 .refdiv = 0,522 .outdiv = 1,523 },524 {525 .refclk = 38400000,526 .div = 0x12,527 .rnfrac = 0x15551,528 .settle_time = 1920,529 .refdiv = 0,530 .outdiv = 1,531 },532 {533 .refclk = 40000000,534 .div = 0x12,535 .rnfrac = 0x26665,536 .settle_time = 2000,537 .refdiv = 0,538 .outdiv = 1,539 },540 {541 .refclk = 52000000,542 .div = 0x1b,543 .rnfrac = 0x4ec4,544 .settle_time = 2600,545 .refdiv = 0,546 .outdiv = 1,547 },548};549 550void ath10k_hw_fill_survey_time(struct ath10k *ar, struct survey_info *survey,551 u32 cc, u32 rcc, u32 cc_prev, u32 rcc_prev)552{553 u32 cc_fix = 0;554 u32 rcc_fix = 0;555 enum ath10k_hw_cc_wraparound_type wraparound_type;556 557 survey->filled |= SURVEY_INFO_TIME |558 SURVEY_INFO_TIME_BUSY;559 560 wraparound_type = ar->hw_params.cc_wraparound_type;561 562 if (cc < cc_prev || rcc < rcc_prev) {563 switch (wraparound_type) {564 case ATH10K_HW_CC_WRAP_SHIFTED_ALL:565 if (cc < cc_prev) {566 cc_fix = 0x7fffffff;567 survey->filled &= ~SURVEY_INFO_TIME_BUSY;568 }569 break;570 case ATH10K_HW_CC_WRAP_SHIFTED_EACH:571 if (cc < cc_prev)572 cc_fix = 0x7fffffff;573 574 if (rcc < rcc_prev)575 rcc_fix = 0x7fffffff;576 break;577 case ATH10K_HW_CC_WRAP_DISABLED:578 break;579 }580 }581 582 cc -= cc_prev - cc_fix;583 rcc -= rcc_prev - rcc_fix;584 585 survey->time = CCNT_TO_MSEC(ar, cc);586 survey->time_busy = CCNT_TO_MSEC(ar, rcc);587}588 589/* The firmware does not support setting the coverage class. Instead this590 * function monitors and modifies the corresponding MAC registers.591 */592static void ath10k_hw_qca988x_set_coverage_class(struct ath10k *ar,593 s16 value)594{595 u32 slottime_reg;596 u32 slottime;597 u32 timeout_reg;598 u32 ack_timeout;599 u32 cts_timeout;600 u32 phyclk_reg;601 u32 phyclk;602 u64 fw_dbglog_mask;603 u32 fw_dbglog_level;604 605 mutex_lock(&ar->conf_mutex);606 607 /* Only modify registers if the core is started. */608 if ((ar->state != ATH10K_STATE_ON) &&609 (ar->state != ATH10K_STATE_RESTARTED)) {610 spin_lock_bh(&ar->data_lock);611 /* Store config value for when radio boots up */612 ar->fw_coverage.coverage_class = value;613 spin_unlock_bh(&ar->data_lock);614 goto unlock;615 }616 617 /* Retrieve the current values of the two registers that need to be618 * adjusted.619 */620 slottime_reg = ath10k_hif_read32(ar, WLAN_MAC_BASE_ADDRESS +621 WAVE1_PCU_GBL_IFS_SLOT);622 timeout_reg = ath10k_hif_read32(ar, WLAN_MAC_BASE_ADDRESS +623 WAVE1_PCU_ACK_CTS_TIMEOUT);624 phyclk_reg = ath10k_hif_read32(ar, WLAN_MAC_BASE_ADDRESS +625 WAVE1_PHYCLK);626 phyclk = MS(phyclk_reg, WAVE1_PHYCLK_USEC) + 1;627 628 if (value < 0)629 value = ar->fw_coverage.coverage_class;630 631 /* Break out if the coverage class and registers have the expected632 * value.633 */634 if (value == ar->fw_coverage.coverage_class &&635 slottime_reg == ar->fw_coverage.reg_slottime_conf &&636 timeout_reg == ar->fw_coverage.reg_ack_cts_timeout_conf &&637 phyclk_reg == ar->fw_coverage.reg_phyclk)638 goto unlock;639 640 /* Store new initial register values from the firmware. */641 if (slottime_reg != ar->fw_coverage.reg_slottime_conf)642 ar->fw_coverage.reg_slottime_orig = slottime_reg;643 if (timeout_reg != ar->fw_coverage.reg_ack_cts_timeout_conf)644 ar->fw_coverage.reg_ack_cts_timeout_orig = timeout_reg;645 ar->fw_coverage.reg_phyclk = phyclk_reg;646 647 /* Calculate new value based on the (original) firmware calculation. */648 slottime_reg = ar->fw_coverage.reg_slottime_orig;649 timeout_reg = ar->fw_coverage.reg_ack_cts_timeout_orig;650 651 /* Do some sanity checks on the slottime register. */652 if (slottime_reg % phyclk) {653 ath10k_warn(ar,654 "failed to set coverage class: expected integer microsecond value in register\n");655 656 goto store_regs;657 }658 659 slottime = MS(slottime_reg, WAVE1_PCU_GBL_IFS_SLOT);660 slottime = slottime / phyclk;661 if (slottime != 9 && slottime != 20) {662 ath10k_warn(ar,663 "failed to set coverage class: expected slot time of 9 or 20us in HW register. It is %uus.\n",664 slottime);665 666 goto store_regs;667 }668 669 /* Recalculate the register values by adding the additional propagation670 * delay (3us per coverage class).671 */672 673 slottime = MS(slottime_reg, WAVE1_PCU_GBL_IFS_SLOT);674 slottime += value * 3 * phyclk;675 slottime = min_t(u32, slottime, WAVE1_PCU_GBL_IFS_SLOT_MAX);676 slottime = SM(slottime, WAVE1_PCU_GBL_IFS_SLOT);677 slottime_reg = (slottime_reg & ~WAVE1_PCU_GBL_IFS_SLOT_MASK) | slottime;678 679 /* Update ack timeout (lower halfword). */680 ack_timeout = MS(timeout_reg, WAVE1_PCU_ACK_CTS_TIMEOUT_ACK);681 ack_timeout += 3 * value * phyclk;682 ack_timeout = min_t(u32, ack_timeout, WAVE1_PCU_ACK_CTS_TIMEOUT_MAX);683 ack_timeout = SM(ack_timeout, WAVE1_PCU_ACK_CTS_TIMEOUT_ACK);684 685 /* Update cts timeout (upper halfword). */686 cts_timeout = MS(timeout_reg, WAVE1_PCU_ACK_CTS_TIMEOUT_CTS);687 cts_timeout += 3 * value * phyclk;688 cts_timeout = min_t(u32, cts_timeout, WAVE1_PCU_ACK_CTS_TIMEOUT_MAX);689 cts_timeout = SM(cts_timeout, WAVE1_PCU_ACK_CTS_TIMEOUT_CTS);690 691 timeout_reg = ack_timeout | cts_timeout;692 693 ath10k_hif_write32(ar,694 WLAN_MAC_BASE_ADDRESS + WAVE1_PCU_GBL_IFS_SLOT,695 slottime_reg);696 ath10k_hif_write32(ar,697 WLAN_MAC_BASE_ADDRESS + WAVE1_PCU_ACK_CTS_TIMEOUT,698 timeout_reg);699 700 /* Ensure we have a debug level of WARN set for the case that the701 * coverage class is larger than 0. This is important as we need to702 * set the registers again if the firmware does an internal reset and703 * this way we will be notified of the event.704 */705 fw_dbglog_mask = ath10k_debug_get_fw_dbglog_mask(ar);706 fw_dbglog_level = ath10k_debug_get_fw_dbglog_level(ar);707 708 if (value > 0) {709 if (fw_dbglog_level > ATH10K_DBGLOG_LEVEL_WARN)710 fw_dbglog_level = ATH10K_DBGLOG_LEVEL_WARN;711 fw_dbglog_mask = ~0;712 }713 714 ath10k_wmi_dbglog_cfg(ar, fw_dbglog_mask, fw_dbglog_level);715 716store_regs:717 /* After an error we will not retry setting the coverage class. */718 spin_lock_bh(&ar->data_lock);719 ar->fw_coverage.coverage_class = value;720 spin_unlock_bh(&ar->data_lock);721 722 ar->fw_coverage.reg_slottime_conf = slottime_reg;723 ar->fw_coverage.reg_ack_cts_timeout_conf = timeout_reg;724 725unlock:726 mutex_unlock(&ar->conf_mutex);727}728 729/**730 * ath10k_hw_qca6174_enable_pll_clock() - enable the qca6174 hw pll clock731 * @ar: the ath10k blob732 *733 * This function is very hardware specific, the clock initialization734 * steps is very sensitive and could lead to unknown crash, so they735 * should be done in sequence.736 *737 * *** Be aware if you planned to refactor them. ***738 *739 * Return: 0 if successfully enable the pll, otherwise EINVAL740 */741static int ath10k_hw_qca6174_enable_pll_clock(struct ath10k *ar)742{743 int ret, wait_limit;744 u32 clk_div_addr, pll_init_addr, speed_addr;745 u32 addr, reg_val, mem_val;746 struct ath10k_hw_params *hw;747 const struct ath10k_hw_clk_params *hw_clk;748 749 hw = &ar->hw_params;750 751 if (ar->regs->core_clk_div_address == 0 ||752 ar->regs->cpu_pll_init_address == 0 ||753 ar->regs->cpu_speed_address == 0)754 return -EINVAL;755 756 clk_div_addr = ar->regs->core_clk_div_address;757 pll_init_addr = ar->regs->cpu_pll_init_address;758 speed_addr = ar->regs->cpu_speed_address;759 760 /* Read efuse register to find out the right hw clock configuration */761 addr = (RTC_SOC_BASE_ADDRESS | EFUSE_OFFSET);762 ret = ath10k_bmi_read_soc_reg(ar, addr, ®_val);763 if (ret)764 return -EINVAL;765 766 /* sanitize if the hw refclk index is out of the boundary */767 if (MS(reg_val, EFUSE_XTAL_SEL) > ATH10K_HW_REFCLK_COUNT)768 return -EINVAL;769 770 hw_clk = &hw->hw_clk[MS(reg_val, EFUSE_XTAL_SEL)];771 772 /* Set the rnfrac and outdiv params to bb_pll register */773 addr = (RTC_SOC_BASE_ADDRESS | BB_PLL_CONFIG_OFFSET);774 ret = ath10k_bmi_read_soc_reg(ar, addr, ®_val);775 if (ret)776 return -EINVAL;777 778 reg_val &= ~(BB_PLL_CONFIG_FRAC_MASK | BB_PLL_CONFIG_OUTDIV_MASK);779 reg_val |= (SM(hw_clk->rnfrac, BB_PLL_CONFIG_FRAC) |780 SM(hw_clk->outdiv, BB_PLL_CONFIG_OUTDIV));781 ret = ath10k_bmi_write_soc_reg(ar, addr, reg_val);782 if (ret)783 return -EINVAL;784 785 /* Set the correct settle time value to pll_settle register */786 addr = (RTC_WMAC_BASE_ADDRESS | WLAN_PLL_SETTLE_OFFSET);787 ret = ath10k_bmi_read_soc_reg(ar, addr, ®_val);788 if (ret)789 return -EINVAL;790 791 reg_val &= ~WLAN_PLL_SETTLE_TIME_MASK;792 reg_val |= SM(hw_clk->settle_time, WLAN_PLL_SETTLE_TIME);793 ret = ath10k_bmi_write_soc_reg(ar, addr, reg_val);794 if (ret)795 return -EINVAL;796 797 /* Set the clock_ctrl div to core_clk_ctrl register */798 addr = (RTC_SOC_BASE_ADDRESS | SOC_CORE_CLK_CTRL_OFFSET);799 ret = ath10k_bmi_read_soc_reg(ar, addr, ®_val);800 if (ret)801 return -EINVAL;802 803 reg_val &= ~SOC_CORE_CLK_CTRL_DIV_MASK;804 reg_val |= SM(1, SOC_CORE_CLK_CTRL_DIV);805 ret = ath10k_bmi_write_soc_reg(ar, addr, reg_val);806 if (ret)807 return -EINVAL;808 809 /* Set the clock_div register */810 mem_val = 1;811 ret = ath10k_bmi_write_memory(ar, clk_div_addr, &mem_val,812 sizeof(mem_val));813 if (ret)814 return -EINVAL;815 816 /* Configure the pll_control register */817 addr = (RTC_WMAC_BASE_ADDRESS | WLAN_PLL_CONTROL_OFFSET);818 ret = ath10k_bmi_read_soc_reg(ar, addr, ®_val);819 if (ret)820 return -EINVAL;821 822 reg_val |= (SM(hw_clk->refdiv, WLAN_PLL_CONTROL_REFDIV) |823 SM(hw_clk->div, WLAN_PLL_CONTROL_DIV) |824 SM(1, WLAN_PLL_CONTROL_NOPWD));825 ret = ath10k_bmi_write_soc_reg(ar, addr, reg_val);826 if (ret)827 return -EINVAL;828 829 /* busy wait (max 1s) the rtc_sync status register indicate ready */830 wait_limit = 100000;831 addr = (RTC_WMAC_BASE_ADDRESS | RTC_SYNC_STATUS_OFFSET);832 do {833 ret = ath10k_bmi_read_soc_reg(ar, addr, ®_val);834 if (ret)835 return -EINVAL;836 837 if (!MS(reg_val, RTC_SYNC_STATUS_PLL_CHANGING))838 break;839 840 wait_limit--;841 udelay(10);842 843 } while (wait_limit > 0);844 845 if (MS(reg_val, RTC_SYNC_STATUS_PLL_CHANGING))846 return -EINVAL;847 848 /* Unset the pll_bypass in pll_control register */849 addr = (RTC_WMAC_BASE_ADDRESS | WLAN_PLL_CONTROL_OFFSET);850 ret = ath10k_bmi_read_soc_reg(ar, addr, ®_val);851 if (ret)852 return -EINVAL;853 854 reg_val &= ~WLAN_PLL_CONTROL_BYPASS_MASK;855 reg_val |= SM(0, WLAN_PLL_CONTROL_BYPASS);856 ret = ath10k_bmi_write_soc_reg(ar, addr, reg_val);857 if (ret)858 return -EINVAL;859 860 /* busy wait (max 1s) the rtc_sync status register indicate ready */861 wait_limit = 100000;862 addr = (RTC_WMAC_BASE_ADDRESS | RTC_SYNC_STATUS_OFFSET);863 do {864 ret = ath10k_bmi_read_soc_reg(ar, addr, ®_val);865 if (ret)866 return -EINVAL;867 868 if (!MS(reg_val, RTC_SYNC_STATUS_PLL_CHANGING))869 break;870 871 wait_limit--;872 udelay(10);873 874 } while (wait_limit > 0);875 876 if (MS(reg_val, RTC_SYNC_STATUS_PLL_CHANGING))877 return -EINVAL;878 879 /* Enable the hardware cpu clock register */880 addr = (RTC_SOC_BASE_ADDRESS | SOC_CPU_CLOCK_OFFSET);881 ret = ath10k_bmi_read_soc_reg(ar, addr, ®_val);882 if (ret)883 return -EINVAL;884 885 reg_val &= ~SOC_CPU_CLOCK_STANDARD_MASK;886 reg_val |= SM(1, SOC_CPU_CLOCK_STANDARD);887 ret = ath10k_bmi_write_soc_reg(ar, addr, reg_val);888 if (ret)889 return -EINVAL;890 891 /* unset the nopwd from pll_control register */892 addr = (RTC_WMAC_BASE_ADDRESS | WLAN_PLL_CONTROL_OFFSET);893 ret = ath10k_bmi_read_soc_reg(ar, addr, ®_val);894 if (ret)895 return -EINVAL;896 897 reg_val &= ~WLAN_PLL_CONTROL_NOPWD_MASK;898 ret = ath10k_bmi_write_soc_reg(ar, addr, reg_val);899 if (ret)900 return -EINVAL;901 902 /* enable the pll_init register */903 mem_val = 1;904 ret = ath10k_bmi_write_memory(ar, pll_init_addr, &mem_val,905 sizeof(mem_val));906 if (ret)907 return -EINVAL;908 909 /* set the target clock frequency to speed register */910 ret = ath10k_bmi_write_memory(ar, speed_addr, &hw->target_cpu_freq,911 sizeof(hw->target_cpu_freq));912 if (ret)913 return -EINVAL;914 915 return 0;916}917 918/* Program CPU_ADDR_MSB to allow different memory919 * region access.920 */921static void ath10k_hw_map_target_mem(struct ath10k *ar, u32 msb)922{923 u32 address = SOC_CORE_BASE_ADDRESS + FW_RAM_CONFIG_ADDRESS;924 925 ath10k_hif_write32(ar, address, msb);926}927 928/* 1. Write to memory region of target, such as IRAM and DRAM.929 * 2. Target address( 0 ~ 00100000 & 0x00400000~0x00500000)930 * can be written directly. See ath10k_pci_targ_cpu_to_ce_addr() too.931 * 3. In order to access the region other than the above,932 * we need to set the value of register CPU_ADDR_MSB.933 * 4. Target memory access space is limited to 1M size. If the size is larger934 * than 1M, need to split it and program CPU_ADDR_MSB accordingly.935 */936static int ath10k_hw_diag_segment_msb_download(struct ath10k *ar,937 const void *buffer,938 u32 address,939 u32 length)940{941 u32 addr = address & REGION_ACCESS_SIZE_MASK;942 int ret, remain_size, size;943 const u8 *buf;944 945 ath10k_hw_map_target_mem(ar, CPU_ADDR_MSB_REGION_VAL(address));946 947 if (addr + length > REGION_ACCESS_SIZE_LIMIT) {948 size = REGION_ACCESS_SIZE_LIMIT - addr;949 remain_size = length - size;950 951 ret = ath10k_hif_diag_write(ar, address, buffer, size);952 if (ret) {953 ath10k_warn(ar,954 "failed to download the first %d bytes segment to address:0x%x: %d\n",955 size, address, ret);956 goto done;957 }958 959 /* Change msb to the next memory region*/960 ath10k_hw_map_target_mem(ar,961 CPU_ADDR_MSB_REGION_VAL(address) + 1);962 buf = buffer + size;963 ret = ath10k_hif_diag_write(ar,964 address & ~REGION_ACCESS_SIZE_MASK,965 buf, remain_size);966 if (ret) {967 ath10k_warn(ar,968 "failed to download the second %d bytes segment to address:0x%x: %d\n",969 remain_size,970 address & ~REGION_ACCESS_SIZE_MASK,971 ret);972 goto done;973 }974 } else {975 ret = ath10k_hif_diag_write(ar, address, buffer, length);976 if (ret) {977 ath10k_warn(ar,978 "failed to download the only %d bytes segment to address:0x%x: %d\n",979 length, address, ret);980 goto done;981 }982 }983 984done:985 /* Change msb to DRAM */986 ath10k_hw_map_target_mem(ar,987 CPU_ADDR_MSB_REGION_VAL(DRAM_BASE_ADDRESS));988 return ret;989}990 991static int ath10k_hw_diag_segment_download(struct ath10k *ar,992 const void *buffer,993 u32 address,994 u32 length)995{996 if (address >= DRAM_BASE_ADDRESS + REGION_ACCESS_SIZE_LIMIT)997 /* Needs to change MSB for memory write */998 return ath10k_hw_diag_segment_msb_download(ar, buffer,999 address, length);1000 else1001 return ath10k_hif_diag_write(ar, address, buffer, length);1002}1003 1004int ath10k_hw_diag_fast_download(struct ath10k *ar,1005 u32 address,1006 const void *buffer,1007 u32 length)1008{1009 const u8 *buf = buffer;1010 bool sgmt_end = false;1011 u32 base_addr = 0;1012 u32 base_len = 0;1013 u32 left = 0;1014 struct bmi_segmented_file_header *hdr;1015 struct bmi_segmented_metadata *metadata;1016 int ret = 0;1017 1018 if (length < sizeof(*hdr))1019 return -EINVAL;1020 1021 /* check firmware header. If it has no correct magic number1022 * or it's compressed, returns error.1023 */1024 hdr = (struct bmi_segmented_file_header *)buf;1025 if (__le32_to_cpu(hdr->magic_num) != BMI_SGMTFILE_MAGIC_NUM) {1026 ath10k_dbg(ar, ATH10K_DBG_BOOT,1027 "Not a supported firmware, magic_num:0x%x\n",1028 hdr->magic_num);1029 return -EINVAL;1030 }1031 1032 if (hdr->file_flags != 0) {1033 ath10k_dbg(ar, ATH10K_DBG_BOOT,1034 "Not a supported firmware, file_flags:0x%x\n",1035 hdr->file_flags);1036 return -EINVAL;1037 }1038 1039 metadata = (struct bmi_segmented_metadata *)hdr->data;1040 left = length - sizeof(*hdr);1041 1042 while (left > 0) {1043 if (left < sizeof(*metadata)) {1044 ath10k_warn(ar, "firmware segment is truncated: %d\n",1045 left);1046 ret = -EINVAL;1047 break;1048 }1049 base_addr = __le32_to_cpu(metadata->addr);1050 base_len = __le32_to_cpu(metadata->length);1051 buf = metadata->data;1052 left -= sizeof(*metadata);1053 1054 switch (base_len) {1055 case BMI_SGMTFILE_BEGINADDR:1056 /* base_addr is the start address to run */1057 ret = ath10k_bmi_set_start(ar, base_addr);1058 base_len = 0;1059 break;1060 case BMI_SGMTFILE_DONE:1061 /* no more segment */1062 base_len = 0;1063 sgmt_end = true;1064 ret = 0;1065 break;1066 case BMI_SGMTFILE_BDDATA:1067 case BMI_SGMTFILE_EXEC:1068 ath10k_warn(ar,1069 "firmware has unsupported segment:%d\n",1070 base_len);1071 ret = -EINVAL;1072 break;1073 default:1074 if (base_len > left) {1075 /* sanity check */1076 ath10k_warn(ar,1077 "firmware has invalid segment length, %d > %d\n",1078 base_len, left);1079 ret = -EINVAL;1080 break;1081 }1082 1083 ret = ath10k_hw_diag_segment_download(ar,1084 buf,1085 base_addr,1086 base_len);1087 1088 if (ret)1089 ath10k_warn(ar,1090 "failed to download firmware via diag interface:%d\n",1091 ret);1092 break;1093 }1094 1095 if (ret || sgmt_end)1096 break;1097 1098 metadata = (struct bmi_segmented_metadata *)(buf + base_len);1099 left -= base_len;1100 }1101 1102 if (ret == 0)1103 ath10k_dbg(ar, ATH10K_DBG_BOOT,1104 "boot firmware fast diag download successfully.\n");1105 return ret;1106}1107 1108static int ath10k_htt_tx_rssi_enable(struct htt_resp *resp)1109{1110 return (resp->data_tx_completion.flags2 & HTT_TX_CMPL_FLAG_DATA_RSSI);1111}1112 1113static int ath10k_htt_tx_rssi_enable_wcn3990(struct htt_resp *resp)1114{1115 return (resp->data_tx_completion.flags2 &1116 HTT_TX_DATA_RSSI_ENABLE_WCN3990);1117}1118 1119static int ath10k_get_htt_tx_data_rssi_pad(struct htt_resp *resp)1120{1121 struct htt_data_tx_completion_ext extd;1122 int pad_bytes = 0;1123 1124 if (resp->data_tx_completion.flags2 & HTT_TX_DATA_APPEND_RETRIES)1125 pad_bytes += sizeof(extd.a_retries) /1126 sizeof(extd.msdus_rssi[0]);1127 1128 if (resp->data_tx_completion.flags2 & HTT_TX_DATA_APPEND_TIMESTAMP)1129 pad_bytes += sizeof(extd.t_stamp) / sizeof(extd.msdus_rssi[0]);1130 1131 return pad_bytes;1132}1133 1134const struct ath10k_hw_ops qca988x_ops = {1135 .set_coverage_class = ath10k_hw_qca988x_set_coverage_class,1136 .is_rssi_enable = ath10k_htt_tx_rssi_enable,1137};1138 1139const struct ath10k_hw_ops qca99x0_ops = {1140 .is_rssi_enable = ath10k_htt_tx_rssi_enable,1141};1142 1143const struct ath10k_hw_ops qca6174_ops = {1144 .set_coverage_class = ath10k_hw_qca988x_set_coverage_class,1145 .enable_pll_clk = ath10k_hw_qca6174_enable_pll_clock,1146 .is_rssi_enable = ath10k_htt_tx_rssi_enable,1147};1148 1149const struct ath10k_hw_ops qca6174_sdio_ops = {1150 .enable_pll_clk = ath10k_hw_qca6174_enable_pll_clock,1151};1152 1153const struct ath10k_hw_ops wcn3990_ops = {1154 .tx_data_rssi_pad_bytes = ath10k_get_htt_tx_data_rssi_pad,1155 .is_rssi_enable = ath10k_htt_tx_rssi_enable_wcn3990,1156};1157