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1/* SPDX-License-Identifier: ISC */2/*3 * Copyright (c) 2018 The Linux Foundation. All rights reserved.4 */5#ifndef _ATH10K_QMI_H_6#define _ATH10K_QMI_H_7 8#include <linux/soc/qcom/qmi.h>9#include <linux/qrtr.h>10#include "qmi_wlfw_v01.h"11 12#define MAX_NUM_MEMORY_REGIONS 213#define MAX_TIMESTAMP_LEN 3214#define MAX_BUILD_ID_LEN 12815#define MAX_NUM_CAL_V01 516 17enum ath10k_qmi_driver_event_type {18 ATH10K_QMI_EVENT_SERVER_ARRIVE,19 ATH10K_QMI_EVENT_SERVER_EXIT,20 ATH10K_QMI_EVENT_FW_READY_IND,21 ATH10K_QMI_EVENT_FW_DOWN_IND,22 ATH10K_QMI_EVENT_MSA_READY_IND,23 ATH10K_QMI_EVENT_MAX,24};25 26struct ath10k_msa_mem_info {27 phys_addr_t addr;28 u32 size;29 bool secure;30};31 32struct ath10k_qmi_chip_info {33 u32 chip_id;34 u32 chip_family;35};36 37struct ath10k_qmi_board_info {38 u32 board_id;39};40 41struct ath10k_qmi_soc_info {42 u32 soc_id;43};44 45struct ath10k_qmi_cal_data {46 u32 cal_id;47 u32 total_size;48 u8 *data;49};50 51struct ath10k_tgt_pipe_cfg {52 __le32 pipe_num;53 __le32 pipe_dir;54 __le32 nentries;55 __le32 nbytes_max;56 __le32 flags;57 __le32 reserved;58};59 60struct ath10k_svc_pipe_cfg {61 __le32 service_id;62 __le32 pipe_dir;63 __le32 pipe_num;64};65 66struct ath10k_shadow_reg_cfg {67 __le16 ce_id;68 __le16 reg_offset;69};70 71struct ath10k_qmi_wlan_enable_cfg {72 u32 num_ce_tgt_cfg;73 struct ath10k_tgt_pipe_cfg *ce_tgt_cfg;74 u32 num_ce_svc_pipe_cfg;75 struct ath10k_svc_pipe_cfg *ce_svc_cfg;76 u32 num_shadow_reg_cfg;77 struct ath10k_shadow_reg_cfg *shadow_reg_cfg;78};79 80struct ath10k_qmi_driver_event {81 struct list_head list;82 enum ath10k_qmi_driver_event_type type;83 void *data;84};85 86enum ath10k_qmi_state {87 ATH10K_QMI_STATE_INIT_DONE,88 ATH10K_QMI_STATE_DEINIT,89};90 91struct ath10k_qmi {92 struct ath10k *ar;93 struct qmi_handle qmi_hdl;94 struct sockaddr_qrtr sq;95 struct work_struct event_work;96 struct workqueue_struct *event_wq;97 struct list_head event_list;98 spinlock_t event_lock; /* spinlock for qmi event list */99 u32 nr_mem_region;100 struct ath10k_msa_mem_info mem_region[MAX_NUM_MEMORY_REGIONS];101 struct ath10k_qmi_chip_info chip_info;102 struct ath10k_qmi_board_info board_info;103 struct ath10k_qmi_soc_info soc_info;104 char fw_build_id[MAX_BUILD_ID_LEN + 1];105 u32 fw_version;106 bool fw_ready;107 char fw_build_timestamp[MAX_TIMESTAMP_LEN + 1];108 struct ath10k_qmi_cal_data cal_data[MAX_NUM_CAL_V01];109 bool msa_fixed_perm;110 bool no_msa_ready_indicator;111 enum ath10k_qmi_state state;112};113 114int ath10k_qmi_wlan_enable(struct ath10k *ar,115 struct ath10k_qmi_wlan_enable_cfg *config,116 enum wlfw_driver_mode_enum_v01 mode,117 const char *version);118int ath10k_qmi_wlan_disable(struct ath10k *ar);119int ath10k_qmi_init(struct ath10k *ar, u32 msa_size);120int ath10k_qmi_deinit(struct ath10k *ar);121int ath10k_qmi_set_fw_log_mode(struct ath10k *ar, u8 fw_log_mode);122 123#endif /* ATH10K_QMI_H */124