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1/* SPDX-License-Identifier: BSD-3-Clause-Clear */2/*3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.4 * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.5 */6 7#ifndef ATH11K_HW_H8#define ATH11K_HW_H9 10#include "hal.h"11#include "wmi.h"12 13/* Target configuration defines */14 15/* Num VDEVS per radio */16#define TARGET_NUM_VDEVS(ab) (ab->hw_params.num_vdevs)17 18#define TARGET_NUM_PEERS_PDEV(ab) (ab->hw_params.num_peers + TARGET_NUM_VDEVS(ab))19 20/* Num of peers for Single Radio mode */21#define TARGET_NUM_PEERS_SINGLE(ab) (TARGET_NUM_PEERS_PDEV(ab))22 23/* Num of peers for DBS */24#define TARGET_NUM_PEERS_DBS(ab) (2 * TARGET_NUM_PEERS_PDEV(ab))25 26/* Num of peers for DBS_SBS */27#define TARGET_NUM_PEERS_DBS_SBS(ab) (3 * TARGET_NUM_PEERS_PDEV(ab))28 29/* Max num of stations (per radio) */30#define TARGET_NUM_STATIONS(ab) (ab->hw_params.num_peers)31 32#define TARGET_NUM_PEERS(ab, x) TARGET_NUM_PEERS_##x(ab)33#define TARGET_NUM_PEER_KEYS 234#define TARGET_NUM_TIDS(ab, x) (2 * TARGET_NUM_PEERS(ab, x) + \35 4 * TARGET_NUM_VDEVS(ab) + 8)36 37#define TARGET_AST_SKID_LIMIT 1638#define TARGET_NUM_OFFLD_PEERS 439#define TARGET_NUM_OFFLD_REORDER_BUFFS 440 41#define TARGET_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(4))42#define TARGET_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(4))43#define TARGET_RX_TIMEOUT_LO_PRI 10044#define TARGET_RX_TIMEOUT_HI_PRI 4045 46#define TARGET_DECAP_MODE_RAW 047#define TARGET_DECAP_MODE_NATIVE_WIFI 148#define TARGET_DECAP_MODE_ETH 249 50#define TARGET_SCAN_MAX_PENDING_REQS 451#define TARGET_BMISS_OFFLOAD_MAX_VDEV 352#define TARGET_ROAM_OFFLOAD_MAX_VDEV 353#define TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES 854#define TARGET_GTK_OFFLOAD_MAX_VDEV 355#define TARGET_NUM_MCAST_GROUPS 1256#define TARGET_NUM_MCAST_TABLE_ELEMS 6457#define TARGET_MCAST2UCAST_MODE 258#define TARGET_TX_DBG_LOG_SIZE 102459#define TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 160#define TARGET_VOW_CONFIG 061#define TARGET_NUM_MSDU_DESC (2500)62#define TARGET_MAX_FRAG_ENTRIES 663#define TARGET_MAX_BCN_OFFLD 1664#define TARGET_NUM_WDS_ENTRIES 3265#define TARGET_DMA_BURST_SIZE 166#define TARGET_RX_BATCHMODE 167#define TARGET_EMA_MAX_PROFILE_PERIOD 868 69#define ATH11K_HW_MAX_QUEUES 470#define ATH11K_QUEUE_LEN 409671 72#define ATH11k_HW_RATECODE_CCK_SHORT_PREAM_MASK 0x473 74#define ATH11K_FW_DIR "ath11k"75 76#define ATH11K_BOARD_MAGIC "QCA-ATH11K-BOARD"77#define ATH11K_BOARD_API2_FILE "board-2.bin"78#define ATH11K_DEFAULT_BOARD_FILE "board.bin"79#define ATH11K_DEFAULT_CAL_FILE "caldata.bin"80#define ATH11K_AMSS_FILE "amss.bin"81#define ATH11K_M3_FILE "m3.bin"82#define ATH11K_REGDB_FILE_NAME "regdb.bin"83 84#define ATH11K_CE_OFFSET(ab) (ab->mem_ce - ab->mem)85 86enum ath11k_hw_rate_cck {87 ATH11K_HW_RATE_CCK_LP_11M = 0,88 ATH11K_HW_RATE_CCK_LP_5_5M,89 ATH11K_HW_RATE_CCK_LP_2M,90 ATH11K_HW_RATE_CCK_LP_1M,91 ATH11K_HW_RATE_CCK_SP_11M,92 ATH11K_HW_RATE_CCK_SP_5_5M,93 ATH11K_HW_RATE_CCK_SP_2M,94};95 96enum ath11k_hw_rate_ofdm {97 ATH11K_HW_RATE_OFDM_48M = 0,98 ATH11K_HW_RATE_OFDM_24M,99 ATH11K_HW_RATE_OFDM_12M,100 ATH11K_HW_RATE_OFDM_6M,101 ATH11K_HW_RATE_OFDM_54M,102 ATH11K_HW_RATE_OFDM_36M,103 ATH11K_HW_RATE_OFDM_18M,104 ATH11K_HW_RATE_OFDM_9M,105};106 107enum ath11k_bus {108 ATH11K_BUS_AHB,109 ATH11K_BUS_PCI,110};111 112#define ATH11K_EXT_IRQ_GRP_NUM_MAX 11113 114struct hal_rx_desc;115struct hal_tcl_data_cmd;116 117struct ath11k_hw_ring_mask {118 u8 tx[ATH11K_EXT_IRQ_GRP_NUM_MAX];119 u8 rx_mon_status[ATH11K_EXT_IRQ_GRP_NUM_MAX];120 u8 rx[ATH11K_EXT_IRQ_GRP_NUM_MAX];121 u8 rx_err[ATH11K_EXT_IRQ_GRP_NUM_MAX];122 u8 rx_wbm_rel[ATH11K_EXT_IRQ_GRP_NUM_MAX];123 u8 reo_status[ATH11K_EXT_IRQ_GRP_NUM_MAX];124 u8 rxdma2host[ATH11K_EXT_IRQ_GRP_NUM_MAX];125 u8 host2rxdma[ATH11K_EXT_IRQ_GRP_NUM_MAX];126};127 128struct ath11k_hw_tcl2wbm_rbm_map {129 u8 tcl_ring_num;130 u8 wbm_ring_num;131 u8 rbm_id;132};133 134struct ath11k_hw_hal_params {135 enum hal_rx_buf_return_buf_manager rx_buf_rbm;136 const struct ath11k_hw_tcl2wbm_rbm_map *tcl2wbm_rbm_map;137};138 139struct ath11k_hw_params {140 const char *name;141 u16 hw_rev;142 u8 max_radios;143 u32 bdf_addr;144 145 struct {146 const char *dir;147 size_t board_size;148 size_t cal_offset;149 } fw;150 151 const struct ath11k_hw_ops *hw_ops;152 const struct ath11k_hw_ring_mask *ring_mask;153 154 bool internal_sleep_clock;155 156 const struct ath11k_hw_regs *regs;157 u32 qmi_service_ins_id;158 const struct ce_attr *host_ce_config;159 u32 ce_count;160 const struct ce_pipe_config *target_ce_config;161 u32 target_ce_count;162 const struct service_to_pipe *svc_to_ce_map;163 u32 svc_to_ce_map_len;164 const struct ce_ie_addr *ce_ie_addr;165 const struct ce_remap *ce_remap;166 167 bool single_pdev_only;168 169 bool rxdma1_enable;170 int num_rxdma_per_pdev;171 bool rx_mac_buf_ring;172 bool vdev_start_delay;173 bool htt_peer_map_v2;174 175 struct {176 u8 fft_sz;177 u8 fft_pad_sz;178 u8 summary_pad_sz;179 u8 fft_hdr_len;180 u16 max_fft_bins;181 bool fragment_160mhz;182 } spectral;183 184 u16 interface_modes;185 bool supports_monitor;186 bool full_monitor_mode;187 bool supports_shadow_regs;188 bool idle_ps;189 bool supports_sta_ps;190 bool coldboot_cal_mm;191 bool coldboot_cal_ftm;192 bool cbcal_restart_fw;193 int fw_mem_mode;194 u32 num_vdevs;195 u32 num_peers;196 bool supports_suspend;197 u32 hal_desc_sz;198 bool supports_regdb;199 bool fix_l1ss;200 bool credit_flow;201 u8 max_tx_ring;202 const struct ath11k_hw_hal_params *hal_params;203 bool supports_dynamic_smps_6ghz;204 bool alloc_cacheable_memory;205 bool supports_rssi_stats;206 bool fw_wmi_diag_event;207 bool current_cc_support;208 bool dbr_debug_support;209 bool global_reset;210 const struct cfg80211_sar_capa *bios_sar_capa;211 bool m3_fw_support;212 bool fixed_bdf_addr;213 bool fixed_mem_region;214 bool static_window_map;215 bool hybrid_bus_type;216 bool fixed_fw_mem;217 bool support_off_channel_tx;218 bool supports_multi_bssid;219 220 struct {221 u32 start;222 u32 end;223 } sram_dump;224 225 bool tcl_ring_retry;226 u32 tx_ring_size;227 bool smp2p_wow_exit;228 bool support_fw_mac_sequence;229 bool support_dual_stations;230};231 232struct ath11k_hw_ops {233 u8 (*get_hw_mac_from_pdev_id)(int pdev_id);234 void (*wmi_init_config)(struct ath11k_base *ab,235 struct target_resource_config *config);236 int (*mac_id_to_pdev_id)(struct ath11k_hw_params *hw, int mac_id);237 int (*mac_id_to_srng_id)(struct ath11k_hw_params *hw, int mac_id);238 void (*tx_mesh_enable)(struct ath11k_base *ab,239 struct hal_tcl_data_cmd *tcl_cmd);240 bool (*rx_desc_get_first_msdu)(struct hal_rx_desc *desc);241 bool (*rx_desc_get_last_msdu)(struct hal_rx_desc *desc);242 u8 (*rx_desc_get_l3_pad_bytes)(struct hal_rx_desc *desc);243 u8 *(*rx_desc_get_hdr_status)(struct hal_rx_desc *desc);244 bool (*rx_desc_encrypt_valid)(struct hal_rx_desc *desc);245 u32 (*rx_desc_get_encrypt_type)(struct hal_rx_desc *desc);246 u8 (*rx_desc_get_decap_type)(struct hal_rx_desc *desc);247 u8 (*rx_desc_get_mesh_ctl)(struct hal_rx_desc *desc);248 bool (*rx_desc_get_ldpc_support)(struct hal_rx_desc *desc);249 bool (*rx_desc_get_mpdu_seq_ctl_vld)(struct hal_rx_desc *desc);250 bool (*rx_desc_get_mpdu_fc_valid)(struct hal_rx_desc *desc);251 u16 (*rx_desc_get_mpdu_start_seq_no)(struct hal_rx_desc *desc);252 u16 (*rx_desc_get_msdu_len)(struct hal_rx_desc *desc);253 u8 (*rx_desc_get_msdu_sgi)(struct hal_rx_desc *desc);254 u8 (*rx_desc_get_msdu_rate_mcs)(struct hal_rx_desc *desc);255 u8 (*rx_desc_get_msdu_rx_bw)(struct hal_rx_desc *desc);256 u32 (*rx_desc_get_msdu_freq)(struct hal_rx_desc *desc);257 u8 (*rx_desc_get_msdu_pkt_type)(struct hal_rx_desc *desc);258 u8 (*rx_desc_get_msdu_nss)(struct hal_rx_desc *desc);259 u8 (*rx_desc_get_mpdu_tid)(struct hal_rx_desc *desc);260 u16 (*rx_desc_get_mpdu_peer_id)(struct hal_rx_desc *desc);261 void (*rx_desc_copy_attn_end_tlv)(struct hal_rx_desc *fdesc,262 struct hal_rx_desc *ldesc);263 u32 (*rx_desc_get_mpdu_start_tag)(struct hal_rx_desc *desc);264 u32 (*rx_desc_get_mpdu_ppdu_id)(struct hal_rx_desc *desc);265 void (*rx_desc_set_msdu_len)(struct hal_rx_desc *desc, u16 len);266 struct rx_attention *(*rx_desc_get_attention)(struct hal_rx_desc *desc);267 u8 *(*rx_desc_get_msdu_payload)(struct hal_rx_desc *desc);268 void (*reo_setup)(struct ath11k_base *ab);269 u16 (*mpdu_info_get_peerid)(struct hal_rx_mpdu_info *mpdu_info);270 bool (*rx_desc_mac_addr2_valid)(struct hal_rx_desc *desc);271 u8* (*rx_desc_mpdu_start_addr2)(struct hal_rx_desc *desc);272 u32 (*get_ring_selector)(struct sk_buff *skb);273};274 275extern const struct ath11k_hw_ops ipq8074_ops;276extern const struct ath11k_hw_ops ipq6018_ops;277extern const struct ath11k_hw_ops qca6390_ops;278extern const struct ath11k_hw_ops qcn9074_ops;279extern const struct ath11k_hw_ops wcn6855_ops;280extern const struct ath11k_hw_ops wcn6750_ops;281extern const struct ath11k_hw_ops ipq5018_ops;282 283extern const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_ipq8074;284extern const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_qca6390;285extern const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_qcn9074;286extern const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_wcn6750;287 288extern const struct ce_ie_addr ath11k_ce_ie_addr_ipq8074;289extern const struct ce_ie_addr ath11k_ce_ie_addr_ipq5018;290 291extern const struct ce_remap ath11k_ce_remap_ipq5018;292 293extern const struct ath11k_hw_hal_params ath11k_hw_hal_params_ipq8074;294extern const struct ath11k_hw_hal_params ath11k_hw_hal_params_qca6390;295extern const struct ath11k_hw_hal_params ath11k_hw_hal_params_wcn6750;296 297static inline298int ath11k_hw_get_mac_from_pdev_id(struct ath11k_hw_params *hw,299 int pdev_idx)300{301 if (hw->hw_ops->get_hw_mac_from_pdev_id)302 return hw->hw_ops->get_hw_mac_from_pdev_id(pdev_idx);303 304 return 0;305}306 307static inline int ath11k_hw_mac_id_to_pdev_id(struct ath11k_hw_params *hw,308 int mac_id)309{310 if (hw->hw_ops->mac_id_to_pdev_id)311 return hw->hw_ops->mac_id_to_pdev_id(hw, mac_id);312 313 return 0;314}315 316static inline int ath11k_hw_mac_id_to_srng_id(struct ath11k_hw_params *hw,317 int mac_id)318{319 if (hw->hw_ops->mac_id_to_srng_id)320 return hw->hw_ops->mac_id_to_srng_id(hw, mac_id);321 322 return 0;323}324 325struct ath11k_fw_ie {326 __le32 id;327 __le32 len;328 u8 data[];329};330 331enum ath11k_bd_ie_board_type {332 ATH11K_BD_IE_BOARD_NAME = 0,333 ATH11K_BD_IE_BOARD_DATA = 1,334};335 336enum ath11k_bd_ie_regdb_type {337 ATH11K_BD_IE_REGDB_NAME = 0,338 ATH11K_BD_IE_REGDB_DATA = 1,339};340 341enum ath11k_bd_ie_type {342 /* contains sub IEs of enum ath11k_bd_ie_board_type */343 ATH11K_BD_IE_BOARD = 0,344 /* contains sub IEs of enum ath11k_bd_ie_regdb_type */345 ATH11K_BD_IE_REGDB = 1,346};347 348struct ath11k_hw_regs {349 u32 hal_tcl1_ring_base_lsb;350 u32 hal_tcl1_ring_base_msb;351 u32 hal_tcl1_ring_id;352 u32 hal_tcl1_ring_misc;353 u32 hal_tcl1_ring_tp_addr_lsb;354 u32 hal_tcl1_ring_tp_addr_msb;355 u32 hal_tcl1_ring_consumer_int_setup_ix0;356 u32 hal_tcl1_ring_consumer_int_setup_ix1;357 u32 hal_tcl1_ring_msi1_base_lsb;358 u32 hal_tcl1_ring_msi1_base_msb;359 u32 hal_tcl1_ring_msi1_data;360 u32 hal_tcl2_ring_base_lsb;361 u32 hal_tcl_ring_base_lsb;362 363 u32 hal_tcl_status_ring_base_lsb;364 365 u32 hal_reo1_ring_base_lsb;366 u32 hal_reo1_ring_base_msb;367 u32 hal_reo1_ring_id;368 u32 hal_reo1_ring_misc;369 u32 hal_reo1_ring_hp_addr_lsb;370 u32 hal_reo1_ring_hp_addr_msb;371 u32 hal_reo1_ring_producer_int_setup;372 u32 hal_reo1_ring_msi1_base_lsb;373 u32 hal_reo1_ring_msi1_base_msb;374 u32 hal_reo1_ring_msi1_data;375 u32 hal_reo2_ring_base_lsb;376 u32 hal_reo1_aging_thresh_ix_0;377 u32 hal_reo1_aging_thresh_ix_1;378 u32 hal_reo1_aging_thresh_ix_2;379 u32 hal_reo1_aging_thresh_ix_3;380 381 u32 hal_reo1_ring_hp;382 u32 hal_reo1_ring_tp;383 u32 hal_reo2_ring_hp;384 385 u32 hal_reo_tcl_ring_base_lsb;386 u32 hal_reo_tcl_ring_hp;387 388 u32 hal_reo_status_ring_base_lsb;389 u32 hal_reo_status_hp;390 391 u32 hal_reo_cmd_ring_base_lsb;392 u32 hal_reo_cmd_ring_hp;393 394 u32 hal_sw2reo_ring_base_lsb;395 u32 hal_sw2reo_ring_hp;396 397 u32 hal_seq_wcss_umac_ce0_src_reg;398 u32 hal_seq_wcss_umac_ce0_dst_reg;399 u32 hal_seq_wcss_umac_ce1_src_reg;400 u32 hal_seq_wcss_umac_ce1_dst_reg;401 402 u32 hal_wbm_idle_link_ring_base_lsb;403 u32 hal_wbm_idle_link_ring_misc;404 405 u32 hal_wbm_release_ring_base_lsb;406 407 u32 hal_wbm0_release_ring_base_lsb;408 u32 hal_wbm1_release_ring_base_lsb;409 410 u32 pcie_qserdes_sysclk_en_sel;411 u32 pcie_pcs_osc_dtct_config_base;412 413 u32 hal_shadow_base_addr;414 u32 hal_reo1_misc_ctl;415};416 417extern const struct ath11k_hw_regs ipq8074_regs;418extern const struct ath11k_hw_regs qca6390_regs;419extern const struct ath11k_hw_regs qcn9074_regs;420extern const struct ath11k_hw_regs wcn6855_regs;421extern const struct ath11k_hw_regs wcn6750_regs;422extern const struct ath11k_hw_regs ipq5018_regs;423 424static inline const char *ath11k_bd_ie_type_str(enum ath11k_bd_ie_type type)425{426 switch (type) {427 case ATH11K_BD_IE_BOARD:428 return "board data";429 case ATH11K_BD_IE_REGDB:430 return "regdb data";431 }432 433 return "unknown";434}435 436extern const struct cfg80211_sar_capa ath11k_hw_sar_capa_wcn6855;437 438#endif439