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1/* SPDX-License-Identifier: BSD-3-Clause-Clear */2/*3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.4 * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.5 */6 7#ifndef DEBUG_HTT_STATS_H8#define DEBUG_HTT_STATS_H9 10#define ATH12K_HTT_STATS_BUF_SIZE (1024 * 512)11#define ATH12K_HTT_STATS_COOKIE_LSB GENMASK_ULL(31, 0)12#define ATH12K_HTT_STATS_COOKIE_MSB GENMASK_ULL(63, 32)13#define ATH12K_HTT_STATS_MAGIC_VALUE 0xF0F0F0F014#define ATH12K_HTT_STATS_SUBTYPE_MAX 1615#define ATH12K_HTT_MAX_STRING_LEN 25616 17#define ATH12K_HTT_STATS_RESET_BITMAP32_OFFSET(_idx) ((_idx) & 0x1f)18#define ATH12K_HTT_STATS_RESET_BITMAP64_OFFSET(_idx) ((_idx) & 0x3f)19#define ATH12K_HTT_STATS_RESET_BITMAP32_BIT(_idx) (1 << \20 ATH12K_HTT_STATS_RESET_BITMAP32_OFFSET(_idx))21#define ATH12K_HTT_STATS_RESET_BITMAP64_BIT(_idx) (1 << \22 ATH12K_HTT_STATS_RESET_BITMAP64_OFFSET(_idx))23 24void ath12k_debugfs_htt_stats_register(struct ath12k *ar);25 26#ifdef CONFIG_ATH12K_DEBUGFS27void ath12k_debugfs_htt_ext_stats_handler(struct ath12k_base *ab,28 struct sk_buff *skb);29#else /* CONFIG_ATH12K_DEBUGFS */30static inline void ath12k_debugfs_htt_ext_stats_handler(struct ath12k_base *ab,31 struct sk_buff *skb)32{33}34#endif35 36/**37 * DOC: target -> host extended statistics upload38 *39 * The following field definitions describe the format of the HTT40 * target to host stats upload confirmation message.41 * The message contains a cookie echoed from the HTT host->target stats42 * upload request, which identifies which request the confirmation is43 * for, and a single stats can span over multiple HTT stats indication44 * due to the HTT message size limitation so every HTT ext stats45 * indication will have tag-length-value stats information elements.46 * The tag-length header for each HTT stats IND message also includes a47 * status field, to indicate whether the request for the stat type in48 * question was fully met, partially met, unable to be met, or invalid49 * (if the stat type in question is disabled in the target).50 * A Done bit 1's indicate the end of the of stats info elements.51 *52 *53 * |31 16|15 12|11|10 8|7 5|4 0|54 * |--------------------------------------------------------------|55 * | reserved | msg type |56 * |--------------------------------------------------------------|57 * | cookie LSBs |58 * |--------------------------------------------------------------|59 * | cookie MSBs |60 * |--------------------------------------------------------------|61 * | stats entry length | rsvd | D| S | stat type |62 * |--------------------------------------------------------------|63 * | type-specific stats info |64 * | (see debugfs_htt_stats.h) |65 * |--------------------------------------------------------------|66 * Header fields:67 * - MSG_TYPE68 * Bits 7:069 * Purpose: Identifies this is a extended statistics upload confirmation70 * message.71 * Value: 0x1c72 * - COOKIE_LSBS73 * Bits 31:074 * Purpose: Provide a mechanism to match a target->host stats confirmation75 * message with its preceding host->target stats request message.76 * Value: MSBs of the opaque cookie specified by the host-side requestor77 * - COOKIE_MSBS78 * Bits 31:079 * Purpose: Provide a mechanism to match a target->host stats confirmation80 * message with its preceding host->target stats request message.81 * Value: MSBs of the opaque cookie specified by the host-side requestor82 *83 * Stats Information Element tag-length header fields:84 * - STAT_TYPE85 * Bits 7:086 * Purpose: identifies the type of statistics info held in the87 * following information element88 * Value: ath12k_dbg_htt_ext_stats_type89 * - STATUS90 * Bits 10:891 * Purpose: indicate whether the requested stats are present92 * Value:93 * 0 -> The requested stats have been delivered in full94 * 1 -> The requested stats have been delivered in part95 * 2 -> The requested stats could not be delivered (error case)96 * 3 -> The requested stat type is either not recognized (invalid)97 * - DONE98 * Bits 1199 * Purpose:100 * Indicates the completion of the stats entry, this will be the last101 * stats conf HTT segment for the requested stats type.102 * Value:103 * 0 -> the stats retrieval is ongoing104 * 1 -> the stats retrieval is complete105 * - LENGTH106 * Bits 31:16107 * Purpose: indicate the stats information size108 * Value: This field specifies the number of bytes of stats information109 * that follows the element tag-length header.110 * It is expected but not required that this length is a multiple of111 * 4 bytes.112 */113 114#define ATH12K_HTT_T2H_EXT_STATS_INFO1_DONE BIT(11)115#define ATH12K_HTT_T2H_EXT_STATS_INFO1_LENGTH GENMASK(31, 16)116 117struct ath12k_htt_extd_stats_msg {118 __le32 info0;119 __le64 cookie;120 __le32 info1;121 u8 data[];122} __packed;123 124/* htt_dbg_ext_stats_type */125enum ath12k_dbg_htt_ext_stats_type {126 ATH12K_DBG_HTT_EXT_STATS_RESET = 0,127 ATH12K_DBG_HTT_EXT_STATS_PDEV_TX = 1,128 ATH12K_DBG_HTT_EXT_STATS_PDEV_TX_SCHED = 4,129 ATH12K_DBG_HTT_EXT_STATS_PDEV_ERROR = 5,130 ATH12K_DBG_HTT_EXT_STATS_PDEV_TQM = 6,131 ATH12K_DBG_HTT_EXT_STATS_TX_DE_INFO = 8,132 133 /* keep this last */134 ATH12K_DBG_HTT_NUM_EXT_STATS,135};136 137enum ath12k_dbg_htt_tlv_tag {138 HTT_STATS_TX_PDEV_CMN_TAG = 0,139 HTT_STATS_TX_PDEV_UNDERRUN_TAG = 1,140 HTT_STATS_TX_PDEV_SIFS_TAG = 2,141 HTT_STATS_TX_PDEV_FLUSH_TAG = 3,142 HTT_STATS_TX_TQM_GEN_MPDU_TAG = 11,143 HTT_STATS_TX_TQM_LIST_MPDU_TAG = 12,144 HTT_STATS_TX_TQM_LIST_MPDU_CNT_TAG = 13,145 HTT_STATS_TX_TQM_CMN_TAG = 14,146 HTT_STATS_TX_TQM_PDEV_TAG = 15,147 HTT_STATS_TX_DE_EAPOL_PACKETS_TAG = 17,148 HTT_STATS_TX_DE_CLASSIFY_FAILED_TAG = 18,149 HTT_STATS_TX_DE_CLASSIFY_STATS_TAG = 19,150 HTT_STATS_TX_DE_CLASSIFY_STATUS_TAG = 20,151 HTT_STATS_TX_DE_ENQUEUE_PACKETS_TAG = 21,152 HTT_STATS_TX_DE_ENQUEUE_DISCARD_TAG = 22,153 HTT_STATS_TX_DE_CMN_TAG = 23,154 HTT_STATS_TX_PDEV_SCHEDULER_TXQ_STATS_TAG = 36,155 HTT_STATS_TX_SCHED_CMN_TAG = 37,156 HTT_STATS_SCHED_TXQ_CMD_POSTED_TAG = 39,157 HTT_STATS_TX_TQM_ERROR_STATS_TAG = 43,158 HTT_STATS_SCHED_TXQ_CMD_REAPED_TAG = 44,159 HTT_STATS_HW_INTR_MISC_TAG = 54,160 HTT_STATS_HW_PDEV_ERRS_TAG = 56,161 HTT_STATS_TX_DE_COMPL_STATS_TAG = 65,162 HTT_STATS_WHAL_TX_TAG = 66,163 HTT_STATS_TX_PDEV_SIFS_HIST_TAG = 67,164 HTT_STATS_SCHED_TXQ_SCHED_ORDER_SU_TAG = 86,165 HTT_STATS_SCHED_TXQ_SCHED_INELIGIBILITY_TAG = 87,166 HTT_STATS_HW_WAR_TAG = 89,167 HTT_STATS_SCHED_TXQ_SUPERCYCLE_TRIGGER_TAG = 100,168 HTT_STATS_PDEV_CTRL_PATH_TX_STATS_TAG = 102,169 HTT_STATS_MU_PPDU_DIST_TAG = 129,170 171 HTT_STATS_MAX_TAG,172};173 174#define ATH12K_HTT_STATS_MAC_ID GENMASK(7, 0)175 176#define ATH12K_HTT_TX_PDEV_MAX_SIFS_BURST_STATS 9177#define ATH12K_HTT_TX_PDEV_MAX_FLUSH_REASON_STATS 150178 179/* MU MIMO distribution stats is a 2-dimensional array180 * with dimension one denoting stats for nr4[0] or nr8[1]181 */182#define ATH12K_HTT_STATS_NUM_NR_BINS 2183#define ATH12K_HTT_STATS_MAX_NUM_MU_PPDU_PER_BURST 10184#define ATH12K_HTT_TX_PDEV_MAX_SIFS_BURST_HIST_STATS 10185#define ATH12K_HTT_STATS_MAX_NUM_SCHED_STATUS 9186#define ATH12K_HTT_STATS_NUM_SCHED_STATUS_WORDS \187 (ATH12K_HTT_STATS_NUM_NR_BINS * ATH12K_HTT_STATS_MAX_NUM_SCHED_STATUS)188#define ATH12K_HTT_STATS_MU_PPDU_PER_BURST_WORDS \189 (ATH12K_HTT_STATS_NUM_NR_BINS * ATH12K_HTT_STATS_MAX_NUM_MU_PPDU_PER_BURST)190 191enum ath12k_htt_tx_pdev_underrun_enum {192 HTT_STATS_TX_PDEV_NO_DATA_UNDERRUN = 0,193 HTT_STATS_TX_PDEV_DATA_UNDERRUN_BETWEEN_MPDU = 1,194 HTT_STATS_TX_PDEV_DATA_UNDERRUN_WITHIN_MPDU = 2,195 HTT_TX_PDEV_MAX_URRN_STATS = 3,196};197 198enum ath12k_htt_stats_reset_cfg_param_alloc_pos {199 ATH12K_HTT_STATS_RESET_PARAM_CFG_32_BYTES = 1,200 ATH12K_HTT_STATS_RESET_PARAM_CFG_64_BYTES,201 ATH12K_HTT_STATS_RESET_PARAM_CFG_128_BYTES,202};203 204struct debug_htt_stats_req {205 bool done;206 bool override_cfg_param;207 u8 pdev_id;208 enum ath12k_dbg_htt_ext_stats_type type;209 u32 cfg_param[4];210 u8 peer_addr[ETH_ALEN];211 struct completion htt_stats_rcvd;212 u32 buf_len;213 u8 buf[];214};215 216struct ath12k_htt_tx_pdev_stats_cmn_tlv {217 __le32 mac_id__word;218 __le32 hw_queued;219 __le32 hw_reaped;220 __le32 underrun;221 __le32 hw_paused;222 __le32 hw_flush;223 __le32 hw_filt;224 __le32 tx_abort;225 __le32 mpdu_requed;226 __le32 tx_xretry;227 __le32 data_rc;228 __le32 mpdu_dropped_xretry;229 __le32 illgl_rate_phy_err;230 __le32 cont_xretry;231 __le32 tx_timeout;232 __le32 pdev_resets;233 __le32 phy_underrun;234 __le32 txop_ovf;235 __le32 seq_posted;236 __le32 seq_failed_queueing;237 __le32 seq_completed;238 __le32 seq_restarted;239 __le32 mu_seq_posted;240 __le32 seq_switch_hw_paused;241 __le32 next_seq_posted_dsr;242 __le32 seq_posted_isr;243 __le32 seq_ctrl_cached;244 __le32 mpdu_count_tqm;245 __le32 msdu_count_tqm;246 __le32 mpdu_removed_tqm;247 __le32 msdu_removed_tqm;248 __le32 mpdus_sw_flush;249 __le32 mpdus_hw_filter;250 __le32 mpdus_truncated;251 __le32 mpdus_ack_failed;252 __le32 mpdus_expired;253 __le32 mpdus_seq_hw_retry;254 __le32 ack_tlv_proc;255 __le32 coex_abort_mpdu_cnt_valid;256 __le32 coex_abort_mpdu_cnt;257 __le32 num_total_ppdus_tried_ota;258 __le32 num_data_ppdus_tried_ota;259 __le32 local_ctrl_mgmt_enqued;260 __le32 local_ctrl_mgmt_freed;261 __le32 local_data_enqued;262 __le32 local_data_freed;263 __le32 mpdu_tried;264 __le32 isr_wait_seq_posted;265 266 __le32 tx_active_dur_us_low;267 __le32 tx_active_dur_us_high;268 __le32 remove_mpdus_max_retries;269 __le32 comp_delivered;270 __le32 ppdu_ok;271 __le32 self_triggers;272 __le32 tx_time_dur_data;273 __le32 seq_qdepth_repost_stop;274 __le32 mu_seq_min_msdu_repost_stop;275 __le32 seq_min_msdu_repost_stop;276 __le32 seq_txop_repost_stop;277 __le32 next_seq_cancel;278 __le32 fes_offsets_err_cnt;279 __le32 num_mu_peer_blacklisted;280 __le32 mu_ofdma_seq_posted;281 __le32 ul_mumimo_seq_posted;282 __le32 ul_ofdma_seq_posted;283 284 __le32 thermal_suspend_cnt;285 __le32 dfs_suspend_cnt;286 __le32 tx_abort_suspend_cnt;287 __le32 tgt_specific_opaque_txq_suspend_info;288 __le32 last_suspend_reason;289} __packed;290 291struct ath12k_htt_tx_pdev_stats_urrn_tlv {292 DECLARE_FLEX_ARRAY(__le32, urrn_stats);293} __packed;294 295struct ath12k_htt_tx_pdev_stats_flush_tlv {296 DECLARE_FLEX_ARRAY(__le32, flush_errs);297} __packed;298 299struct ath12k_htt_tx_pdev_stats_phy_err_tlv {300 DECLARE_FLEX_ARRAY(__le32, phy_errs);301} __packed;302 303struct ath12k_htt_tx_pdev_stats_sifs_tlv {304 DECLARE_FLEX_ARRAY(__le32, sifs_status);305} __packed;306 307struct ath12k_htt_pdev_ctrl_path_tx_stats_tlv {308 __le32 fw_tx_mgmt_subtype[ATH12K_HTT_STATS_SUBTYPE_MAX];309} __packed;310 311struct ath12k_htt_tx_pdev_stats_sifs_hist_tlv {312 DECLARE_FLEX_ARRAY(__le32, sifs_hist_status);313} __packed;314 315enum ath12k_htt_stats_hw_mode {316 ATH12K_HTT_STATS_HWMODE_AC = 0,317 ATH12K_HTT_STATS_HWMODE_AX = 1,318 ATH12K_HTT_STATS_HWMODE_BE = 2,319};320 321struct ath12k_htt_tx_pdev_mu_ppdu_dist_stats_tlv {322 __le32 hw_mode;323 __le32 num_seq_term_status[ATH12K_HTT_STATS_NUM_SCHED_STATUS_WORDS];324 __le32 num_ppdu_cmpl_per_burst[ATH12K_HTT_STATS_MU_PPDU_PER_BURST_WORDS];325 __le32 num_seq_posted[ATH12K_HTT_STATS_NUM_NR_BINS];326 __le32 num_ppdu_posted_per_burst[ATH12K_HTT_STATS_MU_PPDU_PER_BURST_WORDS];327} __packed;328 329#define ATH12K_HTT_TX_PDEV_STATS_SCHED_PER_TXQ_MAC_ID GENMASK(7, 0)330#define ATH12K_HTT_TX_PDEV_STATS_SCHED_PER_TXQ_ID GENMASK(15, 8)331 332#define ATH12K_HTT_TX_PDEV_NUM_SCHED_ORDER_LOG 20333 334struct ath12k_htt_stats_tx_sched_cmn_tlv {335 __le32 mac_id__word;336 __le32 current_timestamp;337} __packed;338 339struct ath12k_htt_tx_pdev_stats_sched_per_txq_tlv {340 __le32 mac_id__word;341 __le32 sched_policy;342 __le32 last_sched_cmd_posted_timestamp;343 __le32 last_sched_cmd_compl_timestamp;344 __le32 sched_2_tac_lwm_count;345 __le32 sched_2_tac_ring_full;346 __le32 sched_cmd_post_failure;347 __le32 num_active_tids;348 __le32 num_ps_schedules;349 __le32 sched_cmds_pending;350 __le32 num_tid_register;351 __le32 num_tid_unregister;352 __le32 num_qstats_queried;353 __le32 qstats_update_pending;354 __le32 last_qstats_query_timestamp;355 __le32 num_tqm_cmdq_full;356 __le32 num_de_sched_algo_trigger;357 __le32 num_rt_sched_algo_trigger;358 __le32 num_tqm_sched_algo_trigger;359 __le32 notify_sched;360 __le32 dur_based_sendn_term;361 __le32 su_notify2_sched;362 __le32 su_optimal_queued_msdus_sched;363 __le32 su_delay_timeout_sched;364 __le32 su_min_txtime_sched_delay;365 __le32 su_no_delay;366 __le32 num_supercycles;367 __le32 num_subcycles_with_sort;368 __le32 num_subcycles_no_sort;369} __packed;370 371struct ath12k_htt_sched_txq_cmd_posted_tlv {372 DECLARE_FLEX_ARRAY(__le32, sched_cmd_posted);373} __packed;374 375struct ath12k_htt_sched_txq_cmd_reaped_tlv {376 DECLARE_FLEX_ARRAY(__le32, sched_cmd_reaped);377} __packed;378 379struct ath12k_htt_sched_txq_sched_order_su_tlv {380 DECLARE_FLEX_ARRAY(__le32, sched_order_su);381} __packed;382 383struct ath12k_htt_sched_txq_sched_ineligibility_tlv {384 DECLARE_FLEX_ARRAY(__le32, sched_ineligibility);385} __packed;386 387enum ath12k_htt_sched_txq_supercycle_triggers_tlv_enum {388 ATH12K_HTT_SCHED_SUPERCYCLE_TRIGGER_NONE = 0,389 ATH12K_HTT_SCHED_SUPERCYCLE_TRIGGER_FORCED,390 ATH12K_HTT_SCHED_SUPERCYCLE_TRIGGER_LESS_NUM_TIDQ_ENTRIES,391 ATH12K_HTT_SCHED_SUPERCYCLE_TRIGGER_LESS_NUM_ACTIVE_TIDS,392 ATH12K_HTT_SCHED_SUPERCYCLE_TRIGGER_MAX_ITR_REACHED,393 ATH12K_HTT_SCHED_SUPERCYCLE_TRIGGER_DUR_THRESHOLD_REACHED,394 ATH12K_HTT_SCHED_SUPERCYCLE_TRIGGER_TWT_TRIGGER,395 ATH12K_HTT_SCHED_SUPERCYCLE_TRIGGER_MAX,396};397 398struct ath12k_htt_sched_txq_supercycle_triggers_tlv {399 DECLARE_FLEX_ARRAY(__le32, supercycle_triggers);400} __packed;401 402struct ath12k_htt_hw_stats_pdev_errs_tlv {403 __le32 mac_id__word;404 __le32 tx_abort;405 __le32 tx_abort_fail_count;406 __le32 rx_abort;407 __le32 rx_abort_fail_count;408 __le32 warm_reset;409 __le32 cold_reset;410 __le32 tx_flush;411 __le32 tx_glb_reset;412 __le32 tx_txq_reset;413 __le32 rx_timeout_reset;414 __le32 mac_cold_reset_restore_cal;415 __le32 mac_cold_reset;416 __le32 mac_warm_reset;417 __le32 mac_only_reset;418 __le32 phy_warm_reset;419 __le32 phy_warm_reset_ucode_trig;420 __le32 mac_warm_reset_restore_cal;421 __le32 mac_sfm_reset;422 __le32 phy_warm_reset_m3_ssr;423 __le32 phy_warm_reset_reason_phy_m3;424 __le32 phy_warm_reset_reason_tx_hw_stuck;425 __le32 phy_warm_reset_reason_num_rx_frame_stuck;426 __le32 phy_warm_reset_reason_wal_rx_rec_rx_busy;427 __le32 phy_warm_reset_reason_wal_rx_rec_mac_hng;428 __le32 phy_warm_reset_reason_mac_conv_phy_reset;429 __le32 wal_rx_recovery_rst_mac_hang_cnt;430 __le32 wal_rx_recovery_rst_known_sig_cnt;431 __le32 wal_rx_recovery_rst_no_rx_cnt;432 __le32 wal_rx_recovery_rst_no_rx_consec_cnt;433 __le32 wal_rx_recovery_rst_rx_busy_cnt;434 __le32 wal_rx_recovery_rst_phy_mac_hang_cnt;435 __le32 rx_flush_cnt;436 __le32 phy_warm_reset_reason_tx_exp_cca_stuck;437 __le32 phy_warm_reset_reason_tx_consec_flsh_war;438 __le32 phy_warm_reset_reason_tx_hwsch_reset_war;439 __le32 phy_warm_reset_reason_hwsch_cca_wdog_war;440 __le32 fw_rx_rings_reset;441 __le32 rx_dest_drain_rx_descs_leak_prevented;442 __le32 rx_dest_drain_rx_descs_saved_cnt;443 __le32 rx_dest_drain_rxdma2reo_leak_detected;444 __le32 rx_dest_drain_rxdma2fw_leak_detected;445 __le32 rx_dest_drain_rxdma2wbm_leak_detected;446 __le32 rx_dest_drain_rxdma1_2sw_leak_detected;447 __le32 rx_dest_drain_rx_drain_ok_mac_idle;448 __le32 rx_dest_drain_ok_mac_not_idle;449 __le32 rx_dest_drain_prerequisite_invld;450 __le32 rx_dest_drain_skip_non_lmac_reset;451 __le32 rx_dest_drain_hw_fifo_notempty_post_wait;452} __packed;453 454#define ATH12K_HTT_STATS_MAX_HW_INTR_NAME_LEN 8455struct ath12k_htt_hw_stats_intr_misc_tlv {456 u8 hw_intr_name[ATH12K_HTT_STATS_MAX_HW_INTR_NAME_LEN];457 __le32 mask;458 __le32 count;459} __packed;460 461struct ath12k_htt_hw_stats_whal_tx_tlv {462 __le32 mac_id__word;463 __le32 last_unpause_ppdu_id;464 __le32 hwsch_unpause_wait_tqm_write;465 __le32 hwsch_dummy_tlv_skipped;466 __le32 hwsch_misaligned_offset_received;467 __le32 hwsch_reset_count;468 __le32 hwsch_dev_reset_war;469 __le32 hwsch_delayed_pause;470 __le32 hwsch_long_delayed_pause;471 __le32 sch_rx_ppdu_no_response;472 __le32 sch_selfgen_response;473 __le32 sch_rx_sifs_resp_trigger;474} __packed;475 476struct ath12k_htt_hw_war_stats_tlv {477 __le32 mac_id__word;478 DECLARE_FLEX_ARRAY(__le32, hw_wars);479} __packed;480 481struct ath12k_htt_tx_tqm_cmn_stats_tlv {482 __le32 mac_id__word;483 __le32 max_cmdq_id;484 __le32 list_mpdu_cnt_hist_intvl;485 __le32 add_msdu;486 __le32 q_empty;487 __le32 q_not_empty;488 __le32 drop_notification;489 __le32 desc_threshold;490 __le32 hwsch_tqm_invalid_status;491 __le32 missed_tqm_gen_mpdus;492 __le32 tqm_active_tids;493 __le32 tqm_inactive_tids;494 __le32 tqm_active_msduq_flows;495 __le32 msduq_timestamp_updates;496 __le32 msduq_updates_mpdu_head_info_cmd;497 __le32 msduq_updates_emp_to_nonemp_status;498 __le32 get_mpdu_head_info_cmds_by_query;499 __le32 get_mpdu_head_info_cmds_by_tac;500 __le32 gen_mpdu_cmds_by_query;501 __le32 high_prio_q_not_empty;502} __packed;503 504struct ath12k_htt_tx_tqm_error_stats_tlv {505 __le32 q_empty_failure;506 __le32 q_not_empty_failure;507 __le32 add_msdu_failure;508 __le32 tqm_cache_ctl_err;509 __le32 tqm_soft_reset;510 __le32 tqm_reset_num_in_use_link_descs;511 __le32 tqm_reset_num_lost_link_descs;512 __le32 tqm_reset_num_lost_host_tx_buf_cnt;513 __le32 tqm_reset_num_in_use_internal_tqm;514 __le32 tqm_reset_num_in_use_idle_link_rng;515 __le32 tqm_reset_time_to_tqm_hang_delta_ms;516 __le32 tqm_reset_recovery_time_ms;517 __le32 tqm_reset_num_peers_hdl;518 __le32 tqm_reset_cumm_dirty_hw_mpduq_cnt;519 __le32 tqm_reset_cumm_dirty_hw_msduq_proc;520 __le32 tqm_reset_flush_cache_cmd_su_cnt;521 __le32 tqm_reset_flush_cache_cmd_other_cnt;522 __le32 tqm_reset_flush_cache_cmd_trig_type;523 __le32 tqm_reset_flush_cache_cmd_trig_cfg;524 __le32 tqm_reset_flush_cmd_skp_status_null;525} __packed;526 527struct ath12k_htt_tx_tqm_gen_mpdu_stats_tlv {528 DECLARE_FLEX_ARRAY(__le32, gen_mpdu_end_reason);529} __packed;530 531#define ATH12K_HTT_TX_TQM_MAX_LIST_MPDU_END_REASON 16532#define ATH12K_HTT_TX_TQM_MAX_LIST_MPDU_CNT_HISTOGRAM_BINS 16533 534struct ath12k_htt_tx_tqm_list_mpdu_stats_tlv {535 DECLARE_FLEX_ARRAY(__le32, list_mpdu_end_reason);536} __packed;537 538struct ath12k_htt_tx_tqm_list_mpdu_cnt_tlv {539 DECLARE_FLEX_ARRAY(__le32, list_mpdu_cnt_hist);540} __packed;541 542struct ath12k_htt_tx_tqm_pdev_stats_tlv {543 __le32 msdu_count;544 __le32 mpdu_count;545 __le32 remove_msdu;546 __le32 remove_mpdu;547 __le32 remove_msdu_ttl;548 __le32 send_bar;549 __le32 bar_sync;550 __le32 notify_mpdu;551 __le32 sync_cmd;552 __le32 write_cmd;553 __le32 hwsch_trigger;554 __le32 ack_tlv_proc;555 __le32 gen_mpdu_cmd;556 __le32 gen_list_cmd;557 __le32 remove_mpdu_cmd;558 __le32 remove_mpdu_tried_cmd;559 __le32 mpdu_queue_stats_cmd;560 __le32 mpdu_head_info_cmd;561 __le32 msdu_flow_stats_cmd;562 __le32 remove_msdu_cmd;563 __le32 remove_msdu_ttl_cmd;564 __le32 flush_cache_cmd;565 __le32 update_mpduq_cmd;566 __le32 enqueue;567 __le32 enqueue_notify;568 __le32 notify_mpdu_at_head;569 __le32 notify_mpdu_state_valid;570 __le32 sched_udp_notify1;571 __le32 sched_udp_notify2;572 __le32 sched_nonudp_notify1;573 __le32 sched_nonudp_notify2;574} __packed;575 576struct ath12k_htt_tx_de_cmn_stats_tlv {577 __le32 mac_id__word;578 __le32 tcl2fw_entry_count;579 __le32 not_to_fw;580 __le32 invalid_pdev_vdev_peer;581 __le32 tcl_res_invalid_addrx;582 __le32 wbm2fw_entry_count;583 __le32 invalid_pdev;584 __le32 tcl_res_addrx_timeout;585 __le32 invalid_vdev;586 __le32 invalid_tcl_exp_frame_desc;587 __le32 vdev_id_mismatch_cnt;588} __packed;589 590struct ath12k_htt_tx_de_eapol_packets_stats_tlv {591 __le32 m1_packets;592 __le32 m2_packets;593 __le32 m3_packets;594 __le32 m4_packets;595 __le32 g1_packets;596 __le32 g2_packets;597 __le32 rc4_packets;598 __le32 eap_packets;599 __le32 eapol_start_packets;600 __le32 eapol_logoff_packets;601 __le32 eapol_encap_asf_packets;602} __packed;603 604struct ath12k_htt_tx_de_classify_stats_tlv {605 __le32 arp_packets;606 __le32 igmp_packets;607 __le32 dhcp_packets;608 __le32 host_inspected;609 __le32 htt_included;610 __le32 htt_valid_mcs;611 __le32 htt_valid_nss;612 __le32 htt_valid_preamble_type;613 __le32 htt_valid_chainmask;614 __le32 htt_valid_guard_interval;615 __le32 htt_valid_retries;616 __le32 htt_valid_bw_info;617 __le32 htt_valid_power;618 __le32 htt_valid_key_flags;619 __le32 htt_valid_no_encryption;620 __le32 fse_entry_count;621 __le32 fse_priority_be;622 __le32 fse_priority_high;623 __le32 fse_priority_low;624 __le32 fse_traffic_ptrn_be;625 __le32 fse_traffic_ptrn_over_sub;626 __le32 fse_traffic_ptrn_bursty;627 __le32 fse_traffic_ptrn_interactive;628 __le32 fse_traffic_ptrn_periodic;629 __le32 fse_hwqueue_alloc;630 __le32 fse_hwqueue_created;631 __le32 fse_hwqueue_send_to_host;632 __le32 mcast_entry;633 __le32 bcast_entry;634 __le32 htt_update_peer_cache;635 __le32 htt_learning_frame;636 __le32 fse_invalid_peer;637 __le32 mec_notify;638} __packed;639 640struct ath12k_htt_tx_de_classify_failed_stats_tlv {641 __le32 ap_bss_peer_not_found;642 __le32 ap_bcast_mcast_no_peer;643 __le32 sta_delete_in_progress;644 __le32 ibss_no_bss_peer;645 __le32 invalid_vdev_type;646 __le32 invalid_ast_peer_entry;647 __le32 peer_entry_invalid;648 __le32 ethertype_not_ip;649 __le32 eapol_lookup_failed;650 __le32 qpeer_not_allow_data;651 __le32 fse_tid_override;652 __le32 ipv6_jumbogram_zero_length;653 __le32 qos_to_non_qos_in_prog;654 __le32 ap_bcast_mcast_eapol;655 __le32 unicast_on_ap_bss_peer;656 __le32 ap_vdev_invalid;657 __le32 incomplete_llc;658 __le32 eapol_duplicate_m3;659 __le32 eapol_duplicate_m4;660} __packed;661 662struct ath12k_htt_tx_de_classify_status_stats_tlv {663 __le32 eok;664 __le32 classify_done;665 __le32 lookup_failed;666 __le32 send_host_dhcp;667 __le32 send_host_mcast;668 __le32 send_host_unknown_dest;669 __le32 send_host;670 __le32 status_invalid;671} __packed;672 673struct ath12k_htt_tx_de_enqueue_packets_stats_tlv {674 __le32 enqueued_pkts;675 __le32 to_tqm;676 __le32 to_tqm_bypass;677} __packed;678 679struct ath12k_htt_tx_de_enqueue_discard_stats_tlv {680 __le32 discarded_pkts;681 __le32 local_frames;682 __le32 is_ext_msdu;683} __packed;684 685struct ath12k_htt_tx_de_compl_stats_tlv {686 __le32 tcl_dummy_frame;687 __le32 tqm_dummy_frame;688 __le32 tqm_notify_frame;689 __le32 fw2wbm_enq;690 __le32 tqm_bypass_frame;691} __packed;692 693#endif694