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1/* SPDX-License-Identifier: BSD-3-Clause-Clear */2/*3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.4 * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.5 */6 7#ifndef ATH12K_DP_H8#define ATH12K_DP_H9 10#include "hal_rx.h"11#include "hw.h"12 13#define MAX_RXDMA_PER_PDEV 214 15struct ath12k_base;16struct ath12k_peer;17struct ath12k_dp;18struct ath12k_vif;19struct hal_tcl_status_ring;20struct ath12k_ext_irq_grp;21 22#define DP_MON_PURGE_TIMEOUT_MS 10023#define DP_MON_SERVICE_BUDGET 12824 25struct dp_srng {26 u32 *vaddr_unaligned;27 u32 *vaddr;28 dma_addr_t paddr_unaligned;29 dma_addr_t paddr;30 int size;31 u32 ring_id;32};33 34struct dp_rxdma_mon_ring {35 struct dp_srng refill_buf_ring;36 struct idr bufs_idr;37 /* Protects bufs_idr */38 spinlock_t idr_lock;39 int bufs_max;40};41 42struct dp_rxdma_ring {43 struct dp_srng refill_buf_ring;44 int bufs_max;45};46 47#define ATH12K_TX_COMPL_NEXT(x) (((x) + 1) % DP_TX_COMP_RING_SIZE)48 49struct dp_tx_ring {50 u8 tcl_data_ring_id;51 struct dp_srng tcl_data_ring;52 struct dp_srng tcl_comp_ring;53 struct hal_wbm_completion_ring_tx *tx_status;54 int tx_status_head;55 int tx_status_tail;56};57 58struct ath12k_pdev_mon_stats {59 u32 status_ppdu_state;60 u32 status_ppdu_start;61 u32 status_ppdu_end;62 u32 status_ppdu_compl;63 u32 status_ppdu_start_mis;64 u32 status_ppdu_end_mis;65 u32 status_ppdu_done;66 u32 dest_ppdu_done;67 u32 dest_mpdu_done;68 u32 dest_mpdu_drop;69 u32 dup_mon_linkdesc_cnt;70 u32 dup_mon_buf_cnt;71};72 73struct dp_link_desc_bank {74 void *vaddr_unaligned;75 void *vaddr;76 dma_addr_t paddr_unaligned;77 dma_addr_t paddr;78 u32 size;79};80 81/* Size to enforce scatter idle list mode */82#define DP_LINK_DESC_ALLOC_SIZE_THRESH 0x20000083#define DP_LINK_DESC_BANKS_MAX 884 85#define DP_LINK_DESC_START 0x400086#define DP_LINK_DESC_SHIFT 387 88#define DP_LINK_DESC_COOKIE_SET(id, page) \89 ((((id) + DP_LINK_DESC_START) << DP_LINK_DESC_SHIFT) | (page))90 91#define DP_LINK_DESC_BANK_MASK GENMASK(2, 0)92 93#define DP_RX_DESC_COOKIE_INDEX_MAX 0x3ffff94#define DP_RX_DESC_COOKIE_POOL_ID_MAX 0x1c000095#define DP_RX_DESC_COOKIE_MAX \96 (DP_RX_DESC_COOKIE_INDEX_MAX | DP_RX_DESC_COOKIE_POOL_ID_MAX)97#define DP_NOT_PPDU_ID_WRAP_AROUND 2000098 99enum ath12k_dp_ppdu_state {100 DP_PPDU_STATUS_START,101 DP_PPDU_STATUS_DONE,102};103 104struct dp_mon_mpdu {105 struct list_head list;106 struct sk_buff *head;107 struct sk_buff *tail;108};109 110#define DP_MON_MAX_STATUS_BUF 32111 112struct ath12k_mon_data {113 struct dp_link_desc_bank link_desc_banks[DP_LINK_DESC_BANKS_MAX];114 struct hal_rx_mon_ppdu_info mon_ppdu_info;115 116 u32 mon_ppdu_status;117 u32 mon_last_buf_cookie;118 u64 mon_last_linkdesc_paddr;119 u16 chan_noise_floor;120 121 struct ath12k_pdev_mon_stats rx_mon_stats;122 /* lock for monitor data */123 spinlock_t mon_lock;124 struct sk_buff_head rx_status_q;125 struct dp_mon_mpdu *mon_mpdu;126 struct list_head dp_rx_mon_mpdu_list;127 struct sk_buff *dest_skb_q[DP_MON_MAX_STATUS_BUF];128 struct dp_mon_tx_ppdu_info *tx_prot_ppdu_info;129 struct dp_mon_tx_ppdu_info *tx_data_ppdu_info;130};131 132struct ath12k_pdev_dp {133 u32 mac_id;134 atomic_t num_tx_pending;135 wait_queue_head_t tx_empty_waitq;136 struct dp_srng rxdma_mon_dst_ring[MAX_RXDMA_PER_PDEV];137 struct dp_srng tx_mon_dst_ring[MAX_RXDMA_PER_PDEV];138 139 struct ieee80211_rx_status rx_status;140 struct ath12k_mon_data mon_data;141};142 143#define DP_NUM_CLIENTS_MAX 64144#define DP_AVG_TIDS_PER_CLIENT 2145#define DP_NUM_TIDS_MAX (DP_NUM_CLIENTS_MAX * DP_AVG_TIDS_PER_CLIENT)146#define DP_AVG_MSDUS_PER_FLOW 128147#define DP_AVG_FLOWS_PER_TID 2148#define DP_AVG_MPDUS_PER_TID_MAX 128149#define DP_AVG_MSDUS_PER_MPDU 4150 151#define DP_RX_HASH_ENABLE 1 /* Enable hash based Rx steering */152 153#define DP_BA_WIN_SZ_MAX 1024154 155#define DP_TCL_NUM_RING_MAX 4156 157#define DP_IDLE_SCATTER_BUFS_MAX 16158 159#define DP_WBM_RELEASE_RING_SIZE 64160#define DP_TCL_DATA_RING_SIZE 512161#define DP_TX_COMP_RING_SIZE 32768162#define DP_TX_IDR_SIZE DP_TX_COMP_RING_SIZE163#define DP_TCL_CMD_RING_SIZE 32164#define DP_TCL_STATUS_RING_SIZE 32165#define DP_REO_DST_RING_MAX 8166#define DP_REO_DST_RING_SIZE 2048167#define DP_REO_REINJECT_RING_SIZE 32168#define DP_RX_RELEASE_RING_SIZE 1024169#define DP_REO_EXCEPTION_RING_SIZE 128170#define DP_REO_CMD_RING_SIZE 128171#define DP_REO_STATUS_RING_SIZE 2048172#define DP_RXDMA_BUF_RING_SIZE 4096173#define DP_RX_MAC_BUF_RING_SIZE 2048174#define DP_RXDMA_REFILL_RING_SIZE 2048175#define DP_RXDMA_ERR_DST_RING_SIZE 1024176#define DP_RXDMA_MON_STATUS_RING_SIZE 1024177#define DP_RXDMA_MONITOR_BUF_RING_SIZE 4096178#define DP_RXDMA_MONITOR_DST_RING_SIZE 2048179#define DP_RXDMA_MONITOR_DESC_RING_SIZE 4096180#define DP_TX_MONITOR_BUF_RING_SIZE 4096181#define DP_TX_MONITOR_DEST_RING_SIZE 2048182 183#define DP_TX_MONITOR_BUF_SIZE 2048184#define DP_TX_MONITOR_BUF_SIZE_MIN 48185#define DP_TX_MONITOR_BUF_SIZE_MAX 8192186 187#define DP_RX_BUFFER_SIZE 2048188#define DP_RX_BUFFER_SIZE_LITE 1024189#define DP_RX_BUFFER_ALIGN_SIZE 128190 191#define DP_RXDMA_BUF_COOKIE_BUF_ID GENMASK(17, 0)192#define DP_RXDMA_BUF_COOKIE_PDEV_ID GENMASK(19, 18)193 194#define DP_HW2SW_MACID(mac_id) ({ typeof(mac_id) x = (mac_id); x ? x - 1 : 0; })195#define DP_SW2HW_MACID(mac_id) ((mac_id) + 1)196 197#define DP_TX_DESC_ID_MAC_ID GENMASK(1, 0)198#define DP_TX_DESC_ID_MSDU_ID GENMASK(18, 2)199#define DP_TX_DESC_ID_POOL_ID GENMASK(20, 19)200 201#define ATH12K_SHADOW_DP_TIMER_INTERVAL 20202#define ATH12K_SHADOW_CTRL_TIMER_INTERVAL 10203 204#define ATH12K_NUM_POOL_TX_DESC 32768205 206/* TODO: revisit this count during testing */207#define ATH12K_RX_DESC_COUNT (12288)208 209#define ATH12K_PAGE_SIZE PAGE_SIZE210 211/* Total 1024 entries in PPT, i.e 4K/4 considering 4K aligned212 * SPT pages which makes lower 12bits 0213 */214#define ATH12K_MAX_PPT_ENTRIES 1024215 216/* Total 512 entries in a SPT, i.e 4K Page/8 */217#define ATH12K_MAX_SPT_ENTRIES 512218 219#define ATH12K_NUM_RX_SPT_PAGES ((ATH12K_RX_DESC_COUNT) / ATH12K_MAX_SPT_ENTRIES)220 221#define ATH12K_TX_SPT_PAGES_PER_POOL (ATH12K_NUM_POOL_TX_DESC / \222 ATH12K_MAX_SPT_ENTRIES)223#define ATH12K_NUM_TX_SPT_PAGES (ATH12K_TX_SPT_PAGES_PER_POOL * ATH12K_HW_MAX_QUEUES)224#define ATH12K_NUM_SPT_PAGES (ATH12K_NUM_RX_SPT_PAGES + ATH12K_NUM_TX_SPT_PAGES)225 226#define ATH12K_TX_SPT_PAGE_OFFSET 0227#define ATH12K_RX_SPT_PAGE_OFFSET ATH12K_NUM_TX_SPT_PAGES228 229/* The SPT pages are divided for RX and TX, first block for RX230 * and remaining for TX231 */232#define ATH12K_NUM_TX_SPT_PAGE_START ATH12K_NUM_RX_SPT_PAGES233 234#define ATH12K_DP_RX_DESC_MAGIC 0xBABABABA235 236/* 4K aligned address have last 12 bits set to 0, this check is done237 * so that two spt pages address can be stored per 8bytes238 * of CMEM (PPT)239 */240#define ATH12K_SPT_4K_ALIGN_CHECK 0xFFF241#define ATH12K_SPT_4K_ALIGN_OFFSET 12242#define ATH12K_PPT_ADDR_OFFSET(ppt_index) (4 * (ppt_index))243 244/* To indicate HW of CMEM address, b0-31 are cmem base received via QMI */245#define ATH12K_CMEM_ADDR_MSB 0x10246 247/* Of 20 bits cookie, b0-b8 is to indicate SPT offset and b9-19 for PPT */248#define ATH12K_CC_SPT_MSB 8249#define ATH12K_CC_PPT_MSB 19250#define ATH12K_CC_PPT_SHIFT 9251#define ATH12K_DP_CC_COOKIE_SPT GENMASK(8, 0)252#define ATH12K_DP_CC_COOKIE_PPT GENMASK(19, 9)253 254#define DP_REO_QREF_NUM GENMASK(31, 16)255#define DP_MAX_PEER_ID 2047256 257/* Total size of the LUT is based on 2K peers, each having reference258 * for 17tids, note each entry is of type ath12k_reo_queue_ref259 * hence total size is 2048 * 17 * 8 = 278528260 */261#define DP_REOQ_LUT_SIZE 278528262 263/* Invalid TX Bank ID value */264#define DP_INVALID_BANK_ID -1265 266struct ath12k_dp_tx_bank_profile {267 u8 is_configured;268 u32 num_users;269 u32 bank_config;270};271 272struct ath12k_hp_update_timer {273 struct timer_list timer;274 bool started;275 bool init;276 u32 tx_num;277 u32 timer_tx_num;278 u32 ring_id;279 u32 interval;280 struct ath12k_base *ab;281};282 283struct ath12k_rx_desc_info {284 struct list_head list;285 struct sk_buff *skb;286 u32 cookie;287 u32 magic;288 u8 in_use : 1,289 reserved : 7;290};291 292struct ath12k_tx_desc_info {293 struct list_head list;294 struct sk_buff *skb;295 u32 desc_id; /* Cookie */296 u8 mac_id;297 u8 pool_id;298};299 300struct ath12k_spt_info {301 dma_addr_t paddr;302 u64 *vaddr;303 struct ath12k_rx_desc_info *rxbaddr[ATH12K_NUM_RX_SPT_PAGES];304 struct ath12k_tx_desc_info *txbaddr[ATH12K_NUM_TX_SPT_PAGES];305};306 307struct ath12k_reo_queue_ref {308 u32 info0;309 u32 info1;310} __packed;311 312struct ath12k_reo_q_addr_lut {313 dma_addr_t paddr;314 u32 *vaddr;315};316 317struct ath12k_dp {318 struct ath12k_base *ab;319 u8 num_bank_profiles;320 /* protects the access and update of bank_profiles */321 spinlock_t tx_bank_lock;322 struct ath12k_dp_tx_bank_profile *bank_profiles;323 enum ath12k_htc_ep_id eid;324 struct completion htt_tgt_version_received;325 u8 htt_tgt_ver_major;326 u8 htt_tgt_ver_minor;327 struct dp_link_desc_bank link_desc_banks[DP_LINK_DESC_BANKS_MAX];328 enum hal_rx_buf_return_buf_manager idle_link_rbm;329 struct dp_srng wbm_idle_ring;330 struct dp_srng wbm_desc_rel_ring;331 struct dp_srng reo_reinject_ring;332 struct dp_srng rx_rel_ring;333 struct dp_srng reo_except_ring;334 struct dp_srng reo_cmd_ring;335 struct dp_srng reo_status_ring;336 enum ath12k_peer_metadata_version peer_metadata_ver;337 struct dp_srng reo_dst_ring[DP_REO_DST_RING_MAX];338 struct dp_tx_ring tx_ring[DP_TCL_NUM_RING_MAX];339 struct hal_wbm_idle_scatter_list scatter_list[DP_IDLE_SCATTER_BUFS_MAX];340 struct list_head reo_cmd_list;341 struct list_head reo_cmd_cache_flush_list;342 u32 reo_cmd_cache_flush_count;343 344 /* protects access to below fields,345 * - reo_cmd_list346 * - reo_cmd_cache_flush_list347 * - reo_cmd_cache_flush_count348 */349 spinlock_t reo_cmd_lock;350 struct ath12k_hp_update_timer reo_cmd_timer;351 struct ath12k_hp_update_timer tx_ring_timer[DP_TCL_NUM_RING_MAX];352 struct ath12k_spt_info *spt_info;353 u32 num_spt_pages;354 u32 rx_ppt_base;355 struct list_head rx_desc_free_list;356 /* protects the free desc list */357 spinlock_t rx_desc_lock;358 359 struct list_head tx_desc_free_list[ATH12K_HW_MAX_QUEUES];360 struct list_head tx_desc_used_list[ATH12K_HW_MAX_QUEUES];361 /* protects the free and used desc lists */362 spinlock_t tx_desc_lock[ATH12K_HW_MAX_QUEUES];363 364 struct dp_rxdma_ring rx_refill_buf_ring;365 struct dp_srng rx_mac_buf_ring[MAX_RXDMA_PER_PDEV];366 struct dp_srng rxdma_err_dst_ring[MAX_RXDMA_PER_PDEV];367 struct dp_rxdma_mon_ring rxdma_mon_buf_ring;368 struct dp_rxdma_mon_ring tx_mon_buf_ring;369 struct ath12k_reo_q_addr_lut reoq_lut;370};371 372/* HTT definitions */373 374#define HTT_TCL_META_DATA_TYPE BIT(0)375#define HTT_TCL_META_DATA_VALID_HTT BIT(1)376 377/* vdev meta data */378#define HTT_TCL_META_DATA_VDEV_ID GENMASK(9, 2)379#define HTT_TCL_META_DATA_PDEV_ID GENMASK(11, 10)380#define HTT_TCL_META_DATA_HOST_INSPECTED BIT(12)381 382/* peer meta data */383#define HTT_TCL_META_DATA_PEER_ID GENMASK(15, 2)384 385/* HTT tx completion is overlaid in wbm_release_ring */386#define HTT_TX_WBM_COMP_INFO0_STATUS GENMASK(16, 13)387#define HTT_TX_WBM_COMP_INFO1_REINJECT_REASON GENMASK(3, 0)388#define HTT_TX_WBM_COMP_INFO1_EXCEPTION_FRAME BIT(4)389 390#define HTT_TX_WBM_COMP_INFO2_ACK_RSSI GENMASK(31, 24)391 392struct htt_tx_wbm_completion {393 __le32 rsvd0[2];394 __le32 info0;395 __le32 info1;396 __le32 info2;397 __le32 info3;398 __le32 info4;399 __le32 rsvd1;400 401} __packed;402 403enum htt_h2t_msg_type {404 HTT_H2T_MSG_TYPE_VERSION_REQ = 0,405 HTT_H2T_MSG_TYPE_SRING_SETUP = 0xb,406 HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG = 0xc,407 HTT_H2T_MSG_TYPE_EXT_STATS_CFG = 0x10,408 HTT_H2T_MSG_TYPE_PPDU_STATS_CFG = 0x11,409 HTT_H2T_MSG_TYPE_VDEV_TXRX_STATS_CFG = 0x1a,410 HTT_H2T_MSG_TYPE_TX_MONITOR_CFG = 0x1b,411};412 413#define HTT_VER_REQ_INFO_MSG_ID GENMASK(7, 0)414 415struct htt_ver_req_cmd {416 __le32 ver_reg_info;417} __packed;418 419enum htt_srng_ring_type {420 HTT_HW_TO_SW_RING,421 HTT_SW_TO_HW_RING,422 HTT_SW_TO_SW_RING,423};424 425enum htt_srng_ring_id {426 HTT_RXDMA_HOST_BUF_RING,427 HTT_RXDMA_MONITOR_STATUS_RING,428 HTT_RXDMA_MONITOR_BUF_RING,429 HTT_RXDMA_MONITOR_DESC_RING,430 HTT_RXDMA_MONITOR_DEST_RING,431 HTT_HOST1_TO_FW_RXBUF_RING,432 HTT_HOST2_TO_FW_RXBUF_RING,433 HTT_RXDMA_NON_MONITOR_DEST_RING,434 HTT_TX_MON_HOST2MON_BUF_RING,435 HTT_TX_MON_MON2HOST_DEST_RING,436};437 438/* host -> target HTT_SRING_SETUP message439 *440 * After target is booted up, Host can send SRING setup message for441 * each host facing LMAC SRING. Target setups up HW registers based442 * on setup message and confirms back to Host if response_required is set.443 * Host should wait for confirmation message before sending new SRING444 * setup message445 *446 * The message would appear as follows:447 *448 * |31 24|23 20|19|18 16|15|14 8|7 0|449 * |--------------- +-----------------+----------------+------------------|450 * | ring_type | ring_id | pdev_id | msg_type |451 * |----------------------------------------------------------------------|452 * | ring_base_addr_lo |453 * |----------------------------------------------------------------------|454 * | ring_base_addr_hi |455 * |----------------------------------------------------------------------|456 * |ring_misc_cfg_flag|ring_entry_size| ring_size |457 * |----------------------------------------------------------------------|458 * | ring_head_offset32_remote_addr_lo |459 * |----------------------------------------------------------------------|460 * | ring_head_offset32_remote_addr_hi |461 * |----------------------------------------------------------------------|462 * | ring_tail_offset32_remote_addr_lo |463 * |----------------------------------------------------------------------|464 * | ring_tail_offset32_remote_addr_hi |465 * |----------------------------------------------------------------------|466 * | ring_msi_addr_lo |467 * |----------------------------------------------------------------------|468 * | ring_msi_addr_hi |469 * |----------------------------------------------------------------------|470 * | ring_msi_data |471 * |----------------------------------------------------------------------|472 * | intr_timer_th |IM| intr_batch_counter_th |473 * |----------------------------------------------------------------------|474 * | reserved |RR|PTCF| intr_low_threshold |475 * |----------------------------------------------------------------------|476 * Where477 * IM = sw_intr_mode478 * RR = response_required479 * PTCF = prefetch_timer_cfg480 *481 * The message is interpreted as follows:482 * dword0 - b'0:7 - msg_type: This will be set to483 * HTT_H2T_MSG_TYPE_SRING_SETUP484 * b'8:15 - pdev_id:485 * 0 (for rings at SOC/UMAC level),486 * 1/2/3 mac id (for rings at LMAC level)487 * b'16:23 - ring_id: identify which ring is to setup,488 * more details can be got from enum htt_srng_ring_id489 * b'24:31 - ring_type: identify type of host rings,490 * more details can be got from enum htt_srng_ring_type491 * dword1 - b'0:31 - ring_base_addr_lo: Lower 32bits of ring base address492 * dword2 - b'0:31 - ring_base_addr_hi: Upper 32bits of ring base address493 * dword3 - b'0:15 - ring_size: size of the ring in unit of 4-bytes words494 * b'16:23 - ring_entry_size: Size of each entry in 4-byte word units495 * b'24:31 - ring_misc_cfg_flag: Valid only for HW_TO_SW_RING and496 * SW_TO_HW_RING.497 * Refer to HTT_SRING_SETUP_RING_MISC_CFG_RING defs.498 * dword4 - b'0:31 - ring_head_off32_remote_addr_lo:499 * Lower 32 bits of memory address of the remote variable500 * storing the 4-byte word offset that identifies the head501 * element within the ring.502 * (The head offset variable has type u32.)503 * Valid for HW_TO_SW and SW_TO_SW rings.504 * dword5 - b'0:31 - ring_head_off32_remote_addr_hi:505 * Upper 32 bits of memory address of the remote variable506 * storing the 4-byte word offset that identifies the head507 * element within the ring.508 * (The head offset variable has type u32.)509 * Valid for HW_TO_SW and SW_TO_SW rings.510 * dword6 - b'0:31 - ring_tail_off32_remote_addr_lo:511 * Lower 32 bits of memory address of the remote variable512 * storing the 4-byte word offset that identifies the tail513 * element within the ring.514 * (The tail offset variable has type u32.)515 * Valid for HW_TO_SW and SW_TO_SW rings.516 * dword7 - b'0:31 - ring_tail_off32_remote_addr_hi:517 * Upper 32 bits of memory address of the remote variable518 * storing the 4-byte word offset that identifies the tail519 * element within the ring.520 * (The tail offset variable has type u32.)521 * Valid for HW_TO_SW and SW_TO_SW rings.522 * dword8 - b'0:31 - ring_msi_addr_lo: Lower 32bits of MSI cfg address523 * valid only for HW_TO_SW_RING and SW_TO_HW_RING524 * dword9 - b'0:31 - ring_msi_addr_hi: Upper 32bits of MSI cfg address525 * valid only for HW_TO_SW_RING and SW_TO_HW_RING526 * dword10 - b'0:31 - ring_msi_data: MSI data527 * Refer to HTT_SRING_SETUP_RING_MSC_CFG_xxx defs528 * valid only for HW_TO_SW_RING and SW_TO_HW_RING529 * dword11 - b'0:14 - intr_batch_counter_th:530 * batch counter threshold is in units of 4-byte words.531 * HW internally maintains and increments batch count.532 * (see SRING spec for detail description).533 * When batch count reaches threshold value, an interrupt534 * is generated by HW.535 * b'15 - sw_intr_mode:536 * This configuration shall be static.537 * Only programmed at power up.538 * 0: generate pulse style sw interrupts539 * 1: generate level style sw interrupts540 * b'16:31 - intr_timer_th:541 * The timer init value when timer is idle or is542 * initialized to start downcounting.543 * In 8us units (to cover a range of 0 to 524 ms)544 * dword12 - b'0:15 - intr_low_threshold:545 * Used only by Consumer ring to generate ring_sw_int_p.546 * Ring entries low threshold water mark, that is used547 * in combination with the interrupt timer as well as548 * the clearing of the level interrupt.549 * b'16:18 - prefetch_timer_cfg:550 * Used only by Consumer ring to set timer mode to551 * support Application prefetch handling.552 * The external tail offset/pointer will be updated553 * at following intervals:554 * 3'b000: (Prefetch feature disabled; used only for debug)555 * 3'b001: 1 usec556 * 3'b010: 4 usec557 * 3'b011: 8 usec (default)558 * 3'b100: 16 usec559 * Others: Reserved560 * b'19 - response_required:561 * Host needs HTT_T2H_MSG_TYPE_SRING_SETUP_DONE as response562 * b'20:31 - reserved: reserved for future use563 */564 565#define HTT_SRNG_SETUP_CMD_INFO0_MSG_TYPE GENMASK(7, 0)566#define HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID GENMASK(15, 8)567#define HTT_SRNG_SETUP_CMD_INFO0_RING_ID GENMASK(23, 16)568#define HTT_SRNG_SETUP_CMD_INFO0_RING_TYPE GENMASK(31, 24)569 570#define HTT_SRNG_SETUP_CMD_INFO1_RING_SIZE GENMASK(15, 0)571#define HTT_SRNG_SETUP_CMD_INFO1_RING_ENTRY_SIZE GENMASK(23, 16)572#define HTT_SRNG_SETUP_CMD_INFO1_RING_LOOP_CNT_DIS BIT(25)573#define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_MSI_SWAP BIT(27)574#define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_HOST_FW_SWAP BIT(28)575#define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_TLV_SWAP BIT(29)576 577#define HTT_SRNG_SETUP_CMD_INTR_INFO_BATCH_COUNTER_THRESH GENMASK(14, 0)578#define HTT_SRNG_SETUP_CMD_INTR_INFO_SW_INTR_MODE BIT(15)579#define HTT_SRNG_SETUP_CMD_INTR_INFO_INTR_TIMER_THRESH GENMASK(31, 16)580 581#define HTT_SRNG_SETUP_CMD_INFO2_INTR_LOW_THRESH GENMASK(15, 0)582#define HTT_SRNG_SETUP_CMD_INFO2_PRE_FETCH_TIMER_CFG GENMASK(18, 16)583#define HTT_SRNG_SETUP_CMD_INFO2_RESPONSE_REQUIRED BIT(19)584 585struct htt_srng_setup_cmd {586 __le32 info0;587 __le32 ring_base_addr_lo;588 __le32 ring_base_addr_hi;589 __le32 info1;590 __le32 ring_head_off32_remote_addr_lo;591 __le32 ring_head_off32_remote_addr_hi;592 __le32 ring_tail_off32_remote_addr_lo;593 __le32 ring_tail_off32_remote_addr_hi;594 __le32 ring_msi_addr_lo;595 __le32 ring_msi_addr_hi;596 __le32 msi_data;597 __le32 intr_info;598 __le32 info2;599} __packed;600 601/* host -> target FW PPDU_STATS config message602 *603 * @details604 * The following field definitions describe the format of the HTT host605 * to target FW for PPDU_STATS_CFG msg.606 * The message allows the host to configure the PPDU_STATS_IND messages607 * produced by the target.608 *609 * |31 24|23 16|15 8|7 0|610 * |-----------------------------------------------------------|611 * | REQ bit mask | pdev_mask | msg type |612 * |-----------------------------------------------------------|613 * Header fields:614 * - MSG_TYPE615 * Bits 7:0616 * Purpose: identifies this is a req to configure ppdu_stats_ind from target617 * Value: 0x11618 * - PDEV_MASK619 * Bits 8:15620 * Purpose: identifies which pdevs this PPDU stats configuration applies to621 * Value: This is a overloaded field, refer to usage and interpretation of622 * PDEV in interface document.623 * Bit 8 : Reserved for SOC stats624 * Bit 9 - 15 : Indicates PDEV_MASK in DBDC625 * Indicates MACID_MASK in DBS626 * - REQ_TLV_BIT_MASK627 * Bits 16:31628 * Purpose: each set bit indicates the corresponding PPDU stats TLV type629 * needs to be included in the target's PPDU_STATS_IND messages.630 * Value: refer htt_ppdu_stats_tlv_tag_t <<<???631 *632 */633 634struct htt_ppdu_stats_cfg_cmd {635 __le32 msg;636} __packed;637 638#define HTT_PPDU_STATS_CFG_MSG_TYPE GENMASK(7, 0)639#define HTT_PPDU_STATS_CFG_PDEV_ID GENMASK(15, 8)640#define HTT_PPDU_STATS_CFG_TLV_TYPE_BITMASK GENMASK(31, 16)641 642enum htt_ppdu_stats_tag_type {643 HTT_PPDU_STATS_TAG_COMMON,644 HTT_PPDU_STATS_TAG_USR_COMMON,645 HTT_PPDU_STATS_TAG_USR_RATE,646 HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_64,647 HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_256,648 HTT_PPDU_STATS_TAG_SCH_CMD_STATUS,649 HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON,650 HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_64,651 HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_256,652 HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS,653 HTT_PPDU_STATS_TAG_USR_COMPLTN_FLUSH,654 HTT_PPDU_STATS_TAG_USR_COMMON_ARRAY,655 HTT_PPDU_STATS_TAG_INFO,656 HTT_PPDU_STATS_TAG_TX_MGMTCTRL_PAYLOAD,657 658 /* New TLV's are added above to this line */659 HTT_PPDU_STATS_TAG_MAX,660};661 662#define HTT_PPDU_STATS_TAG_DEFAULT (BIT(HTT_PPDU_STATS_TAG_COMMON) \663 | BIT(HTT_PPDU_STATS_TAG_USR_COMMON) \664 | BIT(HTT_PPDU_STATS_TAG_USR_RATE) \665 | BIT(HTT_PPDU_STATS_TAG_SCH_CMD_STATUS) \666 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON) \667 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS) \668 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_FLUSH) \669 | BIT(HTT_PPDU_STATS_TAG_USR_COMMON_ARRAY))670 671#define HTT_PPDU_STATS_TAG_PKTLOG (BIT(HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_64) | \672 BIT(HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_256) | \673 BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_64) | \674 BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_256) | \675 BIT(HTT_PPDU_STATS_TAG_INFO) | \676 BIT(HTT_PPDU_STATS_TAG_TX_MGMTCTRL_PAYLOAD) | \677 HTT_PPDU_STATS_TAG_DEFAULT)678 679enum htt_stats_internal_ppdu_frametype {680 HTT_STATS_PPDU_FTYPE_CTRL,681 HTT_STATS_PPDU_FTYPE_DATA,682 HTT_STATS_PPDU_FTYPE_BAR,683 HTT_STATS_PPDU_FTYPE_MAX684};685 686/* HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG Message687 *688 * details:689 * HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG message is sent by host to690 * configure RXDMA rings.691 * The configuration is per ring based and includes both packet subtypes692 * and PPDU/MPDU TLVs.693 *694 * The message would appear as follows:695 *696 * |31 26|25|24|23 16|15 8|7 0|697 * |-----------------+----------------+----------------+---------------|698 * | rsvd1 |PS|SS| ring_id | pdev_id | msg_type |699 * |-------------------------------------------------------------------|700 * | rsvd2 | ring_buffer_size |701 * |-------------------------------------------------------------------|702 * | packet_type_enable_flags_0 |703 * |-------------------------------------------------------------------|704 * | packet_type_enable_flags_1 |705 * |-------------------------------------------------------------------|706 * | packet_type_enable_flags_2 |707 * |-------------------------------------------------------------------|708 * | packet_type_enable_flags_3 |709 * |-------------------------------------------------------------------|710 * | tlv_filter_in_flags |711 * |-------------------------------------------------------------------|712 * Where:713 * PS = pkt_swap714 * SS = status_swap715 * The message is interpreted as follows:716 * dword0 - b'0:7 - msg_type: This will be set to717 * HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG718 * b'8:15 - pdev_id:719 * 0 (for rings at SOC/UMAC level),720 * 1/2/3 mac id (for rings at LMAC level)721 * b'16:23 - ring_id : Identify the ring to configure.722 * More details can be got from enum htt_srng_ring_id723 * b'24 - status_swap: 1 is to swap status TLV724 * b'25 - pkt_swap: 1 is to swap packet TLV725 * b'26:31 - rsvd1: reserved for future use726 * dword1 - b'0:16 - ring_buffer_size: size of buffers referenced by rx ring,727 * in byte units.728 * Valid only for HW_TO_SW_RING and SW_TO_HW_RING729 * - b'16:31 - rsvd2: Reserved for future use730 * dword2 - b'0:31 - packet_type_enable_flags_0:731 * Enable MGMT packet from 0b0000 to 0b1001732 * bits from low to high: FP, MD, MO - 3 bits733 * FP: Filter_Pass734 * MD: Monitor_Direct735 * MO: Monitor_Other736 * 10 mgmt subtypes * 3 bits -> 30 bits737 * Refer to PKT_TYPE_ENABLE_FLAG0_xxx_MGMT_xxx defs738 * dword3 - b'0:31 - packet_type_enable_flags_1:739 * Enable MGMT packet from 0b1010 to 0b1111740 * bits from low to high: FP, MD, MO - 3 bits741 * Refer to PKT_TYPE_ENABLE_FLAG1_xxx_MGMT_xxx defs742 * dword4 - b'0:31 - packet_type_enable_flags_2:743 * Enable CTRL packet from 0b0000 to 0b1001744 * bits from low to high: FP, MD, MO - 3 bits745 * Refer to PKT_TYPE_ENABLE_FLAG2_xxx_CTRL_xxx defs746 * dword5 - b'0:31 - packet_type_enable_flags_3:747 * Enable CTRL packet from 0b1010 to 0b1111,748 * MCAST_DATA, UCAST_DATA, NULL_DATA749 * bits from low to high: FP, MD, MO - 3 bits750 * Refer to PKT_TYPE_ENABLE_FLAG3_xxx_CTRL_xxx defs751 * dword6 - b'0:31 - tlv_filter_in_flags:752 * Filter in Attention/MPDU/PPDU/Header/User tlvs753 * Refer to CFG_TLV_FILTER_IN_FLAG defs754 */755 756#define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE GENMASK(7, 0)757#define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID GENMASK(15, 8)758#define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_RING_ID GENMASK(23, 16)759#define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_SS BIT(24)760#define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PS BIT(25)761#define HTT_RX_RING_SELECTION_CFG_CMD_INFO1_BUF_SIZE GENMASK(15, 0)762#define HTT_RX_RING_SELECTION_CFG_CMD_OFFSET_VALID BIT(26)763 764#define HTT_RX_RING_SELECTION_CFG_RX_PACKET_OFFSET GENMASK(15, 0)765#define HTT_RX_RING_SELECTION_CFG_RX_HEADER_OFFSET GENMASK(31, 16)766#define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_OFFSET GENMASK(15, 0)767#define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_OFFSET GENMASK(31, 16)768#define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_OFFSET GENMASK(15, 0)769#define HTT_RX_RING_SELECTION_CFG_RX_MSDU_START_OFFSET GENMASK(31, 16)770#define HTT_RX_RING_SELECTION_CFG_RX_ATTENTION_OFFSET GENMASK(15, 0)771 772#define HTT_RX_RING_SELECTION_CFG_WORD_MASK_COMPACT_SET BIT(23)773#define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_MASK GENMASK(15, 0)774#define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_MASK GENMASK(18, 16)775#define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_MASK GENMASK(16, 0)776 777enum htt_rx_filter_tlv_flags {778 HTT_RX_FILTER_TLV_FLAGS_MPDU_START = BIT(0),779 HTT_RX_FILTER_TLV_FLAGS_MSDU_START = BIT(1),780 HTT_RX_FILTER_TLV_FLAGS_RX_PACKET = BIT(2),781 HTT_RX_FILTER_TLV_FLAGS_MSDU_END = BIT(3),782 HTT_RX_FILTER_TLV_FLAGS_MPDU_END = BIT(4),783 HTT_RX_FILTER_TLV_FLAGS_PACKET_HEADER = BIT(5),784 HTT_RX_FILTER_TLV_FLAGS_PER_MSDU_HEADER = BIT(6),785 HTT_RX_FILTER_TLV_FLAGS_ATTENTION = BIT(7),786 HTT_RX_FILTER_TLV_FLAGS_PPDU_START = BIT(8),787 HTT_RX_FILTER_TLV_FLAGS_PPDU_END = BIT(9),788 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS = BIT(10),789 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT = BIT(11),790 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE = BIT(12),791};792 793enum htt_rx_mgmt_pkt_filter_tlv_flags0 {794 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(0),795 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(1),796 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(2),797 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(3),798 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(4),799 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(5),800 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(6),801 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(7),802 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(8),803 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(9),804 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(10),805 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(11),806 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(12),807 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(13),808 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(14),809 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(15),810 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(16),811 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(17),812 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(18),813 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(19),814 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(20),815 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(21),816 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(22),817 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(23),818 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(24),819 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(25),820 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(26),821 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(27),822 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(28),823 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(29),824};825 826enum htt_rx_mgmt_pkt_filter_tlv_flags1 {827 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(0),828 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(1),829 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(2),830 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(3),831 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(4),832 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(5),833 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(6),834 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(7),835 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(8),836 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(9),837 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(10),838 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(11),839 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(12),840 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(13),841 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(14),842 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(15),843 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(16),844 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(17),845};846 847enum htt_rx_ctrl_pkt_filter_tlv_flags2 {848 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(0),849 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(1),850 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(2),851 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(3),852 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(4),853 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(5),854 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(6),855 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(7),856 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(8),857 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(9),858 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(10),859 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(11),860 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(12),861 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(13),862 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(14),863 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(15),864 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(16),865 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(17),866 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(18),867 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(19),868 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(20),869 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(21),870 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(22),871 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(23),872 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(24),873 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(25),874 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(26),875 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(27),876 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(28),877 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(29),878};879 880enum htt_rx_ctrl_pkt_filter_tlv_flags3 {881 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(0),882 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(1),883 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(2),884 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(3),885 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(4),886 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(5),887 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(6),888 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(7),889 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(8),890 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(9),891 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(10),892 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(11),893 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(12),894 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(13),895 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(14),896 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(15),897 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(16),898 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(17),899};900 901enum htt_rx_data_pkt_filter_tlv_flasg3 {902 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(18),903 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(19),904 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(20),905 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(21),906 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(22),907 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(23),908 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(24),909 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(25),910 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(26),911};912 913#define HTT_RX_FP_MGMT_FILTER_FLAGS0 \914 (HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \915 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \916 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \917 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \918 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \919 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \920 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \921 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \922 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM)923 924#define HTT_RX_MD_MGMT_FILTER_FLAGS0 \925 (HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \926 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \927 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \928 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \929 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \930 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \931 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \932 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \933 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM)934 935#define HTT_RX_MO_MGMT_FILTER_FLAGS0 \936 (HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \937 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \938 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \939 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \940 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \941 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \942 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \943 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \944 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM)945 946#define HTT_RX_FP_MGMT_FILTER_FLAGS1 (HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \947 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \948 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \949 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \950 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK)951 952#define HTT_RX_MD_MGMT_FILTER_FLAGS1 (HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \953 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \954 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \955 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \956 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK)957 958#define HTT_RX_MO_MGMT_FILTER_FLAGS1 (HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \959 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \960 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \961 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \962 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK)963 964#define HTT_RX_FP_CTRL_FILTER_FLASG2 (HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \965 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \966 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BA)967 968#define HTT_RX_MD_CTRL_FILTER_FLASG2 (HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \969 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \970 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BA)971 972#define HTT_RX_MO_CTRL_FILTER_FLASG2 (HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \973 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \974 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BA)975 976#define HTT_RX_FP_CTRL_FILTER_FLASG3 (HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \977 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \978 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \979 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \980 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \981 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK)982 983#define HTT_RX_MD_CTRL_FILTER_FLASG3 (HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \984 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \985 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \986 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \987 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \988 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK)989 990#define HTT_RX_MO_CTRL_FILTER_FLASG3 (HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \991 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \992 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \993 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \994 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \995 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK)996 997#define HTT_RX_FP_DATA_FILTER_FLASG3 (HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST \998 | HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST \999 | HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA)1000 1001#define HTT_RX_MD_DATA_FILTER_FLASG3 (HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_MCAST \1002 | HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_UCAST \1003 | HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA)1004 1005#define HTT_RX_MO_DATA_FILTER_FLASG3 (HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_MCAST \1006 | HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_UCAST \1007 | HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA)1008 1009#define HTT_RX_MON_FP_MGMT_FILTER_FLAGS0 \1010 (HTT_RX_FP_MGMT_FILTER_FLAGS0 | \1011 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7)1012 1013#define HTT_RX_MON_MO_MGMT_FILTER_FLAGS0 \1014 (HTT_RX_MO_MGMT_FILTER_FLAGS0 | \1015 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7)1016 1017#define HTT_RX_MON_FP_MGMT_FILTER_FLAGS1 \1018 (HTT_RX_FP_MGMT_FILTER_FLAGS1 | \1019 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15)1020 1021#define HTT_RX_MON_MO_MGMT_FILTER_FLAGS1 \1022 (HTT_RX_MO_MGMT_FILTER_FLAGS1 | \1023 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15)1024 1025#define HTT_RX_MON_FP_CTRL_FILTER_FLASG2 \1026 (HTT_RX_FP_CTRL_FILTER_FLASG2 | \1027 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 | \1028 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 | \1029 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER | \1030 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 | \1031 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL | \1032 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP | \1033 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT)1034 1035#define HTT_RX_MON_MO_CTRL_FILTER_FLASG2 \1036 (HTT_RX_MO_CTRL_FILTER_FLASG2 | \1037 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 | \1038 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 | \1039 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER | \1040 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 | \1041 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL | \1042 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP | \1043 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT)1044 1045#define HTT_RX_MON_FP_CTRL_FILTER_FLASG3 HTT_RX_FP_CTRL_FILTER_FLASG31046 1047#define HTT_RX_MON_MO_CTRL_FILTER_FLASG3 HTT_RX_MO_CTRL_FILTER_FLASG31048 1049#define HTT_RX_MON_FP_DATA_FILTER_FLASG3 HTT_RX_FP_DATA_FILTER_FLASG31050 1051#define HTT_RX_MON_MO_DATA_FILTER_FLASG3 HTT_RX_MO_DATA_FILTER_FLASG31052 1053#define HTT_RX_MON_FILTER_TLV_FLAGS \1054 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \1055 HTT_RX_FILTER_TLV_FLAGS_PPDU_START | \1056 HTT_RX_FILTER_TLV_FLAGS_PPDU_END | \1057 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS | \1058 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT | \1059 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE)1060 1061#define HTT_RX_MON_FILTER_TLV_FLAGS_MON_STATUS_RING \1062 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \1063 HTT_RX_FILTER_TLV_FLAGS_PPDU_START | \1064 HTT_RX_FILTER_TLV_FLAGS_PPDU_END | \1065 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS | \1066 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT | \1067 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE)1068 1069#define HTT_RX_MON_FILTER_TLV_FLAGS_MON_BUF_RING \1070 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \1071 HTT_RX_FILTER_TLV_FLAGS_MSDU_START | \1072 HTT_RX_FILTER_TLV_FLAGS_RX_PACKET | \1073 HTT_RX_FILTER_TLV_FLAGS_MSDU_END | \1074 HTT_RX_FILTER_TLV_FLAGS_MPDU_END | \1075 HTT_RX_FILTER_TLV_FLAGS_PACKET_HEADER | \1076 HTT_RX_FILTER_TLV_FLAGS_PER_MSDU_HEADER | \1077 HTT_RX_FILTER_TLV_FLAGS_ATTENTION)1078 1079/* msdu start. mpdu end, attention, rx hdr tlv's are not subscribed */1080#define HTT_RX_TLV_FLAGS_RXDMA_RING \1081 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \1082 HTT_RX_FILTER_TLV_FLAGS_RX_PACKET | \1083 HTT_RX_FILTER_TLV_FLAGS_MSDU_END)1084 1085#define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE GENMASK(7, 0)1086#define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID GENMASK(15, 8)1087 1088struct htt_rx_ring_selection_cfg_cmd {1089 __le32 info0;1090 __le32 info1;1091 __le32 pkt_type_en_flags0;1092 __le32 pkt_type_en_flags1;1093 __le32 pkt_type_en_flags2;1094 __le32 pkt_type_en_flags3;1095 __le32 rx_filter_tlv;1096 __le32 rx_packet_offset;1097 __le32 rx_mpdu_offset;1098 __le32 rx_msdu_offset;1099 __le32 rx_attn_offset;1100 __le32 info2;1101 __le32 reserved[2];1102 __le32 rx_mpdu_start_end_mask;1103 __le32 rx_msdu_end_word_mask;1104 __le32 info3;1105} __packed;1106 1107struct htt_rx_ring_tlv_filter {1108 u32 rx_filter; /* see htt_rx_filter_tlv_flags */1109 u32 pkt_filter_flags0; /* MGMT */1110 u32 pkt_filter_flags1; /* MGMT */1111 u32 pkt_filter_flags2; /* CTRL */1112 u32 pkt_filter_flags3; /* DATA */1113 bool offset_valid;1114 u16 rx_packet_offset;1115 u16 rx_header_offset;1116 u16 rx_mpdu_end_offset;1117 u16 rx_mpdu_start_offset;1118 u16 rx_msdu_end_offset;1119 u16 rx_msdu_start_offset;1120 u16 rx_attn_offset;1121 u16 rx_mpdu_start_wmask;1122 u16 rx_mpdu_end_wmask;1123 u32 rx_msdu_end_wmask;1124};1125 1126#define HTT_STATS_FRAME_CTRL_TYPE_MGMT 0x01127#define HTT_STATS_FRAME_CTRL_TYPE_CTRL 0x11128#define HTT_STATS_FRAME_CTRL_TYPE_DATA 0x21129#define HTT_STATS_FRAME_CTRL_TYPE_RESV 0x31130 1131#define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE GENMASK(7, 0)1132#define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID GENMASK(15, 8)1133#define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_RING_ID GENMASK(23, 16)1134#define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_SS BIT(24)1135#define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PS BIT(25)1136 1137#define HTT_TX_RING_SELECTION_CFG_CMD_INFO1_RING_BUFF_SIZE GENMASK(15, 0)1138#define HTT_TX_RING_SELECTION_CFG_CMD_INFO1_PKT_TYPE GENMASK(18, 16)1139#define HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_MGMT GENMASK(21, 19)1140#define HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_CTRL GENMASK(24, 22)1141#define HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_DATA GENMASK(27, 25)1142 1143#define HTT_TX_RING_SELECTION_CFG_CMD_INFO2_PKT_TYPE_EN_FLAG GENMASK(2, 0)1144 1145struct htt_tx_ring_selection_cfg_cmd {1146 __le32 info0;1147 __le32 info1;1148 __le32 info2;1149 __le32 tlv_filter_mask_in0;1150 __le32 tlv_filter_mask_in1;1151 __le32 tlv_filter_mask_in2;1152 __le32 tlv_filter_mask_in3;1153 __le32 reserved[3];1154} __packed;1155 1156#define HTT_TX_RING_TLV_FILTER_MGMT_DMA_LEN GENMASK(3, 0)1157#define HTT_TX_RING_TLV_FILTER_CTRL_DMA_LEN GENMASK(7, 4)1158#define HTT_TX_RING_TLV_FILTER_DATA_DMA_LEN GENMASK(11, 8)1159 1160#define HTT_TX_MON_FILTER_HYBRID_MODE \1161 (HTT_TX_FILTER_TLV_FLAGS0_RESPONSE_START_STATUS | \1162 HTT_TX_FILTER_TLV_FLAGS0_RESPONSE_END_STATUS | \1163 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START | \1164 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_END | \1165 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START_PPDU | \1166 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_USER_PPDU | \1167 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_ACK_OR_BA | \1168 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_1K_BA | \1169 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START_PROT | \1170 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_PROT | \1171 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_USER_RESPONSE | \1172 HTT_TX_FILTER_TLV_FLAGS0_RECEIVED_RESPONSE_INFO | \1173 HTT_TX_FILTER_TLV_FLAGS0_RECEIVED_RESPONSE_INFO_PART2)1174 1175struct htt_tx_ring_tlv_filter {1176 u32 tx_mon_downstream_tlv_flags;1177 u32 tx_mon_upstream_tlv_flags0;1178 u32 tx_mon_upstream_tlv_flags1;1179 u32 tx_mon_upstream_tlv_flags2;1180 bool tx_mon_mgmt_filter;1181 bool tx_mon_data_filter;1182 bool tx_mon_ctrl_filter;1183 u16 tx_mon_pkt_dma_len;1184} __packed;1185 1186enum htt_tx_mon_upstream_tlv_flags0 {1187 HTT_TX_FILTER_TLV_FLAGS0_RESPONSE_START_STATUS = BIT(1),1188 HTT_TX_FILTER_TLV_FLAGS0_RESPONSE_END_STATUS = BIT(2),1189 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START = BIT(3),1190 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_END = BIT(4),1191 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START_PPDU = BIT(5),1192 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_USER_PPDU = BIT(6),1193 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_ACK_OR_BA = BIT(7),1194 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_1K_BA = BIT(8),1195 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START_PROT = BIT(9),1196 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_PROT = BIT(10),1197 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_USER_RESPONSE = BIT(11),1198 HTT_TX_FILTER_TLV_FLAGS0_RX_FRAME_BITMAP_ACK = BIT(12),1199 HTT_TX_FILTER_TLV_FLAGS0_RX_FRAME_1K_BITMAP_ACK = BIT(13),1200 HTT_TX_FILTER_TLV_FLAGS0_COEX_TX_STATUS = BIT(14),1201 HTT_TX_FILTER_TLV_FLAGS0_RECEIVED_RESPONSE_INFO = BIT(15),1202 HTT_TX_FILTER_TLV_FLAGS0_RECEIVED_RESPONSE_INFO_PART2 = BIT(16),1203};1204 1205#define HTT_TX_FILTER_TLV_FLAGS2_TXPCU_PHYTX_OTHER_TRANSMIT_INFO32 BIT(11)1206 1207/* HTT message target->host */1208 1209enum htt_t2h_msg_type {1210 HTT_T2H_MSG_TYPE_VERSION_CONF,1211 HTT_T2H_MSG_TYPE_PEER_MAP = 0x3,1212 HTT_T2H_MSG_TYPE_PEER_UNMAP = 0x4,1213 HTT_T2H_MSG_TYPE_RX_ADDBA = 0x5,1214 HTT_T2H_MSG_TYPE_PKTLOG = 0x8,1215 HTT_T2H_MSG_TYPE_SEC_IND = 0xb,1216 HTT_T2H_MSG_TYPE_PEER_MAP2 = 0x1e,1217 HTT_T2H_MSG_TYPE_PEER_UNMAP2 = 0x1f,1218 HTT_T2H_MSG_TYPE_PPDU_STATS_IND = 0x1d,1219 HTT_T2H_MSG_TYPE_EXT_STATS_CONF = 0x1c,1220 HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND = 0x24,1221 HTT_T2H_MSG_TYPE_MLO_TIMESTAMP_OFFSET_IND = 0x28,1222 HTT_T2H_MSG_TYPE_PEER_MAP3 = 0x2b,1223 HTT_T2H_MSG_TYPE_VDEV_TXRX_STATS_PERIODIC_IND = 0x2c,1224};1225 1226#define HTT_TARGET_VERSION_MAJOR 31227 1228#define HTT_T2H_MSG_TYPE GENMASK(7, 0)1229#define HTT_T2H_VERSION_CONF_MINOR GENMASK(15, 8)1230#define HTT_T2H_VERSION_CONF_MAJOR GENMASK(23, 16)1231 1232struct htt_t2h_version_conf_msg {1233 __le32 version;1234} __packed;1235 1236#define HTT_T2H_PEER_MAP_INFO_VDEV_ID GENMASK(15, 8)1237#define HTT_T2H_PEER_MAP_INFO_PEER_ID GENMASK(31, 16)1238#define HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16 GENMASK(15, 0)1239#define HTT_T2H_PEER_MAP_INFO1_HW_PEER_ID GENMASK(31, 16)1240#define HTT_T2H_PEER_MAP_INFO2_AST_HASH_VAL GENMASK(15, 0)1241#define HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_M BIT(16)1242#define HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_S 161243 1244struct htt_t2h_peer_map_event {1245 __le32 info;1246 __le32 mac_addr_l32;1247 __le32 info1;1248 __le32 info2;1249} __packed;1250 1251#define HTT_T2H_PEER_UNMAP_INFO_VDEV_ID HTT_T2H_PEER_MAP_INFO_VDEV_ID1252#define HTT_T2H_PEER_UNMAP_INFO_PEER_ID HTT_T2H_PEER_MAP_INFO_PEER_ID1253#define HTT_T2H_PEER_UNMAP_INFO1_MAC_ADDR_H16 \1254 HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H161255#define HTT_T2H_PEER_MAP_INFO1_NEXT_HOP_M HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_M1256#define HTT_T2H_PEER_MAP_INFO1_NEXT_HOP_S HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_S1257 1258struct htt_t2h_peer_unmap_event {1259 __le32 info;1260 __le32 mac_addr_l32;1261 __le32 info1;1262} __packed;1263 1264struct htt_resp_msg {1265 union {1266 struct htt_t2h_version_conf_msg version_msg;1267 struct htt_t2h_peer_map_event peer_map_ev;1268 struct htt_t2h_peer_unmap_event peer_unmap_ev;1269 };1270} __packed;1271 1272#define HTT_VDEV_GET_STATS_U64(msg_l32, msg_u32)\1273 (((u64)__le32_to_cpu(msg_u32) << 32) | (__le32_to_cpu(msg_l32)))1274#define HTT_T2H_VDEV_STATS_PERIODIC_MSG_TYPE GENMASK(7, 0)1275#define HTT_T2H_VDEV_STATS_PERIODIC_PDEV_ID GENMASK(15, 8)1276#define HTT_T2H_VDEV_STATS_PERIODIC_NUM_VDEV GENMASK(23, 16)1277#define HTT_T2H_VDEV_STATS_PERIODIC_PAYLOAD_BYTES GENMASK(15, 0)1278#define HTT_VDEV_TXRX_STATS_COMMON_TLV 01279#define HTT_VDEV_TXRX_STATS_HW_STATS_TLV 11280 1281struct htt_t2h_vdev_txrx_stats_ind {1282 __le32 vdev_id;1283 __le32 rx_msdu_byte_cnt_lo;1284 __le32 rx_msdu_byte_cnt_hi;1285 __le32 rx_msdu_cnt_lo;1286 __le32 rx_msdu_cnt_hi;1287 __le32 tx_msdu_byte_cnt_lo;1288 __le32 tx_msdu_byte_cnt_hi;1289 __le32 tx_msdu_cnt_lo;1290 __le32 tx_msdu_cnt_hi;1291 __le32 tx_retry_cnt_lo;1292 __le32 tx_retry_cnt_hi;1293 __le32 tx_retry_byte_cnt_lo;1294 __le32 tx_retry_byte_cnt_hi;1295 __le32 tx_drop_cnt_lo;1296 __le32 tx_drop_cnt_hi;1297 __le32 tx_drop_byte_cnt_lo;1298 __le32 tx_drop_byte_cnt_hi;1299 __le32 msdu_ttl_cnt_lo;1300 __le32 msdu_ttl_cnt_hi;1301 __le32 msdu_ttl_byte_cnt_lo;1302 __le32 msdu_ttl_byte_cnt_hi;1303} __packed;1304 1305struct htt_t2h_vdev_common_stats_tlv {1306 __le32 soc_drop_count_lo;1307 __le32 soc_drop_count_hi;1308} __packed;1309 1310/* ppdu stats1311 *1312 * @details1313 * The following field definitions describe the format of the HTT target1314 * to host ppdu stats indication message.1315 *1316 *1317 * |31 16|15 12|11 10|9 8|7 0 |1318 * |----------------------------------------------------------------------|1319 * | payload_size | rsvd |pdev_id|mac_id | msg type |1320 * |----------------------------------------------------------------------|1321 * | ppdu_id |1322 * |----------------------------------------------------------------------|1323 * | Timestamp in us |1324 * |----------------------------------------------------------------------|1325 * | reserved |1326 * |----------------------------------------------------------------------|1327 * | type-specific stats info |1328 * | (see htt_ppdu_stats.h) |1329 * |----------------------------------------------------------------------|1330 * Header fields:1331 * - MSG_TYPE1332 * Bits 7:01333 * Purpose: Identifies this is a PPDU STATS indication1334 * message.1335 * Value: 0x1d1336 * - mac_id1337 * Bits 9:81338 * Purpose: mac_id of this ppdu_id1339 * Value: 0-31340 * - pdev_id1341 * Bits 11:101342 * Purpose: pdev_id of this ppdu_id1343 * Value: 0-31344 * 0 (for rings at SOC level),1345 * 1/2/3 PDEV -> 0/1/21346 * - payload_size1347 * Bits 31:161348 * Purpose: total tlv size1349 * Value: payload_size in bytes1350 */1351 1352#define HTT_T2H_PPDU_STATS_INFO_PDEV_ID GENMASK(11, 10)1353#define HTT_T2H_PPDU_STATS_INFO_PAYLOAD_SIZE GENMASK(31, 16)1354 1355struct ath12k_htt_ppdu_stats_msg {1356 __le32 info;1357 __le32 ppdu_id;1358 __le32 timestamp;1359 __le32 rsvd;1360 u8 data[];1361} __packed;1362 1363struct htt_tlv {1364 __le32 header;1365 u8 value[];1366} __packed;1367 1368#define HTT_TLV_TAG GENMASK(11, 0)1369#define HTT_TLV_LEN GENMASK(23, 12)1370 1371enum HTT_PPDU_STATS_BW {1372 HTT_PPDU_STATS_BANDWIDTH_5MHZ = 0,1373 HTT_PPDU_STATS_BANDWIDTH_10MHZ = 1,1374 HTT_PPDU_STATS_BANDWIDTH_20MHZ = 2,1375 HTT_PPDU_STATS_BANDWIDTH_40MHZ = 3,1376 HTT_PPDU_STATS_BANDWIDTH_80MHZ = 4,1377 HTT_PPDU_STATS_BANDWIDTH_160MHZ = 5, /* includes 80+80 */1378 HTT_PPDU_STATS_BANDWIDTH_DYN = 6,1379};1380 1381#define HTT_PPDU_STATS_CMN_FLAGS_FRAME_TYPE_M GENMASK(7, 0)1382#define HTT_PPDU_STATS_CMN_FLAGS_QUEUE_TYPE_M GENMASK(15, 8)1383/* bw - HTT_PPDU_STATS_BW */1384#define HTT_PPDU_STATS_CMN_FLAGS_BW_M GENMASK(19, 16)1385 1386struct htt_ppdu_stats_common {1387 __le32 ppdu_id;1388 __le16 sched_cmdid;1389 u8 ring_id;1390 u8 num_users;1391 __le32 flags; /* %HTT_PPDU_STATS_COMMON_FLAGS_*/1392 __le32 chain_mask;1393 __le32 fes_duration_us; /* frame exchange sequence */1394 __le32 ppdu_sch_eval_start_tstmp_us;1395 __le32 ppdu_sch_end_tstmp_us;1396 __le32 ppdu_start_tstmp_us;1397 /* BIT [15 : 0] - phy mode (WLAN_PHY_MODE) with which ppdu was transmitted1398 * BIT [31 : 16] - bandwidth (in MHz) with which ppdu was transmitted1399 */1400 __le16 phy_mode;1401 __le16 bw_mhz;1402} __packed;1403 1404enum htt_ppdu_stats_gi {1405 HTT_PPDU_STATS_SGI_0_8_US,1406 HTT_PPDU_STATS_SGI_0_4_US,1407 HTT_PPDU_STATS_SGI_1_6_US,1408 HTT_PPDU_STATS_SGI_3_2_US,1409};1410 1411#define HTT_PPDU_STATS_USER_RATE_INFO0_USER_POS_M GENMASK(3, 0)1412#define HTT_PPDU_STATS_USER_RATE_INFO0_MU_GROUP_ID_M GENMASK(11, 4)1413 1414enum HTT_PPDU_STATS_PPDU_TYPE {1415 HTT_PPDU_STATS_PPDU_TYPE_SU,1416 HTT_PPDU_STATS_PPDU_TYPE_MU_MIMO,1417 HTT_PPDU_STATS_PPDU_TYPE_MU_OFDMA,1418 HTT_PPDU_STATS_PPDU_TYPE_MU_MIMO_OFDMA,1419 HTT_PPDU_STATS_PPDU_TYPE_UL_TRIG,1420 HTT_PPDU_STATS_PPDU_TYPE_BURST_BCN,1421 HTT_PPDU_STATS_PPDU_TYPE_UL_BSR_RESP,1422 HTT_PPDU_STATS_PPDU_TYPE_UL_BSR_TRIG,1423 HTT_PPDU_STATS_PPDU_TYPE_UL_RESP,1424 HTT_PPDU_STATS_PPDU_TYPE_MAX1425};1426 1427#define HTT_PPDU_STATS_USER_RATE_INFO1_RESP_TYPE_VALD_M BIT(0)1428#define HTT_PPDU_STATS_USER_RATE_INFO1_PPDU_TYPE_M GENMASK(5, 1)1429 1430#define HTT_PPDU_STATS_USER_RATE_FLAGS_LTF_SIZE_M GENMASK(1, 0)1431#define HTT_PPDU_STATS_USER_RATE_FLAGS_STBC_M BIT(2)1432#define HTT_PPDU_STATS_USER_RATE_FLAGS_HE_RE_M BIT(3)1433#define HTT_PPDU_STATS_USER_RATE_FLAGS_TXBF_M GENMASK(7, 4)1434#define HTT_PPDU_STATS_USER_RATE_FLAGS_BW_M GENMASK(11, 8)1435#define HTT_PPDU_STATS_USER_RATE_FLAGS_NSS_M GENMASK(15, 12)1436#define HTT_PPDU_STATS_USER_RATE_FLAGS_MCS_M GENMASK(19, 16)1437#define HTT_PPDU_STATS_USER_RATE_FLAGS_PREAMBLE_M GENMASK(23, 20)1438#define HTT_PPDU_STATS_USER_RATE_FLAGS_GI_M GENMASK(27, 24)1439#define HTT_PPDU_STATS_USER_RATE_FLAGS_DCM_M BIT(28)1440#define HTT_PPDU_STATS_USER_RATE_FLAGS_LDPC_M BIT(29)1441 1442#define HTT_USR_RATE_PREAMBLE(_val) \1443 le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_PREAMBLE_M)1444#define HTT_USR_RATE_BW(_val) \1445 le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_BW_M)1446#define HTT_USR_RATE_NSS(_val) \1447 le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_NSS_M)1448#define HTT_USR_RATE_MCS(_val) \1449 le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_MCS_M)1450#define HTT_USR_RATE_GI(_val) \1451 le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_GI_M)1452#define HTT_USR_RATE_DCM(_val) \1453 le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_DCM_M)1454 1455#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_LTF_SIZE_M GENMASK(1, 0)1456#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_STBC_M BIT(2)1457#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_HE_RE_M BIT(3)1458#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_TXBF_M GENMASK(7, 4)1459#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_BW_M GENMASK(11, 8)1460#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_NSS_M GENMASK(15, 12)1461#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_MCS_M GENMASK(19, 16)1462#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_PREAMBLE_M GENMASK(23, 20)1463#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_GI_M GENMASK(27, 24)1464#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_DCM_M BIT(28)1465#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_LDPC_M BIT(29)1466 1467struct htt_ppdu_stats_user_rate {1468 u8 tid_num;1469 u8 reserved0;1470 __le16 sw_peer_id;1471 __le32 info0; /* %HTT_PPDU_STATS_USER_RATE_INFO0_*/1472 __le16 ru_end;1473 __le16 ru_start;1474 __le16 resp_ru_end;1475 __le16 resp_ru_start;1476 __le32 info1; /* %HTT_PPDU_STATS_USER_RATE_INFO1_ */1477 __le32 rate_flags; /* %HTT_PPDU_STATS_USER_RATE_FLAGS_ */1478 /* Note: resp_rate_info is only valid for if resp_type is UL */1479 __le32 resp_rate_flags; /* %HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_ */1480} __packed;1481 1482#define HTT_PPDU_STATS_TX_INFO_FLAGS_RATECODE_M GENMASK(7, 0)1483#define HTT_PPDU_STATS_TX_INFO_FLAGS_IS_AMPDU_M BIT(8)1484#define HTT_PPDU_STATS_TX_INFO_FLAGS_BA_ACK_FAILED_M GENMASK(10, 9)1485#define HTT_PPDU_STATS_TX_INFO_FLAGS_BW_M GENMASK(13, 11)1486#define HTT_PPDU_STATS_TX_INFO_FLAGS_SGI_M BIT(14)1487#define HTT_PPDU_STATS_TX_INFO_FLAGS_PEERID_M GENMASK(31, 16)1488 1489#define HTT_TX_INFO_IS_AMSDU(_flags) \1490 u32_get_bits(_flags, HTT_PPDU_STATS_TX_INFO_FLAGS_IS_AMPDU_M)1491#define HTT_TX_INFO_BA_ACK_FAILED(_flags) \1492 u32_get_bits(_flags, HTT_PPDU_STATS_TX_INFO_FLAGS_BA_ACK_FAILED_M)1493#define HTT_TX_INFO_RATECODE(_flags) \1494 u32_get_bits(_flags, HTT_PPDU_STATS_TX_INFO_FLAGS_RATECODE_M)1495#define HTT_TX_INFO_PEERID(_flags) \1496 u32_get_bits(_flags, HTT_PPDU_STATS_TX_INFO_FLAGS_PEERID_M)1497 1498enum htt_ppdu_stats_usr_compln_status {1499 HTT_PPDU_STATS_USER_STATUS_OK,1500 HTT_PPDU_STATS_USER_STATUS_FILTERED,1501 HTT_PPDU_STATS_USER_STATUS_RESP_TIMEOUT,1502 HTT_PPDU_STATS_USER_STATUS_RESP_MISMATCH,1503 HTT_PPDU_STATS_USER_STATUS_ABORT,1504};1505 1506#define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRY_M GENMASK(3, 0)1507#define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_SHORT_RETRY_M GENMASK(7, 4)1508#define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_IS_AMPDU_M BIT(8)1509#define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_RESP_TYPE_M GENMASK(12, 9)1510 1511#define HTT_USR_CMPLTN_IS_AMPDU(_val) \1512 le32_get_bits(_val, HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_IS_AMPDU_M)1513#define HTT_USR_CMPLTN_LONG_RETRY(_val) \1514 le32_get_bits(_val, HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRY_M)1515#define HTT_USR_CMPLTN_SHORT_RETRY(_val) \1516 le32_get_bits(_val, HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_SHORT_RETRY_M)1517 1518struct htt_ppdu_stats_usr_cmpltn_cmn {1519 u8 status;1520 u8 tid_num;1521 __le16 sw_peer_id;1522 /* RSSI value of last ack packet (units = dB above noise floor) */1523 __le32 ack_rssi;1524 __le16 mpdu_tried;1525 __le16 mpdu_success;1526 __le32 flags; /* %HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRIES*/1527} __packed;1528 1529#define HTT_PPDU_STATS_ACK_BA_INFO_NUM_MPDU_M GENMASK(8, 0)1530#define HTT_PPDU_STATS_ACK_BA_INFO_NUM_MSDU_M GENMASK(24, 9)1531#define HTT_PPDU_STATS_ACK_BA_INFO_TID_NUM GENMASK(31, 25)1532 1533#define HTT_PPDU_STATS_NON_QOS_TID 161534 1535struct htt_ppdu_stats_usr_cmpltn_ack_ba_status {1536 __le32 ppdu_id;1537 __le16 sw_peer_id;1538 __le16 reserved0;1539 __le32 info; /* %HTT_PPDU_STATS_USR_CMPLTN_CMN_INFO_ */1540 __le16 current_seq;1541 __le16 start_seq;1542 __le32 success_bytes;1543} __packed;1544 1545struct htt_ppdu_user_stats {1546 u16 peer_id;1547 u16 delay_ba;1548 u32 tlv_flags;1549 bool is_valid_peer_id;1550 struct htt_ppdu_stats_user_rate rate;1551 struct htt_ppdu_stats_usr_cmpltn_cmn cmpltn_cmn;1552 struct htt_ppdu_stats_usr_cmpltn_ack_ba_status ack_ba;1553};1554 1555#define HTT_PPDU_STATS_MAX_USERS 81556#define HTT_PPDU_DESC_MAX_DEPTH 161557 1558struct htt_ppdu_stats {1559 struct htt_ppdu_stats_common common;1560 struct htt_ppdu_user_stats user_stats[HTT_PPDU_STATS_MAX_USERS];1561};1562 1563struct htt_ppdu_stats_info {1564 u32 tlv_bitmap;1565 u32 ppdu_id;1566 u32 frame_type;1567 u32 frame_ctrl;1568 u32 delay_ba;1569 u32 bar_num_users;1570 struct htt_ppdu_stats ppdu_stats;1571 struct list_head list;1572};1573 1574/* @brief target -> host MLO offset indiciation message1575 *1576 * @details1577 * The following field definitions describe the format of the HTT target1578 * to host mlo offset indication message.1579 *1580 *1581 * |31 29|28 |26|25 22|21 16|15 13|12 10 |9 8|7 0|1582 * |---------------------------------------------------------------------|1583 * | rsvd1 | mac_freq |chip_id |pdev_id|msgtype|1584 * |---------------------------------------------------------------------|1585 * | sync_timestamp_lo_us |1586 * |---------------------------------------------------------------------|1587 * | sync_timestamp_hi_us |1588 * |---------------------------------------------------------------------|1589 * | mlo_offset_lo |1590 * |---------------------------------------------------------------------|1591 * | mlo_offset_hi |1592 * |---------------------------------------------------------------------|1593 * | mlo_offset_clcks |1594 * |---------------------------------------------------------------------|1595 * | rsvd2 | mlo_comp_clks |mlo_comp_us |1596 * |---------------------------------------------------------------------|1597 * | rsvd3 |mlo_comp_timer |1598 * |---------------------------------------------------------------------|1599 * Header fields1600 * - MSG_TYPE1601 * Bits 7:01602 * Purpose: Identifies this is a MLO offset indication msg1603 * - PDEV_ID1604 * Bits 9:81605 * Purpose: Pdev of this MLO offset1606 * - CHIP_ID1607 * Bits 12:101608 * Purpose: chip_id of this MLO offset1609 * - MAC_FREQ1610 * Bits 28:131611 * - SYNC_TIMESTAMP_LO_US1612 * Purpose: clock frequency of the mac HW block in MHz1613 * Bits: 31:01614 * Purpose: lower 32 bits of the WLAN global time stamp at which1615 * last sync interrupt was received1616 * - SYNC_TIMESTAMP_HI_US1617 * Bits: 31:01618 * Purpose: upper 32 bits of WLAN global time stamp at which1619 * last sync interrupt was received1620 * - MLO_OFFSET_LO1621 * Bits: 31:01622 * Purpose: lower 32 bits of the MLO offset in us1623 * - MLO_OFFSET_HI1624 * Bits: 31:01625 * Purpose: upper 32 bits of the MLO offset in us1626 * - MLO_COMP_US1627 * Bits: 15:01628 * Purpose: MLO time stamp compensation applied in us1629 * - MLO_COMP_CLCKS1630 * Bits: 25:161631 * Purpose: MLO time stamp compensation applied in clock ticks1632 * - MLO_COMP_TIMER1633 * Bits: 21:01634 * Purpose: Periodic timer at which compensation is applied1635 */1636 1637#define HTT_T2H_MLO_OFFSET_INFO_MSG_TYPE GENMASK(7, 0)1638#define HTT_T2H_MLO_OFFSET_INFO_PDEV_ID GENMASK(9, 8)1639 1640struct ath12k_htt_mlo_offset_msg {1641 __le32 info;1642 __le32 sync_timestamp_lo_us;1643 __le32 sync_timestamp_hi_us;1644 __le32 mlo_offset_hi;1645 __le32 mlo_offset_lo;1646 __le32 mlo_offset_clks;1647 __le32 mlo_comp_clks;1648 __le32 mlo_comp_timer;1649} __packed;1650 1651/* @brief host -> target FW extended statistics retrieve1652 *1653 * @details1654 * The following field definitions describe the format of the HTT host1655 * to target FW extended stats retrieve message.1656 * The message specifies the type of stats the host wants to retrieve.1657 *1658 * |31 24|23 16|15 8|7 0|1659 * |-----------------------------------------------------------|1660 * | reserved | stats type | pdev_mask | msg type |1661 * |-----------------------------------------------------------|1662 * | config param [0] |1663 * |-----------------------------------------------------------|1664 * | config param [1] |1665 * |-----------------------------------------------------------|1666 * | config param [2] |1667 * |-----------------------------------------------------------|1668 * | config param [3] |1669 * |-----------------------------------------------------------|1670 * | reserved |1671 * |-----------------------------------------------------------|1672 * | cookie LSBs |1673 * |-----------------------------------------------------------|1674 * | cookie MSBs |1675 * |-----------------------------------------------------------|1676 * Header fields:1677 * - MSG_TYPE1678 * Bits 7:01679 * Purpose: identifies this is a extended stats upload request message1680 * Value: 0x101681 * - PDEV_MASK1682 * Bits 8:151683 * Purpose: identifies the mask of PDEVs to retrieve stats from1684 * Value: This is a overloaded field, refer to usage and interpretation of1685 * PDEV in interface document.1686 * Bit 8 : Reserved for SOC stats1687 * Bit 9 - 15 : Indicates PDEV_MASK in DBDC1688 * Indicates MACID_MASK in DBS1689 * - STATS_TYPE1690 * Bits 23:161691 * Purpose: identifies which FW statistics to upload1692 * Value: Defined by htt_dbg_ext_stats_type (see htt_stats.h)1693 * - Reserved1694 * Bits 31:241695 * - CONFIG_PARAM [0]1696 * Bits 31:01697 * Purpose: give an opaque configuration value to the specified stats type1698 * Value: stats-type specific configuration value1699 * Refer to htt_stats.h for interpretation for each stats sub_type1700 * - CONFIG_PARAM [1]1701 * Bits 31:01702 * Purpose: give an opaque configuration value to the specified stats type1703 * Value: stats-type specific configuration value1704 * Refer to htt_stats.h for interpretation for each stats sub_type1705 * - CONFIG_PARAM [2]1706 * Bits 31:01707 * Purpose: give an opaque configuration value to the specified stats type1708 * Value: stats-type specific configuration value1709 * Refer to htt_stats.h for interpretation for each stats sub_type1710 * - CONFIG_PARAM [3]1711 * Bits 31:01712 * Purpose: give an opaque configuration value to the specified stats type1713 * Value: stats-type specific configuration value1714 * Refer to htt_stats.h for interpretation for each stats sub_type1715 * - Reserved [31:0] for future use.1716 * - COOKIE_LSBS1717 * Bits 31:01718 * Purpose: Provide a mechanism to match a target->host stats confirmation1719 * message with its preceding host->target stats request message.1720 * Value: LSBs of the opaque cookie specified by the host-side requestor1721 * - COOKIE_MSBS1722 * Bits 31:01723 * Purpose: Provide a mechanism to match a target->host stats confirmation1724 * message with its preceding host->target stats request message.1725 * Value: MSBs of the opaque cookie specified by the host-side requestor1726 */1727 1728struct htt_ext_stats_cfg_hdr {1729 u8 msg_type;1730 u8 pdev_mask;1731 u8 stats_type;1732 u8 reserved;1733} __packed;1734 1735struct htt_ext_stats_cfg_cmd {1736 struct htt_ext_stats_cfg_hdr hdr;1737 __le32 cfg_param0;1738 __le32 cfg_param1;1739 __le32 cfg_param2;1740 __le32 cfg_param3;1741 __le32 reserved;1742 __le32 cookie_lsb;1743 __le32 cookie_msb;1744} __packed;1745 1746/* htt stats config default params */1747#define HTT_STAT_DEFAULT_RESET_START_OFFSET 01748#define HTT_STAT_DEFAULT_CFG0_ALL_HWQS 0xffffffff1749#define HTT_STAT_DEFAULT_CFG0_ALL_TXQS 0xffffffff1750#define HTT_STAT_DEFAULT_CFG0_ALL_CMDQS 0xffff1751#define HTT_STAT_DEFAULT_CFG0_ALL_RINGS 0xffff1752#define HTT_STAT_DEFAULT_CFG0_ACTIVE_PEERS 0xff1753#define HTT_STAT_DEFAULT_CFG0_CCA_CUMULATIVE 0x001754#define HTT_STAT_DEFAULT_CFG0_ACTIVE_VDEVS 0x001755 1756/* HTT_DBG_EXT_STATS_PEER_INFO1757 * PARAMS:1758 * @config_param0:1759 * [Bit0] - [0] for sw_peer_id, [1] for mac_addr based request1760 * [Bit15 : Bit 1] htt_peer_stats_req_mode_t1761 * [Bit31 : Bit16] sw_peer_id1762 * @config_param1:1763 * peer_stats_req_type_mask:32 (enum htt_peer_stats_tlv_enum)1764 * 0 bit htt_peer_stats_cmn_tlv1765 * 1 bit htt_peer_details_tlv1766 * 2 bit htt_tx_peer_rate_stats_tlv1767 * 3 bit htt_rx_peer_rate_stats_tlv1768 * 4 bit htt_tx_tid_stats_tlv/htt_tx_tid_stats_v1_tlv1769 * 5 bit htt_rx_tid_stats_tlv1770 * 6 bit htt_msdu_flow_stats_tlv1771 * @config_param2: [Bit31 : Bit0] mac_addr31to01772 * @config_param3: [Bit15 : Bit0] mac_addr47to321773 * [Bit31 : Bit16] reserved1774 */1775#define HTT_STAT_PEER_INFO_MAC_ADDR BIT(0)1776#define HTT_STAT_DEFAULT_PEER_REQ_TYPE 0x7f1777 1778/* Used to set different configs to the specified stats type.*/1779struct htt_ext_stats_cfg_params {1780 u32 cfg0;1781 u32 cfg1;1782 u32 cfg2;1783 u32 cfg3;1784};1785 1786enum vdev_stats_offload_timer_duration {1787 ATH12K_STATS_TIMER_DUR_500MS = 1,1788 ATH12K_STATS_TIMER_DUR_1SEC = 2,1789 ATH12K_STATS_TIMER_DUR_2SEC = 3,1790};1791 1792static inline void ath12k_dp_get_mac_addr(u32 addr_l32, u16 addr_h16, u8 *addr)1793{1794 memcpy(addr, &addr_l32, 4);1795 memcpy(addr + 4, &addr_h16, ETH_ALEN - 4);1796}1797 1798int ath12k_dp_service_srng(struct ath12k_base *ab,1799 struct ath12k_ext_irq_grp *irq_grp,1800 int budget);1801int ath12k_dp_htt_connect(struct ath12k_dp *dp);1802void ath12k_dp_vdev_tx_attach(struct ath12k *ar, struct ath12k_vif *arvif);1803void ath12k_dp_free(struct ath12k_base *ab);1804int ath12k_dp_alloc(struct ath12k_base *ab);1805void ath12k_dp_cc_config(struct ath12k_base *ab);1806int ath12k_dp_pdev_alloc(struct ath12k_base *ab);1807void ath12k_dp_pdev_pre_alloc(struct ath12k_base *ab);1808void ath12k_dp_pdev_free(struct ath12k_base *ab);1809int ath12k_dp_tx_htt_srng_setup(struct ath12k_base *ab, u32 ring_id,1810 int mac_id, enum hal_ring_type ring_type);1811int ath12k_dp_peer_setup(struct ath12k *ar, int vdev_id, const u8 *addr);1812void ath12k_dp_peer_cleanup(struct ath12k *ar, int vdev_id, const u8 *addr);1813void ath12k_dp_srng_cleanup(struct ath12k_base *ab, struct dp_srng *ring);1814int ath12k_dp_srng_setup(struct ath12k_base *ab, struct dp_srng *ring,1815 enum hal_ring_type type, int ring_num,1816 int mac_id, int num_entries);1817void ath12k_dp_link_desc_cleanup(struct ath12k_base *ab,1818 struct dp_link_desc_bank *desc_bank,1819 u32 ring_type, struct dp_srng *ring);1820int ath12k_dp_link_desc_setup(struct ath12k_base *ab,1821 struct dp_link_desc_bank *link_desc_banks,1822 u32 ring_type, struct hal_srng *srng,1823 u32 n_link_desc);1824struct ath12k_rx_desc_info *ath12k_dp_get_rx_desc(struct ath12k_base *ab,1825 u32 cookie);1826struct ath12k_tx_desc_info *ath12k_dp_get_tx_desc(struct ath12k_base *ab,1827 u32 desc_id);1828bool ath12k_dp_wmask_compaction_rx_tlv_supported(struct ath12k_base *ab);1829void ath12k_dp_hal_rx_desc_init(struct ath12k_base *ab);1830#endif1831