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1// SPDX-License-Identifier: BSD-3-Clause-Clear2/*3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.4 * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.5 */6 7#include "core.h"8#include "dp_tx.h"9#include "debug.h"10#include "hw.h"11 12static enum hal_tcl_encap_type13ath12k_dp_tx_get_encap_type(struct ath12k_vif *arvif, struct sk_buff *skb)14{15 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);16 struct ath12k_base *ab = arvif->ar->ab;17 18 if (test_bit(ATH12K_FLAG_RAW_MODE, &ab->dev_flags))19 return HAL_TCL_ENCAP_TYPE_RAW;20 21 if (tx_info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP)22 return HAL_TCL_ENCAP_TYPE_ETHERNET;23 24 return HAL_TCL_ENCAP_TYPE_NATIVE_WIFI;25}26 27static void ath12k_dp_tx_encap_nwifi(struct sk_buff *skb)28{29 struct ieee80211_hdr *hdr = (void *)skb->data;30 u8 *qos_ctl;31 32 if (!ieee80211_is_data_qos(hdr->frame_control))33 return;34 35 qos_ctl = ieee80211_get_qos_ctl(hdr);36 memmove(skb->data + IEEE80211_QOS_CTL_LEN,37 skb->data, (void *)qos_ctl - (void *)skb->data);38 skb_pull(skb, IEEE80211_QOS_CTL_LEN);39 40 hdr = (void *)skb->data;41 hdr->frame_control &= ~__cpu_to_le16(IEEE80211_STYPE_QOS_DATA);42}43 44static u8 ath12k_dp_tx_get_tid(struct sk_buff *skb)45{46 struct ieee80211_hdr *hdr = (void *)skb->data;47 struct ath12k_skb_cb *cb = ATH12K_SKB_CB(skb);48 49 if (cb->flags & ATH12K_SKB_HW_80211_ENCAP)50 return skb->priority & IEEE80211_QOS_CTL_TID_MASK;51 else if (!ieee80211_is_data_qos(hdr->frame_control))52 return HAL_DESC_REO_NON_QOS_TID;53 else54 return skb->priority & IEEE80211_QOS_CTL_TID_MASK;55}56 57enum hal_encrypt_type ath12k_dp_tx_get_encrypt_type(u32 cipher)58{59 switch (cipher) {60 case WLAN_CIPHER_SUITE_WEP40:61 return HAL_ENCRYPT_TYPE_WEP_40;62 case WLAN_CIPHER_SUITE_WEP104:63 return HAL_ENCRYPT_TYPE_WEP_104;64 case WLAN_CIPHER_SUITE_TKIP:65 return HAL_ENCRYPT_TYPE_TKIP_MIC;66 case WLAN_CIPHER_SUITE_CCMP:67 return HAL_ENCRYPT_TYPE_CCMP_128;68 case WLAN_CIPHER_SUITE_CCMP_256:69 return HAL_ENCRYPT_TYPE_CCMP_256;70 case WLAN_CIPHER_SUITE_GCMP:71 return HAL_ENCRYPT_TYPE_GCMP_128;72 case WLAN_CIPHER_SUITE_GCMP_256:73 return HAL_ENCRYPT_TYPE_AES_GCMP_256;74 default:75 return HAL_ENCRYPT_TYPE_OPEN;76 }77}78 79static void ath12k_dp_tx_release_txbuf(struct ath12k_dp *dp,80 struct ath12k_tx_desc_info *tx_desc,81 u8 pool_id)82{83 spin_lock_bh(&dp->tx_desc_lock[pool_id]);84 list_move_tail(&tx_desc->list, &dp->tx_desc_free_list[pool_id]);85 spin_unlock_bh(&dp->tx_desc_lock[pool_id]);86}87 88static struct ath12k_tx_desc_info *ath12k_dp_tx_assign_buffer(struct ath12k_dp *dp,89 u8 pool_id)90{91 struct ath12k_tx_desc_info *desc;92 93 spin_lock_bh(&dp->tx_desc_lock[pool_id]);94 desc = list_first_entry_or_null(&dp->tx_desc_free_list[pool_id],95 struct ath12k_tx_desc_info,96 list);97 if (!desc) {98 spin_unlock_bh(&dp->tx_desc_lock[pool_id]);99 ath12k_warn(dp->ab, "failed to allocate data Tx buffer\n");100 return NULL;101 }102 103 list_move_tail(&desc->list, &dp->tx_desc_used_list[pool_id]);104 spin_unlock_bh(&dp->tx_desc_lock[pool_id]);105 106 return desc;107}108 109static void ath12k_hal_tx_cmd_ext_desc_setup(struct ath12k_base *ab,110 struct hal_tx_msdu_ext_desc *tcl_ext_cmd,111 struct hal_tx_info *ti)112{113 tcl_ext_cmd->info0 = le32_encode_bits(ti->paddr,114 HAL_TX_MSDU_EXT_INFO0_BUF_PTR_LO);115 tcl_ext_cmd->info1 = le32_encode_bits(0x0,116 HAL_TX_MSDU_EXT_INFO1_BUF_PTR_HI) |117 le32_encode_bits(ti->data_len,118 HAL_TX_MSDU_EXT_INFO1_BUF_LEN);119 120 tcl_ext_cmd->info1 = le32_encode_bits(1, HAL_TX_MSDU_EXT_INFO1_EXTN_OVERRIDE) |121 le32_encode_bits(ti->encap_type,122 HAL_TX_MSDU_EXT_INFO1_ENCAP_TYPE) |123 le32_encode_bits(ti->encrypt_type,124 HAL_TX_MSDU_EXT_INFO1_ENCRYPT_TYPE);125}126 127#define HTT_META_DATA_ALIGNMENT 0x8128 129static void *ath12k_dp_metadata_align_skb(struct sk_buff *skb, u8 tail_len)130{131 struct sk_buff *tail;132 void *metadata;133 134 if (unlikely(skb_cow_data(skb, tail_len, &tail) < 0))135 return NULL;136 137 metadata = pskb_put(skb, tail, tail_len);138 memset(metadata, 0, tail_len);139 return metadata;140}141 142/* Preparing HTT Metadata when utilized with ext MSDU */143static int ath12k_dp_prepare_htt_metadata(struct sk_buff *skb)144{145 struct hal_tx_msdu_metadata *desc_ext;146 u8 htt_desc_size;147 /* Size rounded of multiple of 8 bytes */148 u8 htt_desc_size_aligned;149 150 htt_desc_size = sizeof(struct hal_tx_msdu_metadata);151 htt_desc_size_aligned = ALIGN(htt_desc_size, HTT_META_DATA_ALIGNMENT);152 153 desc_ext = ath12k_dp_metadata_align_skb(skb, htt_desc_size_aligned);154 if (!desc_ext)155 return -ENOMEM;156 157 desc_ext->info0 = le32_encode_bits(1, HAL_TX_MSDU_METADATA_INFO0_ENCRYPT_FLAG) |158 le32_encode_bits(0, HAL_TX_MSDU_METADATA_INFO0_ENCRYPT_TYPE) |159 le32_encode_bits(1,160 HAL_TX_MSDU_METADATA_INFO0_HOST_TX_DESC_POOL);161 162 return 0;163}164 165static void ath12k_dp_tx_move_payload(struct sk_buff *skb,166 unsigned long delta,167 bool head)168{169 unsigned long len = skb->len;170 171 if (head) {172 skb_push(skb, delta);173 memmove(skb->data, skb->data + delta, len);174 skb_trim(skb, len);175 } else {176 skb_put(skb, delta);177 memmove(skb->data + delta, skb->data, len);178 skb_pull(skb, delta);179 }180}181 182static int ath12k_dp_tx_align_payload(struct ath12k_base *ab,183 struct sk_buff **pskb)184{185 u32 iova_mask = ab->hw_params->iova_mask;186 unsigned long offset, delta1, delta2;187 struct sk_buff *skb2, *skb = *pskb;188 unsigned int headroom = skb_headroom(skb);189 int tailroom = skb_tailroom(skb);190 int ret = 0;191 192 offset = (unsigned long)skb->data & iova_mask;193 delta1 = offset;194 delta2 = iova_mask - offset + 1;195 196 if (headroom >= delta1) {197 ath12k_dp_tx_move_payload(skb, delta1, true);198 } else if (tailroom >= delta2) {199 ath12k_dp_tx_move_payload(skb, delta2, false);200 } else {201 skb2 = skb_realloc_headroom(skb, iova_mask);202 if (!skb2) {203 ret = -ENOMEM;204 goto out;205 }206 207 dev_kfree_skb_any(skb);208 209 offset = (unsigned long)skb2->data & iova_mask;210 if (offset)211 ath12k_dp_tx_move_payload(skb2, offset, true);212 *pskb = skb2;213 }214 215out:216 return ret;217}218 219int ath12k_dp_tx(struct ath12k *ar, struct ath12k_vif *arvif,220 struct sk_buff *skb)221{222 struct ath12k_base *ab = ar->ab;223 struct ath12k_dp *dp = &ab->dp;224 struct hal_tx_info ti = {0};225 struct ath12k_tx_desc_info *tx_desc;226 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);227 struct ath12k_skb_cb *skb_cb = ATH12K_SKB_CB(skb);228 struct hal_tcl_data_cmd *hal_tcl_desc;229 struct hal_tx_msdu_ext_desc *msg;230 struct sk_buff *skb_ext_desc;231 struct hal_srng *tcl_ring;232 struct ieee80211_hdr *hdr = (void *)skb->data;233 struct dp_tx_ring *tx_ring;234 u8 pool_id;235 u8 hal_ring_id;236 int ret;237 u8 ring_selector, ring_map = 0;238 bool tcl_ring_retry;239 bool msdu_ext_desc = false;240 bool add_htt_metadata = false;241 u32 iova_mask = ab->hw_params->iova_mask;242 243 if (test_bit(ATH12K_FLAG_CRASH_FLUSH, &ar->ab->dev_flags))244 return -ESHUTDOWN;245 246 if (!(info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP) &&247 !ieee80211_is_data(hdr->frame_control))248 return -EOPNOTSUPP;249 250 pool_id = skb_get_queue_mapping(skb) & (ATH12K_HW_MAX_QUEUES - 1);251 252 /* Let the default ring selection be based on current processor253 * number, where one of the 3 tcl rings are selected based on254 * the smp_processor_id(). In case that ring255 * is full/busy, we resort to other available rings.256 * If all rings are full, we drop the packet.257 * TODO: Add throttling logic when all rings are full258 */259 ring_selector = ab->hw_params->hw_ops->get_ring_selector(skb);260 261tcl_ring_sel:262 tcl_ring_retry = false;263 ti.ring_id = ring_selector % ab->hw_params->max_tx_ring;264 265 ring_map |= BIT(ti.ring_id);266 ti.rbm_id = ab->hw_params->hal_ops->tcl_to_wbm_rbm_map[ti.ring_id].rbm_id;267 268 tx_ring = &dp->tx_ring[ti.ring_id];269 270 tx_desc = ath12k_dp_tx_assign_buffer(dp, pool_id);271 if (!tx_desc)272 return -ENOMEM;273 274 ti.bank_id = arvif->bank_id;275 ti.meta_data_flags = arvif->tcl_metadata;276 277 if (arvif->tx_encap_type == HAL_TCL_ENCAP_TYPE_RAW &&278 test_bit(ATH12K_FLAG_HW_CRYPTO_DISABLED, &ar->ab->dev_flags)) {279 if (skb_cb->flags & ATH12K_SKB_CIPHER_SET) {280 ti.encrypt_type =281 ath12k_dp_tx_get_encrypt_type(skb_cb->cipher);282 283 if (ieee80211_has_protected(hdr->frame_control))284 skb_put(skb, IEEE80211_CCMP_MIC_LEN);285 } else {286 ti.encrypt_type = HAL_ENCRYPT_TYPE_OPEN;287 }288 289 msdu_ext_desc = true;290 }291 292 ti.encap_type = ath12k_dp_tx_get_encap_type(arvif, skb);293 ti.addr_search_flags = arvif->hal_addr_search_flags;294 ti.search_type = arvif->search_type;295 ti.type = HAL_TCL_DESC_TYPE_BUFFER;296 ti.pkt_offset = 0;297 ti.lmac_id = ar->lmac_id;298 ti.vdev_id = arvif->vdev_id;299 ti.bss_ast_hash = arvif->ast_hash;300 ti.bss_ast_idx = arvif->ast_idx;301 ti.dscp_tid_tbl_idx = 0;302 303 if (skb->ip_summed == CHECKSUM_PARTIAL &&304 ti.encap_type != HAL_TCL_ENCAP_TYPE_RAW) {305 ti.flags0 |= u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO2_IP4_CKSUM_EN) |306 u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO2_UDP4_CKSUM_EN) |307 u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO2_UDP6_CKSUM_EN) |308 u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO2_TCP4_CKSUM_EN) |309 u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO2_TCP6_CKSUM_EN);310 }311 312 ti.flags1 |= u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO3_TID_OVERWRITE);313 314 ti.tid = ath12k_dp_tx_get_tid(skb);315 316 switch (ti.encap_type) {317 case HAL_TCL_ENCAP_TYPE_NATIVE_WIFI:318 ath12k_dp_tx_encap_nwifi(skb);319 break;320 case HAL_TCL_ENCAP_TYPE_RAW:321 if (!test_bit(ATH12K_FLAG_RAW_MODE, &ab->dev_flags)) {322 ret = -EINVAL;323 goto fail_remove_tx_buf;324 }325 break;326 case HAL_TCL_ENCAP_TYPE_ETHERNET:327 /* no need to encap */328 break;329 case HAL_TCL_ENCAP_TYPE_802_3:330 default:331 /* TODO: Take care of other encap modes as well */332 ret = -EINVAL;333 atomic_inc(&ab->soc_stats.tx_err.misc_fail);334 goto fail_remove_tx_buf;335 }336 337 if (iova_mask &&338 (unsigned long)skb->data & iova_mask) {339 ret = ath12k_dp_tx_align_payload(ab, &skb);340 if (ret) {341 ath12k_warn(ab, "failed to align TX buffer %d\n", ret);342 /* don't bail out, give original buffer343 * a chance even unaligned.344 */345 goto map;346 }347 348 /* hdr is pointing to a wrong place after alignment,349 * so refresh it for later use.350 */351 hdr = (void *)skb->data;352 }353map:354 ti.paddr = dma_map_single(ab->dev, skb->data, skb->len, DMA_TO_DEVICE);355 if (dma_mapping_error(ab->dev, ti.paddr)) {356 atomic_inc(&ab->soc_stats.tx_err.misc_fail);357 ath12k_warn(ab, "failed to DMA map data Tx buffer\n");358 ret = -ENOMEM;359 goto fail_remove_tx_buf;360 }361 362 if (!test_bit(ATH12K_FLAG_HW_CRYPTO_DISABLED, &ar->ab->dev_flags) &&363 !(skb_cb->flags & ATH12K_SKB_HW_80211_ENCAP) &&364 !(skb_cb->flags & ATH12K_SKB_CIPHER_SET) &&365 ieee80211_has_protected(hdr->frame_control)) {366 /* Add metadata for sw encrypted vlan group traffic */367 add_htt_metadata = true;368 msdu_ext_desc = true;369 ti.flags0 |= u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO2_TO_FW);370 ti.encap_type = HAL_TCL_ENCAP_TYPE_RAW;371 ti.encrypt_type = HAL_ENCRYPT_TYPE_OPEN;372 }373 374 tx_desc->skb = skb;375 tx_desc->mac_id = ar->pdev_idx;376 ti.desc_id = tx_desc->desc_id;377 ti.data_len = skb->len;378 skb_cb->paddr = ti.paddr;379 skb_cb->vif = arvif->vif;380 skb_cb->ar = ar;381 382 if (msdu_ext_desc) {383 skb_ext_desc = dev_alloc_skb(sizeof(struct hal_tx_msdu_ext_desc));384 if (!skb_ext_desc) {385 ret = -ENOMEM;386 goto fail_unmap_dma;387 }388 389 skb_put(skb_ext_desc, sizeof(struct hal_tx_msdu_ext_desc));390 memset(skb_ext_desc->data, 0, skb_ext_desc->len);391 392 msg = (struct hal_tx_msdu_ext_desc *)skb_ext_desc->data;393 ath12k_hal_tx_cmd_ext_desc_setup(ab, msg, &ti);394 395 if (add_htt_metadata) {396 ret = ath12k_dp_prepare_htt_metadata(skb_ext_desc);397 if (ret < 0) {398 ath12k_dbg(ab, ATH12K_DBG_DP_TX,399 "Failed to add HTT meta data, dropping packet\n");400 goto fail_unmap_dma;401 }402 }403 404 ti.paddr = dma_map_single(ab->dev, skb_ext_desc->data,405 skb_ext_desc->len, DMA_TO_DEVICE);406 ret = dma_mapping_error(ab->dev, ti.paddr);407 if (ret) {408 kfree_skb(skb_ext_desc);409 goto fail_unmap_dma;410 }411 412 ti.data_len = skb_ext_desc->len;413 ti.type = HAL_TCL_DESC_TYPE_EXT_DESC;414 415 skb_cb->paddr_ext_desc = ti.paddr;416 }417 418 hal_ring_id = tx_ring->tcl_data_ring.ring_id;419 tcl_ring = &ab->hal.srng_list[hal_ring_id];420 421 spin_lock_bh(&tcl_ring->lock);422 423 ath12k_hal_srng_access_begin(ab, tcl_ring);424 425 hal_tcl_desc = ath12k_hal_srng_src_get_next_entry(ab, tcl_ring);426 if (!hal_tcl_desc) {427 /* NOTE: It is highly unlikely we'll be running out of tcl_ring428 * desc because the desc is directly enqueued onto hw queue.429 */430 ath12k_hal_srng_access_end(ab, tcl_ring);431 ab->soc_stats.tx_err.desc_na[ti.ring_id]++;432 spin_unlock_bh(&tcl_ring->lock);433 ret = -ENOMEM;434 435 /* Checking for available tcl descriptors in another ring in436 * case of failure due to full tcl ring now, is better than437 * checking this ring earlier for each pkt tx.438 * Restart ring selection if some rings are not checked yet.439 */440 if (ring_map != (BIT(ab->hw_params->max_tx_ring) - 1) &&441 ab->hw_params->tcl_ring_retry) {442 tcl_ring_retry = true;443 ring_selector++;444 }445 446 goto fail_unmap_dma;447 }448 449 ath12k_hal_tx_cmd_desc_setup(ab, hal_tcl_desc, &ti);450 451 ath12k_hal_srng_access_end(ab, tcl_ring);452 453 spin_unlock_bh(&tcl_ring->lock);454 455 ath12k_dbg_dump(ab, ATH12K_DBG_DP_TX, NULL, "dp tx msdu: ",456 skb->data, skb->len);457 458 atomic_inc(&ar->dp.num_tx_pending);459 460 return 0;461 462fail_unmap_dma:463 dma_unmap_single(ab->dev, ti.paddr, ti.data_len, DMA_TO_DEVICE);464 465 if (skb_cb->paddr_ext_desc)466 dma_unmap_single(ab->dev, skb_cb->paddr_ext_desc,467 sizeof(struct hal_tx_msdu_ext_desc),468 DMA_TO_DEVICE);469 470fail_remove_tx_buf:471 ath12k_dp_tx_release_txbuf(dp, tx_desc, pool_id);472 if (tcl_ring_retry)473 goto tcl_ring_sel;474 475 return ret;476}477 478static void ath12k_dp_tx_free_txbuf(struct ath12k_base *ab,479 struct sk_buff *msdu, u8 mac_id,480 struct dp_tx_ring *tx_ring)481{482 struct ath12k *ar;483 struct ath12k_skb_cb *skb_cb;484 u8 pdev_id = ath12k_hw_mac_id_to_pdev_id(ab->hw_params, mac_id);485 486 skb_cb = ATH12K_SKB_CB(msdu);487 ar = ab->pdevs[pdev_id].ar;488 489 dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE);490 if (skb_cb->paddr_ext_desc)491 dma_unmap_single(ab->dev, skb_cb->paddr_ext_desc,492 sizeof(struct hal_tx_msdu_ext_desc), DMA_TO_DEVICE);493 494 ieee80211_free_txskb(ar->ah->hw, msdu);495 496 if (atomic_dec_and_test(&ar->dp.num_tx_pending))497 wake_up(&ar->dp.tx_empty_waitq);498}499 500static void501ath12k_dp_tx_htt_tx_complete_buf(struct ath12k_base *ab,502 struct sk_buff *msdu,503 struct dp_tx_ring *tx_ring,504 struct ath12k_dp_htt_wbm_tx_status *ts)505{506 struct ieee80211_tx_info *info;507 struct ath12k_skb_cb *skb_cb;508 struct ath12k *ar;509 510 skb_cb = ATH12K_SKB_CB(msdu);511 info = IEEE80211_SKB_CB(msdu);512 513 ar = skb_cb->ar;514 515 if (atomic_dec_and_test(&ar->dp.num_tx_pending))516 wake_up(&ar->dp.tx_empty_waitq);517 518 dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE);519 if (skb_cb->paddr_ext_desc)520 dma_unmap_single(ab->dev, skb_cb->paddr_ext_desc,521 sizeof(struct hal_tx_msdu_ext_desc), DMA_TO_DEVICE);522 523 memset(&info->status, 0, sizeof(info->status));524 525 if (ts->acked) {526 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {527 info->flags |= IEEE80211_TX_STAT_ACK;528 info->status.ack_signal = ts->ack_rssi;529 530 if (!test_bit(WMI_TLV_SERVICE_HW_DB2DBM_CONVERSION_SUPPORT,531 ab->wmi_ab.svc_map))532 info->status.ack_signal += ATH12K_DEFAULT_NOISE_FLOOR;533 534 info->status.flags = IEEE80211_TX_STATUS_ACK_SIGNAL_VALID;535 } else {536 info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED;537 }538 }539 540 ieee80211_tx_status_skb(ath12k_ar_to_hw(ar), msdu);541}542 543static void544ath12k_dp_tx_process_htt_tx_complete(struct ath12k_base *ab,545 void *desc, u8 mac_id,546 struct sk_buff *msdu,547 struct dp_tx_ring *tx_ring)548{549 struct htt_tx_wbm_completion *status_desc;550 struct ath12k_dp_htt_wbm_tx_status ts = {0};551 enum hal_wbm_htt_tx_comp_status wbm_status;552 553 status_desc = desc;554 555 wbm_status = le32_get_bits(status_desc->info0,556 HTT_TX_WBM_COMP_INFO0_STATUS);557 558 switch (wbm_status) {559 case HAL_WBM_REL_HTT_TX_COMP_STATUS_OK:560 case HAL_WBM_REL_HTT_TX_COMP_STATUS_DROP:561 case HAL_WBM_REL_HTT_TX_COMP_STATUS_TTL:562 ts.acked = (wbm_status == HAL_WBM_REL_HTT_TX_COMP_STATUS_OK);563 ts.ack_rssi = le32_get_bits(status_desc->info2,564 HTT_TX_WBM_COMP_INFO2_ACK_RSSI);565 ath12k_dp_tx_htt_tx_complete_buf(ab, msdu, tx_ring, &ts);566 break;567 case HAL_WBM_REL_HTT_TX_COMP_STATUS_REINJ:568 case HAL_WBM_REL_HTT_TX_COMP_STATUS_INSPECT:569 ath12k_dp_tx_free_txbuf(ab, msdu, mac_id, tx_ring);570 break;571 case HAL_WBM_REL_HTT_TX_COMP_STATUS_MEC_NOTIFY:572 /* This event is to be handled only when the driver decides to573 * use WDS offload functionality.574 */575 break;576 default:577 ath12k_warn(ab, "Unknown htt tx status %d\n", wbm_status);578 break;579 }580}581 582static void ath12k_dp_tx_complete_msdu(struct ath12k *ar,583 struct sk_buff *msdu,584 struct hal_tx_status *ts)585{586 struct ath12k_base *ab = ar->ab;587 struct ath12k_hw *ah = ar->ah;588 struct ieee80211_tx_info *info;589 struct ath12k_skb_cb *skb_cb;590 591 if (WARN_ON_ONCE(ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_TQM)) {592 /* Must not happen */593 return;594 }595 596 skb_cb = ATH12K_SKB_CB(msdu);597 598 dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE);599 if (skb_cb->paddr_ext_desc)600 dma_unmap_single(ab->dev, skb_cb->paddr_ext_desc,601 sizeof(struct hal_tx_msdu_ext_desc), DMA_TO_DEVICE);602 603 rcu_read_lock();604 605 if (!rcu_dereference(ab->pdevs_active[ar->pdev_idx])) {606 ieee80211_free_txskb(ah->hw, msdu);607 goto exit;608 }609 610 if (!skb_cb->vif) {611 ieee80211_free_txskb(ah->hw, msdu);612 goto exit;613 }614 615 info = IEEE80211_SKB_CB(msdu);616 memset(&info->status, 0, sizeof(info->status));617 618 /* skip tx rate update from ieee80211_status*/619 info->status.rates[0].idx = -1;620 621 switch (ts->status) {622 case HAL_WBM_TQM_REL_REASON_FRAME_ACKED:623 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {624 info->flags |= IEEE80211_TX_STAT_ACK;625 info->status.ack_signal = ts->ack_rssi;626 627 if (!test_bit(WMI_TLV_SERVICE_HW_DB2DBM_CONVERSION_SUPPORT,628 ab->wmi_ab.svc_map))629 info->status.ack_signal += ATH12K_DEFAULT_NOISE_FLOOR;630 631 info->status.flags = IEEE80211_TX_STATUS_ACK_SIGNAL_VALID;632 }633 break;634 case HAL_WBM_TQM_REL_REASON_CMD_REMOVE_TX:635 if (info->flags & IEEE80211_TX_CTL_NO_ACK) {636 info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED;637 break;638 }639 fallthrough;640 case HAL_WBM_TQM_REL_REASON_CMD_REMOVE_MPDU:641 case HAL_WBM_TQM_REL_REASON_DROP_THRESHOLD:642 case HAL_WBM_TQM_REL_REASON_CMD_REMOVE_AGED_FRAMES:643 /* The failure status is due to internal firmware tx failure644 * hence drop the frame; do not update the status of frame to645 * the upper layer646 */647 ieee80211_free_txskb(ah->hw, msdu);648 goto exit;649 default:650 ath12k_dbg(ab, ATH12K_DBG_DP_TX, "tx frame is not acked status %d\n",651 ts->status);652 break;653 }654 655 /* NOTE: Tx rate status reporting. Tx completion status does not have656 * necessary information (for example nss) to build the tx rate.657 * Might end up reporting it out-of-band from HTT stats.658 */659 660 ieee80211_tx_status_skb(ath12k_ar_to_hw(ar), msdu);661 662exit:663 rcu_read_unlock();664}665 666static void ath12k_dp_tx_status_parse(struct ath12k_base *ab,667 struct hal_wbm_completion_ring_tx *desc,668 struct hal_tx_status *ts)669{670 ts->buf_rel_source =671 le32_get_bits(desc->info0, HAL_WBM_COMPL_TX_INFO0_REL_SRC_MODULE);672 if (ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_FW &&673 ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_TQM)674 return;675 676 if (ts->buf_rel_source == HAL_WBM_REL_SRC_MODULE_FW)677 return;678 679 ts->status = le32_get_bits(desc->info0,680 HAL_WBM_COMPL_TX_INFO0_TQM_RELEASE_REASON);681 682 ts->ppdu_id = le32_get_bits(desc->info1,683 HAL_WBM_COMPL_TX_INFO1_TQM_STATUS_NUMBER);684 if (le32_to_cpu(desc->rate_stats.info0) & HAL_TX_RATE_STATS_INFO0_VALID)685 ts->rate_stats = le32_to_cpu(desc->rate_stats.info0);686 else687 ts->rate_stats = 0;688}689 690void ath12k_dp_tx_completion_handler(struct ath12k_base *ab, int ring_id)691{692 struct ath12k *ar;693 struct ath12k_dp *dp = &ab->dp;694 int hal_ring_id = dp->tx_ring[ring_id].tcl_comp_ring.ring_id;695 struct hal_srng *status_ring = &ab->hal.srng_list[hal_ring_id];696 struct ath12k_tx_desc_info *tx_desc = NULL;697 struct sk_buff *msdu;698 struct hal_tx_status ts = { 0 };699 struct dp_tx_ring *tx_ring = &dp->tx_ring[ring_id];700 struct hal_wbm_release_ring *desc;701 u8 mac_id, pdev_id;702 u64 desc_va;703 704 spin_lock_bh(&status_ring->lock);705 706 ath12k_hal_srng_access_begin(ab, status_ring);707 708 while (ATH12K_TX_COMPL_NEXT(tx_ring->tx_status_head) != tx_ring->tx_status_tail) {709 desc = ath12k_hal_srng_dst_get_next_entry(ab, status_ring);710 if (!desc)711 break;712 713 memcpy(&tx_ring->tx_status[tx_ring->tx_status_head],714 desc, sizeof(*desc));715 tx_ring->tx_status_head =716 ATH12K_TX_COMPL_NEXT(tx_ring->tx_status_head);717 }718 719 if (ath12k_hal_srng_dst_peek(ab, status_ring) &&720 (ATH12K_TX_COMPL_NEXT(tx_ring->tx_status_head) == tx_ring->tx_status_tail)) {721 /* TODO: Process pending tx_status messages when kfifo_is_full() */722 ath12k_warn(ab, "Unable to process some of the tx_status ring desc because status_fifo is full\n");723 }724 725 ath12k_hal_srng_access_end(ab, status_ring);726 727 spin_unlock_bh(&status_ring->lock);728 729 while (ATH12K_TX_COMPL_NEXT(tx_ring->tx_status_tail) != tx_ring->tx_status_head) {730 struct hal_wbm_completion_ring_tx *tx_status;731 u32 desc_id;732 733 tx_ring->tx_status_tail =734 ATH12K_TX_COMPL_NEXT(tx_ring->tx_status_tail);735 tx_status = &tx_ring->tx_status[tx_ring->tx_status_tail];736 ath12k_dp_tx_status_parse(ab, tx_status, &ts);737 738 if (le32_get_bits(tx_status->info0, HAL_WBM_COMPL_TX_INFO0_CC_DONE)) {739 /* HW done cookie conversion */740 desc_va = ((u64)le32_to_cpu(tx_status->buf_va_hi) << 32 |741 le32_to_cpu(tx_status->buf_va_lo));742 tx_desc = (struct ath12k_tx_desc_info *)((unsigned long)desc_va);743 } else {744 /* SW does cookie conversion to VA */745 desc_id = le32_get_bits(tx_status->buf_va_hi,746 BUFFER_ADDR_INFO1_SW_COOKIE);747 748 tx_desc = ath12k_dp_get_tx_desc(ab, desc_id);749 }750 if (!tx_desc) {751 ath12k_warn(ab, "unable to retrieve tx_desc!");752 continue;753 }754 755 msdu = tx_desc->skb;756 mac_id = tx_desc->mac_id;757 758 /* Release descriptor as soon as extracting necessary info759 * to reduce contention760 */761 ath12k_dp_tx_release_txbuf(dp, tx_desc, tx_desc->pool_id);762 if (ts.buf_rel_source == HAL_WBM_REL_SRC_MODULE_FW) {763 ath12k_dp_tx_process_htt_tx_complete(ab,764 (void *)tx_status,765 mac_id, msdu,766 tx_ring);767 continue;768 }769 770 pdev_id = ath12k_hw_mac_id_to_pdev_id(ab->hw_params, mac_id);771 ar = ab->pdevs[pdev_id].ar;772 773 if (atomic_dec_and_test(&ar->dp.num_tx_pending))774 wake_up(&ar->dp.tx_empty_waitq);775 776 ath12k_dp_tx_complete_msdu(ar, msdu, &ts);777 }778}779 780static int781ath12k_dp_tx_get_ring_id_type(struct ath12k_base *ab,782 int mac_id, u32 ring_id,783 enum hal_ring_type ring_type,784 enum htt_srng_ring_type *htt_ring_type,785 enum htt_srng_ring_id *htt_ring_id)786{787 int ret = 0;788 789 switch (ring_type) {790 case HAL_RXDMA_BUF:791 /* for some targets, host fills rx buffer to fw and fw fills to792 * rxbuf ring for each rxdma793 */794 if (!ab->hw_params->rx_mac_buf_ring) {795 if (!(ring_id == HAL_SRNG_SW2RXDMA_BUF0 ||796 ring_id == HAL_SRNG_SW2RXDMA_BUF1)) {797 ret = -EINVAL;798 }799 *htt_ring_id = HTT_RXDMA_HOST_BUF_RING;800 *htt_ring_type = HTT_SW_TO_HW_RING;801 } else {802 if (ring_id == HAL_SRNG_SW2RXDMA_BUF0) {803 *htt_ring_id = HTT_HOST1_TO_FW_RXBUF_RING;804 *htt_ring_type = HTT_SW_TO_SW_RING;805 } else {806 *htt_ring_id = HTT_RXDMA_HOST_BUF_RING;807 *htt_ring_type = HTT_SW_TO_HW_RING;808 }809 }810 break;811 case HAL_RXDMA_DST:812 *htt_ring_id = HTT_RXDMA_NON_MONITOR_DEST_RING;813 *htt_ring_type = HTT_HW_TO_SW_RING;814 break;815 case HAL_RXDMA_MONITOR_BUF:816 *htt_ring_id = HTT_RXDMA_MONITOR_BUF_RING;817 *htt_ring_type = HTT_SW_TO_HW_RING;818 break;819 case HAL_RXDMA_MONITOR_STATUS:820 *htt_ring_id = HTT_RXDMA_MONITOR_STATUS_RING;821 *htt_ring_type = HTT_SW_TO_HW_RING;822 break;823 case HAL_RXDMA_MONITOR_DST:824 *htt_ring_id = HTT_RXDMA_MONITOR_DEST_RING;825 *htt_ring_type = HTT_HW_TO_SW_RING;826 break;827 case HAL_RXDMA_MONITOR_DESC:828 *htt_ring_id = HTT_RXDMA_MONITOR_DESC_RING;829 *htt_ring_type = HTT_SW_TO_HW_RING;830 break;831 default:832 ath12k_warn(ab, "Unsupported ring type in DP :%d\n", ring_type);833 ret = -EINVAL;834 }835 return ret;836}837 838int ath12k_dp_tx_htt_srng_setup(struct ath12k_base *ab, u32 ring_id,839 int mac_id, enum hal_ring_type ring_type)840{841 struct htt_srng_setup_cmd *cmd;842 struct hal_srng *srng = &ab->hal.srng_list[ring_id];843 struct hal_srng_params params;844 struct sk_buff *skb;845 u32 ring_entry_sz;846 int len = sizeof(*cmd);847 dma_addr_t hp_addr, tp_addr;848 enum htt_srng_ring_type htt_ring_type;849 enum htt_srng_ring_id htt_ring_id;850 int ret;851 852 skb = ath12k_htc_alloc_skb(ab, len);853 if (!skb)854 return -ENOMEM;855 856 memset(¶ms, 0, sizeof(params));857 ath12k_hal_srng_get_params(ab, srng, ¶ms);858 859 hp_addr = ath12k_hal_srng_get_hp_addr(ab, srng);860 tp_addr = ath12k_hal_srng_get_tp_addr(ab, srng);861 862 ret = ath12k_dp_tx_get_ring_id_type(ab, mac_id, ring_id,863 ring_type, &htt_ring_type,864 &htt_ring_id);865 if (ret)866 goto err_free;867 868 skb_put(skb, len);869 cmd = (struct htt_srng_setup_cmd *)skb->data;870 cmd->info0 = le32_encode_bits(HTT_H2T_MSG_TYPE_SRING_SETUP,871 HTT_SRNG_SETUP_CMD_INFO0_MSG_TYPE);872 if (htt_ring_type == HTT_SW_TO_HW_RING ||873 htt_ring_type == HTT_HW_TO_SW_RING)874 cmd->info0 |= le32_encode_bits(DP_SW2HW_MACID(mac_id),875 HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID);876 else877 cmd->info0 |= le32_encode_bits(mac_id,878 HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID);879 cmd->info0 |= le32_encode_bits(htt_ring_type,880 HTT_SRNG_SETUP_CMD_INFO0_RING_TYPE);881 cmd->info0 |= le32_encode_bits(htt_ring_id,882 HTT_SRNG_SETUP_CMD_INFO0_RING_ID);883 884 cmd->ring_base_addr_lo = cpu_to_le32(params.ring_base_paddr &885 HAL_ADDR_LSB_REG_MASK);886 887 cmd->ring_base_addr_hi = cpu_to_le32((u64)params.ring_base_paddr >>888 HAL_ADDR_MSB_REG_SHIFT);889 890 ret = ath12k_hal_srng_get_entrysize(ab, ring_type);891 if (ret < 0)892 goto err_free;893 894 ring_entry_sz = ret;895 896 ring_entry_sz >>= 2;897 cmd->info1 = le32_encode_bits(ring_entry_sz,898 HTT_SRNG_SETUP_CMD_INFO1_RING_ENTRY_SIZE);899 cmd->info1 |= le32_encode_bits(params.num_entries * ring_entry_sz,900 HTT_SRNG_SETUP_CMD_INFO1_RING_SIZE);901 cmd->info1 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_MSI_SWAP),902 HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_MSI_SWAP);903 cmd->info1 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP),904 HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_TLV_SWAP);905 cmd->info1 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_RING_PTR_SWAP),906 HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_HOST_FW_SWAP);907 if (htt_ring_type == HTT_SW_TO_HW_RING)908 cmd->info1 |= cpu_to_le32(HTT_SRNG_SETUP_CMD_INFO1_RING_LOOP_CNT_DIS);909 910 cmd->ring_head_off32_remote_addr_lo = cpu_to_le32(lower_32_bits(hp_addr));911 cmd->ring_head_off32_remote_addr_hi = cpu_to_le32(upper_32_bits(hp_addr));912 913 cmd->ring_tail_off32_remote_addr_lo = cpu_to_le32(lower_32_bits(tp_addr));914 cmd->ring_tail_off32_remote_addr_hi = cpu_to_le32(upper_32_bits(tp_addr));915 916 cmd->ring_msi_addr_lo = cpu_to_le32(lower_32_bits(params.msi_addr));917 cmd->ring_msi_addr_hi = cpu_to_le32(upper_32_bits(params.msi_addr));918 cmd->msi_data = cpu_to_le32(params.msi_data);919 920 cmd->intr_info =921 le32_encode_bits(params.intr_batch_cntr_thres_entries * ring_entry_sz,922 HTT_SRNG_SETUP_CMD_INTR_INFO_BATCH_COUNTER_THRESH);923 cmd->intr_info |=924 le32_encode_bits(params.intr_timer_thres_us >> 3,925 HTT_SRNG_SETUP_CMD_INTR_INFO_INTR_TIMER_THRESH);926 927 cmd->info2 = 0;928 if (params.flags & HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN) {929 cmd->info2 = le32_encode_bits(params.low_threshold,930 HTT_SRNG_SETUP_CMD_INFO2_INTR_LOW_THRESH);931 }932 933 ath12k_dbg(ab, ATH12K_DBG_HAL,934 "%s msi_addr_lo:0x%x, msi_addr_hi:0x%x, msi_data:0x%x\n",935 __func__, cmd->ring_msi_addr_lo, cmd->ring_msi_addr_hi,936 cmd->msi_data);937 938 ath12k_dbg(ab, ATH12K_DBG_HAL,939 "ring_id:%d, ring_type:%d, intr_info:0x%x, flags:0x%x\n",940 ring_id, ring_type, cmd->intr_info, cmd->info2);941 942 ret = ath12k_htc_send(&ab->htc, ab->dp.eid, skb);943 if (ret)944 goto err_free;945 946 return 0;947 948err_free:949 dev_kfree_skb_any(skb);950 951 return ret;952}953 954#define HTT_TARGET_VERSION_TIMEOUT_HZ (3 * HZ)955 956int ath12k_dp_tx_htt_h2t_ver_req_msg(struct ath12k_base *ab)957{958 struct ath12k_dp *dp = &ab->dp;959 struct sk_buff *skb;960 struct htt_ver_req_cmd *cmd;961 int len = sizeof(*cmd);962 int ret;963 964 init_completion(&dp->htt_tgt_version_received);965 966 skb = ath12k_htc_alloc_skb(ab, len);967 if (!skb)968 return -ENOMEM;969 970 skb_put(skb, len);971 cmd = (struct htt_ver_req_cmd *)skb->data;972 cmd->ver_reg_info = le32_encode_bits(HTT_H2T_MSG_TYPE_VERSION_REQ,973 HTT_VER_REQ_INFO_MSG_ID);974 975 ret = ath12k_htc_send(&ab->htc, dp->eid, skb);976 if (ret) {977 dev_kfree_skb_any(skb);978 return ret;979 }980 981 ret = wait_for_completion_timeout(&dp->htt_tgt_version_received,982 HTT_TARGET_VERSION_TIMEOUT_HZ);983 if (ret == 0) {984 ath12k_warn(ab, "htt target version request timed out\n");985 return -ETIMEDOUT;986 }987 988 if (dp->htt_tgt_ver_major != HTT_TARGET_VERSION_MAJOR) {989 ath12k_err(ab, "unsupported htt major version %d supported version is %d\n",990 dp->htt_tgt_ver_major, HTT_TARGET_VERSION_MAJOR);991 return -EOPNOTSUPP;992 }993 994 return 0;995}996 997int ath12k_dp_tx_htt_h2t_ppdu_stats_req(struct ath12k *ar, u32 mask)998{999 struct ath12k_base *ab = ar->ab;1000 struct ath12k_dp *dp = &ab->dp;1001 struct sk_buff *skb;1002 struct htt_ppdu_stats_cfg_cmd *cmd;1003 int len = sizeof(*cmd);1004 u8 pdev_mask;1005 int ret;1006 int i;1007 1008 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) {1009 skb = ath12k_htc_alloc_skb(ab, len);1010 if (!skb)1011 return -ENOMEM;1012 1013 skb_put(skb, len);1014 cmd = (struct htt_ppdu_stats_cfg_cmd *)skb->data;1015 cmd->msg = le32_encode_bits(HTT_H2T_MSG_TYPE_PPDU_STATS_CFG,1016 HTT_PPDU_STATS_CFG_MSG_TYPE);1017 1018 pdev_mask = 1 << (i + 1);1019 cmd->msg |= le32_encode_bits(pdev_mask, HTT_PPDU_STATS_CFG_PDEV_ID);1020 cmd->msg |= le32_encode_bits(mask, HTT_PPDU_STATS_CFG_TLV_TYPE_BITMASK);1021 1022 ret = ath12k_htc_send(&ab->htc, dp->eid, skb);1023 if (ret) {1024 dev_kfree_skb_any(skb);1025 return ret;1026 }1027 }1028 1029 return 0;1030}1031 1032int ath12k_dp_tx_htt_rx_filter_setup(struct ath12k_base *ab, u32 ring_id,1033 int mac_id, enum hal_ring_type ring_type,1034 int rx_buf_size,1035 struct htt_rx_ring_tlv_filter *tlv_filter)1036{1037 struct htt_rx_ring_selection_cfg_cmd *cmd;1038 struct hal_srng *srng = &ab->hal.srng_list[ring_id];1039 struct hal_srng_params params;1040 struct sk_buff *skb;1041 int len = sizeof(*cmd);1042 enum htt_srng_ring_type htt_ring_type;1043 enum htt_srng_ring_id htt_ring_id;1044 int ret;1045 1046 skb = ath12k_htc_alloc_skb(ab, len);1047 if (!skb)1048 return -ENOMEM;1049 1050 memset(¶ms, 0, sizeof(params));1051 ath12k_hal_srng_get_params(ab, srng, ¶ms);1052 1053 ret = ath12k_dp_tx_get_ring_id_type(ab, mac_id, ring_id,1054 ring_type, &htt_ring_type,1055 &htt_ring_id);1056 if (ret)1057 goto err_free;1058 1059 skb_put(skb, len);1060 cmd = (struct htt_rx_ring_selection_cfg_cmd *)skb->data;1061 cmd->info0 = le32_encode_bits(HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG,1062 HTT_RX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE);1063 if (htt_ring_type == HTT_SW_TO_HW_RING ||1064 htt_ring_type == HTT_HW_TO_SW_RING)1065 cmd->info0 |=1066 le32_encode_bits(DP_SW2HW_MACID(mac_id),1067 HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID);1068 else1069 cmd->info0 |=1070 le32_encode_bits(mac_id,1071 HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID);1072 cmd->info0 |= le32_encode_bits(htt_ring_id,1073 HTT_RX_RING_SELECTION_CFG_CMD_INFO0_RING_ID);1074 cmd->info0 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_MSI_SWAP),1075 HTT_RX_RING_SELECTION_CFG_CMD_INFO0_SS);1076 cmd->info0 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP),1077 HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PS);1078 cmd->info0 |= le32_encode_bits(tlv_filter->offset_valid,1079 HTT_RX_RING_SELECTION_CFG_CMD_OFFSET_VALID);1080 cmd->info1 = le32_encode_bits(rx_buf_size,1081 HTT_RX_RING_SELECTION_CFG_CMD_INFO1_BUF_SIZE);1082 cmd->pkt_type_en_flags0 = cpu_to_le32(tlv_filter->pkt_filter_flags0);1083 cmd->pkt_type_en_flags1 = cpu_to_le32(tlv_filter->pkt_filter_flags1);1084 cmd->pkt_type_en_flags2 = cpu_to_le32(tlv_filter->pkt_filter_flags2);1085 cmd->pkt_type_en_flags3 = cpu_to_le32(tlv_filter->pkt_filter_flags3);1086 cmd->rx_filter_tlv = cpu_to_le32(tlv_filter->rx_filter);1087 1088 if (tlv_filter->offset_valid) {1089 cmd->rx_packet_offset =1090 le32_encode_bits(tlv_filter->rx_packet_offset,1091 HTT_RX_RING_SELECTION_CFG_RX_PACKET_OFFSET);1092 1093 cmd->rx_packet_offset |=1094 le32_encode_bits(tlv_filter->rx_header_offset,1095 HTT_RX_RING_SELECTION_CFG_RX_HEADER_OFFSET);1096 1097 cmd->rx_mpdu_offset =1098 le32_encode_bits(tlv_filter->rx_mpdu_end_offset,1099 HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_OFFSET);1100 1101 cmd->rx_mpdu_offset |=1102 le32_encode_bits(tlv_filter->rx_mpdu_start_offset,1103 HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_OFFSET);1104 1105 cmd->rx_msdu_offset =1106 le32_encode_bits(tlv_filter->rx_msdu_end_offset,1107 HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_OFFSET);1108 1109 cmd->rx_msdu_offset |=1110 le32_encode_bits(tlv_filter->rx_msdu_start_offset,1111 HTT_RX_RING_SELECTION_CFG_RX_MSDU_START_OFFSET);1112 1113 cmd->rx_attn_offset =1114 le32_encode_bits(tlv_filter->rx_attn_offset,1115 HTT_RX_RING_SELECTION_CFG_RX_ATTENTION_OFFSET);1116 }1117 1118 if (tlv_filter->rx_mpdu_start_wmask > 0 &&1119 tlv_filter->rx_msdu_end_wmask > 0) {1120 cmd->info2 |=1121 le32_encode_bits(true,1122 HTT_RX_RING_SELECTION_CFG_WORD_MASK_COMPACT_SET);1123 cmd->rx_mpdu_start_end_mask =1124 le32_encode_bits(tlv_filter->rx_mpdu_start_wmask,1125 HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_MASK);1126 /* mpdu_end is not used for any hardwares so far1127 * please assign it in future if any chip is1128 * using through hal ops1129 */1130 cmd->rx_mpdu_start_end_mask |=1131 le32_encode_bits(tlv_filter->rx_mpdu_end_wmask,1132 HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_MASK);1133 cmd->rx_msdu_end_word_mask =1134 le32_encode_bits(tlv_filter->rx_msdu_end_wmask,1135 HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_MASK);1136 }1137 1138 ret = ath12k_htc_send(&ab->htc, ab->dp.eid, skb);1139 if (ret)1140 goto err_free;1141 1142 return 0;1143 1144err_free:1145 dev_kfree_skb_any(skb);1146 1147 return ret;1148}1149 1150int1151ath12k_dp_tx_htt_h2t_ext_stats_req(struct ath12k *ar, u8 type,1152 struct htt_ext_stats_cfg_params *cfg_params,1153 u64 cookie)1154{1155 struct ath12k_base *ab = ar->ab;1156 struct ath12k_dp *dp = &ab->dp;1157 struct sk_buff *skb;1158 struct htt_ext_stats_cfg_cmd *cmd;1159 int len = sizeof(*cmd);1160 int ret;1161 u32 pdev_id;1162 1163 skb = ath12k_htc_alloc_skb(ab, len);1164 if (!skb)1165 return -ENOMEM;1166 1167 skb_put(skb, len);1168 1169 cmd = (struct htt_ext_stats_cfg_cmd *)skb->data;1170 memset(cmd, 0, sizeof(*cmd));1171 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_EXT_STATS_CFG;1172 1173 pdev_id = ath12k_mac_get_target_pdev_id(ar);1174 cmd->hdr.pdev_mask = 1 << pdev_id;1175 1176 cmd->hdr.stats_type = type;1177 cmd->cfg_param0 = cpu_to_le32(cfg_params->cfg0);1178 cmd->cfg_param1 = cpu_to_le32(cfg_params->cfg1);1179 cmd->cfg_param2 = cpu_to_le32(cfg_params->cfg2);1180 cmd->cfg_param3 = cpu_to_le32(cfg_params->cfg3);1181 cmd->cookie_lsb = cpu_to_le32(lower_32_bits(cookie));1182 cmd->cookie_msb = cpu_to_le32(upper_32_bits(cookie));1183 1184 ret = ath12k_htc_send(&ab->htc, dp->eid, skb);1185 if (ret) {1186 ath12k_warn(ab, "failed to send htt type stats request: %d",1187 ret);1188 dev_kfree_skb_any(skb);1189 return ret;1190 }1191 1192 return 0;1193}1194 1195int ath12k_dp_tx_htt_monitor_mode_ring_config(struct ath12k *ar, bool reset)1196{1197 struct ath12k_base *ab = ar->ab;1198 int ret;1199 1200 ret = ath12k_dp_tx_htt_rx_monitor_mode_ring_config(ar, reset);1201 if (ret) {1202 ath12k_err(ab, "failed to setup rx monitor filter %d\n", ret);1203 return ret;1204 }1205 1206 return 0;1207}1208 1209int ath12k_dp_tx_htt_rx_monitor_mode_ring_config(struct ath12k *ar, bool reset)1210{1211 struct ath12k_base *ab = ar->ab;1212 struct ath12k_dp *dp = &ab->dp;1213 struct htt_rx_ring_tlv_filter tlv_filter = {0};1214 int ret, ring_id;1215 1216 ring_id = dp->rxdma_mon_buf_ring.refill_buf_ring.ring_id;1217 tlv_filter.offset_valid = false;1218 1219 if (!reset) {1220 tlv_filter.rx_filter = HTT_RX_MON_FILTER_TLV_FLAGS_MON_BUF_RING;1221 tlv_filter.pkt_filter_flags0 =1222 HTT_RX_MON_FP_MGMT_FILTER_FLAGS0 |1223 HTT_RX_MON_MO_MGMT_FILTER_FLAGS0;1224 tlv_filter.pkt_filter_flags1 =1225 HTT_RX_MON_FP_MGMT_FILTER_FLAGS1 |1226 HTT_RX_MON_MO_MGMT_FILTER_FLAGS1;1227 tlv_filter.pkt_filter_flags2 =1228 HTT_RX_MON_FP_CTRL_FILTER_FLASG2 |1229 HTT_RX_MON_MO_CTRL_FILTER_FLASG2;1230 tlv_filter.pkt_filter_flags3 =1231 HTT_RX_MON_FP_CTRL_FILTER_FLASG3 |1232 HTT_RX_MON_MO_CTRL_FILTER_FLASG3 |1233 HTT_RX_MON_FP_DATA_FILTER_FLASG3 |1234 HTT_RX_MON_MO_DATA_FILTER_FLASG3;1235 }1236 1237 if (ab->hw_params->rxdma1_enable) {1238 ret = ath12k_dp_tx_htt_rx_filter_setup(ar->ab, ring_id, 0,1239 HAL_RXDMA_MONITOR_BUF,1240 DP_RXDMA_REFILL_RING_SIZE,1241 &tlv_filter);1242 if (ret) {1243 ath12k_err(ab,1244 "failed to setup filter for monitor buf %d\n", ret);1245 return ret;1246 }1247 }1248 1249 return 0;1250}1251 1252int ath12k_dp_tx_htt_tx_filter_setup(struct ath12k_base *ab, u32 ring_id,1253 int mac_id, enum hal_ring_type ring_type,1254 int tx_buf_size,1255 struct htt_tx_ring_tlv_filter *htt_tlv_filter)1256{1257 struct htt_tx_ring_selection_cfg_cmd *cmd;1258 struct hal_srng *srng = &ab->hal.srng_list[ring_id];1259 struct hal_srng_params params;1260 struct sk_buff *skb;1261 int len = sizeof(*cmd);1262 enum htt_srng_ring_type htt_ring_type;1263 enum htt_srng_ring_id htt_ring_id;1264 int ret;1265 1266 skb = ath12k_htc_alloc_skb(ab, len);1267 if (!skb)1268 return -ENOMEM;1269 1270 memset(¶ms, 0, sizeof(params));1271 ath12k_hal_srng_get_params(ab, srng, ¶ms);1272 1273 ret = ath12k_dp_tx_get_ring_id_type(ab, mac_id, ring_id,1274 ring_type, &htt_ring_type,1275 &htt_ring_id);1276 1277 if (ret)1278 goto err_free;1279 1280 skb_put(skb, len);1281 cmd = (struct htt_tx_ring_selection_cfg_cmd *)skb->data;1282 cmd->info0 = le32_encode_bits(HTT_H2T_MSG_TYPE_TX_MONITOR_CFG,1283 HTT_TX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE);1284 if (htt_ring_type == HTT_SW_TO_HW_RING ||1285 htt_ring_type == HTT_HW_TO_SW_RING)1286 cmd->info0 |=1287 le32_encode_bits(DP_SW2HW_MACID(mac_id),1288 HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID);1289 else1290 cmd->info0 |=1291 le32_encode_bits(mac_id,1292 HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID);1293 cmd->info0 |= le32_encode_bits(htt_ring_id,1294 HTT_TX_RING_SELECTION_CFG_CMD_INFO0_RING_ID);1295 cmd->info0 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_MSI_SWAP),1296 HTT_TX_RING_SELECTION_CFG_CMD_INFO0_SS);1297 cmd->info0 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP),1298 HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PS);1299 1300 cmd->info1 |=1301 le32_encode_bits(tx_buf_size,1302 HTT_TX_RING_SELECTION_CFG_CMD_INFO1_RING_BUFF_SIZE);1303 1304 if (htt_tlv_filter->tx_mon_mgmt_filter) {1305 cmd->info1 |=1306 le32_encode_bits(HTT_STATS_FRAME_CTRL_TYPE_MGMT,1307 HTT_TX_RING_SELECTION_CFG_CMD_INFO1_PKT_TYPE);1308 cmd->info1 |=1309 le32_encode_bits(htt_tlv_filter->tx_mon_pkt_dma_len,1310 HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_MGMT);1311 cmd->info2 |=1312 le32_encode_bits(HTT_STATS_FRAME_CTRL_TYPE_MGMT,1313 HTT_TX_RING_SELECTION_CFG_CMD_INFO2_PKT_TYPE_EN_FLAG);1314 }1315 1316 if (htt_tlv_filter->tx_mon_data_filter) {1317 cmd->info1 |=1318 le32_encode_bits(HTT_STATS_FRAME_CTRL_TYPE_CTRL,1319 HTT_TX_RING_SELECTION_CFG_CMD_INFO1_PKT_TYPE);1320 cmd->info1 |=1321 le32_encode_bits(htt_tlv_filter->tx_mon_pkt_dma_len,1322 HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_CTRL);1323 cmd->info2 |=1324 le32_encode_bits(HTT_STATS_FRAME_CTRL_TYPE_CTRL,1325 HTT_TX_RING_SELECTION_CFG_CMD_INFO2_PKT_TYPE_EN_FLAG);1326 }1327 1328 if (htt_tlv_filter->tx_mon_ctrl_filter) {1329 cmd->info1 |=1330 le32_encode_bits(HTT_STATS_FRAME_CTRL_TYPE_DATA,1331 HTT_TX_RING_SELECTION_CFG_CMD_INFO1_PKT_TYPE);1332 cmd->info1 |=1333 le32_encode_bits(htt_tlv_filter->tx_mon_pkt_dma_len,1334 HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_DATA);1335 cmd->info2 |=1336 le32_encode_bits(HTT_STATS_FRAME_CTRL_TYPE_DATA,1337 HTT_TX_RING_SELECTION_CFG_CMD_INFO2_PKT_TYPE_EN_FLAG);1338 }1339 1340 cmd->tlv_filter_mask_in0 =1341 cpu_to_le32(htt_tlv_filter->tx_mon_downstream_tlv_flags);1342 cmd->tlv_filter_mask_in1 =1343 cpu_to_le32(htt_tlv_filter->tx_mon_upstream_tlv_flags0);1344 cmd->tlv_filter_mask_in2 =1345 cpu_to_le32(htt_tlv_filter->tx_mon_upstream_tlv_flags1);1346 cmd->tlv_filter_mask_in3 =1347 cpu_to_le32(htt_tlv_filter->tx_mon_upstream_tlv_flags2);1348 1349 ret = ath12k_htc_send(&ab->htc, ab->dp.eid, skb);1350 if (ret)1351 goto err_free;1352 1353 return 0;1354 1355err_free:1356 dev_kfree_skb_any(skb);1357 return ret;1358}1359