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1/*2 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>3 * Copyright (c) 2006-2007 Nick Kossifidis <mickflemm@gmail.com>4 *5 * Permission to use, copy, modify, and distribute this software for any6 * purpose with or without fee is hereby granted, provided that the above7 * copyright notice and this permission notice appear in all copies.8 *9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.16 */17 18#ifndef _ATH5K_H19#define _ATH5K_H20 21/* TODO: Clean up channel debugging (doesn't work anyway) and start22 * working on reg. control code using all available eeprom information23 * (rev. engineering needed) */24#define CHAN_DEBUG 025 26#include <linux/io.h>27#include <linux/interrupt.h>28#include <linux/types.h>29#include <linux/average.h>30#include <linux/leds.h>31#include <net/mac80211.h>32#include <net/cfg80211.h>33 34/* RX/TX descriptor hw structs35 * TODO: Driver part should only see sw structs */36#include "desc.h"37 38/* EEPROM structs/offsets39 * TODO: Make a more generic struct (eg. add more stuff to ath5k_capabilities)40 * and clean up common bits, then introduce set/get functions in eeprom.c */41#include "eeprom.h"42#include "debug.h"43#include "../ath.h"44#include "ani.h"45 46/* PCI IDs */47#define PCI_DEVICE_ID_ATHEROS_AR5210 0x0007 /* AR5210 */48#define PCI_DEVICE_ID_ATHEROS_AR5311 0x0011 /* AR5311 */49#define PCI_DEVICE_ID_ATHEROS_AR5211 0x0012 /* AR5211 */50#define PCI_DEVICE_ID_ATHEROS_AR5212 0x0013 /* AR5212 */51#define PCI_DEVICE_ID_3COM_3CRDAG675 0x0013 /* 3CRDAG675 (Atheros AR5212) */52#define PCI_DEVICE_ID_3COM_2_3CRPAG175 0x0013 /* 3CRPAG175 (Atheros AR5212) */53#define PCI_DEVICE_ID_ATHEROS_AR5210_AP 0x0207 /* AR5210 (Early) */54#define PCI_DEVICE_ID_ATHEROS_AR5212_IBM 0x1014 /* AR5212 (IBM MiniPCI) */55#define PCI_DEVICE_ID_ATHEROS_AR5210_DEFAULT 0x1107 /* AR5210 (no eeprom) */56#define PCI_DEVICE_ID_ATHEROS_AR5212_DEFAULT 0x1113 /* AR5212 (no eeprom) */57#define PCI_DEVICE_ID_ATHEROS_AR5211_DEFAULT 0x1112 /* AR5211 (no eeprom) */58#define PCI_DEVICE_ID_ATHEROS_AR5212_FPGA 0xf013 /* AR5212 (emulation board) */59#define PCI_DEVICE_ID_ATHEROS_AR5211_LEGACY 0xff12 /* AR5211 (emulation board) */60#define PCI_DEVICE_ID_ATHEROS_AR5211_FPGA11B 0xf11b /* AR5211 (emulation board) */61#define PCI_DEVICE_ID_ATHEROS_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */62#define PCI_DEVICE_ID_ATHEROS_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */63#define PCI_DEVICE_ID_ATHEROS_AR5312_REV8 0x0058 /* AR5312 WMAC (AP43-030) */64#define PCI_DEVICE_ID_ATHEROS_AR5212_0014 0x0014 /* AR5212 compatible */65#define PCI_DEVICE_ID_ATHEROS_AR5212_0015 0x0015 /* AR5212 compatible */66#define PCI_DEVICE_ID_ATHEROS_AR5212_0016 0x0016 /* AR5212 compatible */67#define PCI_DEVICE_ID_ATHEROS_AR5212_0017 0x0017 /* AR5212 compatible */68#define PCI_DEVICE_ID_ATHEROS_AR5212_0018 0x0018 /* AR5212 compatible */69#define PCI_DEVICE_ID_ATHEROS_AR5212_0019 0x0019 /* AR5212 compatible */70#define PCI_DEVICE_ID_ATHEROS_AR2413 0x001a /* AR2413 (Griffin-lite) */71#define PCI_DEVICE_ID_ATHEROS_AR5413 0x001b /* AR5413 (Eagle) */72#define PCI_DEVICE_ID_ATHEROS_AR5424 0x001c /* AR5424 (Condor PCI-E) */73#define PCI_DEVICE_ID_ATHEROS_AR5416 0x0023 /* AR5416 */74#define PCI_DEVICE_ID_ATHEROS_AR5418 0x0024 /* AR5418 */75 76/****************************\77 GENERIC DRIVER DEFINITIONS78\****************************/79 80#define ATH5K_PRINTF(fmt, ...) \81 pr_warn("%s: " fmt, __func__, ##__VA_ARGS__)82 83void __printf(3, 4)84_ath5k_printk(const struct ath5k_hw *ah, const char *level,85 const char *fmt, ...);86 87#define ATH5K_PRINTK(_sc, _level, _fmt, ...) \88 _ath5k_printk(_sc, _level, _fmt, ##__VA_ARGS__)89 90#define ATH5K_PRINTK_LIMIT(_sc, _level, _fmt, ...) \91do { \92 if (net_ratelimit()) \93 ATH5K_PRINTK(_sc, _level, _fmt, ##__VA_ARGS__); \94} while (0)95 96#define ATH5K_INFO(_sc, _fmt, ...) \97 ATH5K_PRINTK(_sc, KERN_INFO, _fmt, ##__VA_ARGS__)98 99#define ATH5K_WARN(_sc, _fmt, ...) \100 ATH5K_PRINTK_LIMIT(_sc, KERN_WARNING, _fmt, ##__VA_ARGS__)101 102#define ATH5K_ERR(_sc, _fmt, ...) \103 ATH5K_PRINTK_LIMIT(_sc, KERN_ERR, _fmt, ##__VA_ARGS__)104 105/*106 * AR5K REGISTER ACCESS107 */108 109/* Some macros to read/write fields */110 111/* First shift, then mask */112#define AR5K_REG_SM(_val, _flags) \113 (((_val) << _flags##_S) & (_flags))114 115/* First mask, then shift */116#define AR5K_REG_MS(_val, _flags) \117 (((_val) & (_flags)) >> _flags##_S)118 119/* Some registers can hold multiple values of interest. For this120 * reason when we want to write to these registers we must first121 * retrieve the values which we do not want to clear (lets call this122 * old_data) and then set the register with this and our new_value:123 * ( old_data | new_value) */124#define AR5K_REG_WRITE_BITS(ah, _reg, _flags, _val) \125 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & ~(_flags)) | \126 (((_val) << _flags##_S) & (_flags)), _reg)127 128#define AR5K_REG_MASKED_BITS(ah, _reg, _flags, _mask) \129 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & \130 (_mask)) | (_flags), _reg)131 132#define AR5K_REG_ENABLE_BITS(ah, _reg, _flags) \133 ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) | (_flags), _reg)134 135#define AR5K_REG_DISABLE_BITS(ah, _reg, _flags) \136 ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) & ~(_flags), _reg)137 138/* Access QCU registers per queue */139#define AR5K_REG_READ_Q(ah, _reg, _queue) \140 (ath5k_hw_reg_read(ah, _reg) & (1 << _queue)) \141 142#define AR5K_REG_WRITE_Q(ah, _reg, _queue) \143 ath5k_hw_reg_write(ah, (1 << _queue), _reg)144 145#define AR5K_Q_ENABLE_BITS(_reg, _queue) do { \146 _reg |= 1 << _queue; \147} while (0)148 149#define AR5K_Q_DISABLE_BITS(_reg, _queue) do { \150 _reg &= ~(1 << _queue); \151} while (0)152 153/* Used while writing initvals */154#define AR5K_REG_WAIT(_i) do { \155 if (_i % 64) \156 udelay(1); \157} while (0)158 159/*160 * Some tunable values (these should be changeable by the user)161 * TODO: Make use of them and add more options OR use debug/configfs162 */163#define AR5K_TUNE_DMA_BEACON_RESP 2164#define AR5K_TUNE_SW_BEACON_RESP 10165#define AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF 0166#define AR5K_TUNE_MIN_TX_FIFO_THRES 1167#define AR5K_TUNE_MAX_TX_FIFO_THRES ((IEEE80211_MAX_FRAME_LEN / 64) + 1)168#define AR5K_TUNE_REGISTER_TIMEOUT 20000169/* Register for RSSI threshold has a mask of 0xff, so 255 seems to170 * be the max value. */171#define AR5K_TUNE_RSSI_THRES 129172/* This must be set when setting the RSSI threshold otherwise it can173 * prevent a reset. If AR5K_RSSI_THR is read after writing to it174 * the BMISS_THRES will be seen as 0, seems hardware doesn't keep175 * track of it. Max value depends on hardware. For AR5210 this is just 7.176 * For AR5211+ this seems to be up to 255. */177#define AR5K_TUNE_BMISS_THRES 7178#define AR5K_TUNE_REGISTER_DWELL_TIME 20000179#define AR5K_TUNE_BEACON_INTERVAL 100180#define AR5K_TUNE_AIFS 2181#define AR5K_TUNE_AIFS_11B 2182#define AR5K_TUNE_AIFS_XR 0183#define AR5K_TUNE_CWMIN 15184#define AR5K_TUNE_CWMIN_11B 31185#define AR5K_TUNE_CWMIN_XR 3186#define AR5K_TUNE_CWMAX 1023187#define AR5K_TUNE_CWMAX_11B 1023188#define AR5K_TUNE_CWMAX_XR 7189#define AR5K_TUNE_NOISE_FLOOR -72190#define AR5K_TUNE_CCA_MAX_GOOD_VALUE -95191#define AR5K_TUNE_MAX_TXPOWER 63192#define AR5K_TUNE_DEFAULT_TXPOWER 25193#define AR5K_TUNE_TPC_TXPOWER false194#define ATH5K_TUNE_CALIBRATION_INTERVAL_FULL 60000 /* 60 sec */195#define ATH5K_TUNE_CALIBRATION_INTERVAL_SHORT 10000 /* 10 sec */196#define ATH5K_TUNE_CALIBRATION_INTERVAL_ANI 1000 /* 1 sec */197#define ATH5K_TX_COMPLETE_POLL_INT 3000 /* 3 sec */198 199#define AR5K_INIT_CARR_SENSE_EN 1200 201/*Swap RX/TX Descriptor for big endian archs*/202#if defined(__BIG_ENDIAN)203#define AR5K_INIT_CFG ( \204 AR5K_CFG_SWTD | AR5K_CFG_SWRD \205)206#else207#define AR5K_INIT_CFG 0x00000000208#endif209 210/* Initial values */211#define AR5K_INIT_CYCRSSI_THR1 2212 213/* Tx retry limit defaults from standard */214#define AR5K_INIT_RETRY_SHORT 7215#define AR5K_INIT_RETRY_LONG 4216 217/* Slot time */218#define AR5K_INIT_SLOT_TIME_TURBO 6219#define AR5K_INIT_SLOT_TIME_DEFAULT 9220#define AR5K_INIT_SLOT_TIME_HALF_RATE 13221#define AR5K_INIT_SLOT_TIME_QUARTER_RATE 21222#define AR5K_INIT_SLOT_TIME_B 20223#define AR5K_SLOT_TIME_MAX 0xffff224 225/* SIFS */226#define AR5K_INIT_SIFS_TURBO 6227#define AR5K_INIT_SIFS_DEFAULT_BG 10228#define AR5K_INIT_SIFS_DEFAULT_A 16229#define AR5K_INIT_SIFS_HALF_RATE 32230#define AR5K_INIT_SIFS_QUARTER_RATE 64231 232/* Used to calculate tx time for non 5/10/40MHz233 * operation */234/* It's preamble time + signal time (16 + 4) */235#define AR5K_INIT_OFDM_PREAMPLE_TIME 20236/* Preamble time for 40MHz (turbo) operation (min ?) */237#define AR5K_INIT_OFDM_PREAMBLE_TIME_MIN 14238#define AR5K_INIT_OFDM_SYMBOL_TIME 4239#define AR5K_INIT_OFDM_PLCP_BITS 22240 241/* Rx latency for 5 and 10MHz operation (max ?) */242#define AR5K_INIT_RX_LAT_MAX 63243/* Tx latencies from initvals (5212 only but no problem244 * because we only tweak them on 5212) */245#define AR5K_INIT_TX_LAT_A 54246#define AR5K_INIT_TX_LAT_BG 384247/* Tx latency for 40MHz (turbo) operation (min ?) */248#define AR5K_INIT_TX_LAT_MIN 32249/* Default Tx/Rx latencies (same for 5211)*/250#define AR5K_INIT_TX_LATENCY_5210 54251#define AR5K_INIT_RX_LATENCY_5210 29252 253/* Tx frame to Tx data start delay */254#define AR5K_INIT_TXF2TXD_START_DEFAULT 14255#define AR5K_INIT_TXF2TXD_START_DELAY_10MHZ 12256#define AR5K_INIT_TXF2TXD_START_DELAY_5MHZ 13257 258/* We need to increase PHY switch and agc settling time259 * on turbo mode */260#define AR5K_SWITCH_SETTLING 5760261#define AR5K_SWITCH_SETTLING_TURBO 7168262 263#define AR5K_AGC_SETTLING 28264/* 38 on 5210 but shouldn't matter */265#define AR5K_AGC_SETTLING_TURBO 37266 267 268 269/*****************************\270* GENERIC CHIPSET DEFINITIONS *271\*****************************/272 273/**274 * enum ath5k_version - MAC Chips275 * @AR5K_AR5210: AR5210 (Crete)276 * @AR5K_AR5211: AR5211 (Oahu/Maui)277 * @AR5K_AR5212: AR5212 (Venice) and newer278 */279enum ath5k_version {280 AR5K_AR5210 = 0,281 AR5K_AR5211 = 1,282 AR5K_AR5212 = 2,283};284 285/**286 * enum ath5k_radio - PHY Chips287 * @AR5K_RF5110: RF5110 (Fez)288 * @AR5K_RF5111: RF5111 (Sombrero)289 * @AR5K_RF5112: RF2112/5112(A) (Derby/Derby2)290 * @AR5K_RF2413: RF2413/2414 (Griffin/Griffin-Lite)291 * @AR5K_RF5413: RF5413/5414/5424 (Eagle/Condor)292 * @AR5K_RF2316: RF2315/2316 (Cobra SoC)293 * @AR5K_RF2317: RF2317 (Spider SoC)294 * @AR5K_RF2425: RF2425/2417 (Swan/Nalla)295 */296enum ath5k_radio {297 AR5K_RF5110 = 0,298 AR5K_RF5111 = 1,299 AR5K_RF5112 = 2,300 AR5K_RF2413 = 3,301 AR5K_RF5413 = 4,302 AR5K_RF2316 = 5,303 AR5K_RF2317 = 6,304 AR5K_RF2425 = 7,305};306 307/*308 * Common silicon revision/version values309 */310 311#define AR5K_SREV_UNKNOWN 0xffff312 313#define AR5K_SREV_AR5210 0x00 /* Crete */314#define AR5K_SREV_AR5311 0x10 /* Maui 1 */315#define AR5K_SREV_AR5311A 0x20 /* Maui 2 */316#define AR5K_SREV_AR5311B 0x30 /* Spirit */317#define AR5K_SREV_AR5211 0x40 /* Oahu */318#define AR5K_SREV_AR5212 0x50 /* Venice */319#define AR5K_SREV_AR5312_R2 0x52 /* AP31 */320#define AR5K_SREV_AR5212_V4 0x54 /* ??? */321#define AR5K_SREV_AR5213 0x55 /* ??? */322#define AR5K_SREV_AR5312_R7 0x57 /* AP30 */323#define AR5K_SREV_AR2313_R8 0x58 /* AP43 */324#define AR5K_SREV_AR5213A 0x59 /* Hainan */325#define AR5K_SREV_AR2413 0x78 /* Griffin lite */326#define AR5K_SREV_AR2414 0x70 /* Griffin */327#define AR5K_SREV_AR2315_R6 0x86 /* AP51-Light */328#define AR5K_SREV_AR2315_R7 0x87 /* AP51-Full */329#define AR5K_SREV_AR5424 0x90 /* Condor */330#define AR5K_SREV_AR2317_R1 0x90 /* AP61-Light */331#define AR5K_SREV_AR2317_R2 0x91 /* AP61-Full */332#define AR5K_SREV_AR5413 0xa4 /* Eagle lite */333#define AR5K_SREV_AR5414 0xa0 /* Eagle */334#define AR5K_SREV_AR2415 0xb0 /* Talon */335#define AR5K_SREV_AR5416 0xc0 /* PCI-E */336#define AR5K_SREV_AR5418 0xca /* PCI-E */337#define AR5K_SREV_AR2425 0xe0 /* Swan */338#define AR5K_SREV_AR2417 0xf0 /* Nala */339 340#define AR5K_SREV_RAD_5110 0x00341#define AR5K_SREV_RAD_5111 0x10342#define AR5K_SREV_RAD_5111A 0x15343#define AR5K_SREV_RAD_2111 0x20344#define AR5K_SREV_RAD_5112 0x30345#define AR5K_SREV_RAD_5112A 0x35346#define AR5K_SREV_RAD_5112B 0x36347#define AR5K_SREV_RAD_2112 0x40348#define AR5K_SREV_RAD_2112A 0x45349#define AR5K_SREV_RAD_2112B 0x46350#define AR5K_SREV_RAD_2413 0x50351#define AR5K_SREV_RAD_5413 0x60352#define AR5K_SREV_RAD_2316 0x70 /* Cobra SoC */353#define AR5K_SREV_RAD_2317 0x80354#define AR5K_SREV_RAD_5424 0xa0 /* Mostly same as 5413 */355#define AR5K_SREV_RAD_2425 0xa2356#define AR5K_SREV_RAD_5133 0xc0357 358#define AR5K_SREV_PHY_5211 0x30359#define AR5K_SREV_PHY_5212 0x41360#define AR5K_SREV_PHY_5212A 0x42361#define AR5K_SREV_PHY_5212B 0x43362#define AR5K_SREV_PHY_2413 0x45363#define AR5K_SREV_PHY_5413 0x61364#define AR5K_SREV_PHY_2425 0x70365 366/* TODO add support to mac80211 for vendor-specific rates and modes */367 368/**369 * DOC: Atheros XR370 *371 * Some of this information is based on Documentation from:372 *373 * http://madwifi-project.org/wiki/ChipsetFeatures/SuperAG374 *375 * Atheros' eXtended Range - range enhancing extension is a modulation scheme376 * that is supposed to double the link distance between an Atheros XR-enabled377 * client device with an Atheros XR-enabled access point. This is achieved378 * by increasing the receiver sensitivity up to, -105dBm, which is about 20dB379 * above what the 802.11 specifications demand. In addition, new (proprietary)380 * data rates are introduced: 3, 2, 1, 0.5 and 0.25 MBit/s.381 *382 * Please note that can you either use XR or TURBO but you cannot use both,383 * they are exclusive.384 *385 * Also note that we do not plan to support XR mode at least for now. You can386 * get a mode similar to XR by using 5MHz bwmode.387 */388 389 390/**391 * DOC: Atheros SuperAG392 *393 * In addition to XR we have another modulation scheme called TURBO mode394 * that is supposed to provide a throughput transmission speed up to 40Mbit/s395 * -60Mbit/s at a 108Mbit/s signaling rate achieved through the bonding of two396 * 54Mbit/s 802.11g channels. To use this feature both ends must support it.397 * There is also a distinction between "static" and "dynamic" turbo modes:398 *399 * - Static: is the dumb version: devices set to this mode stick to it until400 * the mode is turned off.401 *402 * - Dynamic: is the intelligent version, the network decides itself if it403 * is ok to use turbo. As soon as traffic is detected on adjacent channels404 * (which would get used in turbo mode), or when a non-turbo station joins405 * the network, turbo mode won't be used until the situation changes again.406 * Dynamic mode is achieved by Atheros' Adaptive Radio (AR) feature which407 * monitors the used radio band in order to decide whether turbo mode may408 * be used or not.409 *410 * This article claims Super G sticks to bonding of channels 5 and 6 for411 * USA:412 *413 * https://www.pcworld.com/article/id,113428-page,1/article.html414 *415 * The channel bonding seems to be driver specific though.416 *417 * In addition to TURBO modes we also have the following features for even418 * greater speed-up:419 *420 * - Bursting: allows multiple frames to be sent at once, rather than pausing421 * after each frame. Bursting is a standards-compliant feature that can be422 * used with any Access Point.423 *424 * - Fast frames: increases the amount of information that can be sent per425 * frame, also resulting in a reduction of transmission overhead. It is a426 * proprietary feature that needs to be supported by the Access Point.427 *428 * - Compression: data frames are compressed in real time using a Lempel Ziv429 * algorithm. This is done transparently. Once this feature is enabled,430 * compression and decompression takes place inside the chipset, without431 * putting additional load on the host CPU.432 *433 * As with XR we also don't plan to support SuperAG features for now. You can434 * get a mode similar to TURBO by using 40MHz bwmode.435 */436 437 438/**439 * enum ath5k_driver_mode - PHY operation mode440 * @AR5K_MODE_11A: 802.11a441 * @AR5K_MODE_11B: 802.11b442 * @AR5K_MODE_11G: 801.11g443 * @AR5K_MODE_MAX: Used for boundary checks444 *445 * Do not change the order here, we use these as446 * array indices and it also maps EEPROM structures.447 */448enum ath5k_driver_mode {449 AR5K_MODE_11A = 0,450 AR5K_MODE_11B = 1,451 AR5K_MODE_11G = 2,452 AR5K_MODE_MAX = 3453};454 455/**456 * enum ath5k_ant_mode - Antenna operation mode457 * @AR5K_ANTMODE_DEFAULT: Default antenna setup458 * @AR5K_ANTMODE_FIXED_A: Only antenna A is present459 * @AR5K_ANTMODE_FIXED_B: Only antenna B is present460 * @AR5K_ANTMODE_SINGLE_AP: STA locked on a single ap461 * @AR5K_ANTMODE_SECTOR_AP: AP with tx antenna set on tx desc462 * @AR5K_ANTMODE_SECTOR_STA: STA with tx antenna set on tx desc463 * @AR5K_ANTMODE_DEBUG: Debug mode -A -> Rx, B-> Tx-464 * @AR5K_ANTMODE_MAX: Used for boundary checks465 *466 * For more infos on antenna control check out phy.c467 */468enum ath5k_ant_mode {469 AR5K_ANTMODE_DEFAULT = 0,470 AR5K_ANTMODE_FIXED_A = 1,471 AR5K_ANTMODE_FIXED_B = 2,472 AR5K_ANTMODE_SINGLE_AP = 3,473 AR5K_ANTMODE_SECTOR_AP = 4,474 AR5K_ANTMODE_SECTOR_STA = 5,475 AR5K_ANTMODE_DEBUG = 6,476 AR5K_ANTMODE_MAX,477};478 479/**480 * enum ath5k_bw_mode - Bandwidth operation mode481 * @AR5K_BWMODE_DEFAULT: 20MHz, default operation482 * @AR5K_BWMODE_5MHZ: Quarter rate483 * @AR5K_BWMODE_10MHZ: Half rate484 * @AR5K_BWMODE_40MHZ: Turbo485 */486enum ath5k_bw_mode {487 AR5K_BWMODE_DEFAULT = 0,488 AR5K_BWMODE_5MHZ = 1,489 AR5K_BWMODE_10MHZ = 2,490 AR5K_BWMODE_40MHZ = 3491};492 493 494 495/****************\496 TX DEFINITIONS497\****************/498 499/**500 * struct ath5k_tx_status - TX Status descriptor501 * @ts_seqnum: Sequence number502 * @ts_tstamp: Timestamp503 * @ts_status: Status code504 * @ts_final_idx: Final transmission series index505 * @ts_final_retry: Final retry count506 * @ts_rssi: RSSI for received ACK507 * @ts_shortretry: Short retry count508 * @ts_virtcol: Virtual collision count509 * @ts_antenna: Antenna used510 *511 * TX status descriptor gets filled by the hw512 * on each transmission attempt.513 */514struct ath5k_tx_status {515 u16 ts_seqnum;516 u16 ts_tstamp;517 u8 ts_status;518 u8 ts_final_idx;519 u8 ts_final_retry;520 s8 ts_rssi;521 u8 ts_shortretry;522 u8 ts_virtcol;523 u8 ts_antenna;524};525 526#define AR5K_TXSTAT_ALTRATE 0x80527#define AR5K_TXERR_XRETRY 0x01528#define AR5K_TXERR_FILT 0x02529#define AR5K_TXERR_FIFO 0x04530 531/**532 * enum ath5k_tx_queue - Queue types used to classify tx queues.533 * @AR5K_TX_QUEUE_INACTIVE: q is unused -- see ath5k_hw_release_tx_queue534 * @AR5K_TX_QUEUE_DATA: A normal data queue535 * @AR5K_TX_QUEUE_BEACON: The beacon queue536 * @AR5K_TX_QUEUE_CAB: The after-beacon queue537 * @AR5K_TX_QUEUE_UAPSD: Unscheduled Automatic Power Save Delivery queue538 */539enum ath5k_tx_queue {540 AR5K_TX_QUEUE_INACTIVE = 0,541 AR5K_TX_QUEUE_DATA,542 AR5K_TX_QUEUE_BEACON,543 AR5K_TX_QUEUE_CAB,544 AR5K_TX_QUEUE_UAPSD,545};546 547#define AR5K_NUM_TX_QUEUES 10548#define AR5K_NUM_TX_QUEUES_NOQCU 2549 550/**551 * enum ath5k_tx_queue_subtype - Queue sub-types to classify normal data queues552 * @AR5K_WME_AC_BK: Background traffic553 * @AR5K_WME_AC_BE: Best-effort (normal) traffic554 * @AR5K_WME_AC_VI: Video traffic555 * @AR5K_WME_AC_VO: Voice traffic556 *557 * These are the 4 Access Categories as defined in558 * WME spec. 0 is the lowest priority and 4 is the559 * highest. Normal data that hasn't been classified560 * goes to the Best Effort AC.561 */562enum ath5k_tx_queue_subtype {563 AR5K_WME_AC_BK = 0,564 AR5K_WME_AC_BE,565 AR5K_WME_AC_VI,566 AR5K_WME_AC_VO,567};568 569/**570 * enum ath5k_tx_queue_id - Queue ID numbers as returned by the hw functions571 * @AR5K_TX_QUEUE_ID_NOQCU_DATA: Data queue on AR5210 (no QCU available)572 * @AR5K_TX_QUEUE_ID_NOQCU_BEACON: Beacon queue on AR5210 (no QCU available)573 * @AR5K_TX_QUEUE_ID_DATA_MIN: Data queue min index574 * @AR5K_TX_QUEUE_ID_DATA_MAX: Data queue max index575 * @AR5K_TX_QUEUE_ID_CAB: Content after beacon queue576 * @AR5K_TX_QUEUE_ID_BEACON: Beacon queue577 * @AR5K_TX_QUEUE_ID_UAPSD: Urgent Automatic Power Save Delivery,578 *579 * Each number represents a hw queue. If hw does not support hw queues580 * (eg 5210) all data goes in one queue.581 */582enum ath5k_tx_queue_id {583 AR5K_TX_QUEUE_ID_NOQCU_DATA = 0,584 AR5K_TX_QUEUE_ID_NOQCU_BEACON = 1,585 AR5K_TX_QUEUE_ID_DATA_MIN = 0,586 AR5K_TX_QUEUE_ID_DATA_MAX = 3,587 AR5K_TX_QUEUE_ID_UAPSD = 7,588 AR5K_TX_QUEUE_ID_CAB = 8,589 AR5K_TX_QUEUE_ID_BEACON = 9,590};591 592/*593 * Flags to set hw queue's parameters...594 */595#define AR5K_TXQ_FLAG_TXOKINT_ENABLE 0x0001 /* Enable TXOK interrupt */596#define AR5K_TXQ_FLAG_TXERRINT_ENABLE 0x0002 /* Enable TXERR interrupt */597#define AR5K_TXQ_FLAG_TXEOLINT_ENABLE 0x0004 /* Enable TXEOL interrupt -not used- */598#define AR5K_TXQ_FLAG_TXDESCINT_ENABLE 0x0008 /* Enable TXDESC interrupt -not used- */599#define AR5K_TXQ_FLAG_TXURNINT_ENABLE 0x0010 /* Enable TXURN interrupt */600#define AR5K_TXQ_FLAG_CBRORNINT_ENABLE 0x0020 /* Enable CBRORN interrupt */601#define AR5K_TXQ_FLAG_CBRURNINT_ENABLE 0x0040 /* Enable CBRURN interrupt */602#define AR5K_TXQ_FLAG_QTRIGINT_ENABLE 0x0080 /* Enable QTRIG interrupt */603#define AR5K_TXQ_FLAG_TXNOFRMINT_ENABLE 0x0100 /* Enable TXNOFRM interrupt */604#define AR5K_TXQ_FLAG_BACKOFF_DISABLE 0x0200 /* Disable random post-backoff */605#define AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE 0x0300 /* Enable ready time expiry policy (?)*/606#define AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE 0x0800 /* Enable backoff while bursting */607#define AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS 0x1000 /* Disable backoff while bursting */608#define AR5K_TXQ_FLAG_COMPRESSION_ENABLE 0x2000 /* Enable hw compression -not implemented-*/609 610/**611 * struct ath5k_txq - Transmit queue state612 * @qnum: Hardware q number613 * @link: Link ptr in last TX desc614 * @q: Transmit queue (&struct list_head)615 * @lock: Lock on q and link616 * @setup: Is the queue configured617 * @txq_len:Number of queued buffers618 * @txq_max: Max allowed num of queued buffers619 * @txq_poll_mark: Used to check if queue got stuck620 * @txq_stuck: Queue stuck counter621 *622 * One of these exists for each hardware transmit queue.623 * Packets sent to us from above are assigned to queues based624 * on their priority. Not all devices support a complete set625 * of hardware transmit queues. For those devices the array626 * sc_ac2q will map multiple priorities to fewer hardware queues627 * (typically all to one hardware queue).628 */629struct ath5k_txq {630 unsigned int qnum;631 u32 *link;632 struct list_head q;633 spinlock_t lock;634 bool setup;635 int txq_len;636 int txq_max;637 bool txq_poll_mark;638 unsigned int txq_stuck;639};640 641/**642 * struct ath5k_txq_info - A struct to hold TX queue's parameters643 * @tqi_type: One of enum ath5k_tx_queue644 * @tqi_subtype: One of enum ath5k_tx_queue_subtype645 * @tqi_flags: TX queue flags (see above)646 * @tqi_aifs: Arbitrated Inter-frame Space647 * @tqi_cw_min: Minimum Contention Window648 * @tqi_cw_max: Maximum Contention Window649 * @tqi_cbr_period: Constant bit rate period650 * @tqi_ready_time: Time queue waits after an event when RDYTIME is enabled651 */652struct ath5k_txq_info {653 enum ath5k_tx_queue tqi_type;654 enum ath5k_tx_queue_subtype tqi_subtype;655 u16 tqi_flags;656 u8 tqi_aifs;657 u16 tqi_cw_min;658 u16 tqi_cw_max;659 u32 tqi_cbr_period;660 u32 tqi_cbr_overflow_limit;661 u32 tqi_burst_time;662 u32 tqi_ready_time;663};664 665/**666 * enum ath5k_pkt_type - Transmit packet types667 * @AR5K_PKT_TYPE_NORMAL: Normal data668 * @AR5K_PKT_TYPE_ATIM: ATIM669 * @AR5K_PKT_TYPE_PSPOLL: PS-Poll670 * @AR5K_PKT_TYPE_BEACON: Beacon671 * @AR5K_PKT_TYPE_PROBE_RESP: Probe response672 * @AR5K_PKT_TYPE_PIFS: PIFS673 * Used on tx control descriptor674 */675enum ath5k_pkt_type {676 AR5K_PKT_TYPE_NORMAL = 0,677 AR5K_PKT_TYPE_ATIM = 1,678 AR5K_PKT_TYPE_PSPOLL = 2,679 AR5K_PKT_TYPE_BEACON = 3,680 AR5K_PKT_TYPE_PROBE_RESP = 4,681 AR5K_PKT_TYPE_PIFS = 5,682};683 684/*685 * TX power and TPC settings686 */687#define AR5K_TXPOWER_OFDM(_r, _v) ( \688 ((0 & 1) << ((_v) + 6)) | \689 (((ah->ah_txpower.txp_rates_power_table[(_r)]) & 0x3f) << (_v)) \690)691 692#define AR5K_TXPOWER_CCK(_r, _v) ( \693 (ah->ah_txpower.txp_rates_power_table[(_r)] & 0x3f) << (_v) \694)695 696 697 698/****************\699 RX DEFINITIONS700\****************/701 702/**703 * struct ath5k_rx_status - RX Status descriptor704 * @rs_datalen: Data length705 * @rs_tstamp: Timestamp706 * @rs_status: Status code707 * @rs_phyerr: PHY error mask708 * @rs_rssi: RSSI in 0.5dbm units709 * @rs_keyix: Index to the key used for decrypting710 * @rs_rate: Rate used to decode the frame711 * @rs_antenna: Antenna used to receive the frame712 * @rs_more: Indicates this is a frame fragment (Fast frames)713 */714struct ath5k_rx_status {715 u16 rs_datalen;716 u16 rs_tstamp;717 u8 rs_status;718 u8 rs_phyerr;719 s8 rs_rssi;720 u8 rs_keyix;721 u8 rs_rate;722 u8 rs_antenna;723 u8 rs_more;724};725 726#define AR5K_RXERR_CRC 0x01727#define AR5K_RXERR_PHY 0x02728#define AR5K_RXERR_FIFO 0x04729#define AR5K_RXERR_DECRYPT 0x08730#define AR5K_RXERR_MIC 0x10731#define AR5K_RXKEYIX_INVALID ((u8) -1)732#define AR5K_TXKEYIX_INVALID ((u32) -1)733 734 735/**************************\736 BEACON TIMERS DEFINITIONS737\**************************/738 739#define AR5K_BEACON_PERIOD 0x0000ffff740#define AR5K_BEACON_ENA 0x00800000 /*enable beacon xmit*/741#define AR5K_BEACON_RESET_TSF 0x01000000 /*force a TSF reset*/742 743 744/*745 * TSF to TU conversion:746 *747 * TSF is a 64bit value in usec (microseconds).748 * TU is a 32bit value and defined by IEEE802.11 (page 6) as "A measurement of749 * time equal to 1024 usec", so it's roughly milliseconds (usec / 1024).750 */751#define TSF_TO_TU(_tsf) (u32)((_tsf) >> 10)752 753 754 755/*******************************\756 GAIN OPTIMIZATION DEFINITIONS757\*******************************/758 759/**760 * enum ath5k_rfgain - RF Gain optimization engine state761 * @AR5K_RFGAIN_INACTIVE: Engine disabled762 * @AR5K_RFGAIN_ACTIVE: Probe active763 * @AR5K_RFGAIN_READ_REQUESTED: Probe requested764 * @AR5K_RFGAIN_NEED_CHANGE: Gain_F needs change765 */766enum ath5k_rfgain {767 AR5K_RFGAIN_INACTIVE = 0,768 AR5K_RFGAIN_ACTIVE,769 AR5K_RFGAIN_READ_REQUESTED,770 AR5K_RFGAIN_NEED_CHANGE,771};772 773/**774 * struct ath5k_gain - RF Gain optimization engine state data775 * @g_step_idx: Current step index776 * @g_current: Current gain777 * @g_target: Target gain778 * @g_low: Low gain boundary779 * @g_high: High gain boundary780 * @g_f_corr: Gain_F correction781 * @g_state: One of enum ath5k_rfgain782 */783struct ath5k_gain {784 u8 g_step_idx;785 u8 g_current;786 u8 g_target;787 u8 g_low;788 u8 g_high;789 u8 g_f_corr;790 u8 g_state;791};792 793 794 795/********************\796 COMMON DEFINITIONS797\********************/798 799#define AR5K_SLOT_TIME_9 396800#define AR5K_SLOT_TIME_20 880801#define AR5K_SLOT_TIME_MAX 0xffff802 803/**804 * struct ath5k_athchan_2ghz - 2GHz to 5GHZ map for RF5111805 * @a2_flags: Channel flags (internal)806 * @a2_athchan: HW channel number (internal)807 *808 * This structure is used to map 2GHz channels to809 * 5GHz Atheros channels on 2111 frequency converter810 * that comes together with RF5111811 * TODO: Clean up812 */813struct ath5k_athchan_2ghz {814 u32 a2_flags;815 u16 a2_athchan;816};817 818/**819 * enum ath5k_dmasize - DMA size definitions (2^(n+2))820 * @AR5K_DMASIZE_4B: 4Bytes821 * @AR5K_DMASIZE_8B: 8Bytes822 * @AR5K_DMASIZE_16B: 16Bytes823 * @AR5K_DMASIZE_32B: 32Bytes824 * @AR5K_DMASIZE_64B: 64Bytes (Default)825 * @AR5K_DMASIZE_128B: 128Bytes826 * @AR5K_DMASIZE_256B: 256Bytes827 * @AR5K_DMASIZE_512B: 512Bytes828 *829 * These are used to set DMA burst size on hw830 *831 * Note: Some platforms can't handle more than 4Bytes832 * be careful on embedded boards.833 */834enum ath5k_dmasize {835 AR5K_DMASIZE_4B = 0,836 AR5K_DMASIZE_8B,837 AR5K_DMASIZE_16B,838 AR5K_DMASIZE_32B,839 AR5K_DMASIZE_64B,840 AR5K_DMASIZE_128B,841 AR5K_DMASIZE_256B,842 AR5K_DMASIZE_512B843};844 845 846 847/******************\848 RATE DEFINITIONS849\******************/850 851/**852 * DOC: Rate codes853 *854 * Seems the ar5xxx hardware supports up to 32 rates, indexed by 1-32.855 *856 * The rate code is used to get the RX rate or set the TX rate on the857 * hardware descriptors. It is also used for internal modulation control858 * and settings.859 *860 * This is the hardware rate map we are aware of (html unfriendly):861 *862 * Rate code Rate (Kbps)863 * --------- -----------864 * 0x01 3000 (XR)865 * 0x02 1000 (XR)866 * 0x03 250 (XR)867 * 0x04 - 05 -Reserved-868 * 0x06 2000 (XR)869 * 0x07 500 (XR)870 * 0x08 48000 (OFDM)871 * 0x09 24000 (OFDM)872 * 0x0A 12000 (OFDM)873 * 0x0B 6000 (OFDM)874 * 0x0C 54000 (OFDM)875 * 0x0D 36000 (OFDM)876 * 0x0E 18000 (OFDM)877 * 0x0F 9000 (OFDM)878 * 0x10 - 17 -Reserved-879 * 0x18 11000L (CCK)880 * 0x19 5500L (CCK)881 * 0x1A 2000L (CCK)882 * 0x1B 1000L (CCK)883 * 0x1C 11000S (CCK)884 * 0x1D 5500S (CCK)885 * 0x1E 2000S (CCK)886 * 0x1F -Reserved-887 *888 * "S" indicates CCK rates with short preamble and "L" with long preamble.889 *890 * AR5211 has different rate codes for CCK (802.11B) rates. It only uses the891 * lowest 4 bits, so they are the same as above with a 0xF mask.892 * (0xB, 0xA, 0x9 and 0x8 for 1M, 2M, 5.5M and 11M).893 * We handle this in ath5k_setup_bands().894 */895#define AR5K_MAX_RATES 32896 897/* B */898#define ATH5K_RATE_CODE_1M 0x1B899#define ATH5K_RATE_CODE_2M 0x1A900#define ATH5K_RATE_CODE_5_5M 0x19901#define ATH5K_RATE_CODE_11M 0x18902/* A and G */903#define ATH5K_RATE_CODE_6M 0x0B904#define ATH5K_RATE_CODE_9M 0x0F905#define ATH5K_RATE_CODE_12M 0x0A906#define ATH5K_RATE_CODE_18M 0x0E907#define ATH5K_RATE_CODE_24M 0x09908#define ATH5K_RATE_CODE_36M 0x0D909#define ATH5K_RATE_CODE_48M 0x08910#define ATH5K_RATE_CODE_54M 0x0C911 912/* Adding this flag to rate_code on B rates913 * enables short preamble */914#define AR5K_SET_SHORT_PREAMBLE 0x04915 916/*917 * Crypto definitions918 */919 920#define AR5K_KEYCACHE_SIZE 8921extern bool ath5k_modparam_nohwcrypt;922 923/***********************\924 HW RELATED DEFINITIONS925\***********************/926 927/*928 * Misc definitions929 */930#define AR5K_RSSI_EP_MULTIPLIER (1 << 7)931 932#define AR5K_ASSERT_ENTRY(_e, _s) do { \933 if (_e >= _s) \934 return false; \935} while (0)936 937/*938 * Hardware interrupt abstraction939 */940 941/**942 * enum ath5k_int - Hardware interrupt masks helpers943 * @AR5K_INT_RXOK: Frame successfully received944 * @AR5K_INT_RXDESC: Request RX descriptor/Read RX descriptor945 * @AR5K_INT_RXERR: Frame reception failed946 * @AR5K_INT_RXNOFRM: No frame received within a specified time period947 * @AR5K_INT_RXEOL: Reached "End Of List", means we need more RX descriptors948 * @AR5K_INT_RXORN: Indicates we got RX FIFO overrun. Note that Rx overrun is949 * not always fatal, on some chips we can continue operation950 * without resetting the card, that's why %AR5K_INT_FATAL is not951 * common for all chips.952 * @AR5K_INT_RX_ALL: Mask to identify all RX related interrupts953 *954 * @AR5K_INT_TXOK: Frame transmission success955 * @AR5K_INT_TXDESC: Request TX descriptor/Read TX status descriptor956 * @AR5K_INT_TXERR: Frame transmission failure957 * @AR5K_INT_TXEOL: Received End Of List for VEOL (Virtual End Of List). The958 * Queue Control Unit (QCU) signals an EOL interrupt only if a959 * descriptor's LinkPtr is NULL. For more details, refer to:960 * "http://www.freepatentsonline.com/20030225739.html"961 * @AR5K_INT_TXNOFRM: No frame was transmitted within a specified time period962 * @AR5K_INT_TXURN: Indicates we got TX FIFO underrun. In such case we should963 * increase the TX trigger threshold.964 * @AR5K_INT_TX_ALL: Mask to identify all TX related interrupts965 *966 * @AR5K_INT_MIB: Indicates the either Management Information Base counters or967 * one of the PHY error counters reached the maximum value and968 * should be read and cleared.969 * @AR5K_INT_SWI: Software triggered interrupt.970 * @AR5K_INT_RXPHY: RX PHY Error971 * @AR5K_INT_RXKCM: RX Key cache miss972 * @AR5K_INT_SWBA: SoftWare Beacon Alert - indicates its time to send a973 * beacon that must be handled in software. The alternative is if974 * you have VEOL support, in that case you let the hardware deal975 * with things.976 * @AR5K_INT_BRSSI: Beacon received with an RSSI value below our threshold977 * @AR5K_INT_BMISS: If in STA mode this indicates we have stopped seeing978 * beacons from the AP have associated with, we should probably979 * try to reassociate. When in IBSS mode this might mean we have980 * not received any beacons from any local stations. Note that981 * every station in an IBSS schedules to send beacons at the982 * Target Beacon Transmission Time (TBTT) with a random backoff.983 * @AR5K_INT_BNR: Beacon queue got triggered (DMA beacon alert) while empty.984 * @AR5K_INT_TIM: Beacon with local station's TIM bit set985 * @AR5K_INT_DTIM: Beacon with DTIM bit and zero DTIM count received986 * @AR5K_INT_DTIM_SYNC: DTIM sync lost987 * @AR5K_INT_GPIO: GPIO interrupt is used for RF Kill switches connected to988 * our GPIO pins.989 * @AR5K_INT_BCN_TIMEOUT: Beacon timeout, we waited after TBTT but got noting990 * @AR5K_INT_CAB_TIMEOUT: We waited for CAB traffic after the beacon but got991 * nothing or an incomplete CAB frame sequence.992 * @AR5K_INT_QCBRORN: A queue got it's CBR counter expired993 * @AR5K_INT_QCBRURN: A queue got triggered wile empty994 * @AR5K_INT_QTRIG: A queue got triggered995 *996 * @AR5K_INT_FATAL: Fatal errors were encountered, typically caused by bus/DMA997 * errors. Indicates we need to reset the card.998 * @AR5K_INT_GLOBAL: Used to clear and set the IER999 * @AR5K_INT_NOCARD: Signals the card has been removed1000 * @AR5K_INT_COMMON: Common interrupts shared among MACs with the same1001 * bit value1002 *1003 * These are mapped to take advantage of some common bits1004 * between the MACs, to be able to set intr properties1005 * easier. Some of them are not used yet inside hw.c. Most map1006 * to the respective hw interrupt value as they are common among different1007 * MACs.1008 */1009enum ath5k_int {1010 AR5K_INT_RXOK = 0x00000001,1011 AR5K_INT_RXDESC = 0x00000002,1012 AR5K_INT_RXERR = 0x00000004,1013 AR5K_INT_RXNOFRM = 0x00000008,1014 AR5K_INT_RXEOL = 0x00000010,1015 AR5K_INT_RXORN = 0x00000020,1016 AR5K_INT_TXOK = 0x00000040,1017 AR5K_INT_TXDESC = 0x00000080,1018 AR5K_INT_TXERR = 0x00000100,1019 AR5K_INT_TXNOFRM = 0x00000200,1020 AR5K_INT_TXEOL = 0x00000400,1021 AR5K_INT_TXURN = 0x00000800,1022 AR5K_INT_MIB = 0x00001000,1023 AR5K_INT_SWI = 0x00002000,1024 AR5K_INT_RXPHY = 0x00004000,1025 AR5K_INT_RXKCM = 0x00008000,1026 AR5K_INT_SWBA = 0x00010000,1027 AR5K_INT_BRSSI = 0x00020000,1028 AR5K_INT_BMISS = 0x00040000,1029 AR5K_INT_FATAL = 0x00080000, /* Non common */1030 AR5K_INT_BNR = 0x00100000, /* Non common */1031 AR5K_INT_TIM = 0x00200000, /* Non common */1032 AR5K_INT_DTIM = 0x00400000, /* Non common */1033 AR5K_INT_DTIM_SYNC = 0x00800000, /* Non common */1034 AR5K_INT_GPIO = 0x01000000,1035 AR5K_INT_BCN_TIMEOUT = 0x02000000, /* Non common */1036 AR5K_INT_CAB_TIMEOUT = 0x04000000, /* Non common */1037 AR5K_INT_QCBRORN = 0x08000000, /* Non common */1038 AR5K_INT_QCBRURN = 0x10000000, /* Non common */1039 AR5K_INT_QTRIG = 0x20000000, /* Non common */1040 AR5K_INT_GLOBAL = 0x80000000,1041 1042 AR5K_INT_TX_ALL = AR5K_INT_TXOK1043 | AR5K_INT_TXDESC1044 | AR5K_INT_TXERR1045 | AR5K_INT_TXNOFRM1046 | AR5K_INT_TXEOL1047 | AR5K_INT_TXURN,1048 1049 AR5K_INT_RX_ALL = AR5K_INT_RXOK1050 | AR5K_INT_RXDESC1051 | AR5K_INT_RXERR1052 | AR5K_INT_RXNOFRM1053 | AR5K_INT_RXEOL1054 | AR5K_INT_RXORN,1055 1056 AR5K_INT_COMMON = AR5K_INT_RXOK1057 | AR5K_INT_RXDESC1058 | AR5K_INT_RXERR1059 | AR5K_INT_RXNOFRM1060 | AR5K_INT_RXEOL1061 | AR5K_INT_RXORN1062 | AR5K_INT_TXOK1063 | AR5K_INT_TXDESC1064 | AR5K_INT_TXERR1065 | AR5K_INT_TXNOFRM1066 | AR5K_INT_TXEOL1067 | AR5K_INT_TXURN1068 | AR5K_INT_MIB1069 | AR5K_INT_SWI1070 | AR5K_INT_RXPHY1071 | AR5K_INT_RXKCM1072 | AR5K_INT_SWBA1073 | AR5K_INT_BRSSI1074 | AR5K_INT_BMISS1075 | AR5K_INT_GPIO1076 | AR5K_INT_GLOBAL,1077 1078 AR5K_INT_NOCARD = 0xffffffff1079};1080 1081/**1082 * enum ath5k_calibration_mask - Mask which calibration is active at the moment1083 * @AR5K_CALIBRATION_FULL: Full calibration (AGC + SHORT)1084 * @AR5K_CALIBRATION_SHORT: Short calibration (NF + I/Q)1085 * @AR5K_CALIBRATION_NF: Noise Floor calibration1086 * @AR5K_CALIBRATION_ANI: Adaptive Noise Immunity1087 */1088enum ath5k_calibration_mask {1089 AR5K_CALIBRATION_FULL = 0x01,1090 AR5K_CALIBRATION_SHORT = 0x02,1091 AR5K_CALIBRATION_NF = 0x04,1092 AR5K_CALIBRATION_ANI = 0x08,1093};1094 1095/**1096 * enum ath5k_power_mode - Power management modes1097 * @AR5K_PM_UNDEFINED: Undefined1098 * @AR5K_PM_AUTO: Allow card to sleep if possible1099 * @AR5K_PM_AWAKE: Force card to wake up1100 * @AR5K_PM_FULL_SLEEP: Force card to full sleep (DANGEROUS)1101 * @AR5K_PM_NETWORK_SLEEP: Allow to sleep for a specified duration1102 *1103 * Currently only PM_AWAKE is used, FULL_SLEEP and NETWORK_SLEEP/AUTO1104 * are also known to have problems on some cards. This is not a big1105 * problem though because we can have almost the same effect as1106 * FULL_SLEEP by putting card on warm reset (it's almost powered down).1107 */1108enum ath5k_power_mode {1109 AR5K_PM_UNDEFINED = 0,1110 AR5K_PM_AUTO,1111 AR5K_PM_AWAKE,1112 AR5K_PM_FULL_SLEEP,1113 AR5K_PM_NETWORK_SLEEP,1114};1115 1116/*1117 * These match net80211 definitions (not used in1118 * mac80211).1119 * TODO: Clean this up1120 */1121#define AR5K_LED_INIT 0 /*IEEE80211_S_INIT*/1122#define AR5K_LED_SCAN 1 /*IEEE80211_S_SCAN*/1123#define AR5K_LED_AUTH 2 /*IEEE80211_S_AUTH*/1124#define AR5K_LED_ASSOC 3 /*IEEE80211_S_ASSOC*/1125#define AR5K_LED_RUN 4 /*IEEE80211_S_RUN*/1126 1127/* GPIO-controlled software LED */1128#define AR5K_SOFTLED_PIN 01129#define AR5K_SOFTLED_ON 01130#define AR5K_SOFTLED_OFF 11131 1132 1133/* XXX: we *may* move cap_range stuff to struct wiphy */1134struct ath5k_capabilities {1135 /*1136 * Supported PHY modes1137 * (ie. AR5K_MODE_11A, AR5K_MODE_11B, ...)1138 */1139 DECLARE_BITMAP(cap_mode, AR5K_MODE_MAX);1140 1141 /*1142 * Frequency range (without regulation restrictions)1143 */1144 struct {1145 u16 range_2ghz_min;1146 u16 range_2ghz_max;1147 u16 range_5ghz_min;1148 u16 range_5ghz_max;1149 } cap_range;1150 1151 /*1152 * Values stored in the EEPROM (some of them...)1153 */1154 struct ath5k_eeprom_info cap_eeprom;1155 1156 /*1157 * Queue information1158 */1159 struct {1160 u8 q_tx_num;1161 } cap_queues;1162 1163 bool cap_has_phyerr_counters;1164 bool cap_has_mrr_support;1165 bool cap_needs_2GHz_ovr;1166};1167 1168/* size of noise floor history (keep it a power of two) */1169#define ATH5K_NF_CAL_HIST_MAX 81170struct ath5k_nfcal_hist {1171 s16 index; /* current index into nfval */1172 s16 nfval[ATH5K_NF_CAL_HIST_MAX]; /* last few noise floors */1173};1174 1175#define ATH5K_LED_MAX_NAME_LEN 311176 1177/*1178 * State for LED triggers1179 */1180struct ath5k_led {1181 char name[ATH5K_LED_MAX_NAME_LEN + 1]; /* name of the LED in sysfs */1182 struct ath5k_hw *ah; /* driver state */1183 struct led_classdev led_dev; /* led classdev */1184};1185 1186/* Rfkill */1187struct ath5k_rfkill {1188 /* GPIO PIN for rfkill */1189 u16 gpio;1190 /* polarity of rfkill GPIO PIN */1191 bool polarity;1192 /* RFKILL toggle tasklet */1193 struct tasklet_struct toggleq;1194};1195 1196/* statistics */1197struct ath5k_statistics {1198 /* antenna use */1199 unsigned int antenna_rx[5]; /* frames count per antenna RX */1200 unsigned int antenna_tx[5]; /* frames count per antenna TX */1201 1202 /* frame errors */1203 unsigned int rx_all_count; /* all RX frames, including errors */1204 unsigned int tx_all_count; /* all TX frames, including errors */1205 unsigned int rx_bytes_count; /* all RX bytes, including errored pkts1206 * and the MAC headers for each packet1207 */1208 unsigned int tx_bytes_count; /* all TX bytes, including errored pkts1209 * and the MAC headers and padding for1210 * each packet.1211 */1212 unsigned int rxerr_crc;1213 unsigned int rxerr_phy;1214 unsigned int rxerr_phy_code[32];1215 unsigned int rxerr_fifo;1216 unsigned int rxerr_decrypt;1217 unsigned int rxerr_mic;1218 unsigned int rxerr_proc;1219 unsigned int rxerr_jumbo;1220 unsigned int txerr_retry;1221 unsigned int txerr_fifo;1222 unsigned int txerr_filt;1223 1224 /* MIB counters */1225 unsigned int ack_fail;1226 unsigned int rts_fail;1227 unsigned int rts_ok;1228 unsigned int fcs_error;1229 unsigned int beacons;1230 1231 unsigned int mib_intr;1232 unsigned int rxorn_intr;1233 unsigned int rxeol_intr;1234};1235 1236/*1237 * Misc defines1238 */1239 1240#define AR5K_MAX_GPIO 101241#define AR5K_MAX_RF_BANKS 81242 1243#if CHAN_DEBUG1244#define ATH_CHAN_MAX (26 + 26 + 26 + 200 + 200)1245#else1246#define ATH_CHAN_MAX (14 + 14 + 14 + 252 + 20)1247#endif1248 1249#define ATH_RXBUF 40 /* number of RX buffers */1250#define ATH_TXBUF 200 /* number of TX buffers */1251#define ATH_BCBUF 4 /* number of beacon buffers */1252#define ATH5K_TXQ_LEN_MAX (ATH_TXBUF / 4) /* bufs per queue */1253#define ATH5K_TXQ_LEN_LOW (ATH5K_TXQ_LEN_MAX / 2) /* low mark */1254 1255DECLARE_EWMA(beacon_rssi, 10, 8)1256 1257/* Driver state associated with an instance of a device */1258struct ath5k_hw {1259 struct ath_common common;1260 1261 struct pci_dev *pdev;1262 struct device *dev; /* for dma mapping */1263 int irq;1264 u16 devid;1265 void __iomem *iobase; /* address of the device */1266 struct mutex lock; /* dev-level lock */1267 struct ieee80211_hw *hw; /* IEEE 802.11 common */1268 struct ieee80211_supported_band sbands[NUM_NL80211_BANDS];1269 struct ieee80211_channel channels[ATH_CHAN_MAX];1270 struct ieee80211_rate rates[NUM_NL80211_BANDS][AR5K_MAX_RATES];1271 s8 rate_idx[NUM_NL80211_BANDS][AR5K_MAX_RATES];1272 enum nl80211_iftype opmode;1273 1274#ifdef CONFIG_ATH5K_DEBUG1275 struct ath5k_dbg_info debug; /* debug info */1276#endif /* CONFIG_ATH5K_DEBUG */1277 1278 struct ath5k_buf *bufptr; /* allocated buffer ptr */1279 struct ath5k_desc *desc; /* TX/RX descriptors */1280 dma_addr_t desc_daddr; /* DMA (physical) address */1281 size_t desc_len; /* size of TX/RX descriptors */1282 1283 DECLARE_BITMAP(status, 4);1284#define ATH_STAT_INVALID 0 /* disable hardware accesses */1285#define ATH_STAT_LEDSOFT 2 /* enable LED gpio status */1286#define ATH_STAT_STARTED 3 /* opened & irqs enabled */1287#define ATH_STAT_RESET 4 /* hw reset */1288 1289 unsigned int filter_flags; /* HW flags, AR5K_RX_FILTER_* */1290 unsigned int fif_filter_flags; /* Current FIF_* filter flags */1291 struct ieee80211_channel *curchan; /* current h/w channel */1292 1293 u16 nvifs;1294 1295 enum ath5k_int imask; /* interrupt mask copy */1296 1297 spinlock_t irqlock;1298 bool rx_pending; /* rx tasklet pending */1299 bool tx_pending; /* tx tasklet pending */1300 1301 u8 bssidmask[ETH_ALEN];1302 1303 unsigned int led_pin, /* GPIO pin for driving LED */1304 led_on; /* pin setting for LED on */1305 1306 struct work_struct reset_work; /* deferred chip reset */1307 struct work_struct calib_work; /* deferred phy calibration */1308 1309 struct list_head rxbuf; /* receive buffer */1310 spinlock_t rxbuflock;1311 u32 *rxlink; /* link ptr in last RX desc */1312 struct tasklet_struct rxtq; /* rx intr tasklet */1313 struct ath5k_led rx_led; /* rx led */1314 1315 struct list_head txbuf; /* transmit buffer */1316 spinlock_t txbuflock;1317 unsigned int txbuf_len; /* buf count in txbuf list */1318 struct ath5k_txq txqs[AR5K_NUM_TX_QUEUES]; /* tx queues */1319 struct tasklet_struct txtq; /* tx intr tasklet */1320 struct ath5k_led tx_led; /* tx led */1321 1322 struct ath5k_rfkill rf_kill;1323 1324 spinlock_t block; /* protects beacon */1325 struct tasklet_struct beacontq; /* beacon intr tasklet */1326 struct list_head bcbuf; /* beacon buffer */1327 struct ieee80211_vif *bslot[ATH_BCBUF];1328 u16 num_ap_vifs;1329 u16 num_adhoc_vifs;1330 u16 num_mesh_vifs;1331 unsigned int bhalq, /* SW q for outgoing beacons */1332 bmisscount, /* missed beacon transmits */1333 bintval, /* beacon interval in TU */1334 bsent;1335 unsigned int nexttbtt; /* next beacon time in TU */1336 struct ath5k_txq *cabq; /* content after beacon */1337 1338 bool assoc; /* associate state */1339 bool enable_beacon; /* true if beacons are on */1340 1341 struct ath5k_statistics stats;1342 1343 struct ath5k_ani_state ani_state;1344 struct tasklet_struct ani_tasklet; /* ANI calibration */1345 1346 struct delayed_work tx_complete_work;1347 1348 struct survey_info survey; /* collected survey info */1349 1350 enum ath5k_int ah_imr;1351 1352 struct ieee80211_channel *ah_current_channel;1353 bool ah_iq_cal_needed;1354 bool ah_single_chip;1355 1356 enum ath5k_version ah_version;1357 enum ath5k_radio ah_radio;1358 u32 ah_mac_srev;1359 u16 ah_mac_version;1360 u16 ah_phy_revision;1361 u16 ah_radio_5ghz_revision;1362 u16 ah_radio_2ghz_revision;1363 1364#define ah_modes ah_capabilities.cap_mode1365#define ah_ee_version ah_capabilities.cap_eeprom.ee_version1366 1367 u8 ah_retry_long;1368 u8 ah_retry_short;1369 1370 bool ah_use_32khz_clock;1371 1372 u8 ah_coverage_class;1373 bool ah_ack_bitrate_high;1374 u8 ah_bwmode;1375 bool ah_short_slot;1376 1377 /* Antenna Control */1378 u32 ah_ant_ctl[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX];1379 u8 ah_ant_mode;1380 u8 ah_tx_ant;1381 u8 ah_def_ant;1382 1383 struct ath5k_capabilities ah_capabilities;1384 1385 struct ath5k_txq_info ah_txq[AR5K_NUM_TX_QUEUES];1386 u32 ah_txq_status;1387 u32 ah_txq_imr_txok;1388 u32 ah_txq_imr_txerr;1389 u32 ah_txq_imr_txurn;1390 u32 ah_txq_imr_txdesc;1391 u32 ah_txq_imr_txeol;1392 u32 ah_txq_imr_cbrorn;1393 u32 ah_txq_imr_cbrurn;1394 u32 ah_txq_imr_qtrig;1395 u32 ah_txq_imr_nofrm;1396 1397 u32 ah_txq_isr_txok_all;1398 1399 u32 *ah_rf_banks;1400 size_t ah_rf_banks_size;1401 size_t ah_rf_regs_count;1402 struct ath5k_gain ah_gain;1403 u8 ah_offset[AR5K_MAX_RF_BANKS];1404 1405 1406 struct {1407 /* Temporary tables used for interpolation */1408 u8 tmpL[AR5K_EEPROM_N_PD_GAINS]1409 [AR5K_EEPROM_POWER_TABLE_SIZE];1410 u8 tmpR[AR5K_EEPROM_N_PD_GAINS]1411 [AR5K_EEPROM_POWER_TABLE_SIZE];1412 u8 txp_pd_table[AR5K_EEPROM_POWER_TABLE_SIZE * 2];1413 u16 txp_rates_power_table[AR5K_MAX_RATES];1414 u8 txp_min_idx;1415 bool txp_tpc;1416 /* Values in 0.25dB units */1417 s16 txp_min_pwr;1418 s16 txp_max_pwr;1419 s16 txp_cur_pwr;1420 /* Values in 0.5dB units */1421 s16 txp_offset;1422 s16 txp_ofdm;1423 s16 txp_cck_ofdm_gainf_delta;1424 /* Value in dB units */1425 s16 txp_cck_ofdm_pwr_delta;1426 bool txp_setup;1427 int txp_requested; /* Requested tx power in dBm */1428 } ah_txpower;1429 1430 struct ath5k_nfcal_hist ah_nfcal_hist;1431 1432 /* average beacon RSSI in our BSS (used by ANI) */1433 struct ewma_beacon_rssi ah_beacon_rssi_avg;1434 1435 /* noise floor from last periodic calibration */1436 s32 ah_noise_floor;1437 1438 /* Calibration timestamp */1439 unsigned long ah_cal_next_full;1440 unsigned long ah_cal_next_short;1441 unsigned long ah_cal_next_ani;1442 1443 /* Calibration mask */1444 u8 ah_cal_mask;1445 1446 /*1447 * Function pointers1448 */1449 int (*ah_setup_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,1450 unsigned int, unsigned int, int, enum ath5k_pkt_type,1451 unsigned int, unsigned int, unsigned int, unsigned int,1452 unsigned int, unsigned int, unsigned int, unsigned int);1453 int (*ah_proc_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,1454 struct ath5k_tx_status *);1455 int (*ah_proc_rx_desc)(struct ath5k_hw *, struct ath5k_desc *,1456 struct ath5k_rx_status *);1457};1458 1459struct ath_bus_ops {1460 enum ath_bus_type ath_bus_type;1461 void (*read_cachesize)(struct ath_common *common, int *csz);1462 bool (*eeprom_read)(struct ath_common *common, u32 off, u16 *data);1463 int (*eeprom_read_mac)(struct ath5k_hw *ah, u8 *mac);1464};1465 1466/*1467 * Prototypes1468 */1469extern const struct ieee80211_ops ath5k_hw_ops;1470 1471/* Initialization and detach functions */1472int ath5k_hw_init(struct ath5k_hw *ah);1473void ath5k_hw_deinit(struct ath5k_hw *ah);1474 1475int ath5k_sysfs_register(struct ath5k_hw *ah);1476void ath5k_sysfs_unregister(struct ath5k_hw *ah);1477 1478/*Chip id helper functions */1479int ath5k_hw_read_srev(struct ath5k_hw *ah);1480 1481/* LED functions */1482int ath5k_init_leds(struct ath5k_hw *ah);1483void ath5k_led_enable(struct ath5k_hw *ah);1484void ath5k_led_off(struct ath5k_hw *ah);1485void ath5k_unregister_leds(struct ath5k_hw *ah);1486 1487 1488/* Reset Functions */1489int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, struct ieee80211_channel *channel);1490int ath5k_hw_on_hold(struct ath5k_hw *ah);1491int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,1492 struct ieee80211_channel *channel, bool fast, bool skip_pcu);1493int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val,1494 bool is_set);1495/* Power management functions */1496 1497 1498/* Clock rate related functions */1499unsigned int ath5k_hw_htoclock(struct ath5k_hw *ah, unsigned int usec);1500unsigned int ath5k_hw_clocktoh(struct ath5k_hw *ah, unsigned int clock);1501void ath5k_hw_set_clockrate(struct ath5k_hw *ah);1502 1503 1504/* DMA Related Functions */1505void ath5k_hw_start_rx_dma(struct ath5k_hw *ah);1506u32 ath5k_hw_get_rxdp(struct ath5k_hw *ah);1507int ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr);1508int ath5k_hw_start_tx_dma(struct ath5k_hw *ah, unsigned int queue);1509int ath5k_hw_stop_beacon_queue(struct ath5k_hw *ah, unsigned int queue);1510u32 ath5k_hw_get_txdp(struct ath5k_hw *ah, unsigned int queue);1511int ath5k_hw_set_txdp(struct ath5k_hw *ah, unsigned int queue,1512 u32 phys_addr);1513int ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, bool increase);1514/* Interrupt handling */1515bool ath5k_hw_is_intr_pending(struct ath5k_hw *ah);1516int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask);1517enum ath5k_int ath5k_hw_set_imr(struct ath5k_hw *ah, enum ath5k_int new_mask);1518void ath5k_hw_update_mib_counters(struct ath5k_hw *ah);1519/* Init/Stop functions */1520void ath5k_hw_dma_init(struct ath5k_hw *ah);1521int ath5k_hw_dma_stop(struct ath5k_hw *ah);1522 1523/* EEPROM access functions */1524int ath5k_eeprom_init(struct ath5k_hw *ah);1525void ath5k_eeprom_detach(struct ath5k_hw *ah);1526int ath5k_eeprom_mode_from_channel(struct ath5k_hw *ah,1527 struct ieee80211_channel *channel);1528 1529/* Protocol Control Unit Functions */1530/* Helpers */1531int ath5k_hw_get_frame_duration(struct ath5k_hw *ah, enum nl80211_band band,1532 int len, struct ieee80211_rate *rate, bool shortpre);1533unsigned int ath5k_hw_get_default_slottime(struct ath5k_hw *ah);1534unsigned int ath5k_hw_get_default_sifs(struct ath5k_hw *ah);1535int ath5k_hw_set_opmode(struct ath5k_hw *ah, enum nl80211_iftype opmode);1536void ath5k_hw_set_coverage_class(struct ath5k_hw *ah, u8 coverage_class);1537/* RX filter control*/1538int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac);1539void ath5k_hw_set_bssid(struct ath5k_hw *ah);1540void ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask);1541void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1);1542u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah);1543void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter);1544/* Receive (DRU) start/stop functions */1545void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah);1546void ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah);1547/* Beacon control functions */1548u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah);1549void ath5k_hw_set_tsf64(struct ath5k_hw *ah, u64 tsf64);1550void ath5k_hw_reset_tsf(struct ath5k_hw *ah);1551void ath5k_hw_init_beacon_timers(struct ath5k_hw *ah, u32 next_beacon,1552 u32 interval);1553bool ath5k_hw_check_beacon_timers(struct ath5k_hw *ah, int intval);1554/* Init function */1555void ath5k_hw_pcu_init(struct ath5k_hw *ah, enum nl80211_iftype op_mode);1556 1557/* Queue Control Unit, DFS Control Unit Functions */1558int ath5k_hw_get_tx_queueprops(struct ath5k_hw *ah, int queue,1559 struct ath5k_txq_info *queue_info);1560int ath5k_hw_set_tx_queueprops(struct ath5k_hw *ah, int queue,1561 const struct ath5k_txq_info *queue_info);1562int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah,1563 enum ath5k_tx_queue queue_type,1564 struct ath5k_txq_info *queue_info);1565void ath5k_hw_set_tx_retry_limits(struct ath5k_hw *ah,1566 unsigned int queue);1567u32 ath5k_hw_num_tx_pending(struct ath5k_hw *ah, unsigned int queue);1568void ath5k_hw_release_tx_queue(struct ath5k_hw *ah, unsigned int queue);1569int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue);1570int ath5k_hw_set_ifs_intervals(struct ath5k_hw *ah, unsigned int slot_time);1571/* Init function */1572int ath5k_hw_init_queues(struct ath5k_hw *ah);1573 1574/* Hardware Descriptor Functions */1575int ath5k_hw_init_desc_functions(struct ath5k_hw *ah);1576int ath5k_hw_setup_rx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,1577 u32 size, unsigned int flags);1578int ath5k_hw_setup_mrr_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,1579 unsigned int tx_rate1, u_int tx_tries1, u_int tx_rate2,1580 u_int tx_tries2, unsigned int tx_rate3, u_int tx_tries3);1581 1582 1583/* GPIO Functions */1584void ath5k_hw_set_ledstate(struct ath5k_hw *ah, unsigned int state);1585int ath5k_hw_set_gpio_input(struct ath5k_hw *ah, u32 gpio);1586int ath5k_hw_set_gpio_output(struct ath5k_hw *ah, u32 gpio);1587u32 ath5k_hw_get_gpio(struct ath5k_hw *ah, u32 gpio);1588int ath5k_hw_set_gpio(struct ath5k_hw *ah, u32 gpio, u32 val);1589void ath5k_hw_set_gpio_intr(struct ath5k_hw *ah, unsigned int gpio,1590 u32 interrupt_level);1591 1592 1593/* RFkill Functions */1594void ath5k_rfkill_hw_start(struct ath5k_hw *ah);1595void ath5k_rfkill_hw_stop(struct ath5k_hw *ah);1596 1597 1598/* Misc functions TODO: Cleanup */1599int ath5k_hw_set_capabilities(struct ath5k_hw *ah);1600int ath5k_hw_enable_pspoll(struct ath5k_hw *ah, u8 *bssid, u16 assoc_id);1601int ath5k_hw_disable_pspoll(struct ath5k_hw *ah);1602 1603 1604/* Initial register settings functions */1605int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool change_channel);1606 1607 1608/* PHY functions */1609/* Misc PHY functions */1610u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, enum nl80211_band band);1611int ath5k_hw_phy_disable(struct ath5k_hw *ah);1612/* Gain_F optimization */1613enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah);1614int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah);1615/* PHY/RF channel functions */1616bool ath5k_channel_ok(struct ath5k_hw *ah, struct ieee80211_channel *channel);1617/* PHY calibration */1618void ath5k_hw_init_nfcal_hist(struct ath5k_hw *ah);1619int ath5k_hw_phy_calibrate(struct ath5k_hw *ah,1620 struct ieee80211_channel *channel);1621void ath5k_hw_update_noise_floor(struct ath5k_hw *ah);1622/* Spur mitigation */1623bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah,1624 struct ieee80211_channel *channel);1625/* Antenna control */1626void ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode);1627void ath5k_hw_set_antenna_switch(struct ath5k_hw *ah, u8 ee_mode);1628/* TX power setup */1629int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower);1630/* Init function */1631int ath5k_hw_phy_init(struct ath5k_hw *ah, struct ieee80211_channel *channel,1632 u8 mode, bool fast);1633 1634/*1635 * Functions used internally1636 */1637 1638static inline struct ath_common *ath5k_hw_common(struct ath5k_hw *ah)1639{1640 return &ah->common;1641}1642 1643static inline struct ath_regulatory *ath5k_hw_regulatory(struct ath5k_hw *ah)1644{1645 return &(ath5k_hw_common(ah)->regulatory);1646}1647 1648#ifdef CONFIG_ATH5K_AHB1649#define AR5K_AR2315_PCI_BASE ((void __iomem *)0xb0100000)1650 1651static inline void __iomem *ath5k_ahb_reg(struct ath5k_hw *ah, u16 reg)1652{1653 /* On AR2315 and AR2317 the PCI clock domain registers1654 * are outside of the WMAC register space */1655 if (unlikely((reg >= 0x4000) && (reg < 0x5000) &&1656 (ah->ah_mac_srev >= AR5K_SREV_AR2315_R6)))1657 return AR5K_AR2315_PCI_BASE + reg;1658 1659 return ah->iobase + reg;1660}1661 1662static inline u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg)1663{1664 return ioread32(ath5k_ahb_reg(ah, reg));1665}1666 1667static inline void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg)1668{1669 iowrite32(val, ath5k_ahb_reg(ah, reg));1670}1671 1672#else1673 1674static inline u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg)1675{1676 return ioread32(ah->iobase + reg);1677}1678 1679static inline void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg)1680{1681 iowrite32(val, ah->iobase + reg);1682}1683 1684#endif1685 1686static inline enum ath_bus_type ath5k_get_bus_type(struct ath5k_hw *ah)1687{1688 return ath5k_hw_common(ah)->bus_ops->ath_bus_type;1689}1690 1691static inline void ath5k_read_cachesize(struct ath_common *common, int *csz)1692{1693 common->bus_ops->read_cachesize(common, csz);1694}1695 1696static inline bool ath5k_hw_nvram_read(struct ath5k_hw *ah, u32 off, u16 *data)1697{1698 struct ath_common *common = ath5k_hw_common(ah);1699 return common->bus_ops->eeprom_read(common, off, data);1700}1701 1702static inline u32 ath5k_hw_bitswap(u32 val, unsigned int bits)1703{1704 u32 retval = 0, bit, i;1705 1706 for (i = 0; i < bits; i++) {1707 bit = (val >> i) & 1;1708 retval = (retval << 1) | bit;1709 }1710 1711 return retval;1712}1713 1714#endif1715