1606 lines · c
1/*2 * Initial register settings functions3 *4 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>5 * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com>6 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>7 *8 * Permission to use, copy, modify, and distribute this software for any9 * purpose with or without fee is hereby granted, provided that the above10 * copyright notice and this permission notice appear in all copies.11 *12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.19 *20 */21 22#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt23 24#include "ath5k.h"25#include "reg.h"26#include "debug.h"27 28/**29 * struct ath5k_ini - Mode-independent initial register writes30 * @ini_register: Register address31 * @ini_value: Default value32 * @ini_mode: 0 to write 1 to read (and clear)33 */34struct ath5k_ini {35 u16 ini_register;36 u32 ini_value;37 38 enum {39 AR5K_INI_WRITE = 0, /* Default */40 AR5K_INI_READ = 1,41 } ini_mode;42};43 44/**45 * struct ath5k_ini_mode - Mode specific initial register values46 * @mode_register: Register address47 * @mode_value: Set of values for each enum ath5k_driver_mode48 */49struct ath5k_ini_mode {50 u16 mode_register;51 u32 mode_value[3];52};53 54/* Initial register settings for AR5210 */55static const struct ath5k_ini ar5210_ini[] = {56 /* PCU and MAC registers */57 { AR5K_NOQCU_TXDP0, 0 },58 { AR5K_NOQCU_TXDP1, 0 },59 { AR5K_RXDP, 0 },60 { AR5K_CR, 0 },61 { AR5K_ISR, 0, AR5K_INI_READ },62 { AR5K_IMR, 0 },63 { AR5K_IER, AR5K_IER_DISABLE },64 { AR5K_BSR, 0, AR5K_INI_READ },65 { AR5K_TXCFG, AR5K_DMASIZE_128B },66 { AR5K_RXCFG, AR5K_DMASIZE_128B },67 { AR5K_CFG, AR5K_INIT_CFG },68 { AR5K_TOPS, 8 },69 { AR5K_RXNOFRM, 8 },70 { AR5K_RPGTO, 0 },71 { AR5K_TXNOFRM, 0 },72 { AR5K_SFR, 0 },73 { AR5K_MIBC, 0 },74 { AR5K_MISC, 0 },75 { AR5K_RX_FILTER_5210, 0 },76 { AR5K_MCAST_FILTER0_5210, 0 },77 { AR5K_MCAST_FILTER1_5210, 0 },78 { AR5K_TX_MASK0, 0 },79 { AR5K_TX_MASK1, 0 },80 { AR5K_CLR_TMASK, 0 },81 { AR5K_TRIG_LVL, AR5K_TUNE_MIN_TX_FIFO_THRES },82 { AR5K_DIAG_SW_5210, 0 },83 { AR5K_RSSI_THR, AR5K_TUNE_RSSI_THRES },84 { AR5K_TSF_L32_5210, 0 },85 { AR5K_TIMER0_5210, 0 },86 { AR5K_TIMER1_5210, 0xffffffff },87 { AR5K_TIMER2_5210, 0xffffffff },88 { AR5K_TIMER3_5210, 1 },89 { AR5K_CFP_DUR_5210, 0 },90 { AR5K_CFP_PERIOD_5210, 0 },91 /* PHY registers */92 { AR5K_PHY(0), 0x00000047 },93 { AR5K_PHY_AGC, 0x00000000 },94 { AR5K_PHY(3), 0x09848ea6 },95 { AR5K_PHY(4), 0x3d32e000 },96 { AR5K_PHY(5), 0x0000076b },97 { AR5K_PHY_ACT, AR5K_PHY_ACT_DISABLE },98 { AR5K_PHY(8), 0x02020200 },99 { AR5K_PHY(9), 0x00000e0e },100 { AR5K_PHY(10), 0x0a020201 },101 { AR5K_PHY(11), 0x00036ffc },102 { AR5K_PHY(12), 0x00000000 },103 { AR5K_PHY(13), 0x00000e0e },104 { AR5K_PHY(14), 0x00000007 },105 { AR5K_PHY(15), 0x00020100 },106 { AR5K_PHY(16), 0x89630000 },107 { AR5K_PHY(17), 0x1372169c },108 { AR5K_PHY(18), 0x0018b633 },109 { AR5K_PHY(19), 0x1284613c },110 { AR5K_PHY(20), 0x0de8b8e0 },111 { AR5K_PHY(21), 0x00074859 },112 { AR5K_PHY(22), 0x7e80beba },113 { AR5K_PHY(23), 0x313a665e },114 { AR5K_PHY_AGCCTL, 0x00001d08 },115 { AR5K_PHY(25), 0x0001ce00 },116 { AR5K_PHY(26), 0x409a4190 },117 { AR5K_PHY(28), 0x0000000f },118 { AR5K_PHY(29), 0x00000080 },119 { AR5K_PHY(30), 0x00000004 },120 { AR5K_PHY(31), 0x00000018 }, /* 0x987c */121 { AR5K_PHY(64), 0x00000000 }, /* 0x9900 */122 { AR5K_PHY(65), 0x00000000 },123 { AR5K_PHY(66), 0x00000000 },124 { AR5K_PHY(67), 0x00800000 },125 { AR5K_PHY(68), 0x00000003 },126 /* BB gain table (64bytes) */127 { AR5K_BB_GAIN(0), 0x00000000 },128 { AR5K_BB_GAIN(1), 0x00000020 },129 { AR5K_BB_GAIN(2), 0x00000010 },130 { AR5K_BB_GAIN(3), 0x00000030 },131 { AR5K_BB_GAIN(4), 0x00000008 },132 { AR5K_BB_GAIN(5), 0x00000028 },133 { AR5K_BB_GAIN(6), 0x00000028 },134 { AR5K_BB_GAIN(7), 0x00000004 },135 { AR5K_BB_GAIN(8), 0x00000024 },136 { AR5K_BB_GAIN(9), 0x00000014 },137 { AR5K_BB_GAIN(10), 0x00000034 },138 { AR5K_BB_GAIN(11), 0x0000000c },139 { AR5K_BB_GAIN(12), 0x0000002c },140 { AR5K_BB_GAIN(13), 0x00000002 },141 { AR5K_BB_GAIN(14), 0x00000022 },142 { AR5K_BB_GAIN(15), 0x00000012 },143 { AR5K_BB_GAIN(16), 0x00000032 },144 { AR5K_BB_GAIN(17), 0x0000000a },145 { AR5K_BB_GAIN(18), 0x0000002a },146 { AR5K_BB_GAIN(19), 0x00000001 },147 { AR5K_BB_GAIN(20), 0x00000021 },148 { AR5K_BB_GAIN(21), 0x00000011 },149 { AR5K_BB_GAIN(22), 0x00000031 },150 { AR5K_BB_GAIN(23), 0x00000009 },151 { AR5K_BB_GAIN(24), 0x00000029 },152 { AR5K_BB_GAIN(25), 0x00000005 },153 { AR5K_BB_GAIN(26), 0x00000025 },154 { AR5K_BB_GAIN(27), 0x00000015 },155 { AR5K_BB_GAIN(28), 0x00000035 },156 { AR5K_BB_GAIN(29), 0x0000000d },157 { AR5K_BB_GAIN(30), 0x0000002d },158 { AR5K_BB_GAIN(31), 0x00000003 },159 { AR5K_BB_GAIN(32), 0x00000023 },160 { AR5K_BB_GAIN(33), 0x00000013 },161 { AR5K_BB_GAIN(34), 0x00000033 },162 { AR5K_BB_GAIN(35), 0x0000000b },163 { AR5K_BB_GAIN(36), 0x0000002b },164 { AR5K_BB_GAIN(37), 0x00000007 },165 { AR5K_BB_GAIN(38), 0x00000027 },166 { AR5K_BB_GAIN(39), 0x00000017 },167 { AR5K_BB_GAIN(40), 0x00000037 },168 { AR5K_BB_GAIN(41), 0x0000000f },169 { AR5K_BB_GAIN(42), 0x0000002f },170 { AR5K_BB_GAIN(43), 0x0000002f },171 { AR5K_BB_GAIN(44), 0x0000002f },172 { AR5K_BB_GAIN(45), 0x0000002f },173 { AR5K_BB_GAIN(46), 0x0000002f },174 { AR5K_BB_GAIN(47), 0x0000002f },175 { AR5K_BB_GAIN(48), 0x0000002f },176 { AR5K_BB_GAIN(49), 0x0000002f },177 { AR5K_BB_GAIN(50), 0x0000002f },178 { AR5K_BB_GAIN(51), 0x0000002f },179 { AR5K_BB_GAIN(52), 0x0000002f },180 { AR5K_BB_GAIN(53), 0x0000002f },181 { AR5K_BB_GAIN(54), 0x0000002f },182 { AR5K_BB_GAIN(55), 0x0000002f },183 { AR5K_BB_GAIN(56), 0x0000002f },184 { AR5K_BB_GAIN(57), 0x0000002f },185 { AR5K_BB_GAIN(58), 0x0000002f },186 { AR5K_BB_GAIN(59), 0x0000002f },187 { AR5K_BB_GAIN(60), 0x0000002f },188 { AR5K_BB_GAIN(61), 0x0000002f },189 { AR5K_BB_GAIN(62), 0x0000002f },190 { AR5K_BB_GAIN(63), 0x0000002f },191 /* 5110 RF gain table (64btes) */192 { AR5K_RF_GAIN(0), 0x0000001d },193 { AR5K_RF_GAIN(1), 0x0000005d },194 { AR5K_RF_GAIN(2), 0x0000009d },195 { AR5K_RF_GAIN(3), 0x000000dd },196 { AR5K_RF_GAIN(4), 0x0000011d },197 { AR5K_RF_GAIN(5), 0x00000021 },198 { AR5K_RF_GAIN(6), 0x00000061 },199 { AR5K_RF_GAIN(7), 0x000000a1 },200 { AR5K_RF_GAIN(8), 0x000000e1 },201 { AR5K_RF_GAIN(9), 0x00000031 },202 { AR5K_RF_GAIN(10), 0x00000071 },203 { AR5K_RF_GAIN(11), 0x000000b1 },204 { AR5K_RF_GAIN(12), 0x0000001c },205 { AR5K_RF_GAIN(13), 0x0000005c },206 { AR5K_RF_GAIN(14), 0x00000029 },207 { AR5K_RF_GAIN(15), 0x00000069 },208 { AR5K_RF_GAIN(16), 0x000000a9 },209 { AR5K_RF_GAIN(17), 0x00000020 },210 { AR5K_RF_GAIN(18), 0x00000019 },211 { AR5K_RF_GAIN(19), 0x00000059 },212 { AR5K_RF_GAIN(20), 0x00000099 },213 { AR5K_RF_GAIN(21), 0x00000030 },214 { AR5K_RF_GAIN(22), 0x00000005 },215 { AR5K_RF_GAIN(23), 0x00000025 },216 { AR5K_RF_GAIN(24), 0x00000065 },217 { AR5K_RF_GAIN(25), 0x000000a5 },218 { AR5K_RF_GAIN(26), 0x00000028 },219 { AR5K_RF_GAIN(27), 0x00000068 },220 { AR5K_RF_GAIN(28), 0x0000001f },221 { AR5K_RF_GAIN(29), 0x0000001e },222 { AR5K_RF_GAIN(30), 0x00000018 },223 { AR5K_RF_GAIN(31), 0x00000058 },224 { AR5K_RF_GAIN(32), 0x00000098 },225 { AR5K_RF_GAIN(33), 0x00000003 },226 { AR5K_RF_GAIN(34), 0x00000004 },227 { AR5K_RF_GAIN(35), 0x00000044 },228 { AR5K_RF_GAIN(36), 0x00000084 },229 { AR5K_RF_GAIN(37), 0x00000013 },230 { AR5K_RF_GAIN(38), 0x00000012 },231 { AR5K_RF_GAIN(39), 0x00000052 },232 { AR5K_RF_GAIN(40), 0x00000092 },233 { AR5K_RF_GAIN(41), 0x000000d2 },234 { AR5K_RF_GAIN(42), 0x0000002b },235 { AR5K_RF_GAIN(43), 0x0000002a },236 { AR5K_RF_GAIN(44), 0x0000006a },237 { AR5K_RF_GAIN(45), 0x000000aa },238 { AR5K_RF_GAIN(46), 0x0000001b },239 { AR5K_RF_GAIN(47), 0x0000001a },240 { AR5K_RF_GAIN(48), 0x0000005a },241 { AR5K_RF_GAIN(49), 0x0000009a },242 { AR5K_RF_GAIN(50), 0x000000da },243 { AR5K_RF_GAIN(51), 0x00000006 },244 { AR5K_RF_GAIN(52), 0x00000006 },245 { AR5K_RF_GAIN(53), 0x00000006 },246 { AR5K_RF_GAIN(54), 0x00000006 },247 { AR5K_RF_GAIN(55), 0x00000006 },248 { AR5K_RF_GAIN(56), 0x00000006 },249 { AR5K_RF_GAIN(57), 0x00000006 },250 { AR5K_RF_GAIN(58), 0x00000006 },251 { AR5K_RF_GAIN(59), 0x00000006 },252 { AR5K_RF_GAIN(60), 0x00000006 },253 { AR5K_RF_GAIN(61), 0x00000006 },254 { AR5K_RF_GAIN(62), 0x00000006 },255 { AR5K_RF_GAIN(63), 0x00000006 },256 /* PHY activation */257 { AR5K_PHY(53), 0x00000020 },258 { AR5K_PHY(51), 0x00000004 },259 { AR5K_PHY(50), 0x00060106 },260 { AR5K_PHY(39), 0x0000006d },261 { AR5K_PHY(48), 0x00000000 },262 { AR5K_PHY(52), 0x00000014 },263 { AR5K_PHY_ACT, AR5K_PHY_ACT_ENABLE },264};265 266/* Initial register settings for AR5211 */267static const struct ath5k_ini ar5211_ini[] = {268 { AR5K_RXDP, 0x00000000 },269 { AR5K_RTSD0, 0x84849c9c },270 { AR5K_RTSD1, 0x7c7c7c7c },271 { AR5K_RXCFG, 0x00000005 },272 { AR5K_MIBC, 0x00000000 },273 { AR5K_TOPS, 0x00000008 },274 { AR5K_RXNOFRM, 0x00000008 },275 { AR5K_TXNOFRM, 0x00000010 },276 { AR5K_RPGTO, 0x00000000 },277 { AR5K_RFCNT, 0x0000001f },278 { AR5K_QUEUE_TXDP(0), 0x00000000 },279 { AR5K_QUEUE_TXDP(1), 0x00000000 },280 { AR5K_QUEUE_TXDP(2), 0x00000000 },281 { AR5K_QUEUE_TXDP(3), 0x00000000 },282 { AR5K_QUEUE_TXDP(4), 0x00000000 },283 { AR5K_QUEUE_TXDP(5), 0x00000000 },284 { AR5K_QUEUE_TXDP(6), 0x00000000 },285 { AR5K_QUEUE_TXDP(7), 0x00000000 },286 { AR5K_QUEUE_TXDP(8), 0x00000000 },287 { AR5K_QUEUE_TXDP(9), 0x00000000 },288 { AR5K_DCU_FP, 0x00000000 },289 { AR5K_STA_ID1, 0x00000000 },290 { AR5K_BSS_ID0, 0x00000000 },291 { AR5K_BSS_ID1, 0x00000000 },292 { AR5K_RSSI_THR, 0x00000000 },293 { AR5K_CFP_PERIOD_5211, 0x00000000 },294 { AR5K_TIMER0_5211, 0x00000030 },295 { AR5K_TIMER1_5211, 0x0007ffff },296 { AR5K_TIMER2_5211, 0x01ffffff },297 { AR5K_TIMER3_5211, 0x00000031 },298 { AR5K_CFP_DUR_5211, 0x00000000 },299 { AR5K_RX_FILTER_5211, 0x00000000 },300 { AR5K_MCAST_FILTER0_5211, 0x00000000 },301 { AR5K_MCAST_FILTER1_5211, 0x00000002 },302 { AR5K_DIAG_SW_5211, 0x00000000 },303 { AR5K_ADDAC_TEST, 0x00000000 },304 { AR5K_DEFAULT_ANTENNA, 0x00000000 },305 /* PHY registers */306 { AR5K_PHY_AGC, 0x00000000 },307 { AR5K_PHY(3), 0x2d849093 },308 { AR5K_PHY(4), 0x7d32e000 },309 { AR5K_PHY(5), 0x00000f6b },310 { AR5K_PHY_ACT, 0x00000000 },311 { AR5K_PHY(11), 0x00026ffe },312 { AR5K_PHY(12), 0x00000000 },313 { AR5K_PHY(15), 0x00020100 },314 { AR5K_PHY(16), 0x206a017a },315 { AR5K_PHY(19), 0x1284613c },316 { AR5K_PHY(21), 0x00000859 },317 { AR5K_PHY(26), 0x409a4190 }, /* 0x9868 */318 { AR5K_PHY(27), 0x050cb081 },319 { AR5K_PHY(28), 0x0000000f },320 { AR5K_PHY(29), 0x00000080 },321 { AR5K_PHY(30), 0x0000000c },322 { AR5K_PHY(64), 0x00000000 },323 { AR5K_PHY(65), 0x00000000 },324 { AR5K_PHY(66), 0x00000000 },325 { AR5K_PHY(67), 0x00800000 },326 { AR5K_PHY(68), 0x00000001 },327 { AR5K_PHY(71), 0x0000092a },328 { AR5K_PHY_IQ, 0x00000000 },329 { AR5K_PHY(73), 0x00058a05 },330 { AR5K_PHY(74), 0x00000001 },331 { AR5K_PHY(75), 0x00000000 },332 { AR5K_PHY_PAPD_PROBE, 0x00000000 },333 { AR5K_PHY(77), 0x00000000 }, /* 0x9934 */334 { AR5K_PHY(78), 0x00000000 }, /* 0x9938 */335 { AR5K_PHY(79), 0x0000003f }, /* 0x993c */336 { AR5K_PHY(80), 0x00000004 },337 { AR5K_PHY(82), 0x00000000 },338 { AR5K_PHY(83), 0x00000000 },339 { AR5K_PHY(84), 0x00000000 },340 { AR5K_PHY_RADAR, 0x5d50f14c },341 { AR5K_PHY(86), 0x00000018 },342 { AR5K_PHY(87), 0x004b6a8e },343 /* Initial Power table (32bytes)344 * common on all cards/modes.345 * Note: Table is rewritten during346 * txpower setup later using calibration347 * data etc. so next write is non-common */348 { AR5K_PHY_PCDAC_TXPOWER(1), 0x06ff05ff },349 { AR5K_PHY_PCDAC_TXPOWER(2), 0x07ff07ff },350 { AR5K_PHY_PCDAC_TXPOWER(3), 0x08ff08ff },351 { AR5K_PHY_PCDAC_TXPOWER(4), 0x09ff09ff },352 { AR5K_PHY_PCDAC_TXPOWER(5), 0x0aff0aff },353 { AR5K_PHY_PCDAC_TXPOWER(6), 0x0bff0bff },354 { AR5K_PHY_PCDAC_TXPOWER(7), 0x0cff0cff },355 { AR5K_PHY_PCDAC_TXPOWER(8), 0x0dff0dff },356 { AR5K_PHY_PCDAC_TXPOWER(9), 0x0fff0eff },357 { AR5K_PHY_PCDAC_TXPOWER(10), 0x12ff12ff },358 { AR5K_PHY_PCDAC_TXPOWER(11), 0x14ff13ff },359 { AR5K_PHY_PCDAC_TXPOWER(12), 0x16ff15ff },360 { AR5K_PHY_PCDAC_TXPOWER(13), 0x19ff17ff },361 { AR5K_PHY_PCDAC_TXPOWER(14), 0x1bff1aff },362 { AR5K_PHY_PCDAC_TXPOWER(15), 0x1eff1dff },363 { AR5K_PHY_PCDAC_TXPOWER(16), 0x23ff20ff },364 { AR5K_PHY_PCDAC_TXPOWER(17), 0x27ff25ff },365 { AR5K_PHY_PCDAC_TXPOWER(18), 0x2cff29ff },366 { AR5K_PHY_PCDAC_TXPOWER(19), 0x31ff2fff },367 { AR5K_PHY_PCDAC_TXPOWER(20), 0x37ff34ff },368 { AR5K_PHY_PCDAC_TXPOWER(21), 0x3aff3aff },369 { AR5K_PHY_PCDAC_TXPOWER(22), 0x3aff3aff },370 { AR5K_PHY_PCDAC_TXPOWER(23), 0x3aff3aff },371 { AR5K_PHY_PCDAC_TXPOWER(24), 0x3aff3aff },372 { AR5K_PHY_PCDAC_TXPOWER(25), 0x3aff3aff },373 { AR5K_PHY_PCDAC_TXPOWER(26), 0x3aff3aff },374 { AR5K_PHY_PCDAC_TXPOWER(27), 0x3aff3aff },375 { AR5K_PHY_PCDAC_TXPOWER(28), 0x3aff3aff },376 { AR5K_PHY_PCDAC_TXPOWER(29), 0x3aff3aff },377 { AR5K_PHY_PCDAC_TXPOWER(30), 0x3aff3aff },378 { AR5K_PHY_PCDAC_TXPOWER(31), 0x3aff3aff },379 { AR5K_PHY_CCKTXCTL, 0x00000000 },380 { AR5K_PHY(642), 0x503e4646 },381 { AR5K_PHY_GAIN_2GHZ, 0x6480416c },382 { AR5K_PHY(644), 0x0199a003 },383 { AR5K_PHY(645), 0x044cd610 },384 { AR5K_PHY(646), 0x13800040 },385 { AR5K_PHY(647), 0x1be00060 },386 { AR5K_PHY(648), 0x0c53800a },387 { AR5K_PHY(649), 0x0014df3b },388 { AR5K_PHY(650), 0x000001b5 },389 { AR5K_PHY(651), 0x00000020 },390};391 392/* Initial mode-specific settings for AR5211393 * 5211 supports OFDM-only g (draft g) but we394 * need to test it ! */395static const struct ath5k_ini_mode ar5211_ini_mode[] = {396 { AR5K_TXCFG,397 /* A B G */398 { 0x00000015, 0x0000001d, 0x00000015 } },399 { AR5K_QUEUE_DFS_LOCAL_IFS(0),400 { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },401 { AR5K_QUEUE_DFS_LOCAL_IFS(1),402 { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },403 { AR5K_QUEUE_DFS_LOCAL_IFS(2),404 { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },405 { AR5K_QUEUE_DFS_LOCAL_IFS(3),406 { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },407 { AR5K_QUEUE_DFS_LOCAL_IFS(4),408 { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },409 { AR5K_QUEUE_DFS_LOCAL_IFS(5),410 { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },411 { AR5K_QUEUE_DFS_LOCAL_IFS(6),412 { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },413 { AR5K_QUEUE_DFS_LOCAL_IFS(7),414 { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },415 { AR5K_QUEUE_DFS_LOCAL_IFS(8),416 { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },417 { AR5K_QUEUE_DFS_LOCAL_IFS(9),418 { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },419 { AR5K_DCU_GBL_IFS_SLOT,420 { 0x00000168, 0x000001b8, 0x00000168 } },421 { AR5K_DCU_GBL_IFS_SIFS,422 { 0x00000230, 0x000000b0, 0x00000230 } },423 { AR5K_DCU_GBL_IFS_EIFS,424 { 0x00000d98, 0x00001f48, 0x00000d98 } },425 { AR5K_DCU_GBL_IFS_MISC,426 { 0x0000a0e0, 0x00005880, 0x0000a0e0 } },427 { AR5K_TIME_OUT,428 { 0x04000400, 0x20003000, 0x04000400 } },429 { AR5K_USEC_5211,430 { 0x0e8d8fa7, 0x01608f95, 0x0e8d8fa7 } },431 { AR5K_PHY(8),432 { 0x02020200, 0x02010200, 0x02020200 } },433 { AR5K_PHY_RF_CTL2,434 { 0x00000e0e, 0x00000707, 0x00000e0e } },435 { AR5K_PHY_RF_CTL3,436 { 0x0a020001, 0x05010000, 0x0a020001 } },437 { AR5K_PHY_RF_CTL4,438 { 0x00000e0e, 0x00000e0e, 0x00000e0e } },439 { AR5K_PHY_PA_CTL,440 { 0x00000007, 0x0000000b, 0x0000000b } },441 { AR5K_PHY_SETTLING,442 { 0x1372169c, 0x137216a8, 0x1372169c } },443 { AR5K_PHY_GAIN,444 { 0x0018ba67, 0x0018ba69, 0x0018ba69 } },445 { AR5K_PHY_DESIRED_SIZE,446 { 0x0c28b4e0, 0x0c28b4e0, 0x0c28b4e0 } },447 { AR5K_PHY_SIG,448 { 0x7e800d2e, 0x7ec00d2e, 0x7e800d2e } },449 { AR5K_PHY_AGCCOARSE,450 { 0x31375d5e, 0x313a5d5e, 0x31375d5e } },451 { AR5K_PHY_AGCCTL,452 { 0x0000bd10, 0x0000bd38, 0x0000bd10 } },453 { AR5K_PHY_NF,454 { 0x0001ce00, 0x0001ce00, 0x0001ce00 } },455 { AR5K_PHY_RX_DELAY,456 { 0x00002710, 0x0000157c, 0x00002710 } },457 { AR5K_PHY(70),458 { 0x00000190, 0x00000084, 0x00000190 } },459 { AR5K_PHY_FRAME_CTL_5211,460 { 0x6fe01020, 0x6fe00920, 0x6fe01020 } },461 { AR5K_PHY_PCDAC_TXPOWER_BASE,462 { 0x05ff14ff, 0x05ff14ff, 0x05ff19ff } },463 { AR5K_RF_BUFFER_CONTROL_4,464 { 0x00000010, 0x00000010, 0x00000010 } },465};466 467/* Initial register settings for AR5212 and newer chips */468static const struct ath5k_ini ar5212_ini_common_start[] = {469 { AR5K_RXDP, 0x00000000 },470 { AR5K_RXCFG, 0x00000005 },471 { AR5K_MIBC, 0x00000000 },472 { AR5K_TOPS, 0x00000008 },473 { AR5K_RXNOFRM, 0x00000008 },474 { AR5K_TXNOFRM, 0x00000010 },475 { AR5K_RPGTO, 0x00000000 },476 { AR5K_RFCNT, 0x0000001f },477 { AR5K_QUEUE_TXDP(0), 0x00000000 },478 { AR5K_QUEUE_TXDP(1), 0x00000000 },479 { AR5K_QUEUE_TXDP(2), 0x00000000 },480 { AR5K_QUEUE_TXDP(3), 0x00000000 },481 { AR5K_QUEUE_TXDP(4), 0x00000000 },482 { AR5K_QUEUE_TXDP(5), 0x00000000 },483 { AR5K_QUEUE_TXDP(6), 0x00000000 },484 { AR5K_QUEUE_TXDP(7), 0x00000000 },485 { AR5K_QUEUE_TXDP(8), 0x00000000 },486 { AR5K_QUEUE_TXDP(9), 0x00000000 },487 { AR5K_DCU_FP, 0x00000000 },488 { AR5K_DCU_TXP, 0x00000000 },489 /* Tx filter table 0 (32 entries) */490 { AR5K_DCU_TX_FILTER_0(0), 0x00000000 }, /* DCU 0 */491 { AR5K_DCU_TX_FILTER_0(1), 0x00000000 },492 { AR5K_DCU_TX_FILTER_0(2), 0x00000000 },493 { AR5K_DCU_TX_FILTER_0(3), 0x00000000 },494 { AR5K_DCU_TX_FILTER_0(4), 0x00000000 }, /* DCU 1 */495 { AR5K_DCU_TX_FILTER_0(5), 0x00000000 },496 { AR5K_DCU_TX_FILTER_0(6), 0x00000000 },497 { AR5K_DCU_TX_FILTER_0(7), 0x00000000 },498 { AR5K_DCU_TX_FILTER_0(8), 0x00000000 }, /* DCU 2 */499 { AR5K_DCU_TX_FILTER_0(9), 0x00000000 },500 { AR5K_DCU_TX_FILTER_0(10), 0x00000000 },501 { AR5K_DCU_TX_FILTER_0(11), 0x00000000 },502 { AR5K_DCU_TX_FILTER_0(12), 0x00000000 }, /* DCU 3 */503 { AR5K_DCU_TX_FILTER_0(13), 0x00000000 },504 { AR5K_DCU_TX_FILTER_0(14), 0x00000000 },505 { AR5K_DCU_TX_FILTER_0(15), 0x00000000 },506 { AR5K_DCU_TX_FILTER_0(16), 0x00000000 }, /* DCU 4 */507 { AR5K_DCU_TX_FILTER_0(17), 0x00000000 },508 { AR5K_DCU_TX_FILTER_0(18), 0x00000000 },509 { AR5K_DCU_TX_FILTER_0(19), 0x00000000 },510 { AR5K_DCU_TX_FILTER_0(20), 0x00000000 }, /* DCU 5 */511 { AR5K_DCU_TX_FILTER_0(21), 0x00000000 },512 { AR5K_DCU_TX_FILTER_0(22), 0x00000000 },513 { AR5K_DCU_TX_FILTER_0(23), 0x00000000 },514 { AR5K_DCU_TX_FILTER_0(24), 0x00000000 }, /* DCU 6 */515 { AR5K_DCU_TX_FILTER_0(25), 0x00000000 },516 { AR5K_DCU_TX_FILTER_0(26), 0x00000000 },517 { AR5K_DCU_TX_FILTER_0(27), 0x00000000 },518 { AR5K_DCU_TX_FILTER_0(28), 0x00000000 }, /* DCU 7 */519 { AR5K_DCU_TX_FILTER_0(29), 0x00000000 },520 { AR5K_DCU_TX_FILTER_0(30), 0x00000000 },521 { AR5K_DCU_TX_FILTER_0(31), 0x00000000 },522 /* Tx filter table 1 (16 entries) */523 { AR5K_DCU_TX_FILTER_1(0), 0x00000000 },524 { AR5K_DCU_TX_FILTER_1(1), 0x00000000 },525 { AR5K_DCU_TX_FILTER_1(2), 0x00000000 },526 { AR5K_DCU_TX_FILTER_1(3), 0x00000000 },527 { AR5K_DCU_TX_FILTER_1(4), 0x00000000 },528 { AR5K_DCU_TX_FILTER_1(5), 0x00000000 },529 { AR5K_DCU_TX_FILTER_1(6), 0x00000000 },530 { AR5K_DCU_TX_FILTER_1(7), 0x00000000 },531 { AR5K_DCU_TX_FILTER_1(8), 0x00000000 },532 { AR5K_DCU_TX_FILTER_1(9), 0x00000000 },533 { AR5K_DCU_TX_FILTER_1(10), 0x00000000 },534 { AR5K_DCU_TX_FILTER_1(11), 0x00000000 },535 { AR5K_DCU_TX_FILTER_1(12), 0x00000000 },536 { AR5K_DCU_TX_FILTER_1(13), 0x00000000 },537 { AR5K_DCU_TX_FILTER_1(14), 0x00000000 },538 { AR5K_DCU_TX_FILTER_1(15), 0x00000000 },539 { AR5K_DCU_TX_FILTER_CLR, 0x00000000 },540 { AR5K_DCU_TX_FILTER_SET, 0x00000000 },541 { AR5K_STA_ID1, 0x00000000 },542 { AR5K_BSS_ID0, 0x00000000 },543 { AR5K_BSS_ID1, 0x00000000 },544 { AR5K_BEACON_5211, 0x00000000 },545 { AR5K_CFP_PERIOD_5211, 0x00000000 },546 { AR5K_TIMER0_5211, 0x00000030 },547 { AR5K_TIMER1_5211, 0x0007ffff },548 { AR5K_TIMER2_5211, 0x01ffffff },549 { AR5K_TIMER3_5211, 0x00000031 },550 { AR5K_CFP_DUR_5211, 0x00000000 },551 { AR5K_RX_FILTER_5211, 0x00000000 },552 { AR5K_DIAG_SW_5211, 0x00000000 },553 { AR5K_ADDAC_TEST, 0x00000000 },554 { AR5K_DEFAULT_ANTENNA, 0x00000000 },555 { AR5K_FRAME_CTL_QOSM, 0x000fc78f },556 { AR5K_XRMODE, 0x2a82301a },557 { AR5K_XRDELAY, 0x05dc01e0 },558 { AR5K_XRTIMEOUT, 0x1f402710 },559 { AR5K_XRCHIRP, 0x01f40000 },560 { AR5K_XRSTOMP, 0x00001e1c },561 { AR5K_SLEEP0, 0x0002aaaa },562 { AR5K_SLEEP1, 0x02005555 },563 { AR5K_SLEEP2, 0x00000000 },564 { AR_BSSMSKL, 0xffffffff },565 { AR_BSSMSKU, 0x0000ffff },566 { AR5K_TXPC, 0x00000000 },567 { AR5K_PROFCNT_TX, 0x00000000 },568 { AR5K_PROFCNT_RX, 0x00000000 },569 { AR5K_PROFCNT_RXCLR, 0x00000000 },570 { AR5K_PROFCNT_CYCLE, 0x00000000 },571 { AR5K_QUIET_CTL1, 0x00000088 },572 /* Initial rate duration table (32 entries )*/573 { AR5K_RATE_DUR(0), 0x00000000 },574 { AR5K_RATE_DUR(1), 0x0000008c },575 { AR5K_RATE_DUR(2), 0x000000e4 },576 { AR5K_RATE_DUR(3), 0x000002d5 },577 { AR5K_RATE_DUR(4), 0x00000000 },578 { AR5K_RATE_DUR(5), 0x00000000 },579 { AR5K_RATE_DUR(6), 0x000000a0 },580 { AR5K_RATE_DUR(7), 0x000001c9 },581 { AR5K_RATE_DUR(8), 0x0000002c },582 { AR5K_RATE_DUR(9), 0x0000002c },583 { AR5K_RATE_DUR(10), 0x00000030 },584 { AR5K_RATE_DUR(11), 0x0000003c },585 { AR5K_RATE_DUR(12), 0x0000002c },586 { AR5K_RATE_DUR(13), 0x0000002c },587 { AR5K_RATE_DUR(14), 0x00000030 },588 { AR5K_RATE_DUR(15), 0x0000003c },589 { AR5K_RATE_DUR(16), 0x00000000 },590 { AR5K_RATE_DUR(17), 0x00000000 },591 { AR5K_RATE_DUR(18), 0x00000000 },592 { AR5K_RATE_DUR(19), 0x00000000 },593 { AR5K_RATE_DUR(20), 0x00000000 },594 { AR5K_RATE_DUR(21), 0x00000000 },595 { AR5K_RATE_DUR(22), 0x00000000 },596 { AR5K_RATE_DUR(23), 0x00000000 },597 { AR5K_RATE_DUR(24), 0x000000d5 },598 { AR5K_RATE_DUR(25), 0x000000df },599 { AR5K_RATE_DUR(26), 0x00000102 },600 { AR5K_RATE_DUR(27), 0x0000013a },601 { AR5K_RATE_DUR(28), 0x00000075 },602 { AR5K_RATE_DUR(29), 0x0000007f },603 { AR5K_RATE_DUR(30), 0x000000a2 },604 { AR5K_RATE_DUR(31), 0x00000000 },605 { AR5K_QUIET_CTL2, 0x00010002 },606 { AR5K_TSF_PARM, 0x00000001 },607 { AR5K_QOS_NOACK, 0x000000c0 },608 { AR5K_PHY_ERR_FIL, 0x00000000 },609 { AR5K_XRLAT_TX, 0x00000168 },610 { AR5K_ACKSIFS, 0x00000000 },611 /* Rate -> db table612 * notice ...03<-02<-01<-00 ! */613 { AR5K_RATE2DB(0), 0x03020100 },614 { AR5K_RATE2DB(1), 0x07060504 },615 { AR5K_RATE2DB(2), 0x0b0a0908 },616 { AR5K_RATE2DB(3), 0x0f0e0d0c },617 { AR5K_RATE2DB(4), 0x13121110 },618 { AR5K_RATE2DB(5), 0x17161514 },619 { AR5K_RATE2DB(6), 0x1b1a1918 },620 { AR5K_RATE2DB(7), 0x1f1e1d1c },621 /* Db -> Rate table */622 { AR5K_DB2RATE(0), 0x03020100 },623 { AR5K_DB2RATE(1), 0x07060504 },624 { AR5K_DB2RATE(2), 0x0b0a0908 },625 { AR5K_DB2RATE(3), 0x0f0e0d0c },626 { AR5K_DB2RATE(4), 0x13121110 },627 { AR5K_DB2RATE(5), 0x17161514 },628 { AR5K_DB2RATE(6), 0x1b1a1918 },629 { AR5K_DB2RATE(7), 0x1f1e1d1c },630 /* PHY registers (Common settings631 * for all chips/modes) */632 { AR5K_PHY(3), 0xad848e19 },633 { AR5K_PHY(4), 0x7d28e000 },634 { AR5K_PHY_TIMING_3, 0x9c0a9f6b },635 { AR5K_PHY_ACT, 0x00000000 },636 { AR5K_PHY(16), 0x206a017a },637 { AR5K_PHY(21), 0x00000859 },638 { AR5K_PHY_BIN_MASK_1, 0x00000000 },639 { AR5K_PHY_BIN_MASK_2, 0x00000000 },640 { AR5K_PHY_BIN_MASK_3, 0x00000000 },641 { AR5K_PHY_BIN_MASK_CTL, 0x00800000 },642 { AR5K_PHY_ANT_CTL, 0x00000001 },643 /*{ AR5K_PHY(71), 0x0000092a },*/ /* Old value */644 { AR5K_PHY_MAX_RX_LEN, 0x00000c80 },645 { AR5K_PHY_IQ, 0x05100000 },646 { AR5K_PHY_WARM_RESET, 0x00000001 },647 { AR5K_PHY_CTL, 0x00000004 },648 { AR5K_PHY_TXPOWER_RATE1, 0x1e1f2022 },649 { AR5K_PHY_TXPOWER_RATE2, 0x0a0b0c0d },650 { AR5K_PHY_TXPOWER_RATE_MAX, 0x0000003f },651 { AR5K_PHY(82), 0x9280b212 },652 { AR5K_PHY_RADAR, 0x5d50e188 },653 /*{ AR5K_PHY(86), 0x000000ff },*/654 { AR5K_PHY(87), 0x004b6a8e },655 { AR5K_PHY_NFTHRES, 0x000003ce },656 { AR5K_PHY_RESTART, 0x192fb515 },657 { AR5K_PHY(94), 0x00000001 },658 { AR5K_PHY_RFBUS_REQ, 0x00000000 },659 /*{ AR5K_PHY(644), 0x0080a333 },*/ /* Old value */660 /*{ AR5K_PHY(645), 0x00206c10 },*/ /* Old value */661 { AR5K_PHY(644), 0x00806333 },662 { AR5K_PHY(645), 0x00106c10 },663 { AR5K_PHY(646), 0x009c4060 },664 /* { AR5K_PHY(647), 0x1483800a }, */665 /* { AR5K_PHY(648), 0x01831061 }, */ /* Old value */666 { AR5K_PHY(648), 0x018830c6 },667 { AR5K_PHY(649), 0x00000400 },668 /*{ AR5K_PHY(650), 0x000001b5 },*/669 { AR5K_PHY(651), 0x00000000 },670 { AR5K_PHY_TXPOWER_RATE3, 0x20202020 },671 { AR5K_PHY_TXPOWER_RATE4, 0x20202020 },672 /*{ AR5K_PHY(655), 0x13c889af },*/673 { AR5K_PHY(656), 0x38490a20 },674 { AR5K_PHY(657), 0x00007bb6 },675 { AR5K_PHY(658), 0x0fff3ffc },676};677 678/* Initial mode-specific settings for AR5212 (Written before ar5212_ini) */679static const struct ath5k_ini_mode ar5212_ini_mode_start[] = {680 { AR5K_QUEUE_DFS_LOCAL_IFS(0),681 /* A/XR B G */682 { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },683 { AR5K_QUEUE_DFS_LOCAL_IFS(1),684 { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },685 { AR5K_QUEUE_DFS_LOCAL_IFS(2),686 { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },687 { AR5K_QUEUE_DFS_LOCAL_IFS(3),688 { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },689 { AR5K_QUEUE_DFS_LOCAL_IFS(4),690 { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },691 { AR5K_QUEUE_DFS_LOCAL_IFS(5),692 { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },693 { AR5K_QUEUE_DFS_LOCAL_IFS(6),694 { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },695 { AR5K_QUEUE_DFS_LOCAL_IFS(7),696 { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },697 { AR5K_QUEUE_DFS_LOCAL_IFS(8),698 { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },699 { AR5K_QUEUE_DFS_LOCAL_IFS(9),700 { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },701 { AR5K_DCU_GBL_IFS_SIFS,702 { 0x00000230, 0x000000b0, 0x00000160 } },703 { AR5K_DCU_GBL_IFS_SLOT,704 { 0x00000168, 0x000001b8, 0x0000018c } },705 { AR5K_DCU_GBL_IFS_EIFS,706 { 0x00000e60, 0x00001f1c, 0x00003e38 } },707 { AR5K_DCU_GBL_IFS_MISC,708 { 0x0000a0e0, 0x00005880, 0x0000b0e0 } },709 { AR5K_TIME_OUT,710 { 0x03e803e8, 0x04200420, 0x08400840 } },711 { AR5K_PHY(8),712 { 0x02020200, 0x02010200, 0x02020200 } },713 { AR5K_PHY_RF_CTL2,714 { 0x00000e0e, 0x00000707, 0x00000e0e } },715 { AR5K_PHY_SETTLING,716 { 0x1372161c, 0x13721722, 0x137216a2 } },717 { AR5K_PHY_AGCCTL,718 { 0x00009d10, 0x00009d18, 0x00009d18 } },719 { AR5K_PHY_NF,720 { 0x0001ce00, 0x0001ce00, 0x0001ce00 } },721 { AR5K_PHY_WEAK_OFDM_HIGH_THR,722 { 0x409a4190, 0x409a4190, 0x409a4190 } },723 { AR5K_PHY(70),724 { 0x000001b8, 0x00000084, 0x00000108 } },725 { AR5K_PHY_OFDM_SELFCORR,726 { 0x10058a05, 0x10058a05, 0x10058a05 } },727 { 0xa230,728 { 0x00000000, 0x00000000, 0x00000108 } },729};730 731/* Initial mode-specific settings for AR5212 + RF5111732 * (Written after ar5212_ini) */733static const struct ath5k_ini_mode rf5111_ini_mode_end[] = {734 { AR5K_TXCFG,735 /* A/XR B G */736 { 0x00008015, 0x00008015, 0x00008015 } },737 { AR5K_USEC_5211,738 { 0x128d8fa7, 0x04e00f95, 0x12e00fab } },739 { AR5K_PHY_RF_CTL3,740 { 0x0a020001, 0x05010100, 0x0a020001 } },741 { AR5K_PHY_RF_CTL4,742 { 0x00000e0e, 0x00000e0e, 0x00000e0e } },743 { AR5K_PHY_PA_CTL,744 { 0x00000007, 0x0000000b, 0x0000000b } },745 { AR5K_PHY_GAIN,746 { 0x0018da5a, 0x0018ca69, 0x0018ca69 } },747 { AR5K_PHY_DESIRED_SIZE,748 { 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0 } },749 { AR5K_PHY_SIG,750 { 0x7e800d2e, 0x7ee84d2e, 0x7ee84d2e } },751 { AR5K_PHY_AGCCOARSE,752 { 0x3137665e, 0x3137665e, 0x3137665e } },753 { AR5K_PHY_WEAK_OFDM_LOW_THR,754 { 0x050cb081, 0x050cb081, 0x050cb080 } },755 { AR5K_PHY_RX_DELAY,756 { 0x00002710, 0x0000157c, 0x00002af8 } },757 { AR5K_PHY_FRAME_CTL_5211,758 { 0xf7b81020, 0xf7b80d20, 0xf7b81020 } },759 { AR5K_PHY_GAIN_2GHZ,760 { 0x642c416a, 0x6440416a, 0x6440416a } },761 { AR5K_PHY_CCK_RX_CTL_4,762 { 0x1883800a, 0x1873800a, 0x1883800a } },763};764 765/* Common for all modes */766static const struct ath5k_ini rf5111_ini_common_end[] = {767 { AR5K_DCU_FP, 0x00000000 },768 { AR5K_PHY_AGC, 0x00000000 },769 { AR5K_PHY_ADC_CTL, 0x00022ffe },770 { 0x983c, 0x00020100 },771 { AR5K_PHY_GAIN_OFFSET, 0x1284613c },772 { AR5K_PHY_PAPD_PROBE, 0x00004883 },773 { 0x9940, 0x00000004 },774 { 0x9958, 0x000000ff },775 { 0x9974, 0x00000000 },776 { AR5K_PHY_SPENDING, 0x00000018 },777 { AR5K_PHY_CCKTXCTL, 0x00000000 },778 { AR5K_PHY_CCK_CROSSCORR, 0xd03e6788 },779 { AR5K_PHY_DAG_CCK_CTL, 0x000001b5 },780 { 0xa23c, 0x13c889af },781};782 783 784/* Initial mode-specific settings for AR5212 + RF5112785 * (Written after ar5212_ini) */786static const struct ath5k_ini_mode rf5112_ini_mode_end[] = {787 { AR5K_TXCFG,788 /* A/XR B G */789 { 0x00008015, 0x00008015, 0x00008015 } },790 { AR5K_USEC_5211,791 { 0x128d93a7, 0x04e01395, 0x12e013ab } },792 { AR5K_PHY_RF_CTL3,793 { 0x0a020001, 0x05020100, 0x0a020001 } },794 { AR5K_PHY_RF_CTL4,795 { 0x00000e0e, 0x00000e0e, 0x00000e0e } },796 { AR5K_PHY_PA_CTL,797 { 0x00000007, 0x0000000b, 0x0000000b } },798 { AR5K_PHY_GAIN,799 { 0x0018da6d, 0x0018ca75, 0x0018ca75 } },800 { AR5K_PHY_DESIRED_SIZE,801 { 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0 } },802 { AR5K_PHY_SIG,803 { 0x7e800d2e, 0x7ee80d2e, 0x7ee80d2e } },804 { AR5K_PHY_AGCCOARSE,805 { 0x3137665e, 0x3137665e, 0x3137665e } },806 { AR5K_PHY_WEAK_OFDM_LOW_THR,807 { 0x050cb081, 0x050cb081, 0x050cb081 } },808 { AR5K_PHY_RX_DELAY,809 { 0x000007d0, 0x0000044c, 0x00000898 } },810 { AR5K_PHY_FRAME_CTL_5211,811 { 0xf7b81020, 0xf7b80d10, 0xf7b81010 } },812 { AR5K_PHY_CCKTXCTL,813 { 0x00000000, 0x00000008, 0x00000008 } },814 { AR5K_PHY_CCK_CROSSCORR,815 { 0xd6be6788, 0xd03e6788, 0xd03e6788 } },816 { AR5K_PHY_GAIN_2GHZ,817 { 0x642c0140, 0x6442c160, 0x6442c160 } },818 { AR5K_PHY_CCK_RX_CTL_4,819 { 0x1883800a, 0x1873800a, 0x1883800a } },820};821 822static const struct ath5k_ini rf5112_ini_common_end[] = {823 { AR5K_DCU_FP, 0x00000000 },824 { AR5K_PHY_AGC, 0x00000000 },825 { AR5K_PHY_ADC_CTL, 0x00022ffe },826 { 0x983c, 0x00020100 },827 { AR5K_PHY_GAIN_OFFSET, 0x1284613c },828 { AR5K_PHY_PAPD_PROBE, 0x00004882 },829 { 0x9940, 0x00000004 },830 { 0x9958, 0x000000ff },831 { 0x9974, 0x00000000 },832 { AR5K_PHY_DAG_CCK_CTL, 0x000001b5 },833 { 0xa23c, 0x13c889af },834};835 836 837/* Initial mode-specific settings for RF5413/5414838 * (Written after ar5212_ini) */839static const struct ath5k_ini_mode rf5413_ini_mode_end[] = {840 { AR5K_TXCFG,841 /* A/XR B G */842 { 0x00000015, 0x00000015, 0x00000015 } },843 { AR5K_USEC_5211,844 { 0x128d93a7, 0x04e01395, 0x12e013ab } },845 { AR5K_PHY_RF_CTL3,846 { 0x0a020001, 0x05020100, 0x0a020001 } },847 { AR5K_PHY_RF_CTL4,848 { 0x00000e0e, 0x00000e0e, 0x00000e0e } },849 { AR5K_PHY_PA_CTL,850 { 0x00000007, 0x0000000b, 0x0000000b } },851 { AR5K_PHY_GAIN,852 { 0x0018fa61, 0x001a1a63, 0x001a1a63 } },853 { AR5K_PHY_DESIRED_SIZE,854 { 0x0c98b4e0, 0x0c98b0da, 0x0c98b0da } },855 { AR5K_PHY_SIG,856 { 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e } },857 { AR5K_PHY_AGCCOARSE,858 { 0x3139605e, 0x3139605e, 0x3139605e } },859 { AR5K_PHY_WEAK_OFDM_LOW_THR,860 { 0x050cb081, 0x050cb081, 0x050cb081 } },861 { AR5K_PHY_RX_DELAY,862 { 0x000007d0, 0x0000044c, 0x00000898 } },863 { AR5K_PHY_FRAME_CTL_5211,864 { 0xf7b81000, 0xf7b80d00, 0xf7b81000 } },865 { AR5K_PHY_CCKTXCTL,866 { 0x00000000, 0x00000000, 0x00000000 } },867 { AR5K_PHY_CCK_CROSSCORR,868 { 0xd6be6788, 0xd03e6788, 0xd03e6788 } },869 { AR5K_PHY_GAIN_2GHZ,870 { 0x002ec1e0, 0x002ac120, 0x002ac120 } },871 { AR5K_PHY_CCK_RX_CTL_4,872 { 0x1883800a, 0x1863800a, 0x1883800a } },873 { 0xa300,874 { 0x18010000, 0x18010000, 0x18010000 } },875 { 0xa304,876 { 0x30032602, 0x30032602, 0x30032602 } },877 { 0xa308,878 { 0x48073e06, 0x48073e06, 0x48073e06 } },879 { 0xa30c,880 { 0x560b4c0a, 0x560b4c0a, 0x560b4c0a } },881 { 0xa310,882 { 0x641a600f, 0x641a600f, 0x641a600f } },883 { 0xa314,884 { 0x784f6e1b, 0x784f6e1b, 0x784f6e1b } },885 { 0xa318,886 { 0x868f7c5a, 0x868f7c5a, 0x868f7c5a } },887 { 0xa31c,888 { 0x90cf865b, 0x8ecf865b, 0x8ecf865b } },889 { 0xa320,890 { 0x9d4f970f, 0x9b4f970f, 0x9b4f970f } },891 { 0xa324,892 { 0xa7cfa38f, 0xa3cf9f8f, 0xa3cf9f8f } },893 { 0xa328,894 { 0xb55faf1f, 0xb35faf1f, 0xb35faf1f } },895 { 0xa32c,896 { 0xbddfb99f, 0xbbdfb99f, 0xbbdfb99f } },897 { 0xa330,898 { 0xcb7fc53f, 0xcb7fc73f, 0xcb7fc73f } },899 { 0xa334,900 { 0xd5ffd1bf, 0xd3ffd1bf, 0xd3ffd1bf } },901};902 903static const struct ath5k_ini rf5413_ini_common_end[] = {904 { AR5K_DCU_FP, 0x000003e0 },905 { AR5K_5414_CBCFG, 0x00000010 },906 { AR5K_SEQ_MASK, 0x0000000f },907 { 0x809c, 0x00000000 },908 { 0x80a0, 0x00000000 },909 { AR5K_MIC_QOS_CTL, 0x00000000 },910 { AR5K_MIC_QOS_SEL, 0x00000000 },911 { AR5K_MISC_MODE, 0x00000000 },912 { AR5K_OFDM_FIL_CNT, 0x00000000 },913 { AR5K_CCK_FIL_CNT, 0x00000000 },914 { AR5K_PHYERR_CNT1, 0x00000000 },915 { AR5K_PHYERR_CNT1_MASK, 0x00000000 },916 { AR5K_PHYERR_CNT2, 0x00000000 },917 { AR5K_PHYERR_CNT2_MASK, 0x00000000 },918 { AR5K_TSF_THRES, 0x00000000 },919 { 0x8140, 0x800003f9 },920 { 0x8144, 0x00000000 },921 { AR5K_PHY_AGC, 0x00000000 },922 { AR5K_PHY_ADC_CTL, 0x0000a000 },923 { 0x983c, 0x00200400 },924 { AR5K_PHY_GAIN_OFFSET, 0x1284233c },925 { AR5K_PHY_SCR, 0x0000001f },926 { AR5K_PHY_SLMT, 0x00000080 },927 { AR5K_PHY_SCAL, 0x0000000e },928 { 0x9958, 0x00081fff },929 { AR5K_PHY_TIMING_7, 0x00000000 },930 { AR5K_PHY_TIMING_8, 0x02800000 },931 { AR5K_PHY_TIMING_11, 0x00000000 },932 { AR5K_PHY_HEAVY_CLIP_ENABLE, 0x00000000 },933 { 0x99e4, 0xaaaaaaaa },934 { 0x99e8, 0x3c466478 },935 { 0x99ec, 0x000000aa },936 { AR5K_PHY_SCLOCK, 0x0000000c },937 { AR5K_PHY_SDELAY, 0x000000ff },938 { AR5K_PHY_SPENDING, 0x00000014 },939 { AR5K_PHY_DAG_CCK_CTL, 0x000009b5 },940 { 0xa23c, 0x93c889af },941 { AR5K_PHY_FAST_ADC, 0x00000001 },942 { 0xa250, 0x0000a000 },943 { AR5K_PHY_BLUETOOTH, 0x00000000 },944 { AR5K_PHY_TPC_RG1, 0x0cc75380 },945 { 0xa25c, 0x0f0f0f01 },946 { 0xa260, 0x5f690f01 },947 { 0xa264, 0x00418a11 },948 { 0xa268, 0x00000000 },949 { AR5K_PHY_TPC_RG5, 0x0c30c16a },950 { 0xa270, 0x00820820 },951 { 0xa274, 0x081b7caa },952 { 0xa278, 0x1ce739ce },953 { 0xa27c, 0x051701ce },954 { 0xa338, 0x00000000 },955 { 0xa33c, 0x00000000 },956 { 0xa340, 0x00000000 },957 { 0xa344, 0x00000000 },958 { 0xa348, 0x3fffffff },959 { 0xa34c, 0x3fffffff },960 { 0xa350, 0x3fffffff },961 { 0xa354, 0x0003ffff },962 { 0xa358, 0x79a8aa1f },963 { 0xa35c, 0x066c420f },964 { 0xa360, 0x0f282207 },965 { 0xa364, 0x17601685 },966 { 0xa368, 0x1f801104 },967 { 0xa36c, 0x37a00c03 },968 { 0xa370, 0x3fc40883 },969 { 0xa374, 0x57c00803 },970 { 0xa378, 0x5fd80682 },971 { 0xa37c, 0x7fe00482 },972 { 0xa380, 0x7f3c7bba },973 { 0xa384, 0xf3307ff0 },974};975 976/* Initial mode-specific settings for RF2413/2414977 * (Written after ar5212_ini) */978/* XXX: a mode ? */979static const struct ath5k_ini_mode rf2413_ini_mode_end[] = {980 { AR5K_TXCFG,981 /* A/XR B G */982 { 0x00000015, 0x00000015, 0x00000015 } },983 { AR5K_USEC_5211,984 { 0x128d93a7, 0x04e01395, 0x12e013ab } },985 { AR5K_PHY_RF_CTL3,986 { 0x0a020001, 0x05020000, 0x0a020001 } },987 { AR5K_PHY_RF_CTL4,988 { 0x00000e00, 0x00000e00, 0x00000e00 } },989 { AR5K_PHY_PA_CTL,990 { 0x00000002, 0x0000000a, 0x0000000a } },991 { AR5K_PHY_GAIN,992 { 0x0018da6d, 0x001a6a64, 0x001a6a64 } },993 { AR5K_PHY_DESIRED_SIZE,994 { 0x0de8b4e0, 0x0de8b0da, 0x0c98b0da } },995 { AR5K_PHY_SIG,996 { 0x7e800d2e, 0x7ee80d2e, 0x7ec80d2e } },997 { AR5K_PHY_AGCCOARSE,998 { 0x3137665e, 0x3137665e, 0x3139605e } },999 { AR5K_PHY_WEAK_OFDM_LOW_THR,1000 { 0x050cb081, 0x050cb081, 0x050cb081 } },1001 { AR5K_PHY_RX_DELAY,1002 { 0x000007d0, 0x0000044c, 0x00000898 } },1003 { AR5K_PHY_FRAME_CTL_5211,1004 { 0xf7b81000, 0xf7b80d00, 0xf7b81000 } },1005 { AR5K_PHY_CCKTXCTL,1006 { 0x00000000, 0x00000000, 0x00000000 } },1007 { AR5K_PHY_CCK_CROSSCORR,1008 { 0xd6be6788, 0xd03e6788, 0xd03e6788 } },1009 { AR5K_PHY_GAIN_2GHZ,1010 { 0x002c0140, 0x0042c140, 0x0042c140 } },1011 { AR5K_PHY_CCK_RX_CTL_4,1012 { 0x1883800a, 0x1863800a, 0x1883800a } },1013};1014 1015static const struct ath5k_ini rf2413_ini_common_end[] = {1016 { AR5K_DCU_FP, 0x000003e0 },1017 { AR5K_SEQ_MASK, 0x0000000f },1018 { AR5K_MIC_QOS_CTL, 0x00000000 },1019 { AR5K_MIC_QOS_SEL, 0x00000000 },1020 { AR5K_MISC_MODE, 0x00000000 },1021 { AR5K_OFDM_FIL_CNT, 0x00000000 },1022 { AR5K_CCK_FIL_CNT, 0x00000000 },1023 { AR5K_PHYERR_CNT1, 0x00000000 },1024 { AR5K_PHYERR_CNT1_MASK, 0x00000000 },1025 { AR5K_PHYERR_CNT2, 0x00000000 },1026 { AR5K_PHYERR_CNT2_MASK, 0x00000000 },1027 { AR5K_TSF_THRES, 0x00000000 },1028 { 0x8140, 0x800000a8 },1029 { 0x8144, 0x00000000 },1030 { AR5K_PHY_AGC, 0x00000000 },1031 { AR5K_PHY_ADC_CTL, 0x0000a000 },1032 { 0x983c, 0x00200400 },1033 { AR5K_PHY_GAIN_OFFSET, 0x1284233c },1034 { AR5K_PHY_SCR, 0x0000001f },1035 { AR5K_PHY_SLMT, 0x00000080 },1036 { AR5K_PHY_SCAL, 0x0000000e },1037 { 0x9958, 0x000000ff },1038 { AR5K_PHY_TIMING_7, 0x00000000 },1039 { AR5K_PHY_TIMING_8, 0x02800000 },1040 { AR5K_PHY_TIMING_11, 0x00000000 },1041 { AR5K_PHY_HEAVY_CLIP_ENABLE, 0x00000000 },1042 { 0x99e4, 0xaaaaaaaa },1043 { 0x99e8, 0x3c466478 },1044 { 0x99ec, 0x000000aa },1045 { AR5K_PHY_SCLOCK, 0x0000000c },1046 { AR5K_PHY_SDELAY, 0x000000ff },1047 { AR5K_PHY_SPENDING, 0x00000014 },1048 { AR5K_PHY_DAG_CCK_CTL, 0x000009b5 },1049 { 0xa23c, 0x93c889af },1050 { AR5K_PHY_FAST_ADC, 0x00000001 },1051 { 0xa250, 0x0000a000 },1052 { AR5K_PHY_BLUETOOTH, 0x00000000 },1053 { AR5K_PHY_TPC_RG1, 0x0cc75380 },1054 { 0xa25c, 0x0f0f0f01 },1055 { 0xa260, 0x5f690f01 },1056 { 0xa264, 0x00418a11 },1057 { 0xa268, 0x00000000 },1058 { AR5K_PHY_TPC_RG5, 0x0c30c16a },1059 { 0xa270, 0x00820820 },1060 { 0xa274, 0x001b7caa },1061 { 0xa278, 0x1ce739ce },1062 { 0xa27c, 0x051701ce },1063 { 0xa300, 0x18010000 },1064 { 0xa304, 0x30032602 },1065 { 0xa308, 0x48073e06 },1066 { 0xa30c, 0x560b4c0a },1067 { 0xa310, 0x641a600f },1068 { 0xa314, 0x784f6e1b },1069 { 0xa318, 0x868f7c5a },1070 { 0xa31c, 0x8ecf865b },1071 { 0xa320, 0x9d4f970f },1072 { 0xa324, 0xa5cfa18f },1073 { 0xa328, 0xb55faf1f },1074 { 0xa32c, 0xbddfb99f },1075 { 0xa330, 0xcd7fc73f },1076 { 0xa334, 0xd5ffd1bf },1077 { 0xa338, 0x00000000 },1078 { 0xa33c, 0x00000000 },1079 { 0xa340, 0x00000000 },1080 { 0xa344, 0x00000000 },1081 { 0xa348, 0x3fffffff },1082 { 0xa34c, 0x3fffffff },1083 { 0xa350, 0x3fffffff },1084 { 0xa354, 0x0003ffff },1085 { 0xa358, 0x79a8aa1f },1086 { 0xa35c, 0x066c420f },1087 { 0xa360, 0x0f282207 },1088 { 0xa364, 0x17601685 },1089 { 0xa368, 0x1f801104 },1090 { 0xa36c, 0x37a00c03 },1091 { 0xa370, 0x3fc40883 },1092 { 0xa374, 0x57c00803 },1093 { 0xa378, 0x5fd80682 },1094 { 0xa37c, 0x7fe00482 },1095 { 0xa380, 0x7f3c7bba },1096 { 0xa384, 0xf3307ff0 },1097};1098 1099/* Initial mode-specific settings for RF24251100 * (Written after ar5212_ini) */1101/* XXX: a mode ? */1102static const struct ath5k_ini_mode rf2425_ini_mode_end[] = {1103 { AR5K_TXCFG,1104 /* A/XR B G */1105 { 0x00000015, 0x00000015, 0x00000015 } },1106 { AR5K_USEC_5211,1107 { 0x128d93a7, 0x04e01395, 0x12e013ab } },1108 { AR5K_PHY_RF_CTL3,1109 { 0x0a020001, 0x05020100, 0x0a020001 } },1110 { AR5K_PHY_RF_CTL4,1111 { 0x00000e0e, 0x00000e0e, 0x00000e0e } },1112 { AR5K_PHY_PA_CTL,1113 { 0x00000003, 0x0000000b, 0x0000000b } },1114 { AR5K_PHY_SETTLING,1115 { 0x1372161c, 0x13721722, 0x13721422 } },1116 { AR5K_PHY_GAIN,1117 { 0x0018fa61, 0x00199a65, 0x00199a65 } },1118 { AR5K_PHY_DESIRED_SIZE,1119 { 0x0c98b4e0, 0x0c98b0da, 0x0c98b0da } },1120 { AR5K_PHY_SIG,1121 { 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e } },1122 { AR5K_PHY_AGCCOARSE,1123 { 0x3139605e, 0x3139605e, 0x3139605e } },1124 { AR5K_PHY_WEAK_OFDM_LOW_THR,1125 { 0x050cb081, 0x050cb081, 0x050cb081 } },1126 { AR5K_PHY_RX_DELAY,1127 { 0x000007d0, 0x0000044c, 0x00000898 } },1128 { AR5K_PHY_FRAME_CTL_5211,1129 { 0xf7b81000, 0xf7b80d00, 0xf7b81000 } },1130 { AR5K_PHY_CCKTXCTL,1131 { 0x00000000, 0x00000000, 0x00000000 } },1132 { AR5K_PHY_CCK_CROSSCORR,1133 { 0xd6be6788, 0xd03e6788, 0xd03e6788 } },1134 { AR5K_PHY_GAIN_2GHZ,1135 { 0x00000140, 0x0052c140, 0x0052c140 } },1136 { AR5K_PHY_CCK_RX_CTL_4,1137 { 0x1883800a, 0x1863800a, 0x1883800a } },1138 { 0xa324,1139 { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } },1140 { 0xa328,1141 { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } },1142 { 0xa32c,1143 { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } },1144 { 0xa330,1145 { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } },1146 { 0xa334,1147 { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } },1148};1149 1150static const struct ath5k_ini rf2425_ini_common_end[] = {1151 { AR5K_DCU_FP, 0x000003e0 },1152 { AR5K_SEQ_MASK, 0x0000000f },1153 { 0x809c, 0x00000000 },1154 { 0x80a0, 0x00000000 },1155 { AR5K_MIC_QOS_CTL, 0x00000000 },1156 { AR5K_MIC_QOS_SEL, 0x00000000 },1157 { AR5K_MISC_MODE, 0x00000000 },1158 { AR5K_OFDM_FIL_CNT, 0x00000000 },1159 { AR5K_CCK_FIL_CNT, 0x00000000 },1160 { AR5K_PHYERR_CNT1, 0x00000000 },1161 { AR5K_PHYERR_CNT1_MASK, 0x00000000 },1162 { AR5K_PHYERR_CNT2, 0x00000000 },1163 { AR5K_PHYERR_CNT2_MASK, 0x00000000 },1164 { AR5K_TSF_THRES, 0x00000000 },1165 { 0x8140, 0x800003f9 },1166 { 0x8144, 0x00000000 },1167 { AR5K_PHY_AGC, 0x00000000 },1168 { AR5K_PHY_ADC_CTL, 0x0000a000 },1169 { 0x983c, 0x00200400 },1170 { AR5K_PHY_GAIN_OFFSET, 0x1284233c },1171 { AR5K_PHY_SCR, 0x0000001f },1172 { AR5K_PHY_SLMT, 0x00000080 },1173 { AR5K_PHY_SCAL, 0x0000000e },1174 { 0x9958, 0x00081fff },1175 { AR5K_PHY_TIMING_7, 0x00000000 },1176 { AR5K_PHY_TIMING_8, 0x02800000 },1177 { AR5K_PHY_TIMING_11, 0x00000000 },1178 { 0x99dc, 0xfebadbe8 },1179 { AR5K_PHY_HEAVY_CLIP_ENABLE, 0x00000000 },1180 { 0x99e4, 0xaaaaaaaa },1181 { 0x99e8, 0x3c466478 },1182 { 0x99ec, 0x000000aa },1183 { AR5K_PHY_SCLOCK, 0x0000000c },1184 { AR5K_PHY_SDELAY, 0x000000ff },1185 { AR5K_PHY_SPENDING, 0x00000014 },1186 { AR5K_PHY_DAG_CCK_CTL, 0x000009b5 },1187 { AR5K_PHY_TXPOWER_RATE3, 0x20202020 },1188 { AR5K_PHY_TXPOWER_RATE4, 0x20202020 },1189 { 0xa23c, 0x93c889af },1190 { AR5K_PHY_FAST_ADC, 0x00000001 },1191 { 0xa250, 0x0000a000 },1192 { AR5K_PHY_BLUETOOTH, 0x00000000 },1193 { AR5K_PHY_TPC_RG1, 0x0cc75380 },1194 { 0xa25c, 0x0f0f0f01 },1195 { 0xa260, 0x5f690f01 },1196 { 0xa264, 0x00418a11 },1197 { 0xa268, 0x00000000 },1198 { AR5K_PHY_TPC_RG5, 0x0c30c166 },1199 { 0xa270, 0x00820820 },1200 { 0xa274, 0x081a3caa },1201 { 0xa278, 0x1ce739ce },1202 { 0xa27c, 0x051701ce },1203 { 0xa300, 0x16010000 },1204 { 0xa304, 0x2c032402 },1205 { 0xa308, 0x48433e42 },1206 { 0xa30c, 0x5a0f500b },1207 { 0xa310, 0x6c4b624a },1208 { 0xa314, 0x7e8b748a },1209 { 0xa318, 0x96cf8ccb },1210 { 0xa31c, 0xa34f9d0f },1211 { 0xa320, 0xa7cfa58f },1212 { 0xa348, 0x3fffffff },1213 { 0xa34c, 0x3fffffff },1214 { 0xa350, 0x3fffffff },1215 { 0xa354, 0x0003ffff },1216 { 0xa358, 0x79a8aa1f },1217 { 0xa35c, 0x066c420f },1218 { 0xa360, 0x0f282207 },1219 { 0xa364, 0x17601685 },1220 { 0xa368, 0x1f801104 },1221 { 0xa36c, 0x37a00c03 },1222 { 0xa370, 0x3fc40883 },1223 { 0xa374, 0x57c00803 },1224 { 0xa378, 0x5fd80682 },1225 { 0xa37c, 0x7fe00482 },1226 { 0xa380, 0x7f3c7bba },1227 { 0xa384, 0xf3307ff0 },1228};1229 1230/*1231 * Initial BaseBand Gain settings for RF5111/5112 (AR5210 comes with1232 * RF5110 only so initial BB Gain settings are included in AR5K_AR5210_INI)1233 */1234 1235/* RF5111 Initial BaseBand Gain settings */1236static const struct ath5k_ini rf5111_ini_bbgain[] = {1237 { AR5K_BB_GAIN(0), 0x00000000 },1238 { AR5K_BB_GAIN(1), 0x00000020 },1239 { AR5K_BB_GAIN(2), 0x00000010 },1240 { AR5K_BB_GAIN(3), 0x00000030 },1241 { AR5K_BB_GAIN(4), 0x00000008 },1242 { AR5K_BB_GAIN(5), 0x00000028 },1243 { AR5K_BB_GAIN(6), 0x00000004 },1244 { AR5K_BB_GAIN(7), 0x00000024 },1245 { AR5K_BB_GAIN(8), 0x00000014 },1246 { AR5K_BB_GAIN(9), 0x00000034 },1247 { AR5K_BB_GAIN(10), 0x0000000c },1248 { AR5K_BB_GAIN(11), 0x0000002c },1249 { AR5K_BB_GAIN(12), 0x00000002 },1250 { AR5K_BB_GAIN(13), 0x00000022 },1251 { AR5K_BB_GAIN(14), 0x00000012 },1252 { AR5K_BB_GAIN(15), 0x00000032 },1253 { AR5K_BB_GAIN(16), 0x0000000a },1254 { AR5K_BB_GAIN(17), 0x0000002a },1255 { AR5K_BB_GAIN(18), 0x00000006 },1256 { AR5K_BB_GAIN(19), 0x00000026 },1257 { AR5K_BB_GAIN(20), 0x00000016 },1258 { AR5K_BB_GAIN(21), 0x00000036 },1259 { AR5K_BB_GAIN(22), 0x0000000e },1260 { AR5K_BB_GAIN(23), 0x0000002e },1261 { AR5K_BB_GAIN(24), 0x00000001 },1262 { AR5K_BB_GAIN(25), 0x00000021 },1263 { AR5K_BB_GAIN(26), 0x00000011 },1264 { AR5K_BB_GAIN(27), 0x00000031 },1265 { AR5K_BB_GAIN(28), 0x00000009 },1266 { AR5K_BB_GAIN(29), 0x00000029 },1267 { AR5K_BB_GAIN(30), 0x00000005 },1268 { AR5K_BB_GAIN(31), 0x00000025 },1269 { AR5K_BB_GAIN(32), 0x00000015 },1270 { AR5K_BB_GAIN(33), 0x00000035 },1271 { AR5K_BB_GAIN(34), 0x0000000d },1272 { AR5K_BB_GAIN(35), 0x0000002d },1273 { AR5K_BB_GAIN(36), 0x00000003 },1274 { AR5K_BB_GAIN(37), 0x00000023 },1275 { AR5K_BB_GAIN(38), 0x00000013 },1276 { AR5K_BB_GAIN(39), 0x00000033 },1277 { AR5K_BB_GAIN(40), 0x0000000b },1278 { AR5K_BB_GAIN(41), 0x0000002b },1279 { AR5K_BB_GAIN(42), 0x0000002b },1280 { AR5K_BB_GAIN(43), 0x0000002b },1281 { AR5K_BB_GAIN(44), 0x0000002b },1282 { AR5K_BB_GAIN(45), 0x0000002b },1283 { AR5K_BB_GAIN(46), 0x0000002b },1284 { AR5K_BB_GAIN(47), 0x0000002b },1285 { AR5K_BB_GAIN(48), 0x0000002b },1286 { AR5K_BB_GAIN(49), 0x0000002b },1287 { AR5K_BB_GAIN(50), 0x0000002b },1288 { AR5K_BB_GAIN(51), 0x0000002b },1289 { AR5K_BB_GAIN(52), 0x0000002b },1290 { AR5K_BB_GAIN(53), 0x0000002b },1291 { AR5K_BB_GAIN(54), 0x0000002b },1292 { AR5K_BB_GAIN(55), 0x0000002b },1293 { AR5K_BB_GAIN(56), 0x0000002b },1294 { AR5K_BB_GAIN(57), 0x0000002b },1295 { AR5K_BB_GAIN(58), 0x0000002b },1296 { AR5K_BB_GAIN(59), 0x0000002b },1297 { AR5K_BB_GAIN(60), 0x0000002b },1298 { AR5K_BB_GAIN(61), 0x0000002b },1299 { AR5K_BB_GAIN(62), 0x00000002 },1300 { AR5K_BB_GAIN(63), 0x00000016 },1301};1302 1303/* RF5112 Initial BaseBand Gain settings (Same for RF5413/5414+) */1304static const struct ath5k_ini rf5112_ini_bbgain[] = {1305 { AR5K_BB_GAIN(0), 0x00000000 },1306 { AR5K_BB_GAIN(1), 0x00000001 },1307 { AR5K_BB_GAIN(2), 0x00000002 },1308 { AR5K_BB_GAIN(3), 0x00000003 },1309 { AR5K_BB_GAIN(4), 0x00000004 },1310 { AR5K_BB_GAIN(5), 0x00000005 },1311 { AR5K_BB_GAIN(6), 0x00000008 },1312 { AR5K_BB_GAIN(7), 0x00000009 },1313 { AR5K_BB_GAIN(8), 0x0000000a },1314 { AR5K_BB_GAIN(9), 0x0000000b },1315 { AR5K_BB_GAIN(10), 0x0000000c },1316 { AR5K_BB_GAIN(11), 0x0000000d },1317 { AR5K_BB_GAIN(12), 0x00000010 },1318 { AR5K_BB_GAIN(13), 0x00000011 },1319 { AR5K_BB_GAIN(14), 0x00000012 },1320 { AR5K_BB_GAIN(15), 0x00000013 },1321 { AR5K_BB_GAIN(16), 0x00000014 },1322 { AR5K_BB_GAIN(17), 0x00000015 },1323 { AR5K_BB_GAIN(18), 0x00000018 },1324 { AR5K_BB_GAIN(19), 0x00000019 },1325 { AR5K_BB_GAIN(20), 0x0000001a },1326 { AR5K_BB_GAIN(21), 0x0000001b },1327 { AR5K_BB_GAIN(22), 0x0000001c },1328 { AR5K_BB_GAIN(23), 0x0000001d },1329 { AR5K_BB_GAIN(24), 0x00000020 },1330 { AR5K_BB_GAIN(25), 0x00000021 },1331 { AR5K_BB_GAIN(26), 0x00000022 },1332 { AR5K_BB_GAIN(27), 0x00000023 },1333 { AR5K_BB_GAIN(28), 0x00000024 },1334 { AR5K_BB_GAIN(29), 0x00000025 },1335 { AR5K_BB_GAIN(30), 0x00000028 },1336 { AR5K_BB_GAIN(31), 0x00000029 },1337 { AR5K_BB_GAIN(32), 0x0000002a },1338 { AR5K_BB_GAIN(33), 0x0000002b },1339 { AR5K_BB_GAIN(34), 0x0000002c },1340 { AR5K_BB_GAIN(35), 0x0000002d },1341 { AR5K_BB_GAIN(36), 0x00000030 },1342 { AR5K_BB_GAIN(37), 0x00000031 },1343 { AR5K_BB_GAIN(38), 0x00000032 },1344 { AR5K_BB_GAIN(39), 0x00000033 },1345 { AR5K_BB_GAIN(40), 0x00000034 },1346 { AR5K_BB_GAIN(41), 0x00000035 },1347 { AR5K_BB_GAIN(42), 0x00000035 },1348 { AR5K_BB_GAIN(43), 0x00000035 },1349 { AR5K_BB_GAIN(44), 0x00000035 },1350 { AR5K_BB_GAIN(45), 0x00000035 },1351 { AR5K_BB_GAIN(46), 0x00000035 },1352 { AR5K_BB_GAIN(47), 0x00000035 },1353 { AR5K_BB_GAIN(48), 0x00000035 },1354 { AR5K_BB_GAIN(49), 0x00000035 },1355 { AR5K_BB_GAIN(50), 0x00000035 },1356 { AR5K_BB_GAIN(51), 0x00000035 },1357 { AR5K_BB_GAIN(52), 0x00000035 },1358 { AR5K_BB_GAIN(53), 0x00000035 },1359 { AR5K_BB_GAIN(54), 0x00000035 },1360 { AR5K_BB_GAIN(55), 0x00000035 },1361 { AR5K_BB_GAIN(56), 0x00000035 },1362 { AR5K_BB_GAIN(57), 0x00000035 },1363 { AR5K_BB_GAIN(58), 0x00000035 },1364 { AR5K_BB_GAIN(59), 0x00000035 },1365 { AR5K_BB_GAIN(60), 0x00000035 },1366 { AR5K_BB_GAIN(61), 0x00000035 },1367 { AR5K_BB_GAIN(62), 0x00000010 },1368 { AR5K_BB_GAIN(63), 0x0000001a },1369};1370 1371 1372/**1373 * ath5k_hw_ini_registers() - Write initial register dump common for all modes1374 * @ah: The &struct ath5k_hw1375 * @size: Dump size1376 * @ini_regs: The array of &struct ath5k_ini1377 * @skip_pcu: Skip PCU registers1378 */1379static void1380ath5k_hw_ini_registers(struct ath5k_hw *ah, unsigned int size,1381 const struct ath5k_ini *ini_regs, bool skip_pcu)1382{1383 unsigned int i;1384 1385 /* Write initial registers */1386 for (i = 0; i < size; i++) {1387 /* Skip PCU registers if1388 * requested */1389 if (skip_pcu &&1390 ini_regs[i].ini_register >= AR5K_PCU_MIN &&1391 ini_regs[i].ini_register <= AR5K_PCU_MAX)1392 continue;1393 1394 switch (ini_regs[i].ini_mode) {1395 case AR5K_INI_READ:1396 /* Cleared on read */1397 ath5k_hw_reg_read(ah, ini_regs[i].ini_register);1398 break;1399 case AR5K_INI_WRITE:1400 default:1401 AR5K_REG_WAIT(i);1402 ath5k_hw_reg_write(ah, ini_regs[i].ini_value,1403 ini_regs[i].ini_register);1404 }1405 }1406}1407 1408/**1409 * ath5k_hw_ini_mode_registers() - Write initial mode-specific register dump1410 * @ah: The &struct ath5k_hw1411 * @size: Dump size1412 * @ini_mode: The array of &struct ath5k_ini_mode1413 * @mode: One of enum ath5k_driver_mode1414 */1415static void1416ath5k_hw_ini_mode_registers(struct ath5k_hw *ah,1417 unsigned int size, const struct ath5k_ini_mode *ini_mode,1418 u8 mode)1419{1420 unsigned int i;1421 1422 for (i = 0; i < size; i++) {1423 AR5K_REG_WAIT(i);1424 ath5k_hw_reg_write(ah, ini_mode[i].mode_value[mode],1425 (u32)ini_mode[i].mode_register);1426 }1427 1428}1429 1430/**1431 * ath5k_hw_write_initvals() - Write initial chip-specific register dump1432 * @ah: The &struct ath5k_hw1433 * @mode: One of enum ath5k_driver_mode1434 * @skip_pcu: Skip PCU registers1435 *1436 * Write initial chip-specific register dump, to get the chipset on a1437 * clean and ready-to-work state after warm reset.1438 */1439int1440ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool skip_pcu)1441{1442 /*1443 * Write initial register settings1444 */1445 1446 /* For AR5212 and compatible */1447 if (ah->ah_version == AR5K_AR5212) {1448 1449 /* First set of mode-specific settings */1450 ath5k_hw_ini_mode_registers(ah,1451 ARRAY_SIZE(ar5212_ini_mode_start),1452 ar5212_ini_mode_start, mode);1453 1454 /*1455 * Write initial settings common for all modes1456 */1457 ath5k_hw_ini_registers(ah, ARRAY_SIZE(ar5212_ini_common_start),1458 ar5212_ini_common_start, skip_pcu);1459 1460 /* Second set of mode-specific settings */1461 switch (ah->ah_radio) {1462 case AR5K_RF5111:1463 1464 ath5k_hw_ini_mode_registers(ah,1465 ARRAY_SIZE(rf5111_ini_mode_end),1466 rf5111_ini_mode_end, mode);1467 1468 ath5k_hw_ini_registers(ah,1469 ARRAY_SIZE(rf5111_ini_common_end),1470 rf5111_ini_common_end, skip_pcu);1471 1472 /* Baseband gain table */1473 ath5k_hw_ini_registers(ah,1474 ARRAY_SIZE(rf5111_ini_bbgain),1475 rf5111_ini_bbgain, skip_pcu);1476 1477 break;1478 case AR5K_RF5112:1479 1480 ath5k_hw_ini_mode_registers(ah,1481 ARRAY_SIZE(rf5112_ini_mode_end),1482 rf5112_ini_mode_end, mode);1483 1484 ath5k_hw_ini_registers(ah,1485 ARRAY_SIZE(rf5112_ini_common_end),1486 rf5112_ini_common_end, skip_pcu);1487 1488 ath5k_hw_ini_registers(ah,1489 ARRAY_SIZE(rf5112_ini_bbgain),1490 rf5112_ini_bbgain, skip_pcu);1491 1492 break;1493 case AR5K_RF5413:1494 1495 ath5k_hw_ini_mode_registers(ah,1496 ARRAY_SIZE(rf5413_ini_mode_end),1497 rf5413_ini_mode_end, mode);1498 1499 ath5k_hw_ini_registers(ah,1500 ARRAY_SIZE(rf5413_ini_common_end),1501 rf5413_ini_common_end, skip_pcu);1502 1503 ath5k_hw_ini_registers(ah,1504 ARRAY_SIZE(rf5112_ini_bbgain),1505 rf5112_ini_bbgain, skip_pcu);1506 1507 break;1508 case AR5K_RF2316:1509 case AR5K_RF2413:1510 1511 ath5k_hw_ini_mode_registers(ah,1512 ARRAY_SIZE(rf2413_ini_mode_end),1513 rf2413_ini_mode_end, mode);1514 1515 ath5k_hw_ini_registers(ah,1516 ARRAY_SIZE(rf2413_ini_common_end),1517 rf2413_ini_common_end, skip_pcu);1518 1519 /* Override settings from rf2413_ini_common_end */1520 if (ah->ah_radio == AR5K_RF2316) {1521 ath5k_hw_reg_write(ah, 0x00004000,1522 AR5K_PHY_AGC);1523 ath5k_hw_reg_write(ah, 0x081b7caa,1524 0xa274);1525 }1526 1527 ath5k_hw_ini_registers(ah,1528 ARRAY_SIZE(rf5112_ini_bbgain),1529 rf5112_ini_bbgain, skip_pcu);1530 break;1531 case AR5K_RF2317:1532 1533 ath5k_hw_ini_mode_registers(ah,1534 ARRAY_SIZE(rf2413_ini_mode_end),1535 rf2413_ini_mode_end, mode);1536 1537 ath5k_hw_ini_registers(ah,1538 ARRAY_SIZE(rf2425_ini_common_end),1539 rf2425_ini_common_end, skip_pcu);1540 1541 /* Override settings from rf2413_ini_mode_end */1542 ath5k_hw_reg_write(ah, 0x00180a65, AR5K_PHY_GAIN);1543 1544 /* Override settings from rf2413_ini_common_end */1545 ath5k_hw_reg_write(ah, 0x00004000, AR5K_PHY_AGC);1546 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TPC_RG5,1547 AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP, 0xa);1548 ath5k_hw_reg_write(ah, 0x800000a8, 0x8140);1549 ath5k_hw_reg_write(ah, 0x000000ff, 0x9958);1550 1551 ath5k_hw_ini_registers(ah,1552 ARRAY_SIZE(rf5112_ini_bbgain),1553 rf5112_ini_bbgain, skip_pcu);1554 break;1555 case AR5K_RF2425:1556 1557 ath5k_hw_ini_mode_registers(ah,1558 ARRAY_SIZE(rf2425_ini_mode_end),1559 rf2425_ini_mode_end, mode);1560 1561 ath5k_hw_ini_registers(ah,1562 ARRAY_SIZE(rf2425_ini_common_end),1563 rf2425_ini_common_end, skip_pcu);1564 1565 ath5k_hw_ini_registers(ah,1566 ARRAY_SIZE(rf5112_ini_bbgain),1567 rf5112_ini_bbgain, skip_pcu);1568 break;1569 default:1570 return -EINVAL;1571 1572 }1573 1574 /* For AR5211 */1575 } else if (ah->ah_version == AR5K_AR5211) {1576 1577 /* AR5K_MODE_11B */1578 if (mode > 2) {1579 ATH5K_ERR(ah, "unsupported channel mode: %d\n", mode);1580 return -EINVAL;1581 }1582 1583 /* Mode-specific settings */1584 ath5k_hw_ini_mode_registers(ah, ARRAY_SIZE(ar5211_ini_mode),1585 ar5211_ini_mode, mode);1586 1587 /*1588 * Write initial settings common for all modes1589 */1590 ath5k_hw_ini_registers(ah, ARRAY_SIZE(ar5211_ini),1591 ar5211_ini, skip_pcu);1592 1593 /* AR5211 only comes with 5111 */1594 1595 /* Baseband gain table */1596 ath5k_hw_ini_registers(ah, ARRAY_SIZE(rf5111_ini_bbgain),1597 rf5111_ini_bbgain, skip_pcu);1598 /* For AR5210 (for mode settings check out ath5k_hw_reset_tx_queue) */1599 } else if (ah->ah_version == AR5K_AR5210) {1600 ath5k_hw_ini_registers(ah, ARRAY_SIZE(ar5210_ini),1601 ar5210_ini, skip_pcu);1602 }1603 1604 return 0;1605}1606