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1/*2 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>3 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>4 * Copyright (c) 2007-2008 Michael Taylor <mike.taylor@apprion.com>5 *6 * Permission to use, copy, modify, and distribute this software for any7 * purpose with or without fee is hereby granted, provided that the above8 * copyright notice and this permission notice appear in all copies.9 *10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.17 *18 */19 20/*21 * Register values for Atheros 5210/5211/5212 cards from OpenBSD's ar5k22 * maintained by Reyk Floeter23 *24 * I tried to document those registers by looking at ar5k code, some25 * 802.11 (802.11e mostly) papers and by reading various public available26 * Atheros presentations and papers like these:27 *28 * 5210 - http://nova.stanford.edu/~bbaas/ps/isscc2002_slides.pdf29 *30 * 5211 - http://www.hotchips.org/archives/hc14/3_Tue/16_mcfarland.pdf31 *32 * This file also contains register values found on a memory dump of33 * Atheros's ART program (Atheros Radio Test), on ath9k, on legacy-hal34 * released by Atheros and on various debug messages found on the net.35 */36 37#include "../reg.h"38 39/*====MAC DMA REGISTERS====*/40 41/*42 * AR5210-Specific TXDP registers43 * 5210 has only 2 transmit queues so no DCU/QCU, just44 * 2 transmit descriptor pointers...45 */46#define AR5K_NOQCU_TXDP0 0x0000 /* Queue 0 - data */47#define AR5K_NOQCU_TXDP1 0x0004 /* Queue 1 - beacons */48 49/*50 * Mac Control Register51 */52#define AR5K_CR 0x0008 /* Register Address */53#define AR5K_CR_TXE0 0x00000001 /* TX Enable for queue 0 on 5210 */54#define AR5K_CR_TXE1 0x00000002 /* TX Enable for queue 1 on 5210 */55#define AR5K_CR_RXE 0x00000004 /* RX Enable */56#define AR5K_CR_TXD0 0x00000008 /* TX Disable for queue 0 on 5210 */57#define AR5K_CR_TXD1 0x00000010 /* TX Disable for queue 1 on 5210 */58#define AR5K_CR_RXD 0x00000020 /* RX Disable */59#define AR5K_CR_SWI 0x00000040 /* Software Interrupt */60 61/*62 * RX Descriptor Pointer register63 */64#define AR5K_RXDP 0x000c65 66/*67 * Configuration and status register68 */69#define AR5K_CFG 0x0014 /* Register Address */70#define AR5K_CFG_SWTD 0x00000001 /* Byte-swap TX descriptor (for big endian archs) */71#define AR5K_CFG_SWTB 0x00000002 /* Byte-swap TX buffer */72#define AR5K_CFG_SWRD 0x00000004 /* Byte-swap RX descriptor */73#define AR5K_CFG_SWRB 0x00000008 /* Byte-swap RX buffer */74#define AR5K_CFG_SWRG 0x00000010 /* Byte-swap Register access */75#define AR5K_CFG_IBSS 0x00000020 /* 0-BSS, 1-IBSS [5211+] */76#define AR5K_CFG_PHY_OK 0x00000100 /* [5211+] */77#define AR5K_CFG_EEBS 0x00000200 /* EEPROM is busy */78#define AR5K_CFG_CLKGD 0x00000400 /* Clock gated (Disable dynamic clock) */79#define AR5K_CFG_TXCNT 0x00007800 /* Tx frame count (?) [5210] */80#define AR5K_CFG_TXCNT_S 1181#define AR5K_CFG_TXFSTAT 0x00008000 /* Tx frame status (?) [5210] */82#define AR5K_CFG_TXFSTRT 0x00010000 /* [5210] */83#define AR5K_CFG_PCI_THRES 0x00060000 /* PCI Master req q threshold [5211+] */84#define AR5K_CFG_PCI_THRES_S 1785 86/*87 * Interrupt enable register88 */89#define AR5K_IER 0x0024 /* Register Address */90#define AR5K_IER_DISABLE 0x00000000 /* Disable card interrupts */91#define AR5K_IER_ENABLE 0x00000001 /* Enable card interrupts */92 93 94/*95 * 0x0028 is Beacon Control Register on 521096 * and first RTS duration register on 521197 */98 99/*100 * Beacon control register [5210]101 */102#define AR5K_BCR 0x0028 /* Register Address */103#define AR5K_BCR_AP 0x00000000 /* AP mode */104#define AR5K_BCR_ADHOC 0x00000001 /* Ad-Hoc mode */105#define AR5K_BCR_BDMAE 0x00000002 /* DMA enable */106#define AR5K_BCR_TQ1FV 0x00000004 /* Use Queue1 for CAB traffic */107#define AR5K_BCR_TQ1V 0x00000008 /* Use Queue1 for Beacon traffic */108#define AR5K_BCR_BCGET 0x00000010109 110/*111 * First RTS duration register [5211]112 */113#define AR5K_RTSD0 0x0028 /* Register Address */114#define AR5K_RTSD0_6 0x000000ff /* 6Mb RTS duration mask (?) */115#define AR5K_RTSD0_6_S 0 /* 6Mb RTS duration shift (?) */116#define AR5K_RTSD0_9 0x0000ff00 /* 9Mb*/117#define AR5K_RTSD0_9_S 8118#define AR5K_RTSD0_12 0x00ff0000 /* 12Mb*/119#define AR5K_RTSD0_12_S 16120#define AR5K_RTSD0_18 0xff000000 /* 16Mb*/121#define AR5K_RTSD0_18_S 24122 123 124/*125 * 0x002c is Beacon Status Register on 5210126 * and second RTS duration register on 5211127 */128 129/*130 * Beacon status register [5210]131 *132 * As i can see in ar5k_ar5210_tx_start Reyk uses some of the values of BCR133 * for this register, so i guess TQ1V,TQ1FV and BDMAE have the same meaning134 * here and SNP/SNAP means "snapshot" (so this register gets synced with BCR).135 * So SNAPPEDBCRVALID should also stand for "snapped BCR -values- valid", so i136 * renamed it to SNAPSHOTSVALID to make more sense. I really have no idea what137 * else can it be. I also renamed SNPBCMD to SNPADHOC to match BCR.138 */139#define AR5K_BSR 0x002c /* Register Address */140#define AR5K_BSR_BDLYSW 0x00000001 /* SW Beacon delay (?) */141#define AR5K_BSR_BDLYDMA 0x00000002 /* DMA Beacon delay (?) */142#define AR5K_BSR_TXQ1F 0x00000004 /* Beacon queue (1) finished */143#define AR5K_BSR_ATIMDLY 0x00000008 /* ATIM delay (?) */144#define AR5K_BSR_SNPADHOC 0x00000100 /* Ad-hoc mode set (?) */145#define AR5K_BSR_SNPBDMAE 0x00000200 /* Beacon DMA enabled (?) */146#define AR5K_BSR_SNPTQ1FV 0x00000400 /* Queue1 is used for CAB traffic (?) */147#define AR5K_BSR_SNPTQ1V 0x00000800 /* Queue1 is used for Beacon traffic (?) */148#define AR5K_BSR_SNAPSHOTSVALID 0x00001000 /* BCR snapshots are valid (?) */149#define AR5K_BSR_SWBA_CNT 0x00ff0000150 151/*152 * Second RTS duration register [5211]153 */154#define AR5K_RTSD1 0x002c /* Register Address */155#define AR5K_RTSD1_24 0x000000ff /* 24Mb */156#define AR5K_RTSD1_24_S 0157#define AR5K_RTSD1_36 0x0000ff00 /* 36Mb */158#define AR5K_RTSD1_36_S 8159#define AR5K_RTSD1_48 0x00ff0000 /* 48Mb */160#define AR5K_RTSD1_48_S 16161#define AR5K_RTSD1_54 0xff000000 /* 54Mb */162#define AR5K_RTSD1_54_S 24163 164 165/*166 * Transmit configuration register167 */168#define AR5K_TXCFG 0x0030 /* Register Address */169#define AR5K_TXCFG_SDMAMR 0x00000007 /* DMA size (read) */170#define AR5K_TXCFG_SDMAMR_S 0171#define AR5K_TXCFG_B_MODE 0x00000008 /* Set b mode for 5111 (enable 2111) */172#define AR5K_TXCFG_TXFSTP 0x00000008 /* TX DMA full Stop [5210] */173#define AR5K_TXCFG_TXFULL 0x000003f0 /* TX Trigger level mask */174#define AR5K_TXCFG_TXFULL_S 4175#define AR5K_TXCFG_TXFULL_0B 0x00000000176#define AR5K_TXCFG_TXFULL_64B 0x00000010177#define AR5K_TXCFG_TXFULL_128B 0x00000020178#define AR5K_TXCFG_TXFULL_192B 0x00000030179#define AR5K_TXCFG_TXFULL_256B 0x00000040180#define AR5K_TXCFG_TXCONT_EN 0x00000080181#define AR5K_TXCFG_DMASIZE 0x00000100 /* Flag for passing DMA size [5210] */182#define AR5K_TXCFG_JUMBO_DESC_EN 0x00000400 /* Enable jumbo tx descriptors [5211+] */183#define AR5K_TXCFG_ADHOC_BCN_ATIM 0x00000800 /* Adhoc Beacon ATIM Policy */184#define AR5K_TXCFG_ATIM_WINDOW_DEF_DIS 0x00001000 /* Disable ATIM window defer [5211+] */185#define AR5K_TXCFG_RTSRND 0x00001000 /* [5211+] */186#define AR5K_TXCFG_FRMPAD_DIS 0x00002000 /* [5211+] */187#define AR5K_TXCFG_RDY_CBR_DIS 0x00004000 /* Ready time CBR disable [5211+] */188#define AR5K_TXCFG_JUMBO_FRM_MODE 0x00008000 /* Jumbo frame mode [5211+] */189#define AR5K_TXCFG_DCU_DBL_BUF_DIS 0x00008000 /* Disable double buffering on DCU */190#define AR5K_TXCFG_DCU_CACHING_DIS 0x00010000 /* Disable DCU caching */191 192/*193 * Receive configuration register194 */195#define AR5K_RXCFG 0x0034 /* Register Address */196#define AR5K_RXCFG_SDMAMW 0x00000007 /* DMA size (write) */197#define AR5K_RXCFG_SDMAMW_S 0198#define AR5K_RXCFG_ZLFDMA 0x00000008 /* Enable Zero-length frame DMA */199#define AR5K_RXCFG_DEF_ANTENNA 0x00000010 /* Default antenna (?) */200#define AR5K_RXCFG_JUMBO_RXE 0x00000020 /* Enable jumbo rx descriptors [5211+] */201#define AR5K_RXCFG_JUMBO_WRAP 0x00000040 /* Wrap jumbo frames [5211+] */202#define AR5K_RXCFG_SLE_ENTRY 0x00000080 /* Sleep entry policy */203 204/*205 * Receive jumbo descriptor last address register206 * Only found in 5211 (?)207 */208#define AR5K_RXJLA 0x0038209 210/*211 * MIB control register212 */213#define AR5K_MIBC 0x0040 /* Register Address */214#define AR5K_MIBC_COW 0x00000001 /* Counter Overflow Warning */215#define AR5K_MIBC_FMC 0x00000002 /* Freeze MIB Counters */216#define AR5K_MIBC_CMC 0x00000004 /* Clear MIB Counters */217#define AR5K_MIBC_MCS 0x00000008 /* MIB counter strobe, increment all */218 219/*220 * Timeout prescale register221 */222#define AR5K_TOPS 0x0044223#define AR5K_TOPS_M 0x0000ffff224 225/*226 * Receive timeout register (no frame received)227 */228#define AR5K_RXNOFRM 0x0048229#define AR5K_RXNOFRM_M 0x000003ff230 231/*232 * Transmit timeout register (no frame sent)233 */234#define AR5K_TXNOFRM 0x004c235#define AR5K_TXNOFRM_M 0x000003ff236#define AR5K_TXNOFRM_QCU 0x000ffc00237#define AR5K_TXNOFRM_QCU_S 10238 239/*240 * Receive frame gap timeout register241 */242#define AR5K_RPGTO 0x0050243#define AR5K_RPGTO_M 0x000003ff244 245/*246 * Receive frame count limit register247 */248#define AR5K_RFCNT 0x0054249#define AR5K_RFCNT_M 0x0000001f /* [5211+] (?) */250#define AR5K_RFCNT_RFCL 0x0000000f /* [5210] */251 252/*253 * Misc settings register254 * (reserved0-3)255 */256#define AR5K_MISC 0x0058 /* Register Address */257#define AR5K_MISC_DMA_OBS_M 0x000001e0258#define AR5K_MISC_DMA_OBS_S 5259#define AR5K_MISC_MISC_OBS_M 0x00000e00260#define AR5K_MISC_MISC_OBS_S 9261#define AR5K_MISC_MAC_OBS_LSB_M 0x00007000262#define AR5K_MISC_MAC_OBS_LSB_S 12263#define AR5K_MISC_MAC_OBS_MSB_M 0x00038000264#define AR5K_MISC_MAC_OBS_MSB_S 15265#define AR5K_MISC_LED_DECAY 0x001c0000 /* [5210] */266#define AR5K_MISC_LED_BLINK 0x00e00000 /* [5210] */267 268/*269 * QCU/DCU clock gating register (5311)270 * (reserved4-5)271 */272#define AR5K_QCUDCU_CLKGT 0x005c /* Register Address (?) */273#define AR5K_QCUDCU_CLKGT_QCU 0x0000ffff /* Mask for QCU clock */274#define AR5K_QCUDCU_CLKGT_DCU 0x07ff0000 /* Mask for DCU clock */275 276/*277 * Interrupt Status Registers278 *279 * For 5210 there is only one status register but for280 * 5211/5212 we have one primary and 4 secondary registers.281 * So we have AR5K_ISR for 5210 and AR5K_PISR /SISRx for 5211/5212.282 * Most of these bits are common for all chipsets.283 *284 * NOTE: On 5211+ TXOK, TXDESC, TXERR, TXEOL and TXURN contain285 * the logical OR from per-queue interrupt bits found on SISR registers286 * (see below).287 */288#define AR5K_ISR 0x001c /* Register Address [5210] */289#define AR5K_PISR 0x0080 /* Register Address [5211+] */290#define AR5K_ISR_RXOK 0x00000001 /* Frame successfully received */291#define AR5K_ISR_RXDESC 0x00000002 /* RX descriptor request */292#define AR5K_ISR_RXERR 0x00000004 /* Receive error */293#define AR5K_ISR_RXNOFRM 0x00000008 /* No frame received (receive timeout) */294#define AR5K_ISR_RXEOL 0x00000010 /* Empty RX descriptor */295#define AR5K_ISR_RXORN 0x00000020 /* Receive FIFO overrun */296#define AR5K_ISR_TXOK 0x00000040 /* Frame successfully transmitted */297#define AR5K_ISR_TXDESC 0x00000080 /* TX descriptor request */298#define AR5K_ISR_TXERR 0x00000100 /* Transmit error */299#define AR5K_ISR_TXNOFRM 0x00000200 /* No frame transmitted (transmit timeout)300 * NOTE: We don't have per-queue info for this301 * one, but we can enable it per-queue through302 * TXNOFRM_QCU field on TXNOFRM register */303#define AR5K_ISR_TXEOL 0x00000400 /* Empty TX descriptor */304#define AR5K_ISR_TXURN 0x00000800 /* Transmit FIFO underrun */305#define AR5K_ISR_MIB 0x00001000 /* Update MIB counters */306#define AR5K_ISR_SWI 0x00002000 /* Software interrupt */307#define AR5K_ISR_RXPHY 0x00004000 /* PHY error */308#define AR5K_ISR_RXKCM 0x00008000 /* RX Key cache miss */309#define AR5K_ISR_SWBA 0x00010000 /* Software beacon alert */310#define AR5K_ISR_BRSSI 0x00020000 /* Beacon rssi below threshold (?) */311#define AR5K_ISR_BMISS 0x00040000 /* Beacon missed */312#define AR5K_ISR_HIUERR 0x00080000 /* Host Interface Unit error [5211+]313 * 'or' of MCABT, SSERR, DPERR from SISR2 */314#define AR5K_ISR_BNR 0x00100000 /* Beacon not ready [5211+] */315#define AR5K_ISR_MCABT 0x00100000 /* Master Cycle Abort [5210] */316#define AR5K_ISR_RXCHIRP 0x00200000 /* CHIRP Received [5212+] */317#define AR5K_ISR_SSERR 0x00200000 /* Signaled System Error [5210] */318#define AR5K_ISR_DPERR 0x00400000 /* Bus parity error [5210] */319#define AR5K_ISR_RXDOPPLER 0x00400000 /* Doppler chirp received [5212+] */320#define AR5K_ISR_TIM 0x00800000 /* [5211+] */321#define AR5K_ISR_BCNMISC 0x00800000 /* Misc beacon related interrupt322 * 'or' of TIM, CAB_END, DTIM_SYNC, BCN_TIMEOUT,323 * CAB_TIMEOUT and DTIM bits from SISR2 [5212+] */324#define AR5K_ISR_GPIO 0x01000000 /* GPIO (rf kill) */325#define AR5K_ISR_QCBRORN 0x02000000 /* QCU CBR overrun [5211+] */326#define AR5K_ISR_QCBRURN 0x04000000 /* QCU CBR underrun [5211+] */327#define AR5K_ISR_QTRIG 0x08000000 /* QCU scheduling trigger [5211+] */328 329#define AR5K_ISR_BITS_FROM_SISRS (AR5K_ISR_TXOK | AR5K_ISR_TXDESC |\330 AR5K_ISR_TXERR | AR5K_ISR_TXEOL |\331 AR5K_ISR_TXURN | AR5K_ISR_HIUERR |\332 AR5K_ISR_BCNMISC | AR5K_ISR_QCBRORN |\333 AR5K_ISR_QCBRURN | AR5K_ISR_QTRIG)334 335/*336 * Secondary status registers [5211+] (0 - 4)337 *338 * These give the status for each QCU, only QCUs 0-9 are339 * represented.340 */341#define AR5K_SISR0 0x0084 /* Register Address [5211+] */342#define AR5K_SISR0_QCU_TXOK 0x000003ff /* Mask for QCU_TXOK */343#define AR5K_SISR0_QCU_TXOK_S 0344#define AR5K_SISR0_QCU_TXDESC 0x03ff0000 /* Mask for QCU_TXDESC */345#define AR5K_SISR0_QCU_TXDESC_S 16346 347#define AR5K_SISR1 0x0088 /* Register Address [5211+] */348#define AR5K_SISR1_QCU_TXERR 0x000003ff /* Mask for QCU_TXERR */349#define AR5K_SISR1_QCU_TXERR_S 0350#define AR5K_SISR1_QCU_TXEOL 0x03ff0000 /* Mask for QCU_TXEOL */351#define AR5K_SISR1_QCU_TXEOL_S 16352 353#define AR5K_SISR2 0x008c /* Register Address [5211+] */354#define AR5K_SISR2_QCU_TXURN 0x000003ff /* Mask for QCU_TXURN */355#define AR5K_SISR2_QCU_TXURN_S 0356#define AR5K_SISR2_MCABT 0x00010000 /* Master Cycle Abort */357#define AR5K_SISR2_SSERR 0x00020000 /* Signaled System Error */358#define AR5K_SISR2_DPERR 0x00040000 /* Bus parity error */359#define AR5K_SISR2_TIM 0x01000000 /* [5212+] */360#define AR5K_SISR2_CAB_END 0x02000000 /* [5212+] */361#define AR5K_SISR2_DTIM_SYNC 0x04000000 /* DTIM sync lost [5212+] */362#define AR5K_SISR2_BCN_TIMEOUT 0x08000000 /* Beacon Timeout [5212+] */363#define AR5K_SISR2_CAB_TIMEOUT 0x10000000 /* CAB Timeout [5212+] */364#define AR5K_SISR2_DTIM 0x20000000 /* [5212+] */365#define AR5K_SISR2_TSFOOR 0x80000000 /* TSF Out of range */366 367#define AR5K_SISR3 0x0090 /* Register Address [5211+] */368#define AR5K_SISR3_QCBRORN 0x000003ff /* Mask for QCBRORN */369#define AR5K_SISR3_QCBRORN_S 0370#define AR5K_SISR3_QCBRURN 0x03ff0000 /* Mask for QCBRURN */371#define AR5K_SISR3_QCBRURN_S 16372 373#define AR5K_SISR4 0x0094 /* Register Address [5211+] */374#define AR5K_SISR4_QTRIG 0x000003ff /* Mask for QTRIG */375#define AR5K_SISR4_QTRIG_S 0376 377/*378 * Shadow read-and-clear interrupt status registers [5211+]379 */380#define AR5K_RAC_PISR 0x00c0 /* Read and clear PISR */381#define AR5K_RAC_SISR0 0x00c4 /* Read and clear SISR0 */382#define AR5K_RAC_SISR1 0x00c8 /* Read and clear SISR1 */383#define AR5K_RAC_SISR2 0x00cc /* Read and clear SISR2 */384#define AR5K_RAC_SISR3 0x00d0 /* Read and clear SISR3 */385#define AR5K_RAC_SISR4 0x00d4 /* Read and clear SISR4 */386 387/*388 * Interrupt Mask Registers389 *390 * As with ISRs 5210 has one IMR (AR5K_IMR) and 5211/5212 has one primary391 * (AR5K_PIMR) and 4 secondary IMRs (AR5K_SIMRx). Note that ISR/IMR flags match.392 */393#define AR5K_IMR 0x0020 /* Register Address [5210] */394#define AR5K_PIMR 0x00a0 /* Register Address [5211+] */395#define AR5K_IMR_RXOK 0x00000001 /* Frame successfully received*/396#define AR5K_IMR_RXDESC 0x00000002 /* RX descriptor request*/397#define AR5K_IMR_RXERR 0x00000004 /* Receive error*/398#define AR5K_IMR_RXNOFRM 0x00000008 /* No frame received (receive timeout)*/399#define AR5K_IMR_RXEOL 0x00000010 /* Empty RX descriptor*/400#define AR5K_IMR_RXORN 0x00000020 /* Receive FIFO overrun*/401#define AR5K_IMR_TXOK 0x00000040 /* Frame successfully transmitted*/402#define AR5K_IMR_TXDESC 0x00000080 /* TX descriptor request*/403#define AR5K_IMR_TXERR 0x00000100 /* Transmit error*/404#define AR5K_IMR_TXNOFRM 0x00000200 /* No frame transmitted (transmit timeout)*/405#define AR5K_IMR_TXEOL 0x00000400 /* Empty TX descriptor*/406#define AR5K_IMR_TXURN 0x00000800 /* Transmit FIFO underrun*/407#define AR5K_IMR_MIB 0x00001000 /* Update MIB counters*/408#define AR5K_IMR_SWI 0x00002000 /* Software interrupt */409#define AR5K_IMR_RXPHY 0x00004000 /* PHY error*/410#define AR5K_IMR_RXKCM 0x00008000 /* RX Key cache miss */411#define AR5K_IMR_SWBA 0x00010000 /* Software beacon alert*/412#define AR5K_IMR_BRSSI 0x00020000 /* Beacon rssi below threshold (?) */413#define AR5K_IMR_BMISS 0x00040000 /* Beacon missed*/414#define AR5K_IMR_HIUERR 0x00080000 /* Host Interface Unit error [5211+] */415#define AR5K_IMR_BNR 0x00100000 /* Beacon not ready [5211+] */416#define AR5K_IMR_MCABT 0x00100000 /* Master Cycle Abort [5210] */417#define AR5K_IMR_RXCHIRP 0x00200000 /* CHIRP Received [5212+]*/418#define AR5K_IMR_SSERR 0x00200000 /* Signaled System Error [5210] */419#define AR5K_IMR_DPERR 0x00400000 /* Det par Error (?) [5210] */420#define AR5K_IMR_RXDOPPLER 0x00400000 /* Doppler chirp received [5212+] */421#define AR5K_IMR_TIM 0x00800000 /* [5211+] */422#define AR5K_IMR_BCNMISC 0x00800000 /* 'or' of TIM, CAB_END, DTIM_SYNC, BCN_TIMEOUT,423 CAB_TIMEOUT and DTIM bits from SISR2 [5212+] */424#define AR5K_IMR_GPIO 0x01000000 /* GPIO (rf kill)*/425#define AR5K_IMR_QCBRORN 0x02000000 /* QCU CBR overrun (?) [5211+] */426#define AR5K_IMR_QCBRURN 0x04000000 /* QCU CBR underrun (?) [5211+] */427#define AR5K_IMR_QTRIG 0x08000000 /* QCU scheduling trigger [5211+] */428 429/*430 * Secondary interrupt mask registers [5211+] (0 - 4)431 */432#define AR5K_SIMR0 0x00a4 /* Register Address [5211+] */433#define AR5K_SIMR0_QCU_TXOK 0x000003ff /* Mask for QCU_TXOK */434#define AR5K_SIMR0_QCU_TXOK_S 0435#define AR5K_SIMR0_QCU_TXDESC 0x03ff0000 /* Mask for QCU_TXDESC */436#define AR5K_SIMR0_QCU_TXDESC_S 16437 438#define AR5K_SIMR1 0x00a8 /* Register Address [5211+] */439#define AR5K_SIMR1_QCU_TXERR 0x000003ff /* Mask for QCU_TXERR */440#define AR5K_SIMR1_QCU_TXERR_S 0441#define AR5K_SIMR1_QCU_TXEOL 0x03ff0000 /* Mask for QCU_TXEOL */442#define AR5K_SIMR1_QCU_TXEOL_S 16443 444#define AR5K_SIMR2 0x00ac /* Register Address [5211+] */445#define AR5K_SIMR2_QCU_TXURN 0x000003ff /* Mask for QCU_TXURN */446#define AR5K_SIMR2_QCU_TXURN_S 0447#define AR5K_SIMR2_MCABT 0x00010000 /* Master Cycle Abort */448#define AR5K_SIMR2_SSERR 0x00020000 /* Signaled System Error */449#define AR5K_SIMR2_DPERR 0x00040000 /* Bus parity error */450#define AR5K_SIMR2_TIM 0x01000000 /* [5212+] */451#define AR5K_SIMR2_CAB_END 0x02000000 /* [5212+] */452#define AR5K_SIMR2_DTIM_SYNC 0x04000000 /* DTIM Sync lost [5212+] */453#define AR5K_SIMR2_BCN_TIMEOUT 0x08000000 /* Beacon Timeout [5212+] */454#define AR5K_SIMR2_CAB_TIMEOUT 0x10000000 /* CAB Timeout [5212+] */455#define AR5K_SIMR2_DTIM 0x20000000 /* [5212+] */456#define AR5K_SIMR2_TSFOOR 0x80000000 /* TSF OOR (?) */457 458#define AR5K_SIMR3 0x00b0 /* Register Address [5211+] */459#define AR5K_SIMR3_QCBRORN 0x000003ff /* Mask for QCBRORN */460#define AR5K_SIMR3_QCBRORN_S 0461#define AR5K_SIMR3_QCBRURN 0x03ff0000 /* Mask for QCBRURN */462#define AR5K_SIMR3_QCBRURN_S 16463 464#define AR5K_SIMR4 0x00b4 /* Register Address [5211+] */465#define AR5K_SIMR4_QTRIG 0x000003ff /* Mask for QTRIG */466#define AR5K_SIMR4_QTRIG_S 0467 468/*469 * DMA Debug registers 0-7470 * 0xe0 - 0xfc471 */472 473/*474 * Decompression mask registers [5212+]475 */476#define AR5K_DCM_ADDR 0x0400 /*Decompression mask address (index) */477#define AR5K_DCM_DATA 0x0404 /*Decompression mask data */478 479/*480 * Wake On Wireless pattern control register [5212+]481 */482#define AR5K_WOW_PCFG 0x0410 /* Register Address */483#define AR5K_WOW_PCFG_PAT_MATCH_EN 0x00000001 /* Pattern match enable */484#define AR5K_WOW_PCFG_LONG_FRAME_POL 0x00000002 /* Long frame policy */485#define AR5K_WOW_PCFG_WOBMISS 0x00000004 /* Wake on bea(con) miss (?) */486#define AR5K_WOW_PCFG_PAT_0_EN 0x00000100 /* Enable pattern 0 */487#define AR5K_WOW_PCFG_PAT_1_EN 0x00000200 /* Enable pattern 1 */488#define AR5K_WOW_PCFG_PAT_2_EN 0x00000400 /* Enable pattern 2 */489#define AR5K_WOW_PCFG_PAT_3_EN 0x00000800 /* Enable pattern 3 */490#define AR5K_WOW_PCFG_PAT_4_EN 0x00001000 /* Enable pattern 4 */491#define AR5K_WOW_PCFG_PAT_5_EN 0x00002000 /* Enable pattern 5 */492 493/*494 * Wake On Wireless pattern index register (?) [5212+]495 */496#define AR5K_WOW_PAT_IDX 0x0414497 498/*499 * Wake On Wireless pattern data register [5212+]500 */501#define AR5K_WOW_PAT_DATA 0x0418 /* Register Address */502#define AR5K_WOW_PAT_DATA_0_3_V 0x00000001 /* Pattern 0, 3 value */503#define AR5K_WOW_PAT_DATA_1_4_V 0x00000100 /* Pattern 1, 4 value */504#define AR5K_WOW_PAT_DATA_2_5_V 0x00010000 /* Pattern 2, 5 value */505#define AR5K_WOW_PAT_DATA_0_3_M 0x01000000 /* Pattern 0, 3 mask */506#define AR5K_WOW_PAT_DATA_1_4_M 0x04000000 /* Pattern 1, 4 mask */507#define AR5K_WOW_PAT_DATA_2_5_M 0x10000000 /* Pattern 2, 5 mask */508 509/*510 * Decompression configuration registers [5212+]511 */512#define AR5K_DCCFG 0x0420 /* Register Address */513#define AR5K_DCCFG_GLOBAL_EN 0x00000001 /* Enable decompression on all queues */514#define AR5K_DCCFG_BYPASS_EN 0x00000002 /* Bypass decompression */515#define AR5K_DCCFG_BCAST_EN 0x00000004 /* Enable decompression for bcast frames */516#define AR5K_DCCFG_MCAST_EN 0x00000008 /* Enable decompression for mcast frames */517 518/*519 * Compression configuration registers [5212+]520 */521#define AR5K_CCFG 0x0600 /* Register Address */522#define AR5K_CCFG_WINDOW_SIZE 0x00000007 /* Compression window size */523#define AR5K_CCFG_CPC_EN 0x00000008 /* Enable performance counters */524 525#define AR5K_CCFG_CCU 0x0604 /* Register Address */526#define AR5K_CCFG_CCU_CUP_EN 0x00000001 /* CCU Catchup enable */527#define AR5K_CCFG_CCU_CREDIT 0x00000002 /* CCU Credit (field) */528#define AR5K_CCFG_CCU_CD_THRES 0x00000080 /* CCU Cyc(lic?) debt threshold (field) */529#define AR5K_CCFG_CCU_CUP_LCNT 0x00010000 /* CCU Catchup lit(?) count */530#define AR5K_CCFG_CCU_INIT 0x00100200 /* Initial value during reset */531 532/*533 * Compression performance counter registers [5212+]534 */535#define AR5K_CPC0 0x0610 /* Compression performance counter 0 */536#define AR5K_CPC1 0x0614 /* Compression performance counter 1*/537#define AR5K_CPC2 0x0618 /* Compression performance counter 2 */538#define AR5K_CPC3 0x061c /* Compression performance counter 3 */539#define AR5K_CPCOVF 0x0620 /* Compression performance overflow */540 541 542/*543 * Queue control unit (QCU) registers [5211+]544 *545 * Card has 12 TX Queues but i see that only 0-9 are used (?)546 * both in binary HAL (see ah.h) and ar5k. Each queue has it's own547 * TXDP at addresses 0x0800 - 0x082c, a CBR (Constant Bit Rate)548 * configuration register (0x08c0 - 0x08ec), a ready time configuration549 * register (0x0900 - 0x092c), a misc configuration register (0x09c0 -550 * 0x09ec) and a status register (0x0a00 - 0x0a2c). We also have some551 * global registers, QCU transmit enable/disable and "one shot arm (?)"552 * set/clear, which contain status for all queues (we shift by 1 for each553 * queue). To access these registers easily we define some macros here554 * that are used inside HAL. For more infos check out *_tx_queue functs.555 */556 557/*558 * Generic QCU Register access macros559 */560#define AR5K_QUEUE_REG(_r, _q) (((_q) << 2) + _r)561#define AR5K_QCU_GLOBAL_READ(_r, _q) (AR5K_REG_READ(_r) & (1 << _q))562#define AR5K_QCU_GLOBAL_WRITE(_r, _q) AR5K_REG_WRITE(_r, (1 << _q))563 564/*565 * QCU Transmit descriptor pointer registers566 */567#define AR5K_QCU_TXDP_BASE 0x0800 /* Register Address - Queue0 TXDP */568#define AR5K_QUEUE_TXDP(_q) AR5K_QUEUE_REG(AR5K_QCU_TXDP_BASE, _q)569 570/*571 * QCU Transmit enable register572 */573#define AR5K_QCU_TXE 0x0840574#define AR5K_ENABLE_QUEUE(_q) AR5K_QCU_GLOBAL_WRITE(AR5K_QCU_TXE, _q)575#define AR5K_QUEUE_ENABLED(_q) AR5K_QCU_GLOBAL_READ(AR5K_QCU_TXE, _q)576 577/*578 * QCU Transmit disable register579 */580#define AR5K_QCU_TXD 0x0880581#define AR5K_DISABLE_QUEUE(_q) AR5K_QCU_GLOBAL_WRITE(AR5K_QCU_TXD, _q)582#define AR5K_QUEUE_DISABLED(_q) AR5K_QCU_GLOBAL_READ(AR5K_QCU_TXD, _q)583 584/*585 * QCU Constant Bit Rate configuration registers586 */587#define AR5K_QCU_CBRCFG_BASE 0x08c0 /* Register Address - Queue0 CBRCFG */588#define AR5K_QCU_CBRCFG_INTVAL 0x00ffffff /* CBR Interval mask */589#define AR5K_QCU_CBRCFG_INTVAL_S 0590#define AR5K_QCU_CBRCFG_ORN_THRES 0xff000000 /* CBR overrun threshold mask */591#define AR5K_QCU_CBRCFG_ORN_THRES_S 24592#define AR5K_QUEUE_CBRCFG(_q) AR5K_QUEUE_REG(AR5K_QCU_CBRCFG_BASE, _q)593 594/*595 * QCU Ready time configuration registers596 */597#define AR5K_QCU_RDYTIMECFG_BASE 0x0900 /* Register Address - Queue0 RDYTIMECFG */598#define AR5K_QCU_RDYTIMECFG_INTVAL 0x00ffffff /* Ready time interval mask */599#define AR5K_QCU_RDYTIMECFG_INTVAL_S 0600#define AR5K_QCU_RDYTIMECFG_ENABLE 0x01000000 /* Ready time enable mask */601#define AR5K_QUEUE_RDYTIMECFG(_q) AR5K_QUEUE_REG(AR5K_QCU_RDYTIMECFG_BASE, _q)602 603/*604 * QCU one shot arm set registers605 */606#define AR5K_QCU_ONESHOTARM_SET 0x0940 /* Register Address -QCU "one shot arm set (?)" */607#define AR5K_QCU_ONESHOTARM_SET_M 0x0000ffff608 609/*610 * QCU one shot arm clear registers611 */612#define AR5K_QCU_ONESHOTARM_CLEAR 0x0980 /* Register Address -QCU "one shot arm clear (?)" */613#define AR5K_QCU_ONESHOTARM_CLEAR_M 0x0000ffff614 615/*616 * QCU misc registers617 */618#define AR5K_QCU_MISC_BASE 0x09c0 /* Register Address -Queue0 MISC */619#define AR5K_QCU_MISC_FRSHED_M 0x0000000f /* Frame scheduling mask */620#define AR5K_QCU_MISC_FRSHED_ASAP 0 /* ASAP */621#define AR5K_QCU_MISC_FRSHED_CBR 1 /* Constant Bit Rate */622#define AR5K_QCU_MISC_FRSHED_DBA_GT 2 /* DMA Beacon alert gated */623#define AR5K_QCU_MISC_FRSHED_TIM_GT 3 /* TIMT gated */624#define AR5K_QCU_MISC_FRSHED_BCN_SENT_GT 4 /* Beacon sent gated */625#define AR5K_QCU_MISC_ONESHOT_ENABLE 0x00000010 /* Oneshot enable */626#define AR5K_QCU_MISC_CBREXP_DIS 0x00000020 /* Disable CBR expired counter (normal queue) */627#define AR5K_QCU_MISC_CBREXP_BCN_DIS 0x00000040 /* Disable CBR expired counter (beacon queue) */628#define AR5K_QCU_MISC_BCN_ENABLE 0x00000080 /* Enable Beacon use */629#define AR5K_QCU_MISC_CBR_THRES_ENABLE 0x00000100 /* CBR expired threshold enabled */630#define AR5K_QCU_MISC_RDY_VEOL_POLICY 0x00000200 /* TXE reset when RDYTIME expired or VEOL */631#define AR5K_QCU_MISC_CBR_RESET_CNT 0x00000400 /* CBR threshold (counter) reset */632#define AR5K_QCU_MISC_DCU_EARLY 0x00000800 /* DCU early termination */633#define AR5K_QCU_MISC_DCU_CMP_EN 0x00001000 /* Enable frame compression */634#define AR5K_QUEUE_MISC(_q) AR5K_QUEUE_REG(AR5K_QCU_MISC_BASE, _q)635 636 637/*638 * QCU status registers639 */640#define AR5K_QCU_STS_BASE 0x0a00 /* Register Address - Queue0 STS */641#define AR5K_QCU_STS_FRMPENDCNT 0x00000003 /* Frames pending counter */642#define AR5K_QCU_STS_CBREXPCNT 0x0000ff00 /* CBR expired counter */643#define AR5K_QUEUE_STATUS(_q) AR5K_QUEUE_REG(AR5K_QCU_STS_BASE, _q)644 645/*646 * QCU ready time shutdown register647 */648#define AR5K_QCU_RDYTIMESHDN 0x0a40649#define AR5K_QCU_RDYTIMESHDN_M 0x000003ff650 651/*652 * QCU compression buffer base registers [5212+]653 */654#define AR5K_QCU_CBB_SELECT 0x0b00655#define AR5K_QCU_CBB_ADDR 0x0b04656#define AR5K_QCU_CBB_ADDR_S 9657 658/*659 * QCU compression buffer configuration register [5212+]660 * (buffer size)661 */662#define AR5K_QCU_CBCFG 0x0b08663 664 665 666/*667 * Distributed Coordination Function (DCF) control unit (DCU)668 * registers [5211+]669 *670 * These registers control the various characteristics of each queue671 * for 802.11e (WME) compatibility so they go together with672 * QCU registers in pairs. For each queue we have a QCU mask register,673 * (0x1000 - 0x102c), a local-IFS settings register (0x1040 - 0x106c),674 * a retry limit register (0x1080 - 0x10ac), a channel time register675 * (0x10c0 - 0x10ec), a misc-settings register (0x1100 - 0x112c) and676 * a sequence number register (0x1140 - 0x116c). It seems that "global"677 * registers here affect all queues (see use of DCU_GBL_IFS_SLOT in ar5k).678 * We use the same macros here for easier register access.679 *680 */681 682/*683 * DCU QCU mask registers684 */685#define AR5K_DCU_QCUMASK_BASE 0x1000 /* Register Address -Queue0 DCU_QCUMASK */686#define AR5K_DCU_QCUMASK_M 0x000003ff687#define AR5K_QUEUE_QCUMASK(_q) AR5K_QUEUE_REG(AR5K_DCU_QCUMASK_BASE, _q)688 689/*690 * DCU local Inter Frame Space settings register691 */692#define AR5K_DCU_LCL_IFS_BASE 0x1040 /* Register Address -Queue0 DCU_LCL_IFS */693#define AR5K_DCU_LCL_IFS_CW_MIN 0x000003ff /* Minimum Contention Window */694#define AR5K_DCU_LCL_IFS_CW_MIN_S 0695#define AR5K_DCU_LCL_IFS_CW_MAX 0x000ffc00 /* Maximum Contention Window */696#define AR5K_DCU_LCL_IFS_CW_MAX_S 10697#define AR5K_DCU_LCL_IFS_AIFS 0x0ff00000 /* Arbitrated Interframe Space */698#define AR5K_DCU_LCL_IFS_AIFS_S 20699#define AR5K_DCU_LCL_IFS_AIFS_MAX 0xfc /* Anything above that can cause DCU to hang */700#define AR5K_QUEUE_DFS_LOCAL_IFS(_q) AR5K_QUEUE_REG(AR5K_DCU_LCL_IFS_BASE, _q)701 702/*703 * DCU retry limit registers704 * all these fields don't allow zero values705 */706#define AR5K_DCU_RETRY_LMT_BASE 0x1080 /* Register Address -Queue0 DCU_RETRY_LMT */707#define AR5K_DCU_RETRY_LMT_RTS 0x0000000f /* RTS failure limit. Transmission fails if no CTS is received for this number of times */708#define AR5K_DCU_RETRY_LMT_RTS_S 0709#define AR5K_DCU_RETRY_LMT_STA_RTS 0x00003f00 /* STA RTS failure limit. If exceeded CW reset */710#define AR5K_DCU_RETRY_LMT_STA_RTS_S 8711#define AR5K_DCU_RETRY_LMT_STA_DATA 0x000fc000 /* STA data failure limit. If exceeded CW reset. */712#define AR5K_DCU_RETRY_LMT_STA_DATA_S 14713#define AR5K_QUEUE_DFS_RETRY_LIMIT(_q) AR5K_QUEUE_REG(AR5K_DCU_RETRY_LMT_BASE, _q)714 715/*716 * DCU channel time registers717 */718#define AR5K_DCU_CHAN_TIME_BASE 0x10c0 /* Register Address -Queue0 DCU_CHAN_TIME */719#define AR5K_DCU_CHAN_TIME_DUR 0x000fffff /* Channel time duration */720#define AR5K_DCU_CHAN_TIME_DUR_S 0721#define AR5K_DCU_CHAN_TIME_ENABLE 0x00100000 /* Enable channel time */722#define AR5K_QUEUE_DFS_CHANNEL_TIME(_q) AR5K_QUEUE_REG(AR5K_DCU_CHAN_TIME_BASE, _q)723 724/*725 * DCU misc registers [5211+]726 *727 * Note: Arbiter lockout control controls the728 * behaviour on low priority queues when we have multiple queues729 * with pending frames. Intra-frame lockout means we wait until730 * the queue's current frame transmits (with post frame backoff and bursting)731 * before we transmit anything else and global lockout means we732 * wait for the whole queue to finish before higher priority queues733 * can transmit (this is used on beacon and CAB queues).734 * No lockout means there is no special handling.735 */736#define AR5K_DCU_MISC_BASE 0x1100 /* Register Address -Queue0 DCU_MISC */737#define AR5K_DCU_MISC_BACKOFF 0x0000003f /* Mask for backoff threshold */738#define AR5K_DCU_MISC_ETS_RTS_POL 0x00000040 /* End of transmission series739 station RTS/data failure count740 reset policy (?) */741#define AR5K_DCU_MISC_ETS_CW_POL 0x00000080 /* End of transmission series742 CW reset policy */743#define AR5K_DCU_MISC_FRAG_WAIT 0x00000100 /* Wait for next fragment */744#define AR5K_DCU_MISC_BACKOFF_FRAG 0x00000200 /* Enable backoff while bursting */745#define AR5K_DCU_MISC_HCFPOLL_ENABLE 0x00000800 /* CF - Poll enable */746#define AR5K_DCU_MISC_BACKOFF_PERSIST 0x00001000 /* Persistent backoff */747#define AR5K_DCU_MISC_FRMPRFTCH_ENABLE 0x00002000 /* Enable frame pre-fetch */748#define AR5K_DCU_MISC_VIRTCOL 0x0000c000 /* Mask for Virtual Collision (?) */749#define AR5K_DCU_MISC_VIRTCOL_NORMAL 0750#define AR5K_DCU_MISC_VIRTCOL_IGNORE 1751#define AR5K_DCU_MISC_BCN_ENABLE 0x00010000 /* Enable Beacon use */752#define AR5K_DCU_MISC_ARBLOCK_CTL 0x00060000 /* Arbiter lockout control mask */753#define AR5K_DCU_MISC_ARBLOCK_CTL_S 17754#define AR5K_DCU_MISC_ARBLOCK_CTL_NONE 0 /* No arbiter lockout */755#define AR5K_DCU_MISC_ARBLOCK_CTL_INTFRM 1 /* Intra-frame lockout */756#define AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL 2 /* Global lockout */757#define AR5K_DCU_MISC_ARBLOCK_IGNORE 0x00080000 /* Ignore Arbiter lockout */758#define AR5K_DCU_MISC_SEQ_NUM_INCR_DIS 0x00100000 /* Disable sequence number increment */759#define AR5K_DCU_MISC_POST_FR_BKOFF_DIS 0x00200000 /* Disable post-frame backoff */760#define AR5K_DCU_MISC_VIRT_COLL_POLICY 0x00400000 /* Virtual Collision cw policy */761#define AR5K_DCU_MISC_BLOWN_IFS_POLICY 0x00800000 /* Blown IFS policy (?) */762#define AR5K_DCU_MISC_SEQNUM_CTL 0x01000000 /* Sequence number control (?) */763#define AR5K_QUEUE_DFS_MISC(_q) AR5K_QUEUE_REG(AR5K_DCU_MISC_BASE, _q)764 765/*766 * DCU frame sequence number registers767 */768#define AR5K_DCU_SEQNUM_BASE 0x1140769#define AR5K_DCU_SEQNUM_M 0x00000fff770#define AR5K_QUEUE_DCU_SEQNUM(_q) AR5K_QUEUE_REG(AR5K_DCU_SEQNUM_BASE, _q)771 772/*773 * DCU global IFS SIFS register774 */775#define AR5K_DCU_GBL_IFS_SIFS 0x1030776#define AR5K_DCU_GBL_IFS_SIFS_M 0x0000ffff777 778/*779 * DCU global IFS slot interval register780 */781#define AR5K_DCU_GBL_IFS_SLOT 0x1070782#define AR5K_DCU_GBL_IFS_SLOT_M 0x0000ffff783 784/*785 * DCU global IFS EIFS register786 */787#define AR5K_DCU_GBL_IFS_EIFS 0x10b0788#define AR5K_DCU_GBL_IFS_EIFS_M 0x0000ffff789 790/*791 * DCU global IFS misc register792 *793 * LFSR stands for Linear Feedback Shift Register794 * and it's used for generating pseudo-random795 * number sequences.796 *797 * (If i understand correctly, random numbers are798 * used for idle sensing -multiplied with cwmin/max etc-)799 */800#define AR5K_DCU_GBL_IFS_MISC 0x10f0 /* Register Address */801#define AR5K_DCU_GBL_IFS_MISC_LFSR_SLICE 0x00000007 /* LFSR Slice Select */802#define AR5K_DCU_GBL_IFS_MISC_TURBO_MODE 0x00000008 /* Turbo mode */803#define AR5K_DCU_GBL_IFS_MISC_SIFS_DUR_USEC 0x000003f0 /* SIFS Duration mask */804#define AR5K_DCU_GBL_IFS_MISC_SIFS_DUR_USEC_S 4805#define AR5K_DCU_GBL_IFS_MISC_USEC_DUR 0x000ffc00 /* USEC Duration mask */806#define AR5K_DCU_GBL_IFS_MISC_USEC_DUR_S 10807#define AR5K_DCU_GBL_IFS_MISC_DCU_ARB_DELAY 0x00300000 /* DCU Arbiter delay mask */808#define AR5K_DCU_GBL_IFS_MISC_SIFS_CNT_RST 0x00400000 /* SIFS cnt reset policy (?) */809#define AR5K_DCU_GBL_IFS_MISC_AIFS_CNT_RST 0x00800000 /* AIFS cnt reset policy (?) */810#define AR5K_DCU_GBL_IFS_MISC_RND_LFSR_SL_DIS 0x01000000 /* Disable random LFSR slice */811 812/*813 * DCU frame prefetch control register814 */815#define AR5K_DCU_FP 0x1230 /* Register Address */816#define AR5K_DCU_FP_NOBURST_DCU_EN 0x00000001 /* Enable non-burst prefetch on DCU (?) */817#define AR5K_DCU_FP_NOBURST_EN 0x00000010 /* Enable non-burst prefetch (?) */818#define AR5K_DCU_FP_BURST_DCU_EN 0x00000020 /* Enable burst prefetch on DCU (?) */819 820/*821 * DCU transmit pause control/status register822 */823#define AR5K_DCU_TXP 0x1270 /* Register Address */824#define AR5K_DCU_TXP_M 0x000003ff /* Tx pause mask */825#define AR5K_DCU_TXP_STATUS 0x00010000 /* Tx pause status */826 827/*828 * DCU transmit filter table 0 (32 entries)829 * each entry contains a 32bit slice of the830 * 128bit tx filter for each DCU (4 slices per DCU)831 */832#define AR5K_DCU_TX_FILTER_0_BASE 0x1038833#define AR5K_DCU_TX_FILTER_0(_n) (AR5K_DCU_TX_FILTER_0_BASE + (_n * 64))834 835/*836 * DCU transmit filter table 1 (16 entries)837 */838#define AR5K_DCU_TX_FILTER_1_BASE 0x103c839#define AR5K_DCU_TX_FILTER_1(_n) (AR5K_DCU_TX_FILTER_1_BASE + (_n * 64))840 841/*842 * DCU clear transmit filter register843 */844#define AR5K_DCU_TX_FILTER_CLR 0x143c845 846/*847 * DCU set transmit filter register848 */849#define AR5K_DCU_TX_FILTER_SET 0x147c850 851/*852 * Reset control register853 */854#define AR5K_RESET_CTL 0x4000 /* Register Address */855#define AR5K_RESET_CTL_PCU 0x00000001 /* Protocol Control Unit reset */856#define AR5K_RESET_CTL_DMA 0x00000002 /* DMA (Rx/Tx) reset [5210] */857#define AR5K_RESET_CTL_BASEBAND 0x00000002 /* Baseband reset [5211+] */858#define AR5K_RESET_CTL_MAC 0x00000004 /* MAC reset (PCU+Baseband ?) [5210] */859#define AR5K_RESET_CTL_PHY 0x00000008 /* PHY reset [5210] */860#define AR5K_RESET_CTL_PCI 0x00000010 /* PCI Core reset (interrupts etc) */861 862/*863 * Sleep control register864 */865#define AR5K_SLEEP_CTL 0x4004 /* Register Address */866#define AR5K_SLEEP_CTL_SLDUR 0x0000ffff /* Sleep duration mask */867#define AR5K_SLEEP_CTL_SLDUR_S 0868#define AR5K_SLEEP_CTL_SLE 0x00030000 /* Sleep enable mask */869#define AR5K_SLEEP_CTL_SLE_S 16870#define AR5K_SLEEP_CTL_SLE_WAKE 0x00000000 /* Force chip awake */871#define AR5K_SLEEP_CTL_SLE_SLP 0x00010000 /* Force chip sleep */872#define AR5K_SLEEP_CTL_SLE_ALLOW 0x00020000 /* Normal sleep policy */873#define AR5K_SLEEP_CTL_SLE_UNITS 0x00000008 /* [5211+] */874#define AR5K_SLEEP_CTL_DUR_TIM_POL 0x00040000 /* Sleep duration timing policy */875#define AR5K_SLEEP_CTL_DUR_WRITE_POL 0x00080000 /* Sleep duration write policy */876#define AR5K_SLEEP_CTL_SLE_POL 0x00100000 /* Sleep policy mode */877 878/*879 * Interrupt pending register880 */881#define AR5K_INTPEND 0x4008882#define AR5K_INTPEND_M 0x00000001883 884/*885 * Sleep force register886 */887#define AR5K_SFR 0x400c888#define AR5K_SFR_EN 0x00000001889 890/*891 * PCI configuration register892 * TODO: Fix LED stuff893 */894#define AR5K_PCICFG 0x4010 /* Register Address */895#define AR5K_PCICFG_EEAE 0x00000001 /* Eeprom access enable [5210] */896#define AR5K_PCICFG_SLEEP_CLOCK_EN 0x00000002 /* Enable sleep clock */897#define AR5K_PCICFG_CLKRUNEN 0x00000004 /* CLKRUN enable [5211+] */898#define AR5K_PCICFG_EESIZE 0x00000018 /* Mask for EEPROM size [5211+] */899#define AR5K_PCICFG_EESIZE_S 3900#define AR5K_PCICFG_EESIZE_4K 0 /* 4K */901#define AR5K_PCICFG_EESIZE_8K 1 /* 8K */902#define AR5K_PCICFG_EESIZE_16K 2 /* 16K */903#define AR5K_PCICFG_EESIZE_FAIL 3 /* Failed to get size [5211+] */904#define AR5K_PCICFG_LED 0x00000060 /* Led status [5211+] */905#define AR5K_PCICFG_LED_NONE 0x00000000 /* Default [5211+] */906#define AR5K_PCICFG_LED_PEND 0x00000020 /* Scan / Auth pending */907#define AR5K_PCICFG_LED_ASSOC 0x00000040 /* Associated */908#define AR5K_PCICFG_BUS_SEL 0x00000380 /* Mask for "bus select" [5211+] (?) */909#define AR5K_PCICFG_CBEFIX_DIS 0x00000400 /* Disable CBE fix */910#define AR5K_PCICFG_SL_INTEN 0x00000800 /* Enable interrupts when asleep */911#define AR5K_PCICFG_LED_BCTL 0x00001000 /* Led blink (?) [5210] */912#define AR5K_PCICFG_RETRY_FIX 0x00001000 /* Enable pci core retry fix */913#define AR5K_PCICFG_SL_INPEN 0x00002000 /* Sleep even with pending interrupts*/914#define AR5K_PCICFG_SPWR_DN 0x00010000 /* Mask for power status */915#define AR5K_PCICFG_LEDMODE 0x000e0000 /* Ledmode [5211+] */916#define AR5K_PCICFG_LEDMODE_PROP 0x00000000 /* Blink on standard traffic [5211+] */917#define AR5K_PCICFG_LEDMODE_PROM 0x00020000 /* Default mode (blink on any traffic) [5211+] */918#define AR5K_PCICFG_LEDMODE_PWR 0x00040000 /* Some other blinking mode (?) [5211+] */919#define AR5K_PCICFG_LEDMODE_RAND 0x00060000 /* Random blinking (?) [5211+] */920#define AR5K_PCICFG_LEDBLINK 0x00700000 /* Led blink rate */921#define AR5K_PCICFG_LEDBLINK_S 20922#define AR5K_PCICFG_LEDSLOW 0x00800000 /* Slowest led blink rate [5211+] */923#define AR5K_PCICFG_LEDSTATE \924 (AR5K_PCICFG_LED | AR5K_PCICFG_LEDMODE | \925 AR5K_PCICFG_LEDBLINK | AR5K_PCICFG_LEDSLOW)926#define AR5K_PCICFG_SLEEP_CLOCK_RATE 0x03000000 /* Sleep clock rate */927#define AR5K_PCICFG_SLEEP_CLOCK_RATE_S 24928 929/*930 * "General Purpose Input/Output" (GPIO) control register931 *932 * I'm not sure about this but after looking at the code933 * for all chipsets here is what i got.934 *935 * We have 6 GPIOs (pins), each GPIO has 4 modes (2 bits)936 * Mode 0 -> always input937 * Mode 1 -> output when GPIODO for this GPIO is set to 0938 * Mode 2 -> output when GPIODO for this GPIO is set to 1939 * Mode 3 -> always output940 *941 * For more infos check out get_gpio/set_gpio and942 * set_gpio_input/set_gpio_output functs.943 * For more infos on gpio interrupt check out set_gpio_intr.944 */945#define AR5K_NUM_GPIO 6946 947#define AR5K_GPIOCR 0x4014 /* Register Address */948#define AR5K_GPIOCR_INT_ENA 0x00008000 /* Enable GPIO interrupt */949#define AR5K_GPIOCR_INT_SELL 0x00000000 /* Generate interrupt when pin is low */950#define AR5K_GPIOCR_INT_SELH 0x00010000 /* Generate interrupt when pin is high */951#define AR5K_GPIOCR_IN(n) (0 << ((n) * 2)) /* Mode 0 for pin n */952#define AR5K_GPIOCR_OUT0(n) (1 << ((n) * 2)) /* Mode 1 for pin n */953#define AR5K_GPIOCR_OUT1(n) (2 << ((n) * 2)) /* Mode 2 for pin n */954#define AR5K_GPIOCR_OUT(n) (3 << ((n) * 2)) /* Mode 3 for pin n */955#define AR5K_GPIOCR_INT_SEL(n) ((n) << 12) /* Interrupt for GPIO pin n */956 957/*958 * "General Purpose Input/Output" (GPIO) data output register959 */960#define AR5K_GPIODO 0x4018961 962/*963 * "General Purpose Input/Output" (GPIO) data input register964 */965#define AR5K_GPIODI 0x401c966#define AR5K_GPIODI_M 0x0000002f967 968/*969 * Silicon revision register970 */971#define AR5K_SREV 0x4020 /* Register Address */972#define AR5K_SREV_REV 0x0000000f /* Mask for revision */973#define AR5K_SREV_REV_S 0974#define AR5K_SREV_VER 0x000000ff /* Mask for version */975#define AR5K_SREV_VER_S 4976 977/*978 * TXE write posting register979 */980#define AR5K_TXEPOST 0x4028981 982/*983 * QCU sleep mask984 */985#define AR5K_QCU_SLEEP_MASK 0x402c986 987/* 0x4068 is compression buffer configuration988 * register on 5414 and pm configuration register989 * on 5424 and newer pci-e chips. */990 991/*992 * Compression buffer configuration993 * register (enable/disable) [5414]994 */995#define AR5K_5414_CBCFG 0x4068996#define AR5K_5414_CBCFG_BUF_DIS 0x10 /* Disable buffer */997 998/*999 * PCI-E Power management configuration1000 * and status register [5424+]1001 */1002#define AR5K_PCIE_PM_CTL 0x4068 /* Register address */1003/* Only 5424 */1004#define AR5K_PCIE_PM_CTL_L1_WHEN_D2 0x00000001 /* enable PCIe core enter L11005 when d2_sleep_en is asserted */1006#define AR5K_PCIE_PM_CTL_L0_L0S_CLEAR 0x00000002 /* Clear L0 and L0S counters */1007#define AR5K_PCIE_PM_CTL_L0_L0S_EN 0x00000004 /* Start L0 nd L0S counters */1008#define AR5K_PCIE_PM_CTL_LDRESET_EN 0x00000008 /* Enable reset when link goes1009 down */1010/* Wake On Wireless */1011#define AR5K_PCIE_PM_CTL_PME_EN 0x00000010 /* PME Enable */1012#define AR5K_PCIE_PM_CTL_AUX_PWR_DET 0x00000020 /* Aux power detect */1013#define AR5K_PCIE_PM_CTL_PME_CLEAR 0x00000040 /* Clear PME */1014#define AR5K_PCIE_PM_CTL_PSM_D0 0x000000801015#define AR5K_PCIE_PM_CTL_PSM_D1 0x000001001016#define AR5K_PCIE_PM_CTL_PSM_D2 0x000002001017#define AR5K_PCIE_PM_CTL_PSM_D3 0x000004001018 1019/*1020 * PCI-E Workaround enable register1021 */1022#define AR5K_PCIE_WAEN 0x407c1023 1024/*1025 * PCI-E Serializer/Deserializer1026 * registers1027 */1028#define AR5K_PCIE_SERDES 0x40801029#define AR5K_PCIE_SERDES_RESET 0x40841030 1031/*====EEPROM REGISTERS====*/1032 1033/*1034 * EEPROM access registers1035 *1036 * Here we got a difference between 5210/5211-121037 * read data register for 5210 is at 0x6800 and1038 * status register is at 0x6c00. There is also1039 * no eeprom command register on 5210 and the1040 * offsets are different.1041 *1042 * To read eeprom data for a specific offset:1043 * 5210 - enable eeprom access (AR5K_PCICFG_EEAE)1044 * read AR5K_EEPROM_BASE +(4 * offset)1045 * check the eeprom status register1046 * and read eeprom data register.1047 *1048 * 5211 - write offset to AR5K_EEPROM_BASE1049 * 5212 write AR5K_EEPROM_CMD_READ on AR5K_EEPROM_CMD1050 * check the eeprom status register1051 * and read eeprom data register.1052 *1053 * To write eeprom data for a specific offset:1054 * 5210 - enable eeprom access (AR5K_PCICFG_EEAE)1055 * write data to AR5K_EEPROM_BASE +(4 * offset)1056 * check the eeprom status register1057 * 5211 - write AR5K_EEPROM_CMD_RESET on AR5K_EEPROM_CMD1058 * 5212 write offset to AR5K_EEPROM_BASE1059 * write data to data register1060 * write AR5K_EEPROM_CMD_WRITE on AR5K_EEPROM_CMD1061 * check the eeprom status register1062 *1063 * For more infos check eeprom_* functs and the ar5k.c1064 * file posted in madwifi-devel mailing list.1065 * http://sourceforge.net/mailarchive/message.php?msg_id=89665251066 *1067 */1068#define AR5K_EEPROM_BASE 0x60001069 1070/*1071 * EEPROM data register1072 */1073#define AR5K_EEPROM_DATA_5211 0x60041074#define AR5K_EEPROM_DATA_5210 0x68001075#define AR5K_EEPROM_DATA (ah->ah_version == AR5K_AR5210 ? \1076 AR5K_EEPROM_DATA_5210 : AR5K_EEPROM_DATA_5211)1077 1078/*1079 * EEPROM command register1080 */1081#define AR5K_EEPROM_CMD 0x6008 /* Register Address */1082#define AR5K_EEPROM_CMD_READ 0x00000001 /* EEPROM read */1083#define AR5K_EEPROM_CMD_WRITE 0x00000002 /* EEPROM write */1084#define AR5K_EEPROM_CMD_RESET 0x00000004 /* EEPROM reset */1085 1086/*1087 * EEPROM status register1088 */1089#define AR5K_EEPROM_STAT_5210 0x6c00 /* Register Address [5210] */1090#define AR5K_EEPROM_STAT_5211 0x600c /* Register Address [5211+] */1091#define AR5K_EEPROM_STATUS (ah->ah_version == AR5K_AR5210 ? \1092 AR5K_EEPROM_STAT_5210 : AR5K_EEPROM_STAT_5211)1093#define AR5K_EEPROM_STAT_RDERR 0x00000001 /* EEPROM read failed */1094#define AR5K_EEPROM_STAT_RDDONE 0x00000002 /* EEPROM read successful */1095#define AR5K_EEPROM_STAT_WRERR 0x00000004 /* EEPROM write failed */1096#define AR5K_EEPROM_STAT_WRDONE 0x00000008 /* EEPROM write successful */1097 1098/*1099 * EEPROM config register1100 */1101#define AR5K_EEPROM_CFG 0x6010 /* Register Address */1102#define AR5K_EEPROM_CFG_SIZE 0x00000003 /* Size determination override */1103#define AR5K_EEPROM_CFG_SIZE_AUTO 01104#define AR5K_EEPROM_CFG_SIZE_4KBIT 11105#define AR5K_EEPROM_CFG_SIZE_8KBIT 21106#define AR5K_EEPROM_CFG_SIZE_16KBIT 31107#define AR5K_EEPROM_CFG_WR_WAIT_DIS 0x00000004 /* Disable write wait */1108#define AR5K_EEPROM_CFG_CLK_RATE 0x00000018 /* Clock rate */1109#define AR5K_EEPROM_CFG_CLK_RATE_S 31110#define AR5K_EEPROM_CFG_CLK_RATE_156KHZ 01111#define AR5K_EEPROM_CFG_CLK_RATE_312KHZ 11112#define AR5K_EEPROM_CFG_CLK_RATE_625KHZ 21113#define AR5K_EEPROM_CFG_PROT_KEY 0x00ffff00 /* Protection key */1114#define AR5K_EEPROM_CFG_PROT_KEY_S 81115#define AR5K_EEPROM_CFG_LIND_EN 0x01000000 /* Enable length indicator (?) */1116 1117 1118/*1119 * TODO: Wake On Wireless registers1120 * Range 0x7000 - 0x7ce01121 */1122 1123/*1124 * Protocol Control Unit (PCU) registers1125 */1126/*1127 * Used for checking initial register writes1128 * during channel reset (see reset func)1129 */1130#define AR5K_PCU_MIN 0x80001131#define AR5K_PCU_MAX 0x8fff1132 1133/*1134 * First station id register (Lower 32 bits of MAC address)1135 */1136#define AR5K_STA_ID0 0x80001137#define AR5K_STA_ID0_ARRD_L32 0xffffffff1138 1139/*1140 * Second station id register (Upper 16 bits of MAC address + PCU settings)1141 */1142#define AR5K_STA_ID1 0x8004 /* Register Address */1143#define AR5K_STA_ID1_ADDR_U16 0x0000ffff /* Upper 16 bits of MAC address */1144#define AR5K_STA_ID1_AP 0x00010000 /* Set AP mode */1145#define AR5K_STA_ID1_ADHOC 0x00020000 /* Set Ad-Hoc mode */1146#define AR5K_STA_ID1_PWR_SV 0x00040000 /* Power save reporting */1147#define AR5K_STA_ID1_NO_KEYSRCH 0x00080000 /* No key search */1148#define AR5K_STA_ID1_NO_PSPOLL 0x00100000 /* No power save polling [5210] */1149#define AR5K_STA_ID1_PCF_5211 0x00100000 /* Enable PCF on [5211+] */1150#define AR5K_STA_ID1_PCF_5210 0x00200000 /* Enable PCF on [5210]*/1151#define AR5K_STA_ID1_PCF (ah->ah_version == AR5K_AR5210 ? \1152 AR5K_STA_ID1_PCF_5210 : AR5K_STA_ID1_PCF_5211)1153#define AR5K_STA_ID1_DEFAULT_ANTENNA 0x00200000 /* Use default antenna */1154#define AR5K_STA_ID1_DESC_ANTENNA 0x00400000 /* Update antenna from descriptor */1155#define AR5K_STA_ID1_RTS_DEF_ANTENNA 0x00800000 /* Use default antenna for RTS */1156#define AR5K_STA_ID1_ACKCTS_6MB 0x01000000 /* Rate to use for ACK/CTS. 0: highest mandatory rate <= RX rate; 1: 1Mbps in B mode */1157#define AR5K_STA_ID1_BASE_RATE_11B 0x02000000 /* 802.11b base rate. 0: 1, 2, 5.5 and 11Mbps; 1: 1 and 2Mbps. [5211+] */1158#define AR5K_STA_ID1_SELFGEN_DEF_ANT 0x04000000 /* Use def. antenna for self generated frames */1159#define AR5K_STA_ID1_CRYPT_MIC_EN 0x08000000 /* Enable MIC */1160#define AR5K_STA_ID1_KEYSRCH_MODE 0x10000000 /* Look up key when key id != 0 */1161#define AR5K_STA_ID1_PRESERVE_SEQ_NUM 0x20000000 /* Preserve sequence number */1162#define AR5K_STA_ID1_CBCIV_ENDIAN 0x40000000 /* ??? */1163#define AR5K_STA_ID1_KEYSRCH_MCAST 0x80000000 /* Do key cache search for mcast frames */1164 1165#define AR5K_STA_ID1_ANTENNA_SETTINGS (AR5K_STA_ID1_DEFAULT_ANTENNA | \1166 AR5K_STA_ID1_DESC_ANTENNA | \1167 AR5K_STA_ID1_RTS_DEF_ANTENNA | \1168 AR5K_STA_ID1_SELFGEN_DEF_ANT)1169 1170/*1171 * First BSSID register (MAC address, lower 32bits)1172 */1173#define AR5K_BSS_ID0 0x80081174 1175/*1176 * Second BSSID register (MAC address in upper 16 bits)1177 *1178 * AID: Association ID1179 */1180#define AR5K_BSS_ID1 0x800c1181#define AR5K_BSS_ID1_AID 0xffff00001182#define AR5K_BSS_ID1_AID_S 161183 1184/*1185 * Backoff slot time register1186 */1187#define AR5K_SLOT_TIME 0x80101188 1189/*1190 * ACK/CTS timeout register1191 */1192#define AR5K_TIME_OUT 0x8014 /* Register Address */1193#define AR5K_TIME_OUT_ACK 0x00001fff /* ACK timeout mask */1194#define AR5K_TIME_OUT_ACK_S 01195#define AR5K_TIME_OUT_CTS 0x1fff0000 /* CTS timeout mask */1196#define AR5K_TIME_OUT_CTS_S 161197 1198/*1199 * RSSI threshold register1200 */1201#define AR5K_RSSI_THR 0x8018 /* Register Address */1202#define AR5K_RSSI_THR_M 0x000000ff /* Mask for RSSI threshold [5211+] */1203#define AR5K_RSSI_THR_BMISS_5210 0x00000700 /* Mask for Beacon Missed threshold [5210] */1204#define AR5K_RSSI_THR_BMISS_5210_S 81205#define AR5K_RSSI_THR_BMISS_5211 0x0000ff00 /* Mask for Beacon Missed threshold [5211+] */1206#define AR5K_RSSI_THR_BMISS_5211_S 81207#define AR5K_RSSI_THR_BMISS (ah->ah_version == AR5K_AR5210 ? \1208 AR5K_RSSI_THR_BMISS_5210 : AR5K_RSSI_THR_BMISS_5211)1209#define AR5K_RSSI_THR_BMISS_S 81210 1211/*1212 * 5210 has more PCU registers because there is no QCU/DCU1213 * so queue parameters are set here, this way a lot common1214 * registers have different address for 5210. To make things1215 * easier we define a macro based on ah->ah_version for common1216 * registers with different addresses and common flags.1217 */1218 1219/*1220 * Retry limit register1221 *1222 * Retry limit register for 5210 (no QCU/DCU so it's done in PCU)1223 */1224#define AR5K_NODCU_RETRY_LMT 0x801c /* Register Address */1225#define AR5K_NODCU_RETRY_LMT_SH_RETRY 0x0000000f /* Short retry limit mask */1226#define AR5K_NODCU_RETRY_LMT_SH_RETRY_S 01227#define AR5K_NODCU_RETRY_LMT_LG_RETRY 0x000000f0 /* Long retry mask */1228#define AR5K_NODCU_RETRY_LMT_LG_RETRY_S 41229#define AR5K_NODCU_RETRY_LMT_SSH_RETRY 0x00003f00 /* Station short retry limit mask */1230#define AR5K_NODCU_RETRY_LMT_SSH_RETRY_S 81231#define AR5K_NODCU_RETRY_LMT_SLG_RETRY 0x000fc000 /* Station long retry limit mask */1232#define AR5K_NODCU_RETRY_LMT_SLG_RETRY_S 141233#define AR5K_NODCU_RETRY_LMT_CW_MIN 0x3ff00000 /* Minimum contention window mask */1234#define AR5K_NODCU_RETRY_LMT_CW_MIN_S 201235 1236/*1237 * Transmit latency register1238 */1239#define AR5K_USEC_5210 0x8020 /* Register Address [5210] */1240#define AR5K_USEC_5211 0x801c /* Register Address [5211+] */1241#define AR5K_USEC (ah->ah_version == AR5K_AR5210 ? \1242 AR5K_USEC_5210 : AR5K_USEC_5211)1243#define AR5K_USEC_1 0x0000007f /* clock cycles for 1us */1244#define AR5K_USEC_1_S 01245#define AR5K_USEC_32 0x00003f80 /* clock cycles for 1us while on 32MHz clock */1246#define AR5K_USEC_32_S 71247#define AR5K_USEC_TX_LATENCY_5211 0x007fc0001248#define AR5K_USEC_TX_LATENCY_5211_S 141249#define AR5K_USEC_RX_LATENCY_5211 0x1f8000001250#define AR5K_USEC_RX_LATENCY_5211_S 231251#define AR5K_USEC_TX_LATENCY_5210 0x000fc000 /* also for 5311 */1252#define AR5K_USEC_TX_LATENCY_5210_S 141253#define AR5K_USEC_RX_LATENCY_5210 0x03f00000 /* also for 5311 */1254#define AR5K_USEC_RX_LATENCY_5210_S 201255 1256/*1257 * PCU beacon control register1258 */1259#define AR5K_BEACON_5210 0x8024 /*Register Address [5210] */1260#define AR5K_BEACON_5211 0x8020 /*Register Address [5211+] */1261#define AR5K_BEACON (ah->ah_version == AR5K_AR5210 ? \1262 AR5K_BEACON_5210 : AR5K_BEACON_5211)1263#define AR5K_BEACON_PERIOD 0x0000ffff /* Mask for beacon period */1264#define AR5K_BEACON_PERIOD_S 01265#define AR5K_BEACON_TIM 0x007f0000 /* Mask for TIM offset */1266#define AR5K_BEACON_TIM_S 161267#define AR5K_BEACON_ENABLE 0x00800000 /* Enable beacons */1268#define AR5K_BEACON_RESET_TSF 0x01000000 /* Force TSF reset */1269 1270/*1271 * CFP period register1272 */1273#define AR5K_CFP_PERIOD_5210 0x80281274#define AR5K_CFP_PERIOD_5211 0x80241275#define AR5K_CFP_PERIOD (ah->ah_version == AR5K_AR5210 ? \1276 AR5K_CFP_PERIOD_5210 : AR5K_CFP_PERIOD_5211)1277 1278/*1279 * Next beacon time register1280 */1281#define AR5K_TIMER0_5210 0x802c1282#define AR5K_TIMER0_5211 0x80281283#define AR5K_TIMER0 (ah->ah_version == AR5K_AR5210 ? \1284 AR5K_TIMER0_5210 : AR5K_TIMER0_5211)1285 1286/*1287 * Next DMA beacon alert register1288 */1289#define AR5K_TIMER1_5210 0x80301290#define AR5K_TIMER1_5211 0x802c1291#define AR5K_TIMER1 (ah->ah_version == AR5K_AR5210 ? \1292 AR5K_TIMER1_5210 : AR5K_TIMER1_5211)1293 1294/*1295 * Next software beacon alert register1296 */1297#define AR5K_TIMER2_5210 0x80341298#define AR5K_TIMER2_5211 0x80301299#define AR5K_TIMER2 (ah->ah_version == AR5K_AR5210 ? \1300 AR5K_TIMER2_5210 : AR5K_TIMER2_5211)1301 1302/*1303 * Next ATIM window time register1304 */1305#define AR5K_TIMER3_5210 0x80381306#define AR5K_TIMER3_5211 0x80341307#define AR5K_TIMER3 (ah->ah_version == AR5K_AR5210 ? \1308 AR5K_TIMER3_5210 : AR5K_TIMER3_5211)1309 1310 1311/*1312 * 5210 First inter frame spacing register (IFS)1313 */1314#define AR5K_IFS0 0x80401315#define AR5K_IFS0_SIFS 0x000007ff1316#define AR5K_IFS0_SIFS_S 01317#define AR5K_IFS0_DIFS 0x007ff8001318#define AR5K_IFS0_DIFS_S 111319 1320/*1321 * 5210 Second inter frame spacing register (IFS)1322 */1323#define AR5K_IFS1 0x80441324#define AR5K_IFS1_PIFS 0x00000fff1325#define AR5K_IFS1_PIFS_S 01326#define AR5K_IFS1_EIFS 0x03fff0001327#define AR5K_IFS1_EIFS_S 121328#define AR5K_IFS1_CS_EN 0x040000001329#define AR5K_IFS1_CS_EN_S 261330 1331/*1332 * CFP duration register1333 */1334#define AR5K_CFP_DUR_5210 0x80481335#define AR5K_CFP_DUR_5211 0x80381336#define AR5K_CFP_DUR (ah->ah_version == AR5K_AR5210 ? \1337 AR5K_CFP_DUR_5210 : AR5K_CFP_DUR_5211)1338 1339/*1340 * Receive filter register1341 */1342#define AR5K_RX_FILTER_5210 0x804c /* Register Address [5210] */1343#define AR5K_RX_FILTER_5211 0x803c /* Register Address [5211+] */1344#define AR5K_RX_FILTER (ah->ah_version == AR5K_AR5210 ? \1345 AR5K_RX_FILTER_5210 : AR5K_RX_FILTER_5211)1346#define AR5K_RX_FILTER_UCAST 0x00000001 /* Don't filter unicast frames */1347#define AR5K_RX_FILTER_MCAST 0x00000002 /* Don't filter multicast frames */1348#define AR5K_RX_FILTER_BCAST 0x00000004 /* Don't filter broadcast frames */1349#define AR5K_RX_FILTER_CONTROL 0x00000008 /* Don't filter control frames */1350#define AR5K_RX_FILTER_BEACON 0x00000010 /* Don't filter beacon frames */1351#define AR5K_RX_FILTER_PROM 0x00000020 /* Set promiscuous mode */1352#define AR5K_RX_FILTER_XRPOLL 0x00000040 /* Don't filter XR poll frame [5212+] */1353#define AR5K_RX_FILTER_PROBEREQ 0x00000080 /* Don't filter probe requests [5212+] */1354#define AR5K_RX_FILTER_PHYERR_5212 0x00000100 /* Don't filter phy errors [5212+] */1355#define AR5K_RX_FILTER_RADARERR_5212 0x00000200 /* Don't filter phy radar errors [5212+] */1356#define AR5K_RX_FILTER_PHYERR_5211 0x00000040 /* [5211] */1357#define AR5K_RX_FILTER_RADARERR_5211 0x00000080 /* [5211] */1358#define AR5K_RX_FILTER_PHYERR \1359 ((ah->ah_version == AR5K_AR5211 ? \1360 AR5K_RX_FILTER_PHYERR_5211 : AR5K_RX_FILTER_PHYERR_5212))1361#define AR5K_RX_FILTER_RADARERR \1362 ((ah->ah_version == AR5K_AR5211 ? \1363 AR5K_RX_FILTER_RADARERR_5211 : AR5K_RX_FILTER_RADARERR_5212))1364 1365/*1366 * Multicast filter register (lower 32 bits)1367 */1368#define AR5K_MCAST_FILTER0_5210 0x80501369#define AR5K_MCAST_FILTER0_5211 0x80401370#define AR5K_MCAST_FILTER0 (ah->ah_version == AR5K_AR5210 ? \1371 AR5K_MCAST_FILTER0_5210 : AR5K_MCAST_FILTER0_5211)1372 1373/*1374 * Multicast filter register (higher 16 bits)1375 */1376#define AR5K_MCAST_FILTER1_5210 0x80541377#define AR5K_MCAST_FILTER1_5211 0x80441378#define AR5K_MCAST_FILTER1 (ah->ah_version == AR5K_AR5210 ? \1379 AR5K_MCAST_FILTER1_5210 : AR5K_MCAST_FILTER1_5211)1380 1381 1382/*1383 * Transmit mask register (lower 32 bits) [5210]1384 */1385#define AR5K_TX_MASK0 0x80581386 1387/*1388 * Transmit mask register (higher 16 bits) [5210]1389 */1390#define AR5K_TX_MASK1 0x805c1391 1392/*1393 * Clear transmit mask [5210]1394 */1395#define AR5K_CLR_TMASK 0x80601396 1397/*1398 * Trigger level register (before transmission) [5210]1399 */1400#define AR5K_TRIG_LVL 0x80641401 1402 1403/*1404 * PCU Diagnostic register1405 *1406 * Used for tweaking/diagnostics.1407 */1408#define AR5K_DIAG_SW_5210 0x8068 /* Register Address [5210] */1409#define AR5K_DIAG_SW_5211 0x8048 /* Register Address [5211+] */1410#define AR5K_DIAG_SW (ah->ah_version == AR5K_AR5210 ? \1411 AR5K_DIAG_SW_5210 : AR5K_DIAG_SW_5211)1412#define AR5K_DIAG_SW_DIS_WEP_ACK 0x00000001 /* Disable ACKs if WEP key is invalid */1413#define AR5K_DIAG_SW_DIS_ACK 0x00000002 /* Disable ACKs */1414#define AR5K_DIAG_SW_DIS_CTS 0x00000004 /* Disable CTSs */1415#define AR5K_DIAG_SW_DIS_ENC 0x00000008 /* Disable HW encryption */1416#define AR5K_DIAG_SW_DIS_DEC 0x00000010 /* Disable HW decryption */1417#define AR5K_DIAG_SW_DIS_TX_5210 0x00000020 /* Disable transmit [5210] */1418#define AR5K_DIAG_SW_DIS_RX_5210 0x00000040 /* Disable receive */1419#define AR5K_DIAG_SW_DIS_RX_5211 0x000000201420#define AR5K_DIAG_SW_DIS_RX (ah->ah_version == AR5K_AR5210 ? \1421 AR5K_DIAG_SW_DIS_RX_5210 : AR5K_DIAG_SW_DIS_RX_5211)1422#define AR5K_DIAG_SW_LOOP_BACK_5210 0x00000080 /* TX Data Loopback (i guess it goes with DIS_TX) [5210] */1423#define AR5K_DIAG_SW_LOOP_BACK_5211 0x000000401424#define AR5K_DIAG_SW_LOOP_BACK (ah->ah_version == AR5K_AR5210 ? \1425 AR5K_DIAG_SW_LOOP_BACK_5210 : AR5K_DIAG_SW_LOOP_BACK_5211)1426#define AR5K_DIAG_SW_CORR_FCS_5210 0x00000100 /* Generate invalid TX FCS */1427#define AR5K_DIAG_SW_CORR_FCS_5211 0x000000801428#define AR5K_DIAG_SW_CORR_FCS (ah->ah_version == AR5K_AR5210 ? \1429 AR5K_DIAG_SW_CORR_FCS_5210 : AR5K_DIAG_SW_CORR_FCS_5211)1430#define AR5K_DIAG_SW_CHAN_INFO_5210 0x00000200 /* Add 56 bytes of channel info before the frame data in the RX buffer */1431#define AR5K_DIAG_SW_CHAN_INFO_5211 0x000001001432#define AR5K_DIAG_SW_CHAN_INFO (ah->ah_version == AR5K_AR5210 ? \1433 AR5K_DIAG_SW_CHAN_INFO_5210 : AR5K_DIAG_SW_CHAN_INFO_5211)1434#define AR5K_DIAG_SW_EN_SCRAM_SEED_5210 0x00000400 /* Enable fixed scrambler seed */1435#define AR5K_DIAG_SW_EN_SCRAM_SEED_5211 0x000002001436#define AR5K_DIAG_SW_EN_SCRAM_SEED (ah->ah_version == AR5K_AR5210 ? \1437 AR5K_DIAG_SW_EN_SCRAM_SEED_5210 : AR5K_DIAG_SW_EN_SCRAM_SEED_5211)1438#define AR5K_DIAG_SW_ECO_ENABLE 0x00000400 /* [5211+] */1439#define AR5K_DIAG_SW_SCVRAM_SEED 0x0003f800 /* [5210] */1440#define AR5K_DIAG_SW_SCRAM_SEED_M 0x0001fc00 /* Scrambler seed mask */1441#define AR5K_DIAG_SW_SCRAM_SEED_S 101442#define AR5K_DIAG_SW_DIS_SEQ_INC_5210 0x00040000 /* Disable seqnum increment (?)[5210] */1443#define AR5K_DIAG_SW_FRAME_NV0_5210 0x000800001444#define AR5K_DIAG_SW_FRAME_NV0_5211 0x00020000 /* Accept frames of non-zero protocol number */1445#define AR5K_DIAG_SW_FRAME_NV0 (ah->ah_version == AR5K_AR5210 ? \1446 AR5K_DIAG_SW_FRAME_NV0_5210 : AR5K_DIAG_SW_FRAME_NV0_5211)1447#define AR5K_DIAG_SW_OBSPT_M 0x000c0000 /* Observation point select (?) */1448#define AR5K_DIAG_SW_OBSPT_S 181449#define AR5K_DIAG_SW_RX_CLEAR_HIGH 0x00100000 /* Ignore carrier sense */1450#define AR5K_DIAG_SW_IGNORE_CARR_SENSE 0x00200000 /* Ignore virtual carrier sense */1451#define AR5K_DIAG_SW_CHANNEL_IDLE_HIGH 0x00400000 /* Force channel idle high */1452#define AR5K_DIAG_SW_PHEAR_ME 0x00800000 /* ??? */1453 1454/*1455 * TSF (clock) register (lower 32 bits)1456 */1457#define AR5K_TSF_L32_5210 0x806c1458#define AR5K_TSF_L32_5211 0x804c1459#define AR5K_TSF_L32 (ah->ah_version == AR5K_AR5210 ? \1460 AR5K_TSF_L32_5210 : AR5K_TSF_L32_5211)1461 1462/*1463 * TSF (clock) register (higher 32 bits)1464 */1465#define AR5K_TSF_U32_5210 0x80701466#define AR5K_TSF_U32_5211 0x80501467#define AR5K_TSF_U32 (ah->ah_version == AR5K_AR5210 ? \1468 AR5K_TSF_U32_5210 : AR5K_TSF_U32_5211)1469 1470/*1471 * Last beacon timestamp register (Read Only)1472 */1473#define AR5K_LAST_TSTP 0x80801474 1475/*1476 * ADDAC test register [5211+]1477 */1478#define AR5K_ADDAC_TEST 0x8054 /* Register Address */1479#define AR5K_ADDAC_TEST_TXCONT 0x00000001 /* Test continuous tx */1480#define AR5K_ADDAC_TEST_TST_MODE 0x00000002 /* Test mode */1481#define AR5K_ADDAC_TEST_LOOP_EN 0x00000004 /* Enable loop */1482#define AR5K_ADDAC_TEST_LOOP_LEN 0x00000008 /* Loop length (field) */1483#define AR5K_ADDAC_TEST_USE_U8 0x00004000 /* Use upper 8 bits */1484#define AR5K_ADDAC_TEST_MSB 0x00008000 /* State of MSB */1485#define AR5K_ADDAC_TEST_TRIG_SEL 0x00010000 /* Trigger select */1486#define AR5K_ADDAC_TEST_TRIG_PTY 0x00020000 /* Trigger polarity */1487#define AR5K_ADDAC_TEST_RXCONT 0x00040000 /* Continuous capture */1488#define AR5K_ADDAC_TEST_CAPTURE 0x00080000 /* Begin capture */1489#define AR5K_ADDAC_TEST_TST_ARM 0x00100000 /* ARM rx buffer for capture */1490 1491/*1492 * Default antenna register [5211+]1493 */1494#define AR5K_DEFAULT_ANTENNA 0x80581495 1496/*1497 * Frame control QoS mask register (?) [5211+]1498 * (FC_QOS_MASK)1499 */1500#define AR5K_FRAME_CTL_QOSM 0x805c1501 1502/*1503 * Seq mask register (?) [5211+]1504 */1505#define AR5K_SEQ_MASK 0x80601506 1507/*1508 * Retry count register [5210]1509 */1510#define AR5K_RETRY_CNT 0x8084 /* Register Address [5210] */1511#define AR5K_RETRY_CNT_SSH 0x0000003f /* Station short retry count (?) */1512#define AR5K_RETRY_CNT_SLG 0x00000fc0 /* Station long retry count (?) */1513 1514/*1515 * Back-off status register [5210]1516 */1517#define AR5K_BACKOFF 0x8088 /* Register Address [5210] */1518#define AR5K_BACKOFF_CW 0x000003ff /* Backoff Contention Window (?) */1519#define AR5K_BACKOFF_CNT 0x03ff0000 /* Backoff count (?) */1520 1521 1522 1523/*1524 * NAV register (current)1525 */1526#define AR5K_NAV_5210 0x808c1527#define AR5K_NAV_5211 0x80841528#define AR5K_NAV (ah->ah_version == AR5K_AR5210 ? \1529 AR5K_NAV_5210 : AR5K_NAV_5211)1530 1531/*1532 * MIB counters:1533 *1534 * max value is 0xc000, if this is reached we get a MIB interrupt.1535 * they can be controlled via AR5K_MIBC and are cleared on read.1536 */1537 1538/*1539 * RTS success (MIB counter)1540 */1541#define AR5K_RTS_OK_5210 0x80901542#define AR5K_RTS_OK_5211 0x80881543#define AR5K_RTS_OK (ah->ah_version == AR5K_AR5210 ? \1544 AR5K_RTS_OK_5210 : AR5K_RTS_OK_5211)1545 1546/*1547 * RTS failure (MIB counter)1548 */1549#define AR5K_RTS_FAIL_5210 0x80941550#define AR5K_RTS_FAIL_5211 0x808c1551#define AR5K_RTS_FAIL (ah->ah_version == AR5K_AR5210 ? \1552 AR5K_RTS_FAIL_5210 : AR5K_RTS_FAIL_5211)1553 1554/*1555 * ACK failure (MIB counter)1556 */1557#define AR5K_ACK_FAIL_5210 0x80981558#define AR5K_ACK_FAIL_5211 0x80901559#define AR5K_ACK_FAIL (ah->ah_version == AR5K_AR5210 ? \1560 AR5K_ACK_FAIL_5210 : AR5K_ACK_FAIL_5211)1561 1562/*1563 * FCS failure (MIB counter)1564 */1565#define AR5K_FCS_FAIL_5210 0x809c1566#define AR5K_FCS_FAIL_5211 0x80941567#define AR5K_FCS_FAIL (ah->ah_version == AR5K_AR5210 ? \1568 AR5K_FCS_FAIL_5210 : AR5K_FCS_FAIL_5211)1569 1570/*1571 * Beacon count register1572 */1573#define AR5K_BEACON_CNT_5210 0x80a01574#define AR5K_BEACON_CNT_5211 0x80981575#define AR5K_BEACON_CNT (ah->ah_version == AR5K_AR5210 ? \1576 AR5K_BEACON_CNT_5210 : AR5K_BEACON_CNT_5211)1577 1578 1579/*===5212 Specific PCU registers===*/1580 1581/*1582 * Transmit power control register1583 */1584#define AR5K_TPC 0x80e81585#define AR5K_TPC_ACK 0x0000003f /* ack frames */1586#define AR5K_TPC_ACK_S 01587#define AR5K_TPC_CTS 0x00003f00 /* cts frames */1588#define AR5K_TPC_CTS_S 81589#define AR5K_TPC_CHIRP 0x003f0000 /* chirp frames */1590#define AR5K_TPC_CHIRP_S 161591#define AR5K_TPC_DOPPLER 0x0f000000 /* doppler chirp span */1592#define AR5K_TPC_DOPPLER_S 241593 1594/*1595 * XR (eXtended Range) mode register1596 */1597#define AR5K_XRMODE 0x80c0 /* Register Address */1598#define AR5K_XRMODE_POLL_TYPE_M 0x0000003f /* Mask for Poll type (?) */1599#define AR5K_XRMODE_POLL_TYPE_S 01600#define AR5K_XRMODE_POLL_SUBTYPE_M 0x0000003c /* Mask for Poll subtype (?) */1601#define AR5K_XRMODE_POLL_SUBTYPE_S 21602#define AR5K_XRMODE_POLL_WAIT_ALL 0x00000080 /* Wait for poll */1603#define AR5K_XRMODE_SIFS_DELAY 0x000fff00 /* Mask for SIFS delay */1604#define AR5K_XRMODE_FRAME_HOLD_M 0xfff00000 /* Mask for frame hold (?) */1605#define AR5K_XRMODE_FRAME_HOLD_S 201606 1607/*1608 * XR delay register1609 */1610#define AR5K_XRDELAY 0x80c4 /* Register Address */1611#define AR5K_XRDELAY_SLOT_DELAY_M 0x0000ffff /* Mask for slot delay */1612#define AR5K_XRDELAY_SLOT_DELAY_S 01613#define AR5K_XRDELAY_CHIRP_DELAY_M 0xffff0000 /* Mask for CHIRP data delay */1614#define AR5K_XRDELAY_CHIRP_DELAY_S 161615 1616/*1617 * XR timeout register1618 */1619#define AR5K_XRTIMEOUT 0x80c8 /* Register Address */1620#define AR5K_XRTIMEOUT_CHIRP_M 0x0000ffff /* Mask for CHIRP timeout */1621#define AR5K_XRTIMEOUT_CHIRP_S 01622#define AR5K_XRTIMEOUT_POLL_M 0xffff0000 /* Mask for Poll timeout */1623#define AR5K_XRTIMEOUT_POLL_S 161624 1625/*1626 * XR chirp register1627 */1628#define AR5K_XRCHIRP 0x80cc /* Register Address */1629#define AR5K_XRCHIRP_SEND 0x00000001 /* Send CHIRP */1630#define AR5K_XRCHIRP_GAP 0xffff0000 /* Mask for CHIRP gap (?) */1631 1632/*1633 * XR stomp register1634 */1635#define AR5K_XRSTOMP 0x80d0 /* Register Address */1636#define AR5K_XRSTOMP_TX 0x00000001 /* Stomp Tx (?) */1637#define AR5K_XRSTOMP_RX 0x00000002 /* Stomp Rx (?) */1638#define AR5K_XRSTOMP_TX_RSSI 0x00000004 /* Stomp Tx RSSI (?) */1639#define AR5K_XRSTOMP_TX_BSSID 0x00000008 /* Stomp Tx BSSID (?) */1640#define AR5K_XRSTOMP_DATA 0x00000010 /* Stomp data (?)*/1641#define AR5K_XRSTOMP_RSSI_THRES 0x0000ff00 /* Mask for XR RSSI threshold */1642 1643/*1644 * First enhanced sleep register1645 */1646#define AR5K_SLEEP0 0x80d4 /* Register Address */1647#define AR5K_SLEEP0_NEXT_DTIM 0x0007ffff /* Mask for next DTIM (?) */1648#define AR5K_SLEEP0_NEXT_DTIM_S 01649#define AR5K_SLEEP0_ASSUME_DTIM 0x00080000 /* Assume DTIM */1650#define AR5K_SLEEP0_ENH_SLEEP_EN 0x00100000 /* Enable enhanced sleep control */1651#define AR5K_SLEEP0_CABTO 0xff000000 /* Mask for CAB Time Out */1652#define AR5K_SLEEP0_CABTO_S 241653 1654/*1655 * Second enhanced sleep register1656 */1657#define AR5K_SLEEP1 0x80d8 /* Register Address */1658#define AR5K_SLEEP1_NEXT_TIM 0x0007ffff /* Mask for next TIM (?) */1659#define AR5K_SLEEP1_NEXT_TIM_S 01660#define AR5K_SLEEP1_BEACON_TO 0xff000000 /* Mask for Beacon Time Out */1661#define AR5K_SLEEP1_BEACON_TO_S 241662 1663/*1664 * Third enhanced sleep register1665 */1666#define AR5K_SLEEP2 0x80dc /* Register Address */1667#define AR5K_SLEEP2_TIM_PER 0x0000ffff /* Mask for TIM period (?) */1668#define AR5K_SLEEP2_TIM_PER_S 01669#define AR5K_SLEEP2_DTIM_PER 0xffff0000 /* Mask for DTIM period (?) */1670#define AR5K_SLEEP2_DTIM_PER_S 161671 1672/*1673 * TX power control (TPC) register1674 *1675 * XXX: PCDAC steps (0.5dBm) or dBm ?1676 *1677 */1678#define AR5K_TXPC 0x80e8 /* Register Address */1679#define AR5K_TXPC_ACK_M 0x0000003f /* ACK tx power */1680#define AR5K_TXPC_ACK_S 01681#define AR5K_TXPC_CTS_M 0x00003f00 /* CTS tx power */1682#define AR5K_TXPC_CTS_S 81683#define AR5K_TXPC_CHIRP_M 0x003f0000 /* CHIRP tx power */1684#define AR5K_TXPC_CHIRP_S 161685#define AR5K_TXPC_DOPPLER 0x0f000000 /* Doppler chirp span (?) */1686#define AR5K_TXPC_DOPPLER_S 241687 1688/*1689 * Profile count registers1690 *1691 * These registers can be cleared and frozen with ATH5K_MIBC, but they do not1692 * generate a MIB interrupt.1693 * Instead of overflowing, they shift by one bit to the right. All registers1694 * shift together, i.e. when one reaches the max, all shift at the same time by1695 * one bit to the right. This way we should always get consistent values.1696 */1697#define AR5K_PROFCNT_TX 0x80ec /* Tx count */1698#define AR5K_PROFCNT_RX 0x80f0 /* Rx count */1699#define AR5K_PROFCNT_RXCLR 0x80f4 /* Busy count */1700#define AR5K_PROFCNT_CYCLE 0x80f8 /* Cycle counter */1701 1702/*1703 * Quiet period control registers1704 */1705#define AR5K_QUIET_CTL1 0x80fc /* Register Address */1706#define AR5K_QUIET_CTL1_NEXT_QT_TSF 0x0000ffff /* Next quiet period TSF (TU) */1707#define AR5K_QUIET_CTL1_NEXT_QT_TSF_S 01708#define AR5K_QUIET_CTL1_QT_EN 0x00010000 /* Enable quiet period */1709#define AR5K_QUIET_CTL1_ACK_CTS_EN 0x00020000 /* Send ACK/CTS during quiet period */1710 1711#define AR5K_QUIET_CTL2 0x8100 /* Register Address */1712#define AR5K_QUIET_CTL2_QT_PER 0x0000ffff /* Mask for quiet period periodicity */1713#define AR5K_QUIET_CTL2_QT_PER_S 01714#define AR5K_QUIET_CTL2_QT_DUR 0xffff0000 /* Mask for quiet period duration */1715#define AR5K_QUIET_CTL2_QT_DUR_S 161716 1717/*1718 * TSF parameter register1719 */1720#define AR5K_TSF_PARM 0x8104 /* Register Address */1721#define AR5K_TSF_PARM_INC 0x000000ff /* Mask for TSF increment */1722#define AR5K_TSF_PARM_INC_S 01723 1724/*1725 * QoS NOACK policy1726 */1727#define AR5K_QOS_NOACK 0x8108 /* Register Address */1728#define AR5K_QOS_NOACK_2BIT_VALUES 0x0000000f /* ??? */1729#define AR5K_QOS_NOACK_2BIT_VALUES_S 01730#define AR5K_QOS_NOACK_BIT_OFFSET 0x00000070 /* ??? */1731#define AR5K_QOS_NOACK_BIT_OFFSET_S 41732#define AR5K_QOS_NOACK_BYTE_OFFSET 0x00000180 /* ??? */1733#define AR5K_QOS_NOACK_BYTE_OFFSET_S 71734 1735/*1736 * PHY error filter register1737 */1738#define AR5K_PHY_ERR_FIL 0x810c1739#define AR5K_PHY_ERR_FIL_RADAR 0x00000020 /* Radar signal */1740#define AR5K_PHY_ERR_FIL_OFDM 0x00020000 /* OFDM false detect (ANI) */1741#define AR5K_PHY_ERR_FIL_CCK 0x02000000 /* CCK false detect (ANI) */1742 1743/*1744 * XR latency register1745 */1746#define AR5K_XRLAT_TX 0x81101747 1748/*1749 * ACK SIFS register1750 */1751#define AR5K_ACKSIFS 0x8114 /* Register Address */1752#define AR5K_ACKSIFS_INC 0x00000000 /* ACK SIFS Increment (field) */1753 1754/*1755 * MIC QoS control register (?)1756 */1757#define AR5K_MIC_QOS_CTL 0x8118 /* Register Address */1758#define AR5K_MIC_QOS_CTL_OFF(_n) (1 << (_n * 2))1759#define AR5K_MIC_QOS_CTL_MQ_EN 0x00010000 /* Enable MIC QoS */1760 1761/*1762 * MIC QoS select register (?)1763 */1764#define AR5K_MIC_QOS_SEL 0x811c1765#define AR5K_MIC_QOS_SEL_OFF(_n) (1 << (_n * 4))1766 1767/*1768 * Misc mode control register (?)1769 */1770#define AR5K_MISC_MODE 0x8120 /* Register Address */1771#define AR5K_MISC_MODE_FBSSID_MATCH 0x00000001 /* Force BSSID match */1772#define AR5K_MISC_MODE_ACKSIFS_MEM 0x00000002 /* ACK SIFS memory (?) */1773#define AR5K_MISC_MODE_COMBINED_MIC 0x00000004 /* use rx/tx MIC key */1774/* more bits */1775 1776/*1777 * OFDM Filter counter1778 */1779#define AR5K_OFDM_FIL_CNT 0x81241780 1781/*1782 * CCK Filter counter1783 */1784#define AR5K_CCK_FIL_CNT 0x81281785 1786/*1787 * PHY Error Counters (same masks as AR5K_PHY_ERR_FIL)1788 */1789#define AR5K_PHYERR_CNT1 0x812c1790#define AR5K_PHYERR_CNT1_MASK 0x81301791 1792#define AR5K_PHYERR_CNT2 0x81341793#define AR5K_PHYERR_CNT2_MASK 0x81381794 1795/* if the PHY Error Counters reach this maximum, we get MIB interrupts */1796#define ATH5K_PHYERR_CNT_MAX 0x00c000001797 1798/*1799 * TSF Threshold register (?)1800 */1801#define AR5K_TSF_THRES 0x813c1802 1803/*1804 * TODO: Wake On Wireless registers1805 * Range: 0x8147 - 0x818c1806 */1807 1808/*1809 * Rate -> ACK SIFS mapping table (32 entries)1810 */1811#define AR5K_RATE_ACKSIFS_BASE 0x8680 /* Register Address */1812#define AR5K_RATE_ACKSIFS(_n) (AR5K_RATE_ACKSIFS_BSE + ((_n) << 2))1813#define AR5K_RATE_ACKSIFS_NORMAL 0x00000001 /* Normal SIFS (field) */1814#define AR5K_RATE_ACKSIFS_TURBO 0x00000400 /* Turbo SIFS (field) */1815 1816/*1817 * Rate -> duration mapping table (32 entries)1818 */1819#define AR5K_RATE_DUR_BASE 0x87001820#define AR5K_RATE_DUR(_n) (AR5K_RATE_DUR_BASE + ((_n) << 2))1821 1822/*1823 * Rate -> db mapping table1824 * (8 entries, each one has 4 8bit fields)1825 */1826#define AR5K_RATE2DB_BASE 0x87c01827#define AR5K_RATE2DB(_n) (AR5K_RATE2DB_BASE + ((_n) << 2))1828 1829/*1830 * db -> Rate mapping table1831 * (8 entries, each one has 4 8bit fields)1832 */1833#define AR5K_DB2RATE_BASE 0x87e01834#define AR5K_DB2RATE(_n) (AR5K_DB2RATE_BASE + ((_n) << 2))1835 1836/*===5212 end===*/1837 1838#define AR5K_KEYTABLE_SIZE_5210 641839#define AR5K_KEYTABLE_SIZE_5211 1281840 1841/*===PHY REGISTERS===*/1842 1843/*1844 * PHY registers start1845 */1846#define AR5K_PHY_BASE 0x98001847#define AR5K_PHY(_n) (AR5K_PHY_BASE + ((_n) << 2))1848 1849/*1850 * TST_2 (Misc config parameters)1851 */1852#define AR5K_PHY_TST2 0x9800 /* Register Address */1853#define AR5K_PHY_TST2_TRIG_SEL 0x00000007 /* Trigger select (?)*/1854#define AR5K_PHY_TST2_TRIG 0x00000010 /* Trigger (?) */1855#define AR5K_PHY_TST2_CBUS_MODE 0x00000060 /* Cardbus mode (?) */1856#define AR5K_PHY_TST2_CLK32 0x00000400 /* CLK_OUT is CLK32 (32kHz external) */1857#define AR5K_PHY_TST2_CHANCOR_DUMP_EN 0x00000800 /* Enable Chancor dump (?) */1858#define AR5K_PHY_TST2_EVEN_CHANCOR_DUMP 0x00001000 /* Even Chancor dump (?) */1859#define AR5K_PHY_TST2_RFSILENT_EN 0x00002000 /* Enable RFSILENT */1860#define AR5K_PHY_TST2_ALT_RFDATA 0x00004000 /* Alternate RFDATA (5-2GHz switch ?) */1861#define AR5K_PHY_TST2_MINI_OBS_EN 0x00008000 /* Enable mini OBS (?) */1862#define AR5K_PHY_TST2_RX2_IS_RX5_INV 0x00010000 /* 2GHz rx path is the 5GHz path inverted (?) */1863#define AR5K_PHY_TST2_SLOW_CLK160 0x00020000 /* Slow CLK160 (?) */1864#define AR5K_PHY_TST2_AGC_OBS_SEL_3 0x00040000 /* AGC OBS Select 3 (?) */1865#define AR5K_PHY_TST2_BBB_OBS_SEL 0x00080000 /* BB OBS Select (field ?) */1866#define AR5K_PHY_TST2_ADC_OBS_SEL 0x00800000 /* ADC OBS Select (field ?) */1867#define AR5K_PHY_TST2_RX_CLR_SEL 0x08000000 /* RX Clear Select (?) */1868#define AR5K_PHY_TST2_FORCE_AGC_CLR 0x10000000 /* Force AGC clear (?) */1869#define AR5K_PHY_SHIFT_2GHZ 0x00004007 /* Used to access 2GHz radios */1870#define AR5K_PHY_SHIFT_5GHZ 0x00000007 /* Used to access 5GHz radios (default) */1871 1872/*1873 * PHY frame control register [5110] /turbo mode register [5111+]1874 *1875 * There is another frame control register for [5111+]1876 * at address 0x9944 (see below) but the 2 first flags1877 * are common here between 5110 frame control register1878 * and [5111+] turbo mode register, so this also works as1879 * a "turbo mode register" for 5110. We treat this one as1880 * a frame control register for 5110 below.1881 */1882#define AR5K_PHY_TURBO 0x9804 /* Register Address */1883#define AR5K_PHY_TURBO_MODE 0x00000001 /* Enable turbo mode */1884#define AR5K_PHY_TURBO_SHORT 0x00000002 /* Set short symbols to turbo mode */1885#define AR5K_PHY_TURBO_MIMO 0x00000004 /* Set turbo for mimo */1886 1887/*1888 * PHY agility command register1889 * (aka TST_1)1890 */1891#define AR5K_PHY_AGC 0x9808 /* Register Address */1892#define AR5K_PHY_TST1 0x98081893#define AR5K_PHY_AGC_DISABLE 0x08000000 /* Disable AGC to A2 (?)*/1894#define AR5K_PHY_TST1_TXHOLD 0x00003800 /* Set tx hold (?) */1895#define AR5K_PHY_TST1_TXSRC_SRC 0x00000002 /* Used with bit 7 (?) */1896#define AR5K_PHY_TST1_TXSRC_SRC_S 11897#define AR5K_PHY_TST1_TXSRC_ALT 0x00000080 /* Set input to tsdac (?) */1898#define AR5K_PHY_TST1_TXSRC_ALT_S 71899 1900 1901/*1902 * PHY timing register 3 [5112+]1903 */1904#define AR5K_PHY_TIMING_3 0x98141905#define AR5K_PHY_TIMING_3_DSC_MAN 0xfffe00001906#define AR5K_PHY_TIMING_3_DSC_MAN_S 171907#define AR5K_PHY_TIMING_3_DSC_EXP 0x0001e0001908#define AR5K_PHY_TIMING_3_DSC_EXP_S 131909 1910/*1911 * PHY chip revision register1912 */1913#define AR5K_PHY_CHIP_ID 0x98181914 1915/*1916 * PHY activation register1917 */1918#define AR5K_PHY_ACT 0x981c /* Register Address */1919#define AR5K_PHY_ACT_ENABLE 0x00000001 /* Activate PHY */1920#define AR5K_PHY_ACT_DISABLE 0x00000002 /* Deactivate PHY */1921 1922/*1923 * PHY RF control registers1924 */1925#define AR5K_PHY_RF_CTL2 0x9824 /* Register Address */1926#define AR5K_PHY_RF_CTL2_TXF2TXD_START 0x0000000f /* TX frame to TX data start */1927#define AR5K_PHY_RF_CTL2_TXF2TXD_START_S 01928 1929#define AR5K_PHY_RF_CTL3 0x9828 /* Register Address */1930#define AR5K_PHY_RF_CTL3_TXE2XLNA_ON 0x0000ff00 /* TX end to XLNA on */1931#define AR5K_PHY_RF_CTL3_TXE2XLNA_ON_S 81932 1933#define AR5K_PHY_ADC_CTL 0x982c1934#define AR5K_PHY_ADC_CTL_INBUFGAIN_OFF 0x000000031935#define AR5K_PHY_ADC_CTL_INBUFGAIN_OFF_S 01936#define AR5K_PHY_ADC_CTL_PWD_DAC_OFF 0x000020001937#define AR5K_PHY_ADC_CTL_PWD_BAND_GAP_OFF 0x000040001938#define AR5K_PHY_ADC_CTL_PWD_ADC_OFF 0x000080001939#define AR5K_PHY_ADC_CTL_INBUFGAIN_ON 0x000300001940#define AR5K_PHY_ADC_CTL_INBUFGAIN_ON_S 161941 1942#define AR5K_PHY_RF_CTL4 0x9834 /* Register Address */1943#define AR5K_PHY_RF_CTL4_TXF2XPA_A_ON 0x00000001 /* TX frame to XPA A on (field) */1944#define AR5K_PHY_RF_CTL4_TXF2XPA_B_ON 0x00000100 /* TX frame to XPA B on (field) */1945#define AR5K_PHY_RF_CTL4_TXE2XPA_A_OFF 0x00010000 /* TX end to XPA A off (field) */1946#define AR5K_PHY_RF_CTL4_TXE2XPA_B_OFF 0x01000000 /* TX end to XPA B off (field) */1947 1948/*1949 * Pre-Amplifier control register1950 * (XPA -> external pre-amplifier)1951 */1952#define AR5K_PHY_PA_CTL 0x9838 /* Register Address */1953#define AR5K_PHY_PA_CTL_XPA_A_HI 0x00000001 /* XPA A high (?) */1954#define AR5K_PHY_PA_CTL_XPA_B_HI 0x00000002 /* XPA B high (?) */1955#define AR5K_PHY_PA_CTL_XPA_A_EN 0x00000004 /* Enable XPA A */1956#define AR5K_PHY_PA_CTL_XPA_B_EN 0x00000008 /* Enable XPA B */1957 1958/*1959 * PHY settling register1960 */1961#define AR5K_PHY_SETTLING 0x9844 /* Register Address */1962#define AR5K_PHY_SETTLING_AGC 0x0000007f /* AGC settling time */1963#define AR5K_PHY_SETTLING_AGC_S 01964#define AR5K_PHY_SETTLING_SWITCH 0x00003f80 /* Switch settling time */1965#define AR5K_PHY_SETTLING_SWITCH_S 71966 1967/*1968 * PHY Gain registers1969 */1970#define AR5K_PHY_GAIN 0x9848 /* Register Address */1971#define AR5K_PHY_GAIN_TXRX_ATTEN 0x0003f000 /* TX-RX Attenuation */1972#define AR5K_PHY_GAIN_TXRX_ATTEN_S 121973#define AR5K_PHY_GAIN_TXRX_RF_MAX 0x007c00001974#define AR5K_PHY_GAIN_TXRX_RF_MAX_S 181975 1976#define AR5K_PHY_GAIN_OFFSET 0x984c /* Register Address */1977#define AR5K_PHY_GAIN_OFFSET_RXTX_FLAG 0x00020000 /* RX-TX flag (?) */1978 1979/*1980 * Desired ADC/PGA size register1981 * (for more infos read ANI patent)1982 */1983#define AR5K_PHY_DESIRED_SIZE 0x9850 /* Register Address */1984#define AR5K_PHY_DESIRED_SIZE_ADC 0x000000ff /* ADC desired size */1985#define AR5K_PHY_DESIRED_SIZE_ADC_S 01986#define AR5K_PHY_DESIRED_SIZE_PGA 0x0000ff00 /* PGA desired size */1987#define AR5K_PHY_DESIRED_SIZE_PGA_S 81988#define AR5K_PHY_DESIRED_SIZE_TOT 0x0ff00000 /* Total desired size */1989#define AR5K_PHY_DESIRED_SIZE_TOT_S 201990 1991/*1992 * PHY signal register1993 * (for more infos read ANI patent)1994 */1995#define AR5K_PHY_SIG 0x9858 /* Register Address */1996#define AR5K_PHY_SIG_FIRSTEP 0x0003f000 /* FIRSTEP */1997#define AR5K_PHY_SIG_FIRSTEP_S 121998#define AR5K_PHY_SIG_FIRPWR 0x03fc0000 /* FIPWR */1999#define AR5K_PHY_SIG_FIRPWR_S 182000 2001/*2002 * PHY coarse agility control register2003 * (for more infos read ANI patent)2004 */2005#define AR5K_PHY_AGCCOARSE 0x985c /* Register Address */2006#define AR5K_PHY_AGCCOARSE_LO 0x00007f80 /* AGC Coarse low */2007#define AR5K_PHY_AGCCOARSE_LO_S 72008#define AR5K_PHY_AGCCOARSE_HI 0x003f8000 /* AGC Coarse high */2009#define AR5K_PHY_AGCCOARSE_HI_S 152010 2011/*2012 * PHY agility control register2013 */2014#define AR5K_PHY_AGCCTL 0x9860 /* Register address */2015#define AR5K_PHY_AGCCTL_CAL 0x00000001 /* Enable PHY calibration */2016#define AR5K_PHY_AGCCTL_NF 0x00000002 /* Enable Noise Floor calibration */2017#define AR5K_PHY_AGCCTL_OFDM_DIV_DIS 0x00000008 /* Disable antenna diversity on OFDM modes */2018#define AR5K_PHY_AGCCTL_NF_EN 0x00008000 /* Enable nf calibration to happen (?) */2019#define AR5K_PHY_AGCTL_FLTR_CAL 0x00010000 /* Allow filter calibration (?) */2020#define AR5K_PHY_AGCCTL_NF_NOUPDATE 0x00020000 /* Don't update nf automatically */2021 2022/*2023 * PHY noise floor status register (CCA = Clear Channel Assessment)2024 */2025#define AR5K_PHY_NF 0x9864 /* Register address */2026#define AR5K_PHY_NF_M 0x000001ff /* Noise floor, written to hardware in 1/2 dBm units */2027#define AR5K_PHY_NF_SVAL(_n) (((_n) & AR5K_PHY_NF_M) | (1 << 9))2028#define AR5K_PHY_NF_THRESH62 0x0007f000 /* Thresh62 -check ANI patent- (field) */2029#define AR5K_PHY_NF_THRESH62_S 122030#define AR5K_PHY_NF_MINCCA_PWR 0x0ff80000 /* Minimum measured noise level, read from hardware in 1 dBm units */2031#define AR5K_PHY_NF_MINCCA_PWR_S 192032 2033/*2034 * PHY ADC saturation register [5110]2035 */2036#define AR5K_PHY_ADCSAT 0x98682037#define AR5K_PHY_ADCSAT_ICNT 0x0001f8002038#define AR5K_PHY_ADCSAT_ICNT_S 112039#define AR5K_PHY_ADCSAT_THR 0x000007e02040#define AR5K_PHY_ADCSAT_THR_S 52041 2042/*2043 * PHY Weak ofdm signal detection threshold registers (ANI) [5212+]2044 */2045 2046/* High thresholds */2047#define AR5K_PHY_WEAK_OFDM_HIGH_THR 0x98682048#define AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_COUNT 0x0000001f2049#define AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_COUNT_S 02050#define AR5K_PHY_WEAK_OFDM_HIGH_THR_M1 0x00fe00002051#define AR5K_PHY_WEAK_OFDM_HIGH_THR_M1_S 172052#define AR5K_PHY_WEAK_OFDM_HIGH_THR_M2 0x7f0000002053#define AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_S 242054 2055/* Low thresholds */2056#define AR5K_PHY_WEAK_OFDM_LOW_THR 0x986c2057#define AR5K_PHY_WEAK_OFDM_LOW_THR_SELFCOR_EN 0x000000012058#define AR5K_PHY_WEAK_OFDM_LOW_THR_M2_COUNT 0x00003f002059#define AR5K_PHY_WEAK_OFDM_LOW_THR_M2_COUNT_S 82060#define AR5K_PHY_WEAK_OFDM_LOW_THR_M1 0x001fc0002061#define AR5K_PHY_WEAK_OFDM_LOW_THR_M1_S 142062#define AR5K_PHY_WEAK_OFDM_LOW_THR_M2 0x0fe000002063#define AR5K_PHY_WEAK_OFDM_LOW_THR_M2_S 212064 2065 2066/*2067 * PHY sleep registers [5112+]2068 */2069#define AR5K_PHY_SCR 0x98702070 2071#define AR5K_PHY_SLMT 0x98742072#define AR5K_PHY_SLMT_32MHZ 0x0000007f2073 2074#define AR5K_PHY_SCAL 0x98782075#define AR5K_PHY_SCAL_32MHZ 0x0000000e2076#define AR5K_PHY_SCAL_32MHZ_5311 0x000000082077#define AR5K_PHY_SCAL_32MHZ_2417 0x0000000a2078#define AR5K_PHY_SCAL_32MHZ_HB63 0x000000322079 2080/*2081 * PHY PLL (Phase Locked Loop) control register2082 */2083#define AR5K_PHY_PLL 0x987c2084#define AR5K_PHY_PLL_20MHZ 0x00000013 /* For half rate (?) */2085/* 40MHz -> 5GHz band */2086#define AR5K_PHY_PLL_40MHZ_5211 0x000000182087#define AR5K_PHY_PLL_40MHZ_5212 0x000000aa2088#define AR5K_PHY_PLL_40MHZ_5413 0x000000042089#define AR5K_PHY_PLL_40MHZ (ah->ah_version == AR5K_AR5211 ? \2090 AR5K_PHY_PLL_40MHZ_5211 : AR5K_PHY_PLL_40MHZ_5212)2091/* 44MHz -> 2.4GHz band */2092#define AR5K_PHY_PLL_44MHZ_5211 0x000000192093#define AR5K_PHY_PLL_44MHZ_5212 0x000000ab2094#define AR5K_PHY_PLL_44MHZ (ah->ah_version == AR5K_AR5211 ? \2095 AR5K_PHY_PLL_44MHZ_5211 : AR5K_PHY_PLL_44MHZ_5212)2096 2097#define AR5K_PHY_PLL_RF5111 0x000000002098#define AR5K_PHY_PLL_RF5112 0x000000402099#define AR5K_PHY_PLL_HALF_RATE 0x000001002100#define AR5K_PHY_PLL_QUARTER_RATE 0x000002002101 2102/*2103 * RF Buffer register2104 *2105 * It's obvious from the code that 0x989c is the buffer register but2106 * for the other special registers that we write to after sending each2107 * packet, i have no idea. So I'll name them BUFFER_CONTROL_X registers2108 * for now. It's interesting that they are also used for some other operations.2109 */2110 2111#define AR5K_RF_BUFFER 0x989c2112#define AR5K_RF_BUFFER_CONTROL_0 0x98c0 /* Channel on 5110 */2113#define AR5K_RF_BUFFER_CONTROL_1 0x98c4 /* Bank 7 on 5112 */2114#define AR5K_RF_BUFFER_CONTROL_2 0x98cc /* Bank 7 on 5111 */2115 2116#define AR5K_RF_BUFFER_CONTROL_3 0x98d0 /* Bank 2 on 5112 */2117 /* Channel set on 5111 */2118 /* Used to read radio revision*/2119 2120#define AR5K_RF_BUFFER_CONTROL_4 0x98d4 /* RF Stage register on 5110 */2121 /* Bank 0,1,2,6 on 5111 */2122 /* Bank 1 on 5112 */2123 /* Used during activation on 5111 */2124 2125#define AR5K_RF_BUFFER_CONTROL_5 0x98d8 /* Bank 3 on 5111 */2126 /* Used during activation on 5111 */2127 /* Channel on 5112 */2128 /* Bank 6 on 5112 */2129 2130#define AR5K_RF_BUFFER_CONTROL_6 0x98dc /* Bank 3 on 5112 */2131 2132/*2133 * PHY RF stage register [5210]2134 */2135#define AR5K_PHY_RFSTG 0x98d42136#define AR5K_PHY_RFSTG_DISABLE 0x000000212137 2138/*2139 * BIN masks (?)2140 */2141#define AR5K_PHY_BIN_MASK_1 0x99002142#define AR5K_PHY_BIN_MASK_2 0x99042143#define AR5K_PHY_BIN_MASK_3 0x99082144 2145#define AR5K_PHY_BIN_MASK_CTL 0x990c2146#define AR5K_PHY_BIN_MASK_CTL_MASK_4 0x00003fff2147#define AR5K_PHY_BIN_MASK_CTL_MASK_4_S 02148#define AR5K_PHY_BIN_MASK_CTL_RATE 0xff0000002149#define AR5K_PHY_BIN_MASK_CTL_RATE_S 242150 2151/*2152 * PHY Antenna control register2153 */2154#define AR5K_PHY_ANT_CTL 0x9910 /* Register Address */2155#define AR5K_PHY_ANT_CTL_TXRX_EN 0x00000001 /* Enable TX/RX (?) */2156#define AR5K_PHY_ANT_CTL_SECTORED_ANT 0x00000004 /* Sectored Antenna */2157#define AR5K_PHY_ANT_CTL_HITUNE5 0x00000008 /* Hitune5 (?) */2158#define AR5K_PHY_ANT_CTL_SWTABLE_IDLE 0x000003f0 /* Switch table idle (?) */2159#define AR5K_PHY_ANT_CTL_SWTABLE_IDLE_S 42160 2161/*2162 * PHY receiver delay register [5111+]2163 */2164#define AR5K_PHY_RX_DELAY 0x9914 /* Register Address */2165#define AR5K_PHY_RX_DELAY_M 0x00003fff /* Mask for RX activate to receive delay (/100ns) */2166 2167/*2168 * PHY max rx length register (?) [5111]2169 */2170#define AR5K_PHY_MAX_RX_LEN 0x991c2171 2172/*2173 * PHY timing register 42174 * I(nphase)/Q(adrature) calibration register [5111+]2175 */2176#define AR5K_PHY_IQ 0x9920 /* Register Address */2177#define AR5K_PHY_IQ_CORR_Q_Q_COFF 0x0000001f /* Mask for q correction info */2178#define AR5K_PHY_IQ_CORR_Q_Q_COFF_S 02179#define AR5K_PHY_IQ_CORR_Q_I_COFF 0x000007e0 /* Mask for i correction info */2180#define AR5K_PHY_IQ_CORR_Q_I_COFF_S 52181#define AR5K_PHY_IQ_CORR_ENABLE 0x00000800 /* Enable i/q correction */2182#define AR5K_PHY_IQ_CAL_NUM_LOG_MAX 0x0000f000 /* Mask for max number of samples in log scale */2183#define AR5K_PHY_IQ_CAL_NUM_LOG_MAX_S 122184#define AR5K_PHY_IQ_RUN 0x00010000 /* Run i/q calibration */2185#define AR5K_PHY_IQ_USE_PT_DF 0x00020000 /* Use pilot track df (?) */2186#define AR5K_PHY_IQ_EARLY_TRIG_THR 0x00200000 /* Early trigger threshold (?) (field) */2187#define AR5K_PHY_IQ_PILOT_MASK_EN 0x10000000 /* Enable pilot mask (?) */2188#define AR5K_PHY_IQ_CHAN_MASK_EN 0x20000000 /* Enable channel mask (?) */2189#define AR5K_PHY_IQ_SPUR_FILT_EN 0x40000000 /* Enable spur filter */2190#define AR5K_PHY_IQ_SPUR_RSSI_EN 0x80000000 /* Enable spur rssi */2191 2192/*2193 * PHY timing register 52194 * OFDM Self-correlator Cyclic RSSI threshold params2195 * (Check out bb_cycpwr_thr1 on ANI patent)2196 */2197#define AR5K_PHY_OFDM_SELFCORR 0x9924 /* Register Address */2198#define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1_EN 0x00000001 /* Enable cyclic RSSI thr 1 */2199#define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1 0x000000fe /* Mask for Cyclic RSSI threshold 1 */2200#define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1_S 12201#define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR3 0x00000100 /* Cyclic RSSI threshold 3 (field) (?) */2202#define AR5K_PHY_OFDM_SELFCORR_RSSI_1ATHR_EN 0x00008000 /* Enable 1A RSSI threshold (?) */2203#define AR5K_PHY_OFDM_SELFCORR_RSSI_1ATHR 0x00010000 /* 1A RSSI threshold (field) (?) */2204#define AR5K_PHY_OFDM_SELFCORR_LSCTHR_HIRSSI 0x00800000 /* Long sc threshold hi rssi (?) */2205 2206/*2207 * PHY-only warm reset register2208 */2209#define AR5K_PHY_WARM_RESET 0x99282210 2211/*2212 * PHY-only control register2213 */2214#define AR5K_PHY_CTL 0x992c /* Register Address */2215#define AR5K_PHY_CTL_RX_DRAIN_RATE 0x00000001 /* RX drain rate (?) */2216#define AR5K_PHY_CTL_LATE_TX_SIG_SYM 0x00000002 /* Late tx signal symbol (?) */2217#define AR5K_PHY_CTL_GEN_SCRAMBLER 0x00000004 /* Generate scrambler */2218#define AR5K_PHY_CTL_TX_ANT_SEL 0x00000008 /* TX antenna select */2219#define AR5K_PHY_CTL_TX_ANT_STATIC 0x00000010 /* Static TX antenna */2220#define AR5K_PHY_CTL_RX_ANT_SEL 0x00000020 /* RX antenna select */2221#define AR5K_PHY_CTL_RX_ANT_STATIC 0x00000040 /* Static RX antenna */2222#define AR5K_PHY_CTL_LOW_FREQ_SLE_EN 0x00000080 /* Enable low freq sleep */2223 2224/*2225 * PHY PAPD probe register [5111+]2226 */2227#define AR5K_PHY_PAPD_PROBE 0x99302228#define AR5K_PHY_PAPD_PROBE_SH_HI_PAR 0x000000012229#define AR5K_PHY_PAPD_PROBE_PCDAC_BIAS 0x000000022230#define AR5K_PHY_PAPD_PROBE_COMP_GAIN 0x000000402231#define AR5K_PHY_PAPD_PROBE_TXPOWER 0x00007e002232#define AR5K_PHY_PAPD_PROBE_TXPOWER_S 92233#define AR5K_PHY_PAPD_PROBE_TX_NEXT 0x000080002234#define AR5K_PHY_PAPD_PROBE_PREDIST_EN 0x000100002235#define AR5K_PHY_PAPD_PROBE_TYPE 0x01800000 /* [5112+] */2236#define AR5K_PHY_PAPD_PROBE_TYPE_S 232237#define AR5K_PHY_PAPD_PROBE_TYPE_OFDM 02238#define AR5K_PHY_PAPD_PROBE_TYPE_XR 12239#define AR5K_PHY_PAPD_PROBE_TYPE_CCK 22240#define AR5K_PHY_PAPD_PROBE_GAINF 0xfe0000002241#define AR5K_PHY_PAPD_PROBE_GAINF_S 252242#define AR5K_PHY_PAPD_PROBE_INI_5111 0x00004883 /* [5212+] */2243#define AR5K_PHY_PAPD_PROBE_INI_5112 0x00004882 /* [5212+] */2244 2245/*2246 * PHY TX rate power registers [5112+]2247 */2248#define AR5K_PHY_TXPOWER_RATE1 0x99342249#define AR5K_PHY_TXPOWER_RATE2 0x99382250#define AR5K_PHY_TXPOWER_RATE_MAX 0x993c2251#define AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE 0x000000402252#define AR5K_PHY_TXPOWER_RATE3 0xa2342253#define AR5K_PHY_TXPOWER_RATE4 0xa2382254 2255/*2256 * PHY frame control register [5111+]2257 */2258#define AR5K_PHY_FRAME_CTL_5210 0x98042259#define AR5K_PHY_FRAME_CTL_5211 0x99442260#define AR5K_PHY_FRAME_CTL (ah->ah_version == AR5K_AR5210 ? \2261 AR5K_PHY_FRAME_CTL_5210 : AR5K_PHY_FRAME_CTL_5211)2262/*---[5111+]---*/2263#define AR5K_PHY_FRAME_CTL_WIN_LEN 0x00000003 /* Force window length (?) */2264#define AR5K_PHY_FRAME_CTL_WIN_LEN_S 02265#define AR5K_PHY_FRAME_CTL_TX_CLIP 0x00000038 /* Mask for tx clip (?) */2266#define AR5K_PHY_FRAME_CTL_TX_CLIP_S 32267#define AR5K_PHY_FRAME_CTL_PREP_CHINFO 0x00010000 /* Prepend chan info */2268#define AR5K_PHY_FRAME_CTL_EMU 0x800000002269#define AR5K_PHY_FRAME_CTL_EMU_S 312270/*---[5110/5111]---*/2271#define AR5K_PHY_FRAME_CTL_TIMING_ERR 0x01000000 /* PHY timing error */2272#define AR5K_PHY_FRAME_CTL_PARITY_ERR 0x02000000 /* Parity error */2273#define AR5K_PHY_FRAME_CTL_ILLRATE_ERR 0x04000000 /* Illegal rate */2274#define AR5K_PHY_FRAME_CTL_ILLLEN_ERR 0x08000000 /* Illegal length */2275#define AR5K_PHY_FRAME_CTL_SERVICE_ERR 0x200000002276#define AR5K_PHY_FRAME_CTL_TXURN_ERR 0x40000000 /* TX underrun */2277#define AR5K_PHY_FRAME_CTL_INI \2278 (AR5K_PHY_FRAME_CTL_SERVICE_ERR | \2279 AR5K_PHY_FRAME_CTL_TXURN_ERR | \2280 AR5K_PHY_FRAME_CTL_ILLLEN_ERR | \2281 AR5K_PHY_FRAME_CTL_ILLRATE_ERR | \2282 AR5K_PHY_FRAME_CTL_PARITY_ERR | \2283 AR5K_PHY_FRAME_CTL_TIMING_ERR)2284 2285/*2286 * PHY Tx Power adjustment register [5212A+]2287 */2288#define AR5K_PHY_TX_PWR_ADJ 0x994c2289#define AR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DELTA 0x00000fc02290#define AR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DELTA_S 62291#define AR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_INDEX 0x00fc00002292#define AR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_INDEX_S 182293 2294/*2295 * PHY radar detection register [5111+]2296 */2297#define AR5K_PHY_RADAR 0x99542298#define AR5K_PHY_RADAR_ENABLE 0x000000012299#define AR5K_PHY_RADAR_DISABLE 0x000000002300#define AR5K_PHY_RADAR_INBANDTHR 0x0000003e /* Inband threshold2301 5-bits, units unknown {0..31}2302 (? MHz ?) */2303#define AR5K_PHY_RADAR_INBANDTHR_S 12304 2305#define AR5K_PHY_RADAR_PRSSI_THR 0x00000fc0 /* Pulse RSSI/SNR threshold2306 6-bits, dBm range {0..63}2307 in dBm units. */2308#define AR5K_PHY_RADAR_PRSSI_THR_S 62309 2310#define AR5K_PHY_RADAR_PHEIGHT_THR 0x0003f000 /* Pulse height threshold2311 6-bits, dBm range {0..63}2312 in dBm units. */2313#define AR5K_PHY_RADAR_PHEIGHT_THR_S 122314 2315#define AR5K_PHY_RADAR_RSSI_THR 0x00fc0000 /* Radar RSSI/SNR threshold.2316 6-bits, dBm range {0..63}2317 in dBm units. */2318#define AR5K_PHY_RADAR_RSSI_THR_S 182319 2320#define AR5K_PHY_RADAR_FIRPWR_THR 0x7f000000 /* Finite Impulse Response2321 filter power out threshold.2322 7-bits, standard power range2323 {0..127} in 1/2 dBm units. */2324#define AR5K_PHY_RADAR_FIRPWR_THRS 242325 2326/*2327 * PHY antenna switch table registers2328 */2329#define AR5K_PHY_ANT_SWITCH_TABLE_0 0x99602330#define AR5K_PHY_ANT_SWITCH_TABLE_1 0x99642331 2332/*2333 * PHY Noise floor threshold2334 */2335#define AR5K_PHY_NFTHRES 0x99682336 2337/*2338 * Sigma Delta register (?) [5213]2339 */2340#define AR5K_PHY_SIGMA_DELTA 0x996C2341#define AR5K_PHY_SIGMA_DELTA_ADC_SEL 0x000000032342#define AR5K_PHY_SIGMA_DELTA_ADC_SEL_S 02343#define AR5K_PHY_SIGMA_DELTA_FILT2 0x000000f82344#define AR5K_PHY_SIGMA_DELTA_FILT2_S 32345#define AR5K_PHY_SIGMA_DELTA_FILT1 0x00001f002346#define AR5K_PHY_SIGMA_DELTA_FILT1_S 82347#define AR5K_PHY_SIGMA_DELTA_ADC_CLIP 0x01ffe0002348#define AR5K_PHY_SIGMA_DELTA_ADC_CLIP_S 132349 2350/*2351 * RF restart register [5112+] (?)2352 */2353#define AR5K_PHY_RESTART 0x9970 /* restart */2354#define AR5K_PHY_RESTART_DIV_GC 0x001c0000 /* Fast diversity gc_limit (?) */2355#define AR5K_PHY_RESTART_DIV_GC_S 182356 2357/*2358 * RF Bus access request register (for synth-only channel switching)2359 */2360#define AR5K_PHY_RFBUS_REQ 0x997C2361#define AR5K_PHY_RFBUS_REQ_REQUEST 0x000000012362 2363/*2364 * Spur mitigation masks (?)2365 */2366#define AR5K_PHY_TIMING_7 0x99802367#define AR5K_PHY_TIMING_8 0x99842368#define AR5K_PHY_TIMING_8_PILOT_MASK_2 0x000fffff2369#define AR5K_PHY_TIMING_8_PILOT_MASK_2_S 02370 2371#define AR5K_PHY_BIN_MASK2_1 0x99882372#define AR5K_PHY_BIN_MASK2_2 0x998c2373#define AR5K_PHY_BIN_MASK2_3 0x99902374 2375#define AR5K_PHY_BIN_MASK2_4 0x99942376#define AR5K_PHY_BIN_MASK2_4_MASK_4 0x00003fff2377#define AR5K_PHY_BIN_MASK2_4_MASK_4_S 02378 2379#define AR5K_PHY_TIMING_9 0x99982380#define AR5K_PHY_TIMING_10 0x999c2381#define AR5K_PHY_TIMING_10_PILOT_MASK_2 0x000fffff2382#define AR5K_PHY_TIMING_10_PILOT_MASK_2_S 02383 2384/*2385 * Spur mitigation control2386 */2387#define AR5K_PHY_TIMING_11 0x99a0 /* Register address */2388#define AR5K_PHY_TIMING_11_SPUR_DELTA_PHASE 0x000fffff /* Spur delta phase */2389#define AR5K_PHY_TIMING_11_SPUR_DELTA_PHASE_S 02390#define AR5K_PHY_TIMING_11_SPUR_FREQ_SD 0x3ff00000 /* Freq sigma delta */2391#define AR5K_PHY_TIMING_11_SPUR_FREQ_SD_S 202392#define AR5K_PHY_TIMING_11_USE_SPUR_IN_AGC 0x40000000 /* Spur filter in AGC detector */2393#define AR5K_PHY_TIMING_11_USE_SPUR_IN_SELFCOR 0x80000000 /* Spur filter in OFDM self correlator */2394 2395/*2396 * Gain tables2397 */2398#define AR5K_BB_GAIN_BASE 0x9b00 /* BaseBand Amplifier Gain table base address */2399#define AR5K_BB_GAIN(_n) (AR5K_BB_GAIN_BASE + ((_n) << 2))2400#define AR5K_RF_GAIN_BASE 0x9a00 /* RF Amplifier Gain table base address */2401#define AR5K_RF_GAIN(_n) (AR5K_RF_GAIN_BASE + ((_n) << 2))2402 2403/*2404 * PHY timing IQ calibration result register [5111+]2405 */2406#define AR5K_PHY_IQRES_CAL_PWR_I 0x9c10 /* I (Inphase) power value */2407#define AR5K_PHY_IQRES_CAL_PWR_Q 0x9c14 /* Q (Quadrature) power value */2408#define AR5K_PHY_IQRES_CAL_CORR 0x9c18 /* I/Q Correlation */2409 2410/*2411 * PHY current RSSI register [5111+]2412 */2413#define AR5K_PHY_CURRENT_RSSI 0x9c1c2414 2415/*2416 * PHY RF Bus grant register2417 */2418#define AR5K_PHY_RFBUS_GRANT 0x9c202419#define AR5K_PHY_RFBUS_GRANT_OK 0x000000012420 2421/*2422 * PHY ADC test register2423 */2424#define AR5K_PHY_ADC_TEST 0x9c242425#define AR5K_PHY_ADC_TEST_I 0x000000012426#define AR5K_PHY_ADC_TEST_Q 0x000002002427 2428/*2429 * PHY DAC test register2430 */2431#define AR5K_PHY_DAC_TEST 0x9c282432#define AR5K_PHY_DAC_TEST_I 0x000000012433#define AR5K_PHY_DAC_TEST_Q 0x000002002434 2435/*2436 * PHY PTAT register (?)2437 */2438#define AR5K_PHY_PTAT 0x9c2c2439 2440/*2441 * PHY Illegal TX rate register [5112+]2442 */2443#define AR5K_PHY_BAD_TX_RATE 0x9c302444 2445/*2446 * PHY SPUR Power register [5112+]2447 */2448#define AR5K_PHY_SPUR_PWR 0x9c34 /* Register Address */2449#define AR5K_PHY_SPUR_PWR_I 0x00000001 /* SPUR Power estimate for I (field) */2450#define AR5K_PHY_SPUR_PWR_Q 0x00000100 /* SPUR Power estimate for Q (field) */2451#define AR5K_PHY_SPUR_PWR_FILT 0x00010000 /* Power with SPUR removed (field) */2452 2453/*2454 * PHY Channel status register [5112+] (?)2455 */2456#define AR5K_PHY_CHAN_STATUS 0x9c382457#define AR5K_PHY_CHAN_STATUS_BT_ACT 0x000000012458#define AR5K_PHY_CHAN_STATUS_RX_CLR_RAW 0x000000022459#define AR5K_PHY_CHAN_STATUS_RX_CLR_MAC 0x000000042460#define AR5K_PHY_CHAN_STATUS_RX_CLR_PAP 0x000000082461 2462/*2463 * Heavy clip enable register2464 */2465#define AR5K_PHY_HEAVY_CLIP_ENABLE 0x99e02466 2467/*2468 * PHY clock sleep registers [5112+]2469 */2470#define AR5K_PHY_SCLOCK 0x99f02471#define AR5K_PHY_SCLOCK_32MHZ 0x0000000c2472#define AR5K_PHY_SDELAY 0x99f42473#define AR5K_PHY_SDELAY_32MHZ 0x000000ff2474#define AR5K_PHY_SPENDING 0x99f82475 2476 2477/*2478 * PHY PAPD I (power?) table (?)2479 * (92! entries)2480 */2481#define AR5K_PHY_PAPD_I_BASE 0xa0002482#define AR5K_PHY_PAPD_I(_n) (AR5K_PHY_PAPD_I_BASE + ((_n) << 2))2483 2484/*2485 * PHY PCDAC TX power table2486 */2487#define AR5K_PHY_PCDAC_TXPOWER_BASE 0xa1802488#define AR5K_PHY_PCDAC_TXPOWER(_n) (AR5K_PHY_PCDAC_TXPOWER_BASE + ((_n) << 2))2489 2490/*2491 * PHY mode register [5111+]2492 */2493#define AR5K_PHY_MODE 0x0a200 /* Register Address */2494#define AR5K_PHY_MODE_MOD 0x00000001 /* PHY Modulation bit */2495#define AR5K_PHY_MODE_MOD_OFDM 02496#define AR5K_PHY_MODE_MOD_CCK 12497#define AR5K_PHY_MODE_FREQ 0x00000002 /* Freq mode bit */2498#define AR5K_PHY_MODE_FREQ_5GHZ 02499#define AR5K_PHY_MODE_FREQ_2GHZ 22500#define AR5K_PHY_MODE_MOD_DYN 0x00000004 /* Enable Dynamic OFDM/CCK mode [5112+] */2501#define AR5K_PHY_MODE_RAD 0x00000008 /* [5212+] */2502#define AR5K_PHY_MODE_RAD_RF5111 02503#define AR5K_PHY_MODE_RAD_RF5112 82504#define AR5K_PHY_MODE_XR 0x00000010 /* Enable XR mode [5112+] */2505#define AR5K_PHY_MODE_HALF_RATE 0x00000020 /* Enable Half rate (test) */2506#define AR5K_PHY_MODE_QUARTER_RATE 0x00000040 /* Enable Quarter rat (test) */2507 2508/*2509 * PHY CCK transmit control register [5111+ (?)]2510 */2511#define AR5K_PHY_CCKTXCTL 0xa2042512#define AR5K_PHY_CCKTXCTL_WORLD 0x000000002513#define AR5K_PHY_CCKTXCTL_JAPAN 0x000000102514#define AR5K_PHY_CCKTXCTL_SCRAMBLER_DIS 0x000000012515#define AR5K_PHY_CCKTXCTK_DAC_SCALE 0x000000042516 2517/*2518 * PHY CCK Cross-correlator Barker RSSI threshold register [5212+]2519 */2520#define AR5K_PHY_CCK_CROSSCORR 0xa2082521#define AR5K_PHY_CCK_CROSSCORR_WEAK_SIG_THR 0x0000003f2522#define AR5K_PHY_CCK_CROSSCORR_WEAK_SIG_THR_S 02523 2524/* Same address is used for antenna diversity activation */2525#define AR5K_PHY_FAST_ANT_DIV 0xa2082526#define AR5K_PHY_FAST_ANT_DIV_EN 0x000020002527 2528/*2529 * PHY 2GHz gain register [5111+]2530 */2531#define AR5K_PHY_GAIN_2GHZ 0xa20c2532#define AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX 0x00fc00002533#define AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX_S 182534#define AR5K_PHY_GAIN_2GHZ_INI_5111 0x6480416c2535 2536#define AR5K_PHY_CCK_RX_CTL_4 0xa21c2537#define AR5K_PHY_CCK_RX_CTL_4_FREQ_EST_SHORT 0x01f800002538#define AR5K_PHY_CCK_RX_CTL_4_FREQ_EST_SHORT_S 192539 2540#define AR5K_PHY_DAG_CCK_CTL 0xa2282541#define AR5K_PHY_DAG_CCK_CTL_EN_RSSI_THR 0x000002002542#define AR5K_PHY_DAG_CCK_CTL_RSSI_THR 0x0001fc002543#define AR5K_PHY_DAG_CCK_CTL_RSSI_THR_S 102544 2545#define AR5K_PHY_FAST_ADC 0xa24c2546 2547#define AR5K_PHY_BLUETOOTH 0xa2542548 2549/*2550 * Transmit Power Control register2551 * [2413+]2552 */2553#define AR5K_PHY_TPC_RG1 0xa2582554#define AR5K_PHY_TPC_RG1_NUM_PD_GAIN 0x0000c0002555#define AR5K_PHY_TPC_RG1_NUM_PD_GAIN_S 142556#define AR5K_PHY_TPC_RG1_PDGAIN_1 0x000300002557#define AR5K_PHY_TPC_RG1_PDGAIN_1_S 162558#define AR5K_PHY_TPC_RG1_PDGAIN_2 0x000c00002559#define AR5K_PHY_TPC_RG1_PDGAIN_2_S 182560#define AR5K_PHY_TPC_RG1_PDGAIN_3 0x003000002561#define AR5K_PHY_TPC_RG1_PDGAIN_3_S 202562 2563#define AR5K_PHY_TPC_RG5 0xa26C2564#define AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP 0x0000000F2565#define AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP_S 02566#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_1 0x000003F02567#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_1_S 42568#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_2 0x0000FC002569#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_2_S 102570#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3 0x003F00002571#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3_S 162572#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4 0x0FC000002573#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4_S 222574 2575/*2576 * PHY PDADC Tx power table2577 */2578#define AR5K_PHY_PDADC_TXPOWER_BASE 0xa2802579#define AR5K_PHY_PDADC_TXPOWER(_n) (AR5K_PHY_PDADC_TXPOWER_BASE + ((_n) << 2))2580 2581/*2582 * Platform registers for WiSoC2583 */2584#define AR5K_AR5312_RESET 0xbc0030202585#define AR5K_AR5312_RESET_BB0_COLD 0x000000042586#define AR5K_AR5312_RESET_BB1_COLD 0x000002002587#define AR5K_AR5312_RESET_WMAC0 0x000020002588#define AR5K_AR5312_RESET_BB0_WARM 0x000040002589#define AR5K_AR5312_RESET_WMAC1 0x000200002590#define AR5K_AR5312_RESET_BB1_WARM 0x000400002591 2592#define AR5K_AR5312_ENABLE 0xbc0030802593#define AR5K_AR5312_ENABLE_WLAN0 0x000000012594#define AR5K_AR5312_ENABLE_WLAN1 0x000000082595 2596#define AR5K_AR2315_RESET 0xb10000042597#define AR5K_AR2315_RESET_WMAC 0x000000012598#define AR5K_AR2315_RESET_BB_WARM 0x000000022599 2600#define AR5K_AR2315_AHB_ARB_CTL 0xb10000082601#define AR5K_AR2315_AHB_ARB_CTL_WLAN 0x000000022602 2603#define AR5K_AR2315_BYTESWAP 0xb100000c2604#define AR5K_AR2315_BYTESWAP_WMAC 0x000000022605